JP4910292B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a high breakdown voltage semiconductor device.

The one-chip power IC is intended to reduce the chip size and increase the functionality by forming a control LSI and a power element on a silicon substrate.
Since the commercial power supply voltage is generally 100 to 240 V, it is necessary to perform voltage conversion according to the target device. For example, in computers and electronic equipment, the voltage is stepped down using a transformer to about several volts, which is the operating voltage of a semiconductor element.
In recent years, with the development of portable devices, transformers have become smaller and lighter. Inductance is reduced by using higher frequencies, and high-speed switching is performed from several hundred kilohertz to several megahertz. Since the maximum peak value of the power supply voltage is applied to the switching element, for example, the element withstand voltage of 240V power supply needs about 700V. In a silicon semiconductor, a high breakdown voltage inevitably accompanies an increase in the element length, which causes an increase in cost.

Means for solving this problem is disclosed in “Lateral high voltage trench MOSFET and manufacturing method thereof” of Patent Document 1. A trench is formed on a semiconductor substrate, and an offset drain region is provided around the trench to achieve a high breakdown voltage. For example, the offset drain length of an element having a withstand voltage of 700 V is required to be 60 μm, and this is replaced with a trench having a depth of 20 μm and a width of about 20 μm.
FIG. 9 is a cross-sectional view of a main part of a conventional trench lateral power MOSFET. In the figure, 1 is a p-type semiconductor substrate, 2 is a trench, 2a is an insulator filling the trench, 3 is an n ^- offset drain region having a uniform thickness around the trench, 4 is a p-well region, 5 is p base region, 6 is an n well region, 7 is an n ⁺ source region, 8 is an n ⁺ drain region, 9 is a gate insulating film, 10 is a gate electrode, 11 is an interlayer insulating film, 12 is a source electrode, and 13 is a drain electrode. , 14 are interlayer insulating films, and 16 is a sealing resin layer (resin coating layer).

The interlayer insulating film 14 deposits a nitride film that hardly allows moisture to pass therethrough as a protective film for the source electrode 12 and the drain electrode 13. In addition, the sealing resin layer 16 needs to employ a material with less movable ions from the viewpoint of reliability.
In the trench lateral element, since the distance between the source electrode 12 and the drain electrode 13 is set to about 10 μm, the electric field strength applied to the interlayer insulating films 11 and 14 and the sealing resin layer 16 becomes higher. Polarized charges and mobile ions are induced and accumulated in the films 11 and 14 and the interface 21. As a result, the potential distribution changes. For example, resin positive ions 22 are accumulated near the end of the source electrode 12, or negative ions 23 are accumulated at the end of the drain electrode 13. In addition, the potential distribution in the n ⁻ offset drain region in the on state is affected by the positive ions 22 or the negative ions 23 induced at the end of the source electrode 12 or the drain electrode 13, and the on-current hardly flows. On-resistance increases.

In Patent Document 2, mobile ions in a mold resin are induced in the vicinity of an electrode, causing polarization in a plasma oxide film disposed in a lower layer, thereby changing the potential distribution of the device and causing a change in breakdown voltage. In order to prevent this, a TEOS (tetraethyl-ortho-silicate) film doped with nitrogen is formed, the electric conductivity is set to an intermediate value between the oxide film and the nitride film, and the polarization charge generated in the TEOS film is used as a leakage current. It is disclosed that the withstand voltage fluctuation can be suppressed by removing.
Further, in FIGS. 11 and 12 of Patent Document 3, in order to prevent the influence of mobile ions in the mold resin, Si ⁺ nitridation in which the composition of silicon is set higher on the source electrode, the drain electrode, and the interlayer insulating film is used. Form a film, further form a passivation film, which is a normal nitride film (insulating nitride film), and then form a conductive film connected to the source or drain electrode on top of it to deplete the Si ⁺ nitride film Thus, the leakage current can be kept low, and thermal runaway (decrease in breakdown voltage) of the power MOSFET at a high temperature can be prevented. Further, it is disclosed that the influence of movable ions of the mold resin can be shielded and the withstand voltage fluctuation of the power MOSFET is eliminated.

Further, Patent Document 4 discloses that a withstand voltage drop with time under high voltage and high humidity during actual use can be prevented by setting the overhang of the field plate and the film thickness of the interlayer insulating film to a predetermined value. ing.
JP-A-8-97411 JP 2003-12459 A JP, 2001-7327, A FIG. JP 2002-270830 A

However, in the actual element, in addition to the influence of the polarization charge described in Patent Document 2, there is an influence caused by accumulating the charge in the mold resin. In particular, a plasma oxide film formed at about 400 ° C. or lower contains Si—H bonds, N—H bonds, and a large amount of hydrogen. Since holes are easily generated, a positive or negative charged state can be taken depending on the state of rearrangement of the holes. For this reason, a thin film containing a large amount of such bonds is likely to cause a fluctuation in breakdown voltage. Therefore, it is necessary to remove the mobile ions themselves generated in the mold resin. For this reason, the TEOS film is usually heat-treated at about 1000 ° C. to make the film highly purified.
However, when a TEOS film is used as a protective film for a source electrode and a drain electrode formed of a low-melting-point material such as aluminum, the high-temperature treatment at about 1000 ° C. cannot be performed because the electrode is altered, and about 400 ° C. The following low-temperature treatment is performed. As a result, a thin film including a large number of bonds as described above is likely to cause a change in breakdown voltage.

In addition, as shown in Patent Document 3, in the case of a structure in which a Si ⁺ nitride film and a conductive film are stacked in order to prevent a fluctuation in breakdown voltage, the manufacturing cost of film formation increases.
An object of the present invention is to provide a semiconductor device that solves the above-mentioned problems and can prevent fluctuations in breakdown voltage at a low manufacturing cost.

In order to achieve the above object, in a semiconductor device provided with a protective film (interlayer insulating film) such as a passivation film , any of metal, semiconductor and carbon formed on the protective film is equivalent. sheet resistance, a structure having a ^{1 × 10 9 Ω / □ ~1} × 10 10 Ω / □ discontinuous film is.
Further, in a semiconductor device including a protective film and a resin coating layer (a sealing resin layer such as a mold resin) formed through the protective film, the protective film is formed between the protective film and the resin coating layer. And a discontinuous thin film having an equivalent sheet resistance value of 1 × 10 ⁹ Ω / □ to 1 × 10 ¹⁰ Ω / □ .
Further, the first semiconductor layer is formed on one surface layer of the semiconductor substrate and is formed on the surface of the semiconductor substrate between the first and second semiconductor regions and the first and second semiconductor regions through which a main current flows. An insulating film formed thereon, a protective film formed on the first and second semiconductor regions and the insulating film, and any one of metal, semiconductor and carbon formed on the protective film , and equivalent And a resin coating layer coated with a discontinuous thin film having a typical sheet resistance value of 1 × 10 ⁹ Ω / □ to 1 × 10 ¹⁰ Ω / □ .

The metal may be carbon, tungsten, or platinum.
Also, a trench formed inside from the surface of the first conductivity type semiconductor layer (eg, p-type semiconductor layer), and a second conductivity type first region (eg, n-type offset drain) formed along the trench. Region), a first conductivity type second region (for example, a p-type well region) and a second conductivity type third region (for example, for example) formed in contact with the first region and across the trench n-type well region), a first conductive type fourth region (for example, a p-type base region) in contact with the first region on the surface layer of the second region, and a second conductive material on the surface layer of the fourth region. A fifth region (for example, an n-type source region) of a type, a sixth region of a first conductivity type (for example, an n-type drain region) formed in the surface layer of the third region, and a first region that fills the trench. 1 insulating film, on the fourth region sandwiched between the fifth region and the second region, A gate insulating film formed over the second region, a gate electrode formed over the gate insulating film and a part of the first insulating film, and the first insulating film over the gate electrode A second insulating film (for example, an interlayer insulating film) formed on the film, and a first main electrode (for example, a source electrode) in contact with the fourth region and the fifth region and extending on the second insulating film ), A second main electrode (for example, a drain electrode) that is in contact with the sixth region and extends on the second insulating film, on the first main electrode, on the second insulating film, and on the second main film In a semiconductor device comprising a third insulating film (for example, a passivation film) formed over an electrode, and a resin coating layer formed on the third insulating film, the third insulating film and the resin coating between the layers, the metal is any of a semiconductor and carbon, are equivalent sheet resistance Good and ^{1 × 10 9 Ω / □ ~1} × 10 10 Ω / □ discontinuous film is is formed.

The first conductive type second region and the second conductive type third region formed on the surface layer of the first conductive type semiconductor layer and facing each other, and the surface layer of the second region A fourth region of the first conductivity type to be formed; a fifth region of the second conductivity type in the surface layer of the fourth region; a sixth region of the second conductivity type formed in the surface layer of the third region; A gate insulating film formed on the fourth region sandwiched between the fifth region and the second region, a gate electrode formed on the gate insulating film, on the gate electrode and on the semiconductor layer A second insulating film formed on the first insulating film; a first main electrode in contact with the fourth region and the fifth region; and extending on the second insulating film; and in contact with the sixth region; A second main electrode extending upward, a third insulating film formed over the first main electrode, the second insulating film, and the second main electrode; A semiconductor device comprising a resin coating layer formed on the third insulating film, and between the resin coating layer and the third insulating film, a metal is any of a semiconductor and carbon equivalent sheet A discontinuous thin film having a resistance value of 1 × 10 ⁹ Ω / □ to 1 × 10 ¹⁰ Ω / □ may be formed.

The discontinuous thin film may be in a floating potential state without being connected to either the first main electrode or the second main electrode.
The discontinuous thin film may be electrically connected to at least one of the first main electrode and the second main electrode.
The equivalent sheet resistance value of the discontinuous thin film is preferably 1 × 10 ⁹ Ω / □ to 1 × 10 ¹⁰ Ω / □. Here, the equivalent sheet resistance value is obtained by converting the resistance value obtained by dividing the applied voltage applied between the first main electrode and the second main electrode by the peak value of the leakage current shown in FIG. 2 into the sheet resistance value. Say.
Moreover, the film thickness of the said discontinuous thin film is good in it being 0.1 nm-2 nm.
Moreover, it is more preferable that the thickness of the discontinuous thin film is 0.1 nm to 0.5 nm.
[Action]
When a discontinuous thin film is inserted between the interlayer insulation film and the resin, the mobile ions and polarization charges existing in the resin coating layer and the interlayer insulation film near the electrodes are neutralized by exchanging electrons through the discontinuous thin film. It is possible to do. It is presumed that leakage current flows as electrons move in the discontinuous thin film.

According to the explanation of the discontinuous film (discontinuous thin film) described in Thin Film Handbook Ohm Co., pp 463-pp 472 (1982), the discontinuous film means that when a metal film is formed on an insulating film, nucleation, A continuous film is formed through a network structure through growth and aggregation. It means that the electrodes are not conductive with metal. The boundary film thickness from the continuous film to the discontinuous film is about 17 nm for Al and about 40 nm for Au. If the film thickness is less than this, a so-called size effect in which the thickness is not proportional to the resistivity appears. When the de Broglie wavelength is below several angstroms, quantum mechanical effects appear. That is, the leakage current flowing through the discontinuous thin film is caused with quantum mechanical behavior.
The characteristics of the electrical conduction of a general discontinuous film are, for example, a sheet resistance as high as 10 kΩ / □ or higher, a negative temperature coefficient, and an activation energy ranging from 0.001 to 0.8 eV over a wide range. It is characteristic to cross.

However, the mechanism of electrical conduction in the discontinuous film includes a thermionic emission model, an activated tunneling model, a substrate impurity, a tunneling model via surface states, etc. and has not been determined.
The discontinuous film is preferably made of a metal or a semiconductor, which is difficult to form a compound with respect to the underlying insulating film, has poor wettability, and easily takes a particle form. For example, the material provided on the oxide film or nitride film is preferably platinum, carbon, tungsten, or the like. As a method for forming the conductive layer, for example, by using a sputtering method, particles can penetrate into the interlayer insulating film.
As in the nucleation method in wet plating, a method of immersing in a solution in which a conductive material is dispersed and attaching a trace amount to the sample surface may be used. Furthermore, a method of changing the film quality and equivalently conducting the film surface by ion implantation may be used. If the discontinuous thin film has a sheet resistance value of several G (giga) Ω / □, the effect of charge accumulation can be reduced. The influence on the potential distribution is small, and device characteristics such as breakdown voltage and on-resistance are not degraded.

  The discontinuous thin film is inserted between the interlayer insulating film and the resin coating layer. Although it is effective even in a floating state (floating potential state), a larger effect can be obtained when it is in contact with the electrode.

According to this invention, by forming a discontinuous thin film on the electrode to which a high electric field is applied and on the passivation film, an interlayer insulating film such as a passivation film in the vicinity of the electrode and a sealing resin layer such as a mold resin Alternatively, it is possible to prevent charges from accumulating at these interfaces.
As a result, the fluctuation of the potential distribution of the element can be prevented and the withstand voltage fluctuation can be prevented at a low manufacturing cost. In addition, a decrease in on-current (an increase in on-resistance) can be prevented.

  The best mode for carrying out the invention will be described in the following examples by taking a horizontal element as an example, but the present invention can also be applied to a vertical element.

FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. This figure shows a cross-sectional structure of a trench lateral MOSFET, and the same parts as those in FIG. In the figure, reference numeral 1 denotes a p-type semiconductor substrate, 2 denotes a trench, 2a denotes an insulator filling the trench, 3 denotes an n ⁻ offset drain region having a uniform thickness around the trench, 4 denotes a p-well region, and 5 denotes p Base region, 6 is an n well region, 7 is an n ⁺ source region, 8 is an n ⁺ drain region, 9 is a gate insulating film, 10 is a gate electrode, 11 is an interlayer insulating film, 12 is a source electrode, 13 is a drain electrode, 14 is an interlayer insulating film, 15 is a carbon discontinuous thin film, and 16 is a sealing resin layer (resin coating layer) such as a mold resin.
A method for manufacturing the semiconductor device having the configuration shown in FIG. 1 will be described. A p-well region 4 and an n-well region 6 were formed on the surface portion of the p-type semiconductor substrate 1 having a specific resistance of 100 Ωcm using a normal semiconductor process. A trench 2 having a width of 20 μm and a depth of 20 μm was formed on the surface portion of the p-well region 4 by a photoetching technique.

Subsequently, a buffer oxide film is formed, phosphorus is implanted into both side walls and the bottom, and heat treatment is performed in a nitrogen atmosphere. The surface concentration is 5 × 10 ¹⁵ cm ⁻³ and the diffusion depth (xj) is about 4 μm. An n ⁻ offset drain region 3 was formed. After a plurality of SOG coating and curing processes, the surface was flattened by CMP (Chemical Mechanical Polishing), and the inside of the trench 2 was filled with an insulator 2a such as an oxide film.
A gate insulating film 9 was formed, polysilicon was deposited thereon, and a gate electrode 10 was formed by a photoetching technique. A p base region 5 was formed on the surface portion of the p well region 4 by self-alignment by the source side end of the gate electrode 10. Simultaneously with the n ⁺ source region 7, an n ⁺ drain region 8 was formed on the surface portion of the n ⁻ offset drain region 3 on the opposite side of the trench 2. An interlayer insulating film 11 was deposited, contact holes were opened in the interlayer insulating film 11, and a source electrode 12 and a drain electrode 13 were formed over the trench 2 by 5 μm each. The distance between the drain electrode 13 and the source electrode 12 was 10 μm. Subsequently, an interlayer insulating film 14 made of a plasma nitride film was formed. Two types of carbon having a high melting point and poor wettability with the plasma nitride film having a thickness of 0.1 nm and 0.5 nm were formed as the carbon discontinuous thin film 15.

The discontinuous carbon film 15 was formed using a hot filament chemical vapor deposition method in which methane gas as a source gas was pyrolyzed with a filament heated to about 2000 ° C. First, the raw material gas concentration and the gas supply flow rate were adjusted to be a 50 nm continuous thin film with a formation time of 120 minutes, and then the film thickness was controlled by time control. The film formation time of 14 seconds was set to a value corresponding to a thickness of 0.1 nm, and the film formation time of 72 seconds was set to a value corresponding to a thickness of 0.5 nm.
The use of materials with poor wettability such as carbon is because the carbon particles on the plasma nitride film are rounded due to surface tension, and a discrete carbon particle layer can be formed at the atomic level to form a discontinuous thin film. It is. Finally, it was sealed with a sealing resin layer 16 such as a mold resin. The film thickness of carbon is controlled by the time for vapor phase growth, and the growth time is on the order of minutes. The other steps are the same as the conventional steps except that the step of forming the carbon discontinuous thin film 15 is added to the conventional step of manufacturing the lateral MOSFET.

  Table 1 shows the results of a BT (Bias Temperature) test under the conditions of a temperature of 125 ° C. and a voltage of 700V.

With respect to the breakdown voltage in the conventional structure, the initial value of 740 V decreased to 700 V after 165 hours, and the breakdown voltage reduction rate was 5.4%.
By applying the present invention, a withstand voltage of 700 V or more was obtained even after 1000 hours. The rate of breakdown voltage reduction was 2.7% at a film thickness of 0.1 nm and 1.4% at a film thickness of 0.5 nm. In both cases, the breakdown voltage reduction rate was improved.
FIG. 2 is a schematic diagram showing a change in leakage current over time. The peak of the leak current appears in a short time, and then the leak current decreases and starts increasing again after passing through the minimum value. This is because the leakage current is generated at a position away from the discontinuous thin film and the first current component flowing at an early stage that occurs when mobile ions located near the discontinuous thin film exchange electrons through the discontinuous thin film. This is because a certain mobile ion is composed of a second current component that flows at a later time which is generated by the exchange of electrons through the discontinuous thin film. When there is no discontinuous thin film, only the second current component is obtained.

When the peak of the first current component appears earlier and the peak value is larger, the exchange between the mobile ions and the electrons is performed quickly, and the neutralization occurs, and the breakdown voltage fluctuation is less likely to occur.
A case where an applied voltage of 700 V is applied to an element to which the carbon discontinuous thin film 15 having a withstand voltage of 740 V is applied will be described. The peak of the first current component appeared after 20 minutes when the film thickness was 0.1 nm, and the peak value of the leakage current was 32 nA. A film thickness of 0.5 nm also appeared after 20 minutes and was almost the same as 0.1 nm at 30 nA. Further, the minimum value of the leakage current appears after 60 hours when the film thickness is 0.1 nm, is 5 nA, and appears after 6 hours when the film thickness is 0.5 nm, 7 nA, and the current value is almost the same. When the time to become 0.5 nm is significantly shorter as 1/10, the mobile ions are neutralized in a short time, and the withstand voltage fluctuation is reduced.
However, if the film thickness exceeds 2 nm, the carbon discontinuous thin film changes to a carbon continuous film, so that there is a possibility that the leakage current increases rapidly and the device causes thermal runaway. Therefore, the film thickness of the carbon discontinuous thin film 15 is preferably 0.1 nm to 2 nm, and preferably 0.1 nm to 0.5 nm.

In this experiment, the electric field strength between the source and the drain is 700 V / 10 μm = 7 × 10 ⁵ V / cm because the applied voltage is 700 V and the distance between the source electrode and the drain electrode is 10 μm, and the leakage at that time The value obtained by subtracting the minimum value from the peak value of the current (increase) is approximately the same as 27 nA and 23 nA at 0.1 μm and 0.5 μm, respectively, and is approximately 25 nA.
Moreover, the equivalent sheet resistance value of the carbon discontinuous thin film obtained by converting the resistance value obtained by dividing the applied voltage by the peak current into the sheet resistance is about 10 GΩ / □. If this equivalent sheet resistance value is less than 1 GΩ / □ (1 × 10 ⁹ Ω / □), the leakage current increases and the generation loss of the element increases, which may cause thermal runaway. On the other hand, if it exceeds 10 GΩ / □, it takes time to neutralize the mobile ions and causes a decrease in pressure resistance. Therefore, the equivalent sheet resistance value of the carbon discontinuous thin film is preferably in the range of 1 GΩ (1 × 10 ⁹ Ω) / □ to 10 GΩ (1 × 10 ¹⁰ Ω) / □.

  Further, in the first embodiment, the carbon discontinuous thin film 15 is not connected to the source electrode 12 and the drain electrode 13, but although not shown, when connected to one of the electrodes, the time when the minimum value of the leakage current appears is shortened, The time for neutralizing the accumulated mobile ions is earlier than in the first embodiment, and voltage fluctuation is less likely to occur.

  FIG. 3 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. The difference from FIG. 1 is that the carbon discontinuous thin film 15 is connected to both the source electrode 12 and the drain electrode 13. Accumulated mobile ions are reduced faster by connecting the carbon discontinuous thin film 15 to both electrodes than in the first embodiment and only one electrode (not shown). There is an effect that the withstand voltage fluctuation is further reduced.

FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the third embodiment of the present invention. The difference from FIG. 1 is that the discontinuous thin film 17 is a discontinuous thin film 17 using a sputtering method.
The process of the present invention is the same as that of Example 1 until the formation of the interlayer insulating film 14 which is a passivation film made of a plasma nitride film. After that, two types of tungsten discontinuous thin films 17 having a film thickness of 0.1 nm and 0.5 nm were formed on the interlayer insulating film 14 by sputtering using a high melting point material and poor wettability with the plasma nitride film.
The tungsten discontinuous film 17 was formed using a hot filament chemical vapor deposition method in which tungsten hexafluoride was heated as a source gas to a filament heated to about 2000 ° C. First, the raw material gas concentration and the gas supply flow rate were adjusted so that a continuous thin film of about 50 nm was formed in a formation time of 100 minutes, and then the film thickness was controlled by time control. The film formation time of 12 seconds was set to a value corresponding to a thickness of 0.1 nm, and the film formation time of 60 seconds was set to a value corresponding to a thickness of 0.5 nm.

  After forming the tungsten discontinuous thin film, it was sealed with a sealing resin layer 16 such as a mold resin to produce a trench lateral MOSFET. Table 2 shows the BT test results under the same conditions as in the first example.

The rate of decrease in pressure resistance after 1000 hours was 2.5% for a film thickness of 0.1 m and 1.0% for a film thickness of 0.5 nm, which is an improvement over the conventional 5.4%. Also, the breakdown voltage reduction rate is somewhat smaller than in Table 1. This is presumed to be due to the difference in material. Further, by connecting the tungsten discontinuous thin film 17 to the source electrode 12 and the drain electrode 13 as shown in FIG. 3, the breakdown voltage reduction rate can be further reduced. Also in this case, as in the case of the carbon discontinuous thin film 15, the equivalent sheet resistance value of the tungsten discontinuous thin film is preferably in the range of 1 GΩ / □ to 10 GΩ / □, and the film thickness of the tungsten discontinuous thin film 17 is 0. .1 nm to 2 nm is preferable, and 0.1 nm to 0.5 nm is preferable.
1, 3, and 4, the effects of the discontinuous thin film of carbon and tungsten were introduced by the vapor phase growth method. However, the combination of materials and shapes is intended to form a path that does not accumulate interface charges. Combinations are possible. In addition to the above, the material of the discontinuous thin film may be platinum or a semiconductor such as SiC. Also in this case, the equivalent sheet resistance value of the discontinuous thin film is preferably in the range of 1 GΩ / □ to 10 GΩ / □, and the film thickness is preferably 0.1 nm to 2 nm, preferably 0.1 nm to 0.5 nm.

FIG. 5 is a sectional view showing the principal part of a semiconductor device according to the fourth embodiment of the present invention. In this example, the discontinuous thin film 18 is formed instead of the third conductive film 421 of FIG.
The film structure will be described below. After forming the first conductive film 417 which is the first metal, a nitride film 420 (n-type Si ⁺ nitride film having n-type conductivity) with a high silicon composition ratio is formed, and a normal film is further formed. A passivation film 419, which is a nitride film (insulating nitride film), is formed, contact holes are formed in the first conductive film 417 formed on the source electrode 612, and a discontinuous thin film 18 is formed on the passivation film 419. Then, a sealing resin layer 620 is formed thereon with a mold resin or the like. This case has the same effect as the case where the discontinuous thin film is connected to only one of the above-described embodiments. The material of the discontinuous thin film 18 is carbon, tungsten, platinum, SiC, or the like.

In the figure, 416 is an interlayer insulating film, 418 is a second conductive film, 601 is a p substrate, 602 is an n ⁺ source region, 603 is a p ⁺ substrate contact region, 604 is an n well region, and 605 is an n ⁺ drain region. 606 is a gate oxide film, 607 is a gate electrode, 612 is a source electrode, and 613 is a drain electrode.
As shown in FIG. 6, the same effect can be obtained by forming the discontinuous thin film 18 instead of the fourth conductive film 521 of FIG. The difference from FIG. 5 is that the n-type Si ⁺ nitride film 420 is a p-type Si ⁺ nitride film 520 having p-type conductivity and connected to the second conductive film 418 formed on the drain electrode 613. This is a point where a discontinuous thin film 18 is formed.

FIG. 7 is a sectional view showing the principal part of the semiconductor device according to the fifth embodiment of the present invention. This is a discontinuous thin film 18 formed between the protective film 14 (714 in FIG. 7) and the resin coating layer 15 (715 in FIG. 7) of Patent Document 4. Further, the interlayer insulating film 25 (725 in FIG. 7) in FIG. 19 is an oxide film, and does not have the FP1 (field plate) in FIG. In this case, the same effect as described above can be obtained.
In the figure, 701 is a high-resistance p-type semiconductor substrate, 702 is a p-type channel region (p-well), 703 is an n ⁺ source region, 704 is a p ⁺ substrate contact, 705 is an n-type drain / drift region, 706 is an n ⁺ drain region, 707 is a gate insulating film, 708 is a thermal oxide film (field oxide film), 709 is a gate electrode layer, 710 is an interlayer insulating film (first interlayer insulating film), and 711 is a source electrode layer. , 712 are drain electrode layers, 715 is a mold resin for the envelope, FP2 is a field plate, and FP3 is a field plate.

FIG. 8 is a cross-sectional view of the principal part of the semiconductor device according to the sixth embodiment of the present invention. This is because the FP2 (FP2 in FIG. 8) and FP3 (FP3 in FIG. 8) of FIG. 19 of Patent Document 4 are formed of the discontinuous thin film 18, and the protective film 14 (714 in FIG. 8) of FIG. A discontinuous thin film 18 is formed between the covering layers 15 (715 in FIG. 8). Since the discontinuous thin film 18 is formed in two places, the effect is greater than in the fifth embodiment.
In the first to sixth embodiments, the case of a horizontal element has been described as an example. However, although not shown, the breakdown voltage structure of the vertical element (on the guard ring or on the passivation film on the field plate). Even when the discontinuous thin film 18 is applied to the above, the same effect as in the case of the lateral element can be obtained.

Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. Schematic diagram showing changes in leakage current over time Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. Sectional drawing of the principal part of the semiconductor device of 4th Example of this invention. Sectional drawing of the principal part of another semiconductor device of 4th Example of this invention Sectional drawing of the principal part of the semiconductor device of 5th Example of this invention Sectional drawing of the principal part of the semiconductor device of 6th Example of this invention Sectional view of the main part of a conventional trench lateral power MOSFET

Explanation of symbols

1 p-type semiconductor substrate 2 trench 2a insulator 3 n offset drain region 4 p well region 5 p base region 6 n well region 7 n ⁺ source region 8 n ⁺ drain region 9 n offset drain region 10 gate electrode 11, 14 interlayer insulation Film 12 source electrode 13 drain electrode 15 carbon discontinuous thin film 16 sealing resin layer 17 tungsten discontinuous thin film 18 discontinuous thin film 416 interlayer insulating film 418 second conductive film 419 passivation film 420 nitride film 601 p substrate 602 n ⁺ source region 603 p ⁺ substrate contact region 604 n well region 605 n ⁺ drain region 606 gate oxide film 607 gate electrode 612 source electrode 613 drain electrode 701 high resistance p type semiconductor substrate 702 p type channel region (p well)
703 n ⁺ source region 704 p ⁺ substrate contact 705 n-type drain / drift region 706 n ⁺ drain region 707 gate insulating film 708 thermal oxide film (field oxide film)
709 Gate electrode layer 710 Interlayer insulating film (first interlayer insulating film)
711 Source electrode layer 712 Drain electrode layer 715 Mold resin for envelope 714 Protective film 715 Resin coating layer 725 Interlayer insulating film (second interlayer insulating film)
FP2 FP3 Field plate

Claims (10)

In the semiconductor device provided with the protective film , the equivalent sheet resistance value of 1 × 10 ⁹ Ω / □ to 1 × 10 ¹⁰ Ω / □ is any of metal, semiconductor, and carbon on the protective film. A semiconductor device characterized by forming a discontinuous thin film. In a semiconductor device including a protective film and a resin coating layer formed on the protective film , any of metal, semiconductor, and carbon is equivalent between the protective film and the resin coating layer. A semiconductor device , wherein a discontinuous thin film having a sheet resistance value of 1 × 10 ⁹ Ω / □ to 1 × 10 ¹⁰ Ω / □ is formed. Formed on one surface layer of the semiconductor substrate and formed on the surface of the semiconductor substrate between the first and second semiconductor regions and the first and second semiconductor regions through which a main current flows. An insulating film, a protective film formed on the first and second semiconductor regions and the insulating film, and one of metal, semiconductor, and carbon formed on the protective film , and equivalent A semiconductor device comprising: a resin coating layer coated with a discontinuous thin film having a sheet resistance value of 1 × 10 ⁹ Ω / □ to 1 × 10 ¹⁰ Ω / □ . A trench formed inside from the surface of the first conductivity type semiconductor layer, a first region of the second conductivity type formed along the trench, and in contact with the first region, facing each other across the trench A first conductivity type second region and a second conductivity type third region, a first conductivity type fourth region in contact with the first region on the surface layer of the second region, and the fourth region A fifth region of the second conductivity type on the surface layer of the region, a sixth region of the second conductivity type formed in the surface layer of the third region, a first insulating film filling the trench, and the fifth A gate insulating film formed over the fourth region and the second region sandwiched between the region and the second region, and over a part of the gate insulating film and the first insulating film A gate electrode formed; a second insulating film formed on the gate electrode and the first insulating film; the fourth region; A first main electrode in contact with the region and extending on the second insulating film; a second main electrode in contact with the sixth region and extending on the second insulating film; and on the first main electrode; In a semiconductor device comprising: a third insulating film formed over the second insulating film and the second main electrode; and a resin coating layer formed on the third insulating film.
Between the third insulating film and the resin coating layer, any of metal, semiconductor, and carbon is used, and an equivalent sheet resistance value is 1 × 10 ⁹ Ω / □ to 1 × 10 ¹⁰ Ω / □. A semiconductor device characterized by forming a discontinuous thin film. Formed on the surface layer of the first conductivity type semiconductor layer and formed on the surface layer of the second region and the second region of the first conductivity type and the second region of the second conductivity type formed opposite to each other. A fourth region of the first conductivity type, a fifth region of the second conductivity type in the surface layer of the fourth region, a sixth region of the second conductivity type formed in the surface layer of the third region, A gate insulating film formed on the fourth region sandwiched between the fifth region and the second region, a gate electrode formed on the gate insulating film, and formed on the gate electrode and the semiconductor layer A first main electrode extending on the second insulating film, in contact with the fourth region, on the second insulating film, and on the second insulating film. A second main electrode extending, a third insulating film formed over the first main electrode, the second insulating film, and the second main electrode; A resin coating layer formed on the insulating film, a semiconductor device equipped with,
Between the third insulating film and the resin coating layer, any of metal, semiconductor, and carbon is used, and an equivalent sheet resistance value is 1 × 10 ⁹ Ω / □ to 1 × 10 ¹⁰ Ω / □. A semiconductor device characterized by forming a discontinuous thin film. The semiconductor device according to claim 4, wherein the discontinuous thin film is not connected to any of the first main electrode and the second main electrode. The semiconductor device according to claim 4, wherein the discontinuous thin film is connected to at least one of the first main electrode and the second main electrode. The semiconductor device according to claim 1, wherein the metal is tungsten or platinum . The semiconductor device according to claim 1, wherein the discontinuous thin film has a thickness of 0.1 nm to 2 nm . The semiconductor device according to claim 9, wherein the discontinuous thin film has a thickness of 0.1 nm to 0.5 nm .