JP4896047B2 - High frequency detector - Google Patents

Description

  The present invention relates to a high frequency detection device that is provided in a control loop for controlling high frequency power and detects a high frequency signal.

  In a high frequency power supply device, for example, a traveling wave power (high frequency signal) taken out by a directional coupler provided at the output end thereof is input to a detection circuit using a diode through an attenuator, whereby a high frequency signal is converted into a direct current signal. After the DC signal is amplified by the DC amplifier circuit, a DC detection signal corresponding to the high frequency output of the power supply device is obtained through the buffer circuit. A high-frequency detection device that detects a high-frequency signal through a detection circuit is disclosed in Patent Document 1, for example. In a detection circuit using a diode, in order to increase detection sensitivity, a bias voltage corresponding to a forward voltage (for example, 0.5 V) when current starts to flow through the diode is applied to the diode.

  In this type of detection device, the detection output varies depending on the temperature characteristics of the detection diode that constitutes the detection circuit. In particular, when detecting a small signal, the voltage drop of the diode is larger than the detection voltage, and the fluctuation due to the temperature change of the diode voltage drop is larger than the change of the detection voltage due to the change of the high-frequency signal. Therefore, the detection error is significantly reduced.

Therefore, as shown in Patent Document 2, a temperature compensation diode having the same temperature characteristics as the detection diode is provided in the same temperature environment as the detection diode, and the temperature compensation diode is energized to detect the temperature. This causes a voltage drop with the same temperature gradient as the diode, and the voltage drop of the temperature compensation diode is applied as a reverse bias voltage to the detector diode, thereby canceling the fluctuation in the detected voltage due to the temperature change. Temperature compensation is performed.
JP 9-33111 A JP-A 64-10704

  Since the detection circuit and DC amplification circuit constituting the high-frequency detection device are configured using semiconductor elements, an offset voltage component is generated at each stage, and the magnitude varies with temperature due to variations in the temperature characteristics of the elements. A drift voltage component is generated. Therefore, when each stage of the detection circuit is configured using semiconductor elements, the offset voltage and the drift voltage are superimposed on the output side of each stage even when no input signal is given to the detection circuit. DC voltage component appears. The output signal of each stage of the detection circuit is a DC signal, and since the circuit from the detection circuit to the output terminal of the DC amplifier circuit is DC-connected, it is generated at each stage of the detection circuit at the output terminal of the detection circuit. The offset voltage component and the drift voltage component are output in the form of addition, and these voltage components cause an error in the detection output. As described above, since the offset voltage component and the drift voltage component cause an error in the detection output, in this specification, a component in which the drift voltage component is superimposed on the offset voltage component is referred to as an “error component”. To.

  The error component is independent of the level of the input signal and is generated due to the characteristics of the elements that make up the circuit. Therefore, the effect of the error component on the detection output is when the level of the input high-frequency signal is low. It becomes more noticeable. For example, assuming that the error signal generated in the detection circuit is 5 W, the error rate is 0.1% when the power of the input high-frequency signal is 5000 W, but the error rate when the input high-frequency signal is 50 W. Will reach 10%, and the detection accuracy will be greatly reduced. In order to increase the detection accuracy of the high frequency signal, it is necessary to reduce the influence of the error component as much as possible.

  As described above, Patent Document 2 discloses a temperature compensation circuit in which a temperature compensation diode having the same temperature characteristics as that of the detection diode is provided, and the detection diode is reverse-biased by a voltage drop generated in the temperature compensation diode. It is described that temperature compensation of the potential at the detection point is performed by providing.

  However, the diode input voltage vs. the detection output characteristic has non-linearity inherent to the diode, and in addition, the detection output characteristic itself has a characteristic that changes with temperature. It is difficult to remove the components, and even when the above temperature compensation is performed, an error due to the non-linearity of the output characteristics and an error due to the change in the output level due to the temperature change appear in the high frequency detection output. . In particular, when performing detection in a wide range from a small signal level to a large signal level, an error due to nonlinearity of the input voltage versus the detection output characteristic of the diode and an error due to a change in temperature appear remarkably. Therefore, when the dynamic range of the signal level to be detected is wide and accurate linearity is required for detection, the method using the temperature compensation circuit as described above is not suitable, and linearity correction according to the detection level is not appropriate. And temperature correction.

  There is also known a method of canceling the error component by predicting the error component generated in the detection circuit and subtracting the predicted error component (fixed value) from the detection output, but it is difficult to accurately predict the error component. In addition, due to variations in element characteristics, the error components that occur also vary, especially when the circuit state is unstable, such as during the transition period from when the power is turned on until the circuit temperature stabilizes. In this case, since the error component changes from moment to moment, if the error component subtracted from the detection output is a fixed value, the error component cannot be canceled accurately. Therefore, this method also has a limit in improving detection accuracy.

  In the above description, the high-frequency detection device that is provided in the control loop of the high-frequency power supply device and detects a high-frequency signal through the detection circuit including the detection circuit and the DC amplification circuit is taken as an example. In a high-frequency detection device that detects a high-frequency signal through a detection circuit using a semiconductor element in which characteristics are inevitably changed with a change in temperature, the error component due to the change in temperature should be removed. Is difficult and causes the same problems as described above.

  An object of the present invention is to provide a high-frequency detection apparatus capable of accurately canceling error components and improving detection accuracy even when the operation of a circuit is unstable.

  The present invention relates to a high-frequency detection device that detects a high-frequency signal through a detection circuit having a characteristic in which an error component included in an output changes with temperature. In the present invention, the error component is provided on the input side of the detection circuit and is turned on. A switch that allows a high-frequency signal to be input to the detection circuit when the switch is in the off-state, stops the input of the high-frequency signal to the detection circuit when the switch is in the off-state, switch control means that turns the switch on and off, A signal with the same magnitude as the output signal of the detection circuit is output for a certain period, and a signal with the same magnitude as the output signal of the detection circuit immediately before the switch is turned off is output for a period when the switch is in the OFF state. The first sample-and-hold means to hold and outputs a signal having the same magnitude as the output signal of the detection circuit during the period when the switch is in the OFF state. A second sample-and-hold means for holding a state of outputting a signal having the same magnitude as the output of the detection circuit immediately before the switch is turned on, There is provided correction calculation means for performing correction calculation for subtracting the output magnitude of the second sample-and-hold means from the output magnitude and outputting the calculation result as a detection signal.

  The first sample-and-hold means can be constituted by a sample-and-hold circuit that performs a sample operation for sampling the output of the period detection circuit while the switch is in an on state and performs a hold operation during a period when the switch is in an off state. The second sample-and-hold means can be constituted by a sample-and-hold circuit that performs a sample operation for sampling the output of the period detection circuit while the switch is in the off state and performs a hold operation during the period when the switch is in the on state.

  As described above, when a switch is provided on the input side of the detection circuit and the switch is turned on and off, a signal of the sum of the detection signal and the error component corresponding to the input high-frequency signal is output during the period in which the switch is on. Is output from the detection circuit, but only the error component generated in the detection circuit is output from the detection circuit during the period when the switch is in the OFF state. Therefore, the signal output from the first sample-and-hold means when the switch is in the on state has a magnitude equal to the sum of the magnitude of the signal corresponding to the high-frequency signal input to the detection circuit and the magnitude of the error component. The signal output from the first sample-and-hold means when the switch is in the OFF state is a signal magnitude and error corresponding to the high-frequency signal input to the detection circuit immediately before the switch is in the OFF state. It is a signal having a magnitude equal to the sum of the magnitudes of the components. The signal output from the second sample-and-hold means when the switch is in the OFF state is a signal having the magnitude of the error component generated in the detection circuit, and the second signal is output when the switch is in the ON state. The signal output by the sample and hold means is a signal having the magnitude of the error component immediately before the switch is turned on.

  Therefore, the error component itself actually generated in the detection circuit can be detected from the output of the second sample and hold means, and the detected error component is subtracted from the output of the first sample and hold means. By performing the correction calculation, it is possible to accurately cancel the error component and improve the detection accuracy. In particular, in the present invention, since the error component actually generated in the detection circuit is detected and the calculation for canceling the error component is performed, the operation of the circuit is unstable and the error component changes. Even at a certain time, it is possible to accurately perform the calculation for removing the error component, thereby improving the detection accuracy.

  Since the high frequency signal is not input to the detection circuit during the switch off state, the detection circuit does not output a detection signal corresponding to the actual high frequency signal. However, when the switch is in the off state, the first sample and hold is performed. A signal having a magnitude obtained by subtracting the error component from the magnitude of the output signal of the first sample-and-hold means is outputted from the means. Is output through the correction calculation means, so that the detection output of the high-frequency signal can be obtained without interruption throughout the entire period.

  In the present invention, an actual high-frequency signal is not detected while the switch is in the OFF state. However, if the period during which the switch is in the OFF state is set sufficiently short, this adversely affects the detection accuracy. There is no effect.

  When an analog arithmetic circuit is used as the correction arithmetic means, an error component is also generated in this arithmetic circuit. In many high-frequency detection devices, a high-frequency signal is detected through a detection circuit having a characteristic that an error component included in the output varies with temperature, and the detection output is output through a buffer circuit. When the buffer circuit is provided in the output stage as described above, an error component is also generated in the buffer circuit. In order to increase the detection accuracy, it is preferable to cancel error components generated in the arithmetic circuit and the buffer circuit as much as possible.

  As described above, when the present invention is applied to a high-frequency detection device configured to output a detection signal of a high-frequency signal through a buffer circuit, the detection is performed when the detection circuit is on and provided on the input side of the detection circuit. A switch that enables high-frequency signal input to the circuit and stops input of the high-frequency signal to the detection circuit when it is in an off state, a switch control means that turns this switch on and off, and a period during which the switch is on is detected A signal having the same magnitude as the output signal of the circuit is output, and during the period when the switch is in the OFF state, a state in which a signal having the same magnitude as the output signal of the detection circuit immediately before the switch is turned OFF is maintained. 1 sample and hold means, and during the period when the switch is in the OFF state, outputs a signal having the same magnitude as the output signal of the detection circuit, and the switch is in the ON state The second sample-and-hold means for holding a state of outputting a signal having the same magnitude as the output of the detection circuit immediately before the switch is turned on, and the magnitude of the output of the first sample-and-hold means And an arithmetic circuit that outputs a signal having the calculated magnitude as a detection signal by performing a correction calculation that reduces the magnitude of the output of the sample-and-hold means. A correction means for correcting the magnitude of the detection signal output from the arithmetic circuit by at least the correction value set to a value corresponding to the offset component is provided, and the detection signal whose magnitude is corrected by the correction value is provided in the buffer circuit. input. In this case, the correction value is set as a fixed value in advance.

  With the configuration described above, it is possible to correct error components generated in the arithmetic circuit and the buffer circuit, so that the detection accuracy can be further improved.

  As described above, when the present invention is applied to a high-frequency detection device configured to output a detection signal of a high-frequency signal through a buffer circuit, the arithmetic circuit outputs the output of the first sample and hold means and the second sample. Using the output of the hold-and-hold means as an input, an operation for subtracting the output of the second sample-and-hold means from the output size of the first sample-and-hold means, and the magnitude obtained by this calculation , And an operation for correcting only a correction value (fixed value) set to a value corresponding to at least the offset component of the error component generated in the arithmetic circuit and the buffer circuit, and a signal having the calculated magnitude is detected. You may comprise so that it may give to a buffer circuit as a signal. As described above, when the correction for the correction value set to a value corresponding to at least the offset component of the error component generated in the arithmetic circuit and the buffer circuit is performed in the arithmetic circuit, the correction means is Can be omitted.

  Further, instead of configuring as described above, an arithmetic circuit is configured to input the output of the first sample and hold means, the output of the second sample and hold means, and a preset correction value, The arithmetic circuit subtracts the output of the second sample-and-hold means from the output of the first sample-and-hold means, and corrects the magnitude obtained by this calculation by the correction value. The signal having the calculated magnitude may be provided to the buffer circuit as a detection signal. In this case, the correction value is set to a value corresponding to at least an offset component of error components generated in the arithmetic circuit and the buffer circuit. As described above, when the correction value is applied to the arithmetic circuit from the outside, the correction value corresponding to the error component generated in the arithmetic circuit and in the buffer circuit can be easily changed.

  If the switch is turned off for a sufficiently short period, turning on and off the switch will hardly cause a decrease in detection accuracy, but turning on and off the switch unnecessarily will not detect the actual high-frequency signal. Creating a period is not desirable. Therefore, the switch control means turns on and off the switch in a short period during the transition period until the detection circuit settles in the steady state, and after the detection circuit enters the steady state, makes the period for turning on and off the switch longer than the transient period. It is preferable to configure as described above.

  Generally, it takes time for the temperature of the detection circuit to stabilize and the circuit to reach a steady state after the device is turned on. During the transition period until the circuit reaches a steady state, the error component generated in the detection circuit fluctuates finely. Therefore, it is preferable to correct the error component at a relatively high frequency. Therefore, it is preferable that the switch is turned on / off in a short period for a fixed time after the power is turned on, and the switch is turned on / off in a long period when the fixed time has elapsed after the power is turned on.

  Also, a means for detecting the temperature of the detection circuit is provided, and when the detected temperature changes, the switch is turned on and off in a short cycle to correct the error component at a high frequency, and the detected temperature is almost constant. It may be configured to switch the cycle of turning on and off the switch to a long cycle when the value is displayed.

  When the detection circuit is provided in a control loop that controls high-frequency power or the like, it is preferable to set the period during which the switch is turned off to be shorter than the time constant of the control loop.

  In a control device that controls high-frequency power and the like, the detection circuit includes a detection circuit that receives a high-frequency signal directly or through an attenuator and detects the input high-frequency signal, and a DC amplification that amplifies the output of the detection circuit Circuit. As described above, the present invention is useful when a detection circuit is configured by a detection circuit that detects a high-frequency signal and a DC amplification circuit that amplifies the output of the detection circuit. However, an error component changes due to a change in temperature. Of course, the present invention can also be applied to a case where a detection circuit having other characteristics having characteristics is used, for example, when the detection circuit is configured by only a DC amplifier circuit.

  As described above, according to the present invention, the switch that switches between the state that enables the input of the high-frequency signal to the detection circuit and the state that stops the input of the high-frequency signal to the detection circuit, and the period during which the switch is on A sample operation for sampling the output of the detection circuit, a first sample and hold means for performing a hold operation while the switch is in an OFF state, and a sample operation for sampling the output of the detection circuit while the switch is in an OFF state The second sample and hold means for performing the hold operation while the switch is in the on state, and a correction operation for subtracting the output of the second sample and hold means from the output of the first sample and hold means, Correction calculation means for outputting as a detection signal, and detection by the second sample and hold means An error component generated in the road is actually detected, and the error component included in the detection signal is canceled by subtracting this error component from the detection signal of the high-frequency signal output from the first sample and hold means. Therefore, even in a transient state where the error component is changing every moment, it is possible to accurately cancel the error component included in the detection output and improve the detection accuracy of the high frequency signal.

  In the present invention, the correction means for correcting the magnitude of the detection signal output from the arithmetic circuit by the correction value set to a value corresponding to at least the offset component of the error component generated in the arithmetic circuit and the buffer circuit is provided. Therefore, it is possible to further improve the detection accuracy by correcting error components generated in the arithmetic circuit and the buffer circuit as much as possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 shows the configuration of a high-frequency detection apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a high-frequency input attenuator to which a high-frequency signal to be detected is input, and 2 denotes a square detection circuit 3. A detection circuit 5 comprising a DC amplification circuit 4 for amplifying the DC output voltage signal of the square detection circuit 5 is a high-speed switch (between the output terminal of the high frequency input attenuator 1 and the input terminal of the square detection circuit 3). A switch that can be turned on and off in a sufficiently short cycle, and in this specification, this switch is also simply referred to as a switch.

  The output of the DC amplifier circuit 4 is input to the analog input terminal 6a of the first sample and hold means 6 and the analog input terminal 7a of the second sample and hold means 7, and the first sample and hold means 6 and the second sample and hold means 6 Output signals obtained at the output terminals 6 c and 7 c of the second sample and hold means 7 are input to the 2-input arithmetic circuit 8. The output of the arithmetic circuit 8 is output as a detection output signal Vs through the buffer circuit 10 after the negative potential given from the potential adding means 9 is added.

In order to control the high-speed switch 5 and the first and second sample and hold means 6 and 7 in synchronization, a control pulse generating means 11 is provided, and a pulse signal Vp0 output from the pulse generating means is supplied to the switch control means 12. Is given to. The clock pulses Vp1 and Vp2 output from the control pulse generating means 11 are input to the clock input terminals 6b and 7b of the first and second sample and hold means 6 and 7, respectively. The control pulse generation means 11 is connected to a control panel (not shown) through the communication means 13, and the frequency (generation period), pulse width, and generation timing of the pulse signals Vp0 to Vp2 according to a command signal given through the communication means 13. And can be adjusted appropriately.

  The high-frequency input attenuator 1 is provided to attenuate the level of the high-frequency signal to a level that does not hinder the input of the high-frequency signal to the detection circuit 2. In this embodiment, the attenuator The input level is attenuated to ¼. The high-speed switch 5 is a switch capable of on / off control that is turned on when a drive signal is applied and turned off when the drive signal disappears. As this switch, a high-speed switch composed of a bipolar transistor, a MOSFET, or the like can be used.

  The switch control means 12 is a means for controlling the high-speed switch 5 to be turned on and off at high speed, and is composed of a circuit for supplying the high-speed switch 5 with a pulse signal Vp0 supplied from the control pulse generation means 11 as a drive signal. The switch control means 12 stops supplying the drive signal to the high-speed switch 5 when the control pulse Vp0 having a narrow width as shown in FIG. Is turned off, and the high speed switch 5 is controlled so that the high speed switch 5 is turned on when the control pulse Vp0 disappears. The pulse width of the control pulse Vp0 is set to the minimum necessary for detecting the error component.

  When the high speed switch 5 is in the on state, the high frequency signal V1 attenuated by the attenuator 1 is input to the square detection circuit 3, and when the high speed switch 5 is in the off state, the high frequency signal to the square detection circuit 3 is input. The input of V1 is stopped.

  The square detection circuit 3 squares the voltage V1 of the input high-frequency signal and outputs a signal having an AC component having a frequency twice the frequency of the high-frequency signal and a DC component proportional to the square of the level of the voltage V1. And a circuit for extracting only a direct current component from the output of this circuit, and outputs a direct current signal proportional to the square of the level of the high frequency signal V1.

  The DC amplifier circuit 4 is a circuit that outputs a signal obtained by amplifying the output of the square detection circuit 3 as an output signal of the detection circuit 2. In the present embodiment, the output of the square detection circuit is amplified by a factor of five. Designed.

  As shown in FIG. 3, the sample and hold means 6 is off while the clock signal is input to the analog input terminal 6a to which the analog input voltage is input, the input side buffer circuit Bfi, and the clock signal input terminal 6b. The sample switch SW that remains on when the clock signal is not input to the clock signal input terminal 6b, and the voltage input to the analog input terminal 6a when the sample switch SW is on is the buffer circuit. The capacitor C is applied through Bfi and the switch SW, and includes a known sample-and-hold circuit including an analog output terminal 6c to which the voltage across the capacitor C is applied via the output side buffer circuit Bfo.

  In this sample and hold circuit, a sample operation is performed when the sample switch SW is in an ON state, and a signal having the same level as the signal input to the analog input terminal 6a is output from the analog output terminal 6c. During the period in which the sample switch is in the OFF state, a hold operation is performed to hold a state in which a signal having the same level as the signal input to the analog input terminal 6a is output from the analog output terminal 6c when the sample switch is in the OFF state. The sample and hold means 7 is configured similarly.

  At the clock signal input terminal 6b of the first sample-and-hold means 6, the sample switch SW is turned off slightly before the high-speed switch 5 is turned off (just before the high-speed switch 5 is turned off). The control pulse Vp1 is applied so that the sample switch is turned on (the sample operation is performed) at a timing slightly delayed from the timing when the high-speed switch 5 is turned on. The first sample and hold means 6 outputs a signal having the same magnitude as the output signal of the period detection circuit 2 (the output signal of the direct current amplifier circuit 4) when the high speed switch 5 is in the on state, and the high speed switch 5 is in the off state. During this period, a state in which a signal having the same magnitude as the output signal of the detection circuit 2 immediately before the high-speed switch 5 is turned off is held.

  Further, the clock signal input terminal 7b of the second sample and hold means 7 has a sample switch at a timing slightly after the timing when the high speed switch 5 is turned off (immediately after the high speed switch 5 is turned off). The control pulse Vp2 is applied so that the SW is turned on and the sample switch is turned off at a timing slightly ahead of the timing when the high speed switch 5 is turned on (just before the high speed switch is turned on). . The second sample and hold means 7 outputs a signal having the same magnitude as the output signal of the period detection circuit in which the high speed switch 5 is in the off state, and the high speed switch 5 is in the on state during the period in which the high speed switch 5 is in the on state. A state in which a signal having the same magnitude as the output of the detection circuit immediately before becomes is held.

  The 2-input arithmetic circuit is composed of an analog subtracting circuit, and performs a correction operation for subtracting the magnitude of the output of the second sample-and-hold means 7 from the magnitude of the output of the first sample-and-hold means 6. A signal having the specified magnitude is output as a detection signal (DC voltage signal). The detection signal output from the arithmetic circuit 8 is a negative correction voltage (voltage corresponding to a correction value set to a value corresponding to an error component generated between the arithmetic circuit 8 and the buffer circuit 10) provided by the potential adding means 9. After being corrected by addition, the signal is input to the buffer circuit 10 and output as a detection signal Vs through the buffer circuit. In the present embodiment, the arithmetic circuit 8 performs a correction operation for subtracting the output level of the second sample and hold means from the output level of the first sample and hold means, and outputs the calculation result as a detection signal. A correction calculation means is configured. A value corresponding to at least an offset component of an error component generated in the arithmetic circuit and the buffer circuit by the potential adding means 9 and a circuit (subtracter in the illustrated example) that adds the output of the potential adding means to the output of the arithmetic circuit 8. The correction means is configured to correct the magnitude of the detection signal output from the arithmetic circuit by the correction value set to.

  In the present embodiment, during the period when the high-speed switch 5 is in the ON state, the sum signal of the detection signal (detection signal corresponding to the high-frequency signal) obtained by square detection of the input high-frequency signal and the error component is Output from the detection circuit 2.

  On the other hand, during the period when the high-speed switch is off, the detection signal obtained by square detection of the high-frequency signal is zero, and only the error component generated in the detection circuit 2 is output from the detection circuit 2. Is done.

  Assuming that the pulse signal Vp0 shown in FIG. 2A is given from the control pulse generating means 11 to the high speed switch 5 through the switch control means 12, the high speed switch 5 has t1 to t2 when the pulse signal Vp0 is generated. Each period of t3 to t4, t5 to t6,... is turned off, and each period of t1, t2 to t3, t4 to t5,. Therefore, as shown in FIG. 2B, a high frequency signal is inputted to the square detection circuit 3 during each period of t1, t2 to t3, t4 to t5,..., T1 to t2, t3 to t4, t5 to No high frequency signal is input to the square detection circuit 3 during each period of t6,.

  FIG. 2C shows the operation of the first sample and hold means 6. Timings t1 ′, t3 ′, t5 ′,... Shown in FIG. 2C are timings slightly advanced from timings t1, t3, t5,... Shown in FIG. ′, T4 ′, t6 ′,... Are timings slightly delayed from the timings t2, t4, t6,... Shown in FIG. The clock signal input terminal 6b of the first sample-and-hold means 6 has a clock signal for each period t1 'to t2', t3 'to t4', t5 'to t6',... Shown in FIG. Vp1 is input, and during these periods, the sample switch is turned off, and the state where the signal H1 having the same magnitude as the output signal of the detection circuit 2 at the timing t1 ', t3', t5 ',. In each period of ~ t1 ', t2'-t3', t4'-t5 ',... In FIG. 2 (C), the sample switch is kept on and a signal having the same magnitude as the output of the detection circuit 2 is output. Output.

  FIG. 2D shows the operation of the second sample and hold means 7. The timings t1 ", t3", t5 ", ... shown in Fig. 2D are timings slightly delayed from the timings t1, t3, t5, ... shown in Fig. 2A. t2 ″, t4 ″, t6 ″,... are timings slightly advanced from timings t2, t4, t6,. A clock signal is input to the clock signal input terminal 7b of the second sample and hold means 7 during the periods of t1 ", t2" to t3 ", t4" to t5 ",... Shown in FIG. During these periods, the sample switch is turned off, and the state in which the signal H2 having the same magnitude as the output signal of the detection circuit 2 at the timings t2 ", t4", t6 ",. During the periods t1 ″ to t2 ″, t3 ″ to t4 ″, t5 ″ to t6 ″,... In FIG. 2D, the sample switch is kept on and has the same magnitude as the output of the detection circuit 2. The signal is output.

  The signal output from the first sample and hold means 6 when the high-speed switch 5 is in the ON state is equal to the sum of the magnitude of the signal corresponding to the high-frequency signal input to the detection circuit 2 and the magnitude of the error component. The signal output by the first sample and hold means 6 when the high-speed switch 5 is in the off state is a high-frequency signal input to the detection circuit 2 immediately before the high-speed switch 5 is in the off state. Is a signal having a magnitude equal to the sum of the magnitude of the signal corresponding to (the signal obtained by amplifying the detection output) and the magnitude of the error component.

  The signal output from the second sample and hold means when the high-speed switch is in the OFF state is a signal having the magnitude of the error component generated in the detection circuit 2, and the high-speed switch 5 is in the ON state. Sometimes the signal output by the second sample and hold means 7 is a signal having the magnitude of the error component immediately before the high-speed switch is turned on. Therefore, the second sample-and-hold means 7 outputs a signal indicating an error component generated in the detection circuit in real time while the high-speed switch 5 is in the off state, and the period during which the high-speed switch 5 is in the on state is A signal indicating an error component generated in the detection circuit when the high-speed switch is turned on is output.

  In the high-frequency detection device shown in FIG. 1, the offset amount generated in the square detection circuit 3 is A, the offset amount generated in the input terminal portion of the DC amplifier circuit 4 is B, and the offset amount generated in the buffer circuit 10 is C. Further, let D be an offset amount generated at the input terminal portion of the 2-input arithmetic circuit 8. The offset amounts A, B, C, and D of each circuit are superimposed with drift components a, b, c, and d, respectively. When the error component is not canceled, these offset amounts and drift components are The superimposed DC voltage component is included in the detection output signal as an error component. Assuming that the output level of the square detection circuit 3 when detecting only the high-frequency input signal component is P, the total generated at the analog output terminal 6c of the first sample and hold means 6 during the period when the high-speed switch 5 is in the ON state. Is (P + A + B + a + b) * 5 (* is a multiplication symbol). On the other hand, the potential of the analog output terminal 7c of the second sample and hold means 7 is (A + B + a + b) * 5.

  The 2-input arithmetic circuit 8 always performs a subtraction operation with an amplification factor of 1 for subtracting the output of the second sample and hold means 7 from the output of the first sample and hold means 6. The output potential of the arithmetic circuit 8 is {(P + A + B + a + b) * 5} − {(A + B + a + b) * 5} + (D + d) = 5P + (D + d). When the output of the arithmetic circuit 8 is directly input to the buffer circuit 10, the potential of the signal output from the buffer circuit (amplification degree 1) is 5P + (D + d) + (C + c). This indicates that the error component (A + B + a + b) * 5 is subtracted from the output signal of the detection circuit 2, and the error component D + d generated in the arithmetic circuit 8 and the error component C + c generated in the buffer circuit 10 remain. When the error component D + d + C + c is small, a signal of 5P + (D + d) + (C + c) may be used as a detection signal. However, when the error component D + d + C + c cannot be ignored, it is preferable to reduce the error component as much as possible. .

  In the present embodiment, potential adding means 9 is provided, and a negative voltage − (D + C) having a correction value corresponding to the sum of the offset component C generated in the buffer circuit 10 and the offset component D generated in the arithmetic circuit 8 is obtained. By adding to the output of the arithmetic circuit 8, the error component is reduced by setting the output of the buffer circuit 10 to 5P + (d + c). The correction value is set in advance as a fixed value based on the actual measurement value.

  The improvement rate of the total error when the potential adding means 9 is not provided is {(D + d) + (C + c)} / {(A + B + a + b) * 5 + (D + d) + (C + c)}, whereas the potential adding means 9 When provided, the error improvement rate is (d + c) / {(A + B + a + b) * 5 + (D + d) + (C + c)}. Thus, by adding a negative voltage having the sum of the offset component C generated in the buffer circuit 10 and the offset component D generated in the arithmetic circuit 8 to the output of the arithmetic circuit 8 (the magnitude of the output of the arithmetic circuit 8). It can be seen that the total error can be greatly improved by subtracting the correction value corresponding to the sum of the offset component C generated in the buffer circuit 10 and the offset component D generated in the arithmetic circuit 8).

  In the detection apparatus of the present embodiment, during the period when the high speed switch 5 is in the OFF state, no high frequency signal is input to the detection circuit 2, so the detection circuit 2 does not output a detection signal corresponding to the actual high frequency signal. When 5 is in the off state, the first sample and hold means 6 outputs a sum signal of the detection signal and the error component immediately before the high speed switch 5 is turned off. Since a signal having a magnitude obtained by subtracting the error component from the magnitude of the output signal 6 is output through the arithmetic circuit 8, a high-frequency signal detection output can be obtained without interruption throughout the entire period.

  The high-frequency detection device according to the present invention is incorporated as one element constituting the control device in a control loop such as a high-frequency power supply device that controls high-frequency power. When the error component actually generated in the detection circuit is detected by creating a period in which the high-frequency signal is not input to the detection circuit with the switch 5 turned off, the switch 5 is in the off state. If the function of holding the detection output of the high-frequency signal is not provided, the detection value cannot be obtained at the moment when the switch 5 is turned off, so that control cannot be performed. In the present invention, the first sample-and-hold means 6 is provided so that the detection output of the high-frequency signal is held even when the switch 5 is in the OFF state. If the period during which the control system is pseudo-controlled by the detection signal is too long, the control system may fall into an uncontrollable state when the magnitude of the high-frequency signal fluctuates greatly during the period during which the pseudo-control is being performed. There is. In order to prevent such a situation from occurring, the period in which the switch 5 is turned off is shortened as much as possible (the pulse width of the control pulse Vp0 is narrowed), and the cycle in which the switch 5 is turned off is shortened. It is necessary to avoid overdoing (avoid turning the switch off frequently). Specifically, it is necessary to make the time for turning off the switch 5 at least shorter than the time constant (first-order lag) of the control loop, and during the period for turning off the switch (pseudo control period). Determine the output fluctuation range of the control target that may occur, and the longer the output fluctuation range, the shorter the switch-off period and the longer the switch-off period. It is. If the high-frequency detection device is not a constituent element of the control loop, the period during which the switch 5 is turned off and the cycle can be appropriately set according to the purpose of use.

  In the above-described embodiment, each unit is configured by an analog circuit. However, among the constituent elements, a part capable of digital processing can be realized using a microprocessor or the like. For example, the function of the sample and hold means 6 and 7 is realized by using a microprocessor, the operation of subtracting the output of the second sample and hold means 7 from the output of the first sample and hold means 6, and a buffer circuit It is possible to cause the microprocessor to perform a correction operation for canceling the offset component generated in step 1, convert the calculation result into an analog signal by a D / A converter, and input the analog signal to the buffer circuit 10.

  Further, as an application example, it is possible to change the cycle of the pulse output from the control pulse generation means 11 according to the state of the detection circuit, and to perform detailed arithmetic processing for removing the error component. In general, when a power supply is turned on, many changes that affect the error components that occur in the detection circuit, such as temperature changes and power supply fluctuations, in the equipment during the transition period from the initial state to the steady state Happens. Similarly, when component parts such as semiconductor elements are viewed individually, initial fluctuations that affect error components generated in the parts also occur during the transition period from the initial state to the steady state. Therefore, during the transition period until the detection circuit shifts to a steady state (in many cases, the temperature is stable), the high speed switch 5 is turned on / off in a short cycle to detect the error component and cancel the error component. After the detection circuit shifts to a steady state, the period for turning on and off the switch 5 is lengthened to detect the error component and calculate the frequency for canceling the error component. It is often effective to keep it low.

  For example, when the power supply is turned on, the error component consisting of the offset and drift components changes from time to time, so that the switch 5 is turned off at a high frequency of about once per second to detect the error component and the error component. Since the calculation for canceling is frequently performed finely and the change of the error component is reduced after the state of the device is stabilized, it is considered that the frequency of setting the switch 5 to the OFF state is about once per minute. It is done.

  As shown in FIG. 1, the communication means 13 is provided, and the frequency (generation period), pulse width, and generation timing of the pulse signals Vp0 to Vp2 are appropriately adjusted according to a command signal given through the communication means 13. If the control pulse generating means 11 is configured so that it can be performed, the error component can be corrected more precisely. For example, when controlling the output of a high-frequency power supply, a signal at the time of starting up the power supply is used as a command signal, and this command signal is given to the control pulse generating means 11 through the communication means 13, and the frequency (generation period), pulse width, The control pulse generation means 11 can be configured to adjust the generation timing as appropriate. In addition, as such a command signal, for example, a power setting signal output from the power supply, a temperature change detection signal in the device, and the like can be used as well as a signal at the time of starting the power supply.

  In the embodiment shown in FIG. 1, the arithmetic circuit 8 (correction arithmetic means) corrects the arithmetic operation by subtracting the output magnitude of the second sample and hold means 7 from the magnitude of the output of the first sample and hold means 6. The magnitude of the corrected signal is further corrected by the potential adding means 9, but the present invention is not limited to this configuration. For example, in the arithmetic circuit 8 to which the output of the first sample-and-hold means 6 and the output of the second sample-and-hold means 7 are input, the second output is calculated from the magnitude of the output of the first sample-and-hold means. The calculation for reducing the output level of the sample and hold means and the magnitude obtained by this calculation are set to a value corresponding to at least the offset component of the error component generated in the calculation circuit 8 and the buffer circuit 10. It is also possible to perform a calculation for correcting only the correction value, and to provide a signal having a calculated magnitude to the buffer circuit as a detection signal.

  In addition, an arithmetic circuit 8 (in this case, a three-input arithmetic operation) inputs the output of the first sample-and-hold means 6, the output of the second sample-and-hold means 7, and a preset correction value. A circuit is used), and an operation for subtracting the output magnitude of the second sample-and-hold means 7 from the magnitude of the output of the first sample-and-hold means 6 is added to the arithmetic circuit. It is also possible to perform a calculation for correcting the calculated magnitude by the correction value, and to provide the buffer circuit 10 with a signal having the calculated magnitude as a detection signal. In this case, the correction value is set to a value corresponding to at least an offset component of error components generated in the arithmetic circuit and the buffer circuit.

  In the above embodiment, the square detection circuit is used as the detection circuit, but the present invention can also be applied to the case where another detection circuit such as a diode detection circuit is used. The present invention can also be applied to a case where the detection circuit is configured to convert a high-frequency signal to be detected into a DC signal without using a detection circuit.

  In the above embodiment, assuming that the high-frequency detection device is provided in a control loop that controls high-frequency power, a high-frequency input is input to the first stage of the detection device in order to prevent an excessive voltage from being applied to the detection circuit. Although the attenuator 1 is provided, the attenuator 1 can be omitted when the level of the high-frequency signal to be detected is low enough that there is no problem with the breakdown voltage of the elements constituting the detection circuit.

FIG. 1 is a block diagram showing the configuration of a high-frequency detection device according to an embodiment of the present invention. (A)-(D) are the waveform diagrams which showed the voltage waveform of each part of FIG. It is the circuit diagram which showed the structural example of the sample and hold means.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High frequency input attenuator 2 Detection circuit 3 Square detection circuit 4 DC amplifier circuit 5 High speed switch 6 1st sample and hold means 7 2nd sample and hold means 8 2 input arithmetic circuit 9 Potential addition means 10 Buffer circuit 11 Control pulse Generation means 12 Switch control means

Claims (7)

In a high-frequency detection device that detects a high-frequency signal through a detection circuit having a characteristic that an error component included in an output varies with temperature,
A switch that is provided on the input side of the detection circuit and enables input of a high-frequency signal to the detection circuit when the detection circuit is in an on state; and a switch that stops input of the high-frequency signal to the detection circuit when the detection circuit is in an off state;
Switch control means for turning on and off the switch;
A signal having the same magnitude as the output signal of the detection circuit is output during a period in which the switch is on, and an output signal from the detection circuit immediately before the switch is in an off state during a period in which the switch is off. First sample and hold means for holding a state of outputting a signal of the same magnitude;
A signal having the same magnitude as the output signal of the detection circuit is output during a period in which the switch is in an off state, and an output of the detection circuit immediately before the switch is in an on state is output during a period in which the switch is in an on state. Second sample and hold means for holding a state of outputting a signal of a magnitude;
Correction calculation means for performing a correction calculation for subtracting the magnitude of the output of the second sample and hold means from the magnitude of the output of the first sample and hold means, and outputting the calculation result as a detection signal;
A high-frequency detection device comprising: In a high-frequency detection device that detects a high-frequency signal through a detection circuit having a characteristic that an error component included in an output varies with temperature, and outputs the detection signal through a buffer circuit,
A switch that is provided on the input side of the detection circuit and enables input of a high-frequency signal to the detection circuit when the detection circuit is in an on state; and a switch that stops input of the high-frequency signal to the detection circuit when the detection circuit is in an off state;
Switch control means for turning on and off the switch;
A signal having the same magnitude as the output signal of the detection circuit is output during a period in which the switch is on, and an output signal from the detection circuit immediately before the switch is in an off state during the period in which the switch is off. First sample and hold means for holding a state of outputting a signal equal in magnitude to
A signal having the same magnitude as the output signal of the detection circuit is output during the period in which the switch is in the off state, and the output from the detection circuit immediately before the switch is in the on state during the period in which the switch is in the on state. Second sample and hold means for holding a state of outputting a signal having the same value;
An arithmetic circuit for performing a correction operation for subtracting the magnitude of the output of the second sample and hold means from the magnitude of the output of the first sample and hold means and outputting a signal having a computed magnitude as a detection signal When,
Correction means for correcting the magnitude of the detection signal output by the arithmetic circuit by a correction value set to a value corresponding to at least an offset component of error components generated in the arithmetic circuit and the buffer circuit;
Comprising
A high-frequency detection device in which the detection signal whose size is corrected by the correction value is input to the buffer circuit. In a high-frequency detection device that detects a high-frequency signal through a detection circuit having a characteristic that an error component included in an output varies with temperature, and outputs the detection signal through a buffer circuit,
A switch that is provided on the input side of the detection circuit and enables input of a high-frequency signal to the detection circuit when the detection circuit is in an on state; and a switch that stops input of the high-frequency signal to the detection circuit when the detection circuit is in an off state;
Switch control means for turning on and off the switch;
A signal having the same magnitude as the output signal of the detection circuit is output during a period in which the switch is on, and an output signal from the detection circuit immediately before the switch is in an off state during the period in which the switch is off. First sample and hold means for holding a state of outputting a signal equal in magnitude to
A signal having the same magnitude as the output signal of the detection circuit is output during the period in which the switch is in the off state, and the output from the detection circuit immediately before the switch is in the on state during the period in which the switch is in the on state. Second sample and hold means for holding a state of outputting a signal having the same value;
An arithmetic circuit to which the output of the first sample and hold means and the output of the second sample and hold means are input;
Comprising
The arithmetic circuit subtracts the magnitude of the output of the second sample-and-hold means from the magnitude of the output of the first sample-and-hold means, and calculates the magnitude obtained by this calculation. The buffer circuit performs a calculation for correcting a correction value set to a value corresponding to at least an offset component of an error component generated in the circuit and the buffer circuit, and uses the signal having the calculated size as a detection signal. That is configured to give to
A high-frequency detector characterized by. In a high-frequency detection device that detects a high-frequency signal through a detection circuit having a characteristic that an error component included in an output varies with temperature, and outputs the detection signal through a buffer circuit,
A switch that is provided on the input side of the detection circuit and enables input of a high-frequency signal to the detection circuit when the detection circuit is in an on state; and a switch that stops input of the high-frequency signal to the detection circuit when the detection circuit is in an off state;
Switch control means for turning on and off the switch;
A signal having the same magnitude as the output signal of the detection circuit is output during a period in which the switch is on, and an output signal from the detection circuit immediately before the switch is in an off state during the period in which the switch is off. First sample and hold means for holding a state of outputting a signal equal in magnitude to
A signal having the same magnitude as the output signal of the detection circuit is output during the period in which the switch is in the off state, and the output from the detection circuit immediately before the switch is in the on state during the period in which the switch is in the on state. Second sample and hold means for holding a state of outputting a signal having the same value;
Using the output of the first sample and hold means, the output of the second sample and hold means, and a preset correction value as inputs, the second output is calculated based on the output of the first sample and hold means. An operation for reducing the magnitude of the output of the sample and hold means and an operation for correcting the magnitude obtained by this calculation by the correction value are performed, and a signal having the calculated magnitude is used as a detection signal. An arithmetic circuit applied to the buffer circuit;
Comprising
The correction value is set to a value corresponding to at least an offset component of an error component generated in the arithmetic circuit and the buffer circuit;
A high-frequency detector characterized by. The switch control means sets a cycle for turning on / off the switch shorter than a cycle for turning on / off the switch when the detection circuit is in a steady state during a transition period until the detection circuit settles in a steady state. The high-frequency detection device according to claim 1, configured as described above. The detection circuit is provided in a control loop that controls high-frequency power,
6. The high-frequency detection device according to claim 1, wherein a period during which the switch is turned off is set to be shorter than a time constant of the control loop.   7. The detection circuit includes a detection circuit that receives a high-frequency signal directly or through an attenuator and detects the input high-frequency signal, and a DC amplification circuit that amplifies the output of the detection circuit. The high frequency detection apparatus as described in any one of.

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