JP4895396B2 - Image decoding apparatus and image decoding method - Google Patents

Description

  The present invention relates to an image decoding apparatus and an image decoding method, and more particularly to a technique suitable for use in decoding a binary arithmetic coded video stream.

  In recent years, in digital signal processing, with the advancement of high integration of LSI and high processing speed, a large amount of digital information such as moving images, still images and voices can be encoded with high efficiency and recorded on a recording medium. It has become possible to perform recording and transmission using a communication medium. Digital high-definition broadcasting and terrestrial digital broadcasting have been started by applying such technology. In addition, digital video cameras and the like have been improved in performance, and image quality has been improved.

  Incidentally, in recent years, H.264 has been established by the International Telecommunications Union (ITU-T) as a standard for image coding. H.264 / AVC is drawing attention. H. H.264 realizes higher-efficiency encoding than MPEG, which is a conventional video encoding standard. H. There are various reasons why H.264 achieves high-efficiency encoding, one of which is due to entropy encoding.

  In particular, H.264 is a method for realizing highly efficient entropy coding. In H.264, CABAC (Context-based Adaptive Binary Arithmetic Coding) can be used as an entropy encoding method. In CABAC, entropy coding is performed using arithmetic coding. At the time of decoding, arithmetic decoding is performed to decode the video stream.

FIG. 4 shows a block diagram of a configuration example of a conventional image decoding apparatus.
As shown in FIG. 4, the conventional image decoding apparatus 400 includes a CABAC decoding unit 401, a storage unit 404, and an image decoding unit 405. The CABAC decoding unit 401 includes an arithmetic decoding unit 402 and a binary decoding unit 403.

  The arithmetic decoding unit 402 performs a binary arithmetic decoding process on the binary arithmetic encoded video stream D40 to generate and output binary data D41. The binary decoding unit 403 decodes the binary data D41 output from the arithmetic decoding unit 402. This decoding is performed according to Syntax described in “ITU-T Recommendation H.264”. Then, a CABAC decoding result D42 such as motion vector information, transform coefficient value, reference picture index, and prediction mode information is output.

  The storage unit 404 has a small-capacity temporary storage memory, and buffers the CABAC decoding result D42. The image decoding unit 405 includes an unquantized inverse quantization unit, an inverse orthogonal transform unit, and the like. The image decoding unit 405 performs various decoding processes on the CABAC decoding result D43 stored in the storage unit 404 and performs video decoding. A stream D44 is generated and output.

  Note that a CABAC decoding apparatus including a single decoding circuit is also disclosed in Patent Document 1, for example.

JP 2007-074648 A

  H. In H.264, high-efficiency encoding can be realized, but the processing time is longer than that of the conventional encoding method. Therefore, in the conventional image decoding device 400 described above, the processing time is not enough when decoding a high-definition image (hereinafter, HD image: High Definition). Therefore, it is conceivable to shorten the processing time by installing a plurality of image decoding apparatuses 400 side by side and performing parallel processing.

  However, in arithmetic code or arithmetic decoding used in CABAC, in order to make the entire encoding target one codeword, a binary arithmetically encoded video stream is divided into, for example, macroblocks, and each macroblock is divided. It cannot be decrypted in parallel processing. That is, since the current macroblock is encoded and decoded using past encoding and decoding results, there is a problem that the encoding and decoding processes must be performed in order.

  From this CABAC characteristic, it is the image decoding unit 405 after the CABAC process that can perform parallel processing. However, it is possible to parallelize the image decoding apparatus 400 in units of slices for which CABAC performs initialization processing.

  Considering this, the motion vector information, transform coefficient value, reference picture index, prediction mode information, and the like output from the CABAC decoding unit 401 are stored in the storage unit 404, and image decoding is performed subsequent to the CABAC decoding unit 401. A plurality of the parts 405 are arranged. By configuring in this way and processing the CABAC decoding result D43 in parallel, the processing time can be reduced, so that an image decoding device capable of processing HD images in a short time can be realized. .

  However, it has been practically difficult to configure an image decoding apparatus that performs parallel processing by performing parallel processing as described above. This is because it is necessary to store information such as motion vector information, transform coefficient values, reference picture indexes, and prediction mode information, which are output results of the CABAC decoding unit 401. However, storing these pieces of information greatly increases the capacity of the temporary storage memory provided in the storage unit 404 and increases the circuit scale.

  The present invention has been made in view of the above-described problems, and it is an object of the present invention to make it possible to parallelize the subsequent circuit of the CABAC decoding unit without significantly increasing the capacity of the temporary storage memory.

An image decoding apparatus according to the present invention is an image decoding apparatus that decodes a binary arithmetically encoded video stream, wherein arithmetic decoding means for arithmetic decoding the video stream, and arithmetic decoding means in the arithmetic decoding means Storage means for storing the decoded binary data; binary decoding of the binary data arithmetically decoded by the arithmetic decoding means; and the position where the binary data was stored in the storage means; Address calculating means for calculating address data relating to the image position after the binary data is decoded, reading means for reading the binary data stored in the storage means, and N (where N is 2 or more has a natural number) number of binary decoder, the binary data read out by said reading means on the basis of the address data, each of said N binary decoding section share And binary decoding means for performing binary decoding processing.

The image decoding method of the present invention is an image decoding method for decoding a binary arithmetically encoded video stream, comprising: an arithmetic decoding step for arithmetically decoding the video stream; and an arithmetic operation in the arithmetic decoding step. A storage step of storing the decoded binary data in the storage means, and binary decoding of the binary data arithmetically decoded in the arithmetic decoding step, and the binary data was stored in the storage means position, and the address calculation step of calculating the address data relating the image position after the binary data is decoded, and reading the read process the binary data stored in the storage means, N (provided that , N is a natural number greater than or equal to 2) binary decoding units, and the binary data read in the reading step is converted into each of the N binary decoding units based on the address data. Les is characterized by having a binary decoding step of treating binary decoding by sharing.

The program of the present invention is a program for causing a computer to execute a step of decoding a binary arithmetically encoded video stream, wherein the arithmetic decoding step of arithmetically decoding the video stream, and the arithmetic decoding step A storage step of storing the decoded binary data in the storage means, and binary decoding of the binary data arithmetically decoded in the arithmetic decoding step, and the binary data was stored in the storage means position, and the address calculation step of calculating the address data relating the image position after the binary data is decoded, and reading the read process the binary data stored in the storage means, N (provided that , N is a natural number greater than or equal to 2) binary decoding units, and the binary data read in the reading step is based on the address data. Each of the binary decoding units is configured to cause a computer to execute a binary decoding process in which binary decoding is performed in a shared manner.

  According to the present invention, it is possible to reduce the capacity of a storage unit for buffering arithmetic decoding results, and to realize an image decoding apparatus having the ability to process HD images by parallelization with a smaller circuit scale. .

(First embodiment)
FIG. 1 is a block diagram illustrating an exemplary configuration of an image decoding apparatus according to an embodiment of the present invention.
As shown in FIG. 1, the image decoding apparatus 100 according to the present embodiment includes an arithmetic decoding unit 101, an address calculation unit 102, a storage unit 103, a first binary decoding unit 104, and a second binary decoding. And a control unit 107.

  The arithmetic decoding unit 101 performs an arithmetic decoding process on the binary arithmetically encoded video stream D10, and outputs binary data D11 and binary data D12. The arithmetic decoding procedure uses a binary arithmetic decoding process described in 9.3.3.2 Arithmetic decoding process of “ITU-T Recommendation H.264”. The storage unit 103 sequentially stores and stores the binary data D11 output from the arithmetic decoding unit 101.

  The address calculation unit 102 performs a binary decoding process on the binary data D12 output from the arithmetic decoding unit 101, and calculates an address at which the binary data D11 indicating a predetermined image position is written in the storage unit 103. . The address indicating the predetermined image position cannot be specified from the binary data D11 that is the binary arithmetic decoding result. Therefore, the address calculation unit 102 performs binary decoding processing to calculate address data for specifying an address indicating a predetermined image position in units of a predetermined number of blocks.

  As described above, the address calculation unit 102 calculates two types of addresses D13 and D14 in which binary data indicating a predetermined image position is stored. Then, the first address D13 is output to the first binary decoding unit 104, and the second address D14 is output to the second binary decoding unit 105.

  The reading unit 106 reads the first binary data D15 and the second binary data D16 stored in the storage unit 103, and outputs the first binary data D15 to the first binary decoding unit 104. The second binary data D16 is output to the second binary decoding unit 105.

  The first binary decoding unit 104 reads the first binary data D15 input from the reading unit 106 using the first address D13 input from the address calculation unit 102. Further, the second binary decoding unit 105 reads the second binary data D16 input from the reading unit 106 using the second address D14 input from the address calculation unit 102.

  The first binary decoding unit 104 performs binary decoding processing on the input first binary data D15, decodes motion vector information, transform coefficient values, reference picture index, prediction mode information, and the like. A binary arithmetic decoding result D17 is generated and output to a subsequent inverse quantization unit (not shown).

  The second binary decoding unit 105 performs a binary decoding process on the input second binary data D16. Then, the motion vector information, the transform coefficient value, the reference picture index, the prediction mode information, and the like are decoded, and a binary arithmetic decoding result D18 is generated and output to a subsequent dequantization unit (not shown). In this embodiment, an example is shown in which two binary decoding units 104 and 105 are provided. However, N (N is a natural number of 2 or more) binary decoding units are provided. Can do.

  The control unit 107 includes a CPU, ROM, RAM, and the like (not shown). Then, the operations of the arithmetic decoding unit 101, the address calculation unit 102, the storage unit 103, the first binary decoding unit 104, the second binary decoding unit 105, and the reading unit 106 described above are controlled and input. The binary arithmetically encoded video stream D10 is subjected to binary arithmetic decoding processing.

  With this configuration, in the image decoding apparatus 100 of the present embodiment, the first binary decoding unit 104 and the second binary decoding unit 105 are arranged in parallel for each predetermined image position. It becomes possible to operate.

Next, an operation example of the image decoding apparatus 100 according to the present embodiment will be described with reference to FIGS. 2 and 3.
FIG. 2 shows an image of the storage unit 103. FIG. 3 shows a video image obtained when a binary arithmetically encoded video stream is decoded.

  In FIG. 2, 201, 202, and 203 indicate binary data output from the arithmetic decoding unit 101 and stored in the storage unit 200. An image 300 shown in FIG. 3 is an image obtained by dividing the image into macro blocks each of 16 × 16 pixels (16 pixels each in length and width) and shown in a matrix. The macroblock unit may be composed of a predetermined number of pixels. In FIG. 3, 301, 303, and 305 are macro blocks at the left end of the image 300. Reference numerals 302, 304, and 306 denote macro blocks at the right end of the image 300. Therefore, the macro blocks 301 to 302, 303 to 304, and 305 to 306 correspond to the screen width of the image 300 in the horizontal direction.

  A grid-like region 201 in FIG. 2 is binary data that is generated by binary arithmetic decoding processing up to the macroblock 302 after decoding the image 300 from the first macroblock 301 and stored in the storage unit 200. A next hatched area 202 indicates binary data generated by the binary arithmetic decoding process from the macroblock 303 to the macroblock 304 and stored in the storage unit 200. A vertical stripe region 203 indicates binary data generated by binary arithmetic decoding processing from the macroblock 305 to the macroblock 306 and stored in the storage unit 200.

  The address calculated by the address calculation unit 102 is an address at which the decoding of the macroblock 302 is finished, the decoding of the next macroblock 303 is started, and the first binary data of the macroblock 303 is written in the storage unit 200. Addr_A in FIG. 2 indicates the corresponding address. Similarly, the address calculation unit 102 calculates the first address Addr_B in which binary data from the macroblock 305 to the macroblock 306 is stored, and the first binary decoding unit 104 and the second binary decoding are calculated. Output to the unit 105.

Next, processing performed by the address calculation unit 102 will be described with reference to FIG.
As shown in FIG. 5, the address calculation unit 500 includes a binary decoding unit 501 and a counter 502.

  The binary decoding unit 501 performs binary decoding processing on the binary data D51 input from the arithmetic decoding unit 101 described above. This binary decoding process is described in 7 Syntax and semantics of “ITU-T Recommendation H.264”. As described above, motion vector information, orthogonal transform coefficient information, prediction mode information, and the like are decoded from binary data D51 input according to Syntax (syntax / rule). For example, binary data below slice header () or slice data () is decoded. The counter 502 always calculates an address at which the binary data D11 is stored in the storage unit 103 described above.

  In the binary decoding unit 501, when the binary decoding process of end_of_slice_flag ends and the binary decoding process of the next macroblock starts, the address D53 calculated by the counter 502 is the address to be obtained. The address D53 is address data that associates the position where the binary data D11 is stored in the storage unit 103 with the image position after the binary data is decoded. The address D53 is output to the second binary decoding unit 105 or the first binary decoding unit 104 described above.

  As described above, binary arithmetic decoding is performed by executing the blocks shown in FIGS. 1 and 5 and the memory image of the storage unit 103 shown in FIG. 2, the image image shown in FIG. 3, and the processing method. Thus, an address indicating a predetermined image position that could not be obtained can be calculated. This makes it possible to operate the binary decoding unit in parallel for each predetermined image position.

  In addition, the storage unit 103 need only store binary data, not a large amount of decoding results such as motion vector information, transform coefficient values, reference picture indexes, and prediction mode information. Therefore, it is possible to perform parallel processing while suppressing the capacity of the storage unit that buffers the arithmetic decoding result. From the above, it is possible to realize an image decoding apparatus having the capability of processing HD images with a smaller circuit scale with a configuration in which the capacity of a storage unit for buffering arithmetic decoding results is suppressed.

FIG. 6 is a flowchart illustrating an example of a decoding process procedure performed by the image decoding apparatus 100 according to the present embodiment.
As shown in FIG. 6, in step S601, the input video stream D10 is arithmetically decoded by the arithmetic decoding unit 101 to generate binary data D11 and binary data D12.

  In step S602, the binary data D11 generated by the arithmetic decoding unit 101 is output to the storage unit 103, and the binary data D12 is output to the address calculation unit 102. In step S603, the binary data D11 output from the arithmetic decoding unit 101 is stored in the storage unit 103, and the binary data D12 is binary decoded in the address calculation unit 102.

  Next, in step S604, the reading unit 106 reads the binary data D11 stored in the storage unit 103. The reading unit 106 performs reading based on the control of the control unit 107 when reading the binary data D <b> 11 stored in the storage unit 103.

  Next, proceeding to step S605, it is determined whether the output destination of the binary data read out at step S604 is the first binary decoding unit 104 or the second binary decoding unit 105. As a result of the determination, if the output destination of the read binary data is the first binary decoding unit 104, the process proceeds to step S606, where the first binary decoding unit is used as the first binary data D15. To 104.

  If it is determined in step S605 that the output destination is the second binary decoding unit 105, the process proceeds to step S607, and the second binary data D16 is sent to the second binary decoding unit 105. Output.

Image decoding apparatus 100 of the present embodiment was configured to detect, as described above, the address of the decrypt the arithmetic decoding unit 101 binary data D11 in the address calculation unit 102. Then, the binary data read from the storage unit 103 is distributed to a plurality of binary decoding units 104 and 105 using the detected address. This makes it possible to decode a binary arithmetically encoded video stream without storing information such as motion vector information, transform coefficient values, reference picture indexes, and prediction mode information.

Thus, the binary data D11 output from the arithmetic decoding unit 101 can be operated in parallel with the first and second binary decoding units 104 and 105 without significantly increasing the capacity of the temporary storage memory. it is possible to decrypt processing Te. Therefore, it is possible to configure an image decoding apparatus capable of decoding a binary arithmetic coded video stream with a small circuit scale.

(Another embodiment according to the present invention)
Each means constituting the image decoding apparatus according to the above-described embodiment of the present invention can be realized by operating a program stored in a RAM or ROM of a computer. This program and a computer-readable recording medium recording the program are included in the present invention.

  In addition, the present invention can be implemented as a system, apparatus, method, program, storage medium, or the like, and can be applied to a system composed of a plurality of devices. Moreover, you may apply to the apparatus which consists of one apparatus.

  In the present invention, a software program (in the embodiment, a program corresponding to the flowchart shown in FIG. 6) for executing each step in the above-described image decoding method is directly or remotely supplied to the system or apparatus. In addition, this includes a case where the system or the computer of the apparatus is also achieved by reading and executing the supplied program code.

  Accordingly, since the functions of the present invention are implemented by computer, the program code installed in the computer also implements the present invention. In other words, the present invention includes a computer program itself for realizing the functional processing of the present invention.

  In that case, as long as it has the function of a program, it may be in the form of object code, a program executed by an interpreter, script data supplied to the OS, and the like.

  Various recording media can be used as a recording medium for supplying the program. For example, floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD (DVD-ROM, DVD- R).

  As another program supply method, a browser on a client computer is used to connect to an Internet home page. The computer program itself of the present invention or a compressed file including an automatic installation function can be downloaded from the homepage by downloading it to a recording medium such as a hard disk.

  It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the present invention.

  In addition, the program of the present invention is encrypted, stored in a storage medium such as a CD-ROM, distributed to users, and key information for decryption is downloaded from a homepage via the Internet to users who have cleared predetermined conditions. Let It is also possible to execute the encrypted program by using the key information and install the program on a computer.

  In addition to the functions of the above-described embodiments being realized by the computer executing the read program, the OS running on the computer performs part or all of the actual processing. Also, the functions of the above-described embodiments can be realized.

  Further, the program read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. Thereafter, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing based on the instructions of the program, and the functions of the above-described embodiments are realized by the processing.

1 is a block diagram illustrating an exemplary configuration of an image decoding device according to an embodiment of the present invention. It is an image figure which shows embodiment of this invention and demonstrates the state of the binary data memorize | stored in the memory | storage part. It is an image figure which showed embodiment of this invention and divided | segmented the image to decode in the macroblock unit of 16x16 pixel, and was shown in matrix form. It is a block diagram which shows the structural example of the conventional image decoding apparatus. It is a block diagram which shows embodiment of this invention and shows the structural example of an address calculation part. It is a flowchart which shows embodiment of this invention and demonstrates the outline of the process sequence of the image decoding method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Image decoding apparatus 101 Arithmetic decoding part 102 Address calculation part 103 Storage part 104 1st binary decoding part 105 2nd binary decoding part 106 Reading part 107 Control part

Claims (8)

An image decoding device for decoding a binary arithmetically encoded video stream,
Arithmetic decoding means for arithmetic decoding the video stream;
Storage means for storing binary data arithmetically decoded by the arithmetic decoding means;
The binary data arithmetically decoded by the arithmetic decoding means is binary decoded, and the position where the binary data is stored in the storage means and the image position after the binary data is decoded Address calculating means for calculating address data to be related;
Reading means for reading binary data stored in the storage means;
N (where N is a natural number greater than or equal to 2) binary decoding units, and the binary data read by the reading unit is converted into the N binary decoding units based on the address data. And a binary decoding means for performing binary decoding processing in a shared manner . The video stream is encoded in units of blocks composed of a predetermined number of pixels,
The image decoding apparatus according to claim 1, wherein the address calculation unit calculates the address data in units of a predetermined number of blocks.   The image decoding apparatus according to claim 2, wherein the predetermined number of block units is a unit corresponding to a horizontal screen width of an image.   3. The image decoding apparatus according to claim 2, wherein the predetermined number of block units are macroblocks each including 16 pixels vertically and horizontally.   The image decoding apparatus according to claim 1, wherein the N binary decoding units perform binary decoding processing in parallel. An image decoding method for decoding a binary arithmetically encoded video stream, comprising:
An arithmetic decoding step of arithmetic decoding the video stream;
A storage step of storing the binary data arithmetically decoded in the arithmetic decoding step in a storage means;
The binary data arithmetically decoded in the arithmetic decoding step is binary decoded, and the position where the binary data is stored in the storage means and the image position after the binary data is decoded An address calculation step for calculating address data to be related;
A reading step of reading binary data stored in the storage means;
N (where N is a natural number greater than or equal to 2) binary decoding units, the binary data read in the reading step is converted into the N binary decoding units based on the address data. An image decoding method comprising: a binary decoding step in which each of them is shared and performs a binary decoding process . A program for causing a computer to execute a process of decoding a binary arithmetically encoded video stream,
An arithmetic decoding step of arithmetic decoding the video stream;
A storage step of storing the binary data arithmetically decoded in the arithmetic decoding step in a storage means;
The binary data arithmetically decoded in the arithmetic decoding step is binary decoded, and the position where the binary data is stored in the storage means and the image position after the binary data is decoded An address calculation step for calculating address data to be related;
A reading step of reading binary data stored in the storage means;
N (where N is a natural number greater than or equal to 2) binary decoding units, the binary data read in the reading step is converted into the N binary decoding units based on the address data. A program that causes a computer to execute a binary decoding process in which each of them shares a binary decoding process .   A computer-readable storage medium storing the program according to claim 7.

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