JP4884325B2 - Receiving machine - Google Patents

Description

  The present invention relates to a receiver used in a communication system, and more particularly to an adaptive equalization technique for compensating for intersymbol interference that distorts a transmission waveform.

  As an ordinary adaptive equalization technique, there is a technique that reduces intersymbol interference by inputting a received signal to a tapped delay line and setting an appropriate tap coefficient by a coefficient estimation circuit (for example, Non-Patent Document 1). .

Qureshi, S. "Adaptive Equalization" Communications Magazine, IEEE Volume 20, Issue 2, Mar. 1982 Pages 9-16

  In the conventional adaptive equalization technique described above, when differential encoding is performed as a transmission signal, it is necessary to add a function for performing reverse processing on the differential encoding. For example, when high-speed operation is required, it is effective to implement the delay detection circuit with an analog circuit. When adaptive equalization is employed in such a system and a signal having intersymbol interference is delayed, a non-linear interference component is generated as a result. This nonlinear component becomes difficult to compensate with a linear device such as a tapped delay line.

  In this way, in the conventional adaptive equalization method using delay detection, linear intersymbol interference becomes a non-linear interference component due to delay detection, and the compensation can be compensated by a linear device such as a tapped delay line. There was a problem that it was difficult.

  The present invention has been made to solve the above problems, and provides a receiver that realizes a good intersymbol interference component compensation function by using a delay detection output and a multi-tap delay line. Objective.

  The present invention includes a plurality of delay detection circuits that perform delay detection with different delay amounts set in advance with respect to a received signal, a plurality of multi-tap delay lines that respectively receive the outputs of the plurality of delay detection circuits, A receiver comprising: an adder circuit that adds outputs of the plurality of multi-tap delay lines; and a determination circuit that receives the output of the adder circuit and determines transmission data.

  According to the present invention, it is possible to provide a receiver that realizes a good intersymbol interference component compensation function by using a delay detection output and a multi-tap delay line.

  In the present invention, a plurality of delay detection circuits in which delay amounts in delay detection are set to different values are prepared, and a multi-tap delay line is prepared for each of the plurality of delay detection outputs. By inputting different nonlinear interference components to the plurality of multi-tap delay lines, it becomes possible to cancel each other's interference components. Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram of a receiver according to an embodiment of the present invention. In FIG. 1, a receiver inputs a received signal input terminal 1 to which a received signal is input and a distributed received signal, and has a predetermined delay amount with respect to the received signal, and performs delay detection with the delay amount. Delay detection circuits (1 to N) 3-1 to 3-N and delay detection outputs of the plurality of delay detection circuits 3-1 to 3-N. Tapped delay line section 4 including a plurality of multi-tapped delay lines 4-1 to 4-N, outputs of the plurality of multi-tapped delay lines 4-1 to 4-N, and coefficients described later An adder circuit 5 for inputting and adding a bias value from the estimation circuit 7, a determination circuit 6 for inputting an output of the adder circuit 5 and determining transmission data, and delays of a plurality of delay detection circuits 3-1 to 3-N Estimate the tap coefficient and bias value in the tapped delay line 4 from the detection output. A coefficient estimation circuit 7 supplied to the tapped delay line unit 4 and the addition circuit 5, and a determination value output terminal 2 that outputs the result of the determination circuit 6 are provided.

  Each multi-tap delay line 4-1 to 4-N of the multi-tap delay line unit 4 obtains a delay element 41 indicated by “D” which gives a delay to the signal, and “+” which calculates the sum of the input signals. And a multiplier 42 that multiplies the input received signal by the set tap coefficient.

  Next, the operation will be described. First, each of the delay detection circuits 3-1 to 3-N performs delay detection according to a preset delay time. Here, it is assumed that the delay detection circuit 3-1, the delay detection circuit 3-2,..., The delay detection circuit 3-N are set with different delay times (delay amounts). Here, the general delay time is set to an integer value of one symbol period, two symbol periods, three symbol periods,. In particular, it is often set to 1 symbol period or 1/2 symbol period.

  The coefficient estimation circuit 7 is based on the reception signals from the delay detection circuits 3-1 to 3 -N and the transmission signals estimated in advance or the transmission signals estimated on the reception side, so that the delay lines 4-1 to 4- Estimate the tap coefficient for N4 and the bias value for the adder circuit 5. For example, the tap coefficient is generally set so that the square error between the adder circuit output signal and the transmission information is minimized (referred to as a least square error criterion). Further, when utilizing the determination value, for example, an algorithm for updating the tap coefficient for each symbol such as an LMS algorithm is used.

  The tapped delay line unit 4 prepares multitapped delay lines 4-1 to 4 -N for different delay detection outputs, and sets tap coefficients according to the output of the coefficient estimation circuit 7. The adder circuit 5 inputs the outputs of the multitapped delay lines 4-1 to 4-N and the bias value output from the coefficient estimation circuit 7, and adds these values. Here, the bias value is generated by nonlinear processing by delay detection, and the characteristic can be improved by removing the value on the receiving side. The determination circuit 6 performs data determination based on a comparison result with a threshold value determined in advance from the output of the addition circuit 5.

  Intersymbol interference is a linear distortion and can be compensated by delay lines 4-1 to 4-N with multi-tap. However, nonlinear distortion occurs at the time of delay detection of a received signal in which intersymbol interference exists, and compensation cannot be performed by the delay lines 4-1 to 4-N with multi-tap. Delay detection results with different delay times have different amounts of nonlinear distortion. By appropriately weighting and adding the different distortions according to the set values of the coefficient estimation circuit 7, nonlinear interference can be canceled with each other.

Embodiment 2. FIG.
FIG. 2 is a block diagram of a receiver according to another embodiment of the present invention. The same or corresponding parts as those in FIG. In this embodiment, the coefficient estimation circuit 7 inputs the output of the determination circuit output 6 for each symbol. Based on this, the coefficient estimation circuit 7 updates the tap coefficient and supplies it to the tapped delay line unit 4. As a result, even when the distortion of the transmission path varies with time, it is possible to follow the variation.

  In the above description, the coefficient estimating circuit 7 estimates the bias value for the adding circuit 5 together with the tap coefficients for the multi-tapped delay lines 4-1 to 4-N4. Each output of the lines 4-1 to 4-N and the bias value output from the coefficient estimation circuit 7 are input and these values are added. However, the present invention includes a case where no bias value is added. The same applies to the second embodiment.

It is a block diagram of the receiver by Embodiment 1 of this invention. It is a block diagram of the receiver by Embodiment 2 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Reception signal input terminal, 2 Judgment value output terminal, 3-1 to 3-N delay detection circuit, 4-tap delay line part, 4-1 to 4-N multitap delay line, 5 addition circuit, 6 judgment circuit 7 coefficient estimation circuit, 41 delay element, 42 multiplier, 43 adder.

Claims (4)

A plurality of delay detection circuits that perform delay detection with different delay amounts set in advance with respect to the received signal; and
A plurality of multi-tap delay lines each receiving the output of the plurality of delay detection circuits;
An adding circuit for adding the outputs of the plurality of multi-tap delay lines;
A determination circuit that inputs the output of the adder circuit and determines transmission data;
A receiver comprising:   A coefficient estimation circuit configured to input delay detection outputs of the plurality of delay detection circuits and estimate tap coefficients of the plurality of multi-tap delay lines, and the plurality of multi-tap delay lines are estimated by the coefficient estimation circuit; The receiver according to claim 1, wherein the tap coefficient is set according to the determined tap coefficient.   The coefficient estimation circuit further estimates a bias value generated by nonlinear processing by delay detection, and the addition circuit inputs the bias value estimated by the coefficient estimation circuit and adds the value. Item 3. The receiver according to Item 2.   4. The receiver according to claim 2, wherein the coefficient estimation circuit inputs an output value of the determination circuit and updates a tap coefficient according to the output value.

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