JP4879572B2 - Semiconductor memory - Google Patents

Description

  The present invention relates to a semiconductor memory such as a flash memory.

As is well known, the flash memory is provided with a redundancy function. This function is a function for providing a redundant cell (unused cell) in advance in a memory cell and replacing a defective part with a redundant cell when a defect occurs in a part of the memory cell, thereby improving the yield. is there.
Conventionally, this replacement of redundant cells has been performed in a test process before shipment. When a memory cell failure occurs during the test, the redundancy function replaces the defective portion with a redundant cell, thereby preventing chip failure. be able to.
Patent Document 1 is known as a document relating to a conventional redundancy function.
JP 2000-276896 A

  The present invention has been made in consideration of the above circumstances, and its purpose is not only to perform a test process before shipment, but also to replace a defective portion with a redundant cell when a failure occurs in a memory cell during actual memory use. It is an object of the present invention to provide a semiconductor memory that can be used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. The invention according to claim 1 includes a plurality of main memory blocks and a plurality of redundant blocks to be replaced when the previous main memory block becomes defective. A memory array, an information storage memory in which a use state of the redundant block is written, a read circuit for reading data written in the information storage memory, and a discrimination circuit for discriminating data written in the information storage memory In the semiconductor memory comprising the (sense amplifier) and the storage means for storing the information of the determination circuit, the means for reading the data by the determination circuit reads at a voltage lower than the gate voltage at the time of write verification. It is a semiconductor memory.
According to a second aspect of the present invention, there is provided a memory array having a plurality of storage blocks and a plurality of redundant blocks, an information storage memory in which a use state of the redundant blocks is written, an erasure instruction from an external circuit, and the storage Erasing means for erasing a block, then reading and checking data in the erased storage block, and writing the address of the storage block in association with the redundant block in the information storage memory when the erase is not performed correctly The information storage memory is checked in response to a write / read command and an address from an external circuit. If an address corresponding to the address received from the external circuit is written in the information storage memory, the address corresponds to the address. When the redundant block is accessed and not written, the address received from the external circuit is In the semiconductor memory including the writing / reading means for accessing the storage block shown, the information storage memory includes a nonvolatile memory cell, a first volatile memory that reads an output of the nonvolatile memory cell, and the first A second volatile memory that reads the output of the volatile memory, and the erasing means writes the data into the nonvolatile memory cell, and then reads the written data at a confirmation level slightly lower than a write threshold. Write to the first volatile memory, perform write confirmation on the data written to the first volatile memory, and after the write confirmation is completed, read the data of the nonvolatile memory cell at a read level lower than the confirmation level. Write to the first volatile memory, and then write the data in the first volatile memory. Write the serial second volatile memory, a semiconductor memory and outputs the data in the volatile memory of the second to the writing / reading means.

  According to the present invention, when a defect occurs in a memory cell during actual use of the memory, the defective part can be replaced with a redundant cell. Thereby, the defect of a semiconductor memory can be reduced. In addition, according to the present invention, since re-reading at the read level is performed after writing is confirmed, there is an effect that it is possible to prevent an error that a non-defective product is erroneously determined to be defective.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing write and erase operations of a semiconductor memory (flash memory) according to an embodiment of the present invention. In this figure, reference numeral 1 denotes an interface circuit to which a command, data and address from an external circuit are inputted, and 2 denotes a command user interface (hereinafter referred to as CUI) for decoding the command inputted to the interface circuit 1. A control circuit 3 controls writing, reading, and erasing of the memory array 4. Reference numeral 5 denotes a power supply circuit that supplies DC power to each unit. Further, a high voltage (+) is generated during writing to the memory array 4, a medium voltage (+) is generated during reading, and a negative voltage (−) is generated during erasing, and is output to the memory array 4.

  A decoder 6 receives a control signal output from the control circuit 3 and an address signal from the interface circuit 1 and outputs a signal designating a write / erase / read mode to the memory array 4. In addition, an address and data are output to the memory cell 4 at the time of writing and an address is output to the memory cell 4 at the time of reading, and the designated memory cell is selected. Further, an address and data are output to the memory cell 4 at the time of writing, and an address is output to the memory cell 4 at the time of reading. Further, the data read from the memory array 4 is output to the control circuit 3 via the sense amplifier 8. As shown in the figure, the memory array 4 has storage blocks BLK0 to BLK15 and redundant blocks BRD0 and BRD1. Here, the storage blocks BLK0 to BLK15 are original storage areas, and the redundant blocks BRD0 and BRD1 are redundancy storage areas that are used instead when any of the storage blocks BLK0 to BLK15 becomes defective.

  The BRD information storage memory 9 is a memory in which data relating to the use state of the redundant blocks BRD0 and BRD1 is stored. As shown in FIG. 2, the address information storage unit K0 corresponding to the redundant block BRD0 and the address corresponding to the redundant block BRD1 The information storage unit K1, the latch La to which the output data of the storage units K0 and K1 are added, the latch L0 corresponding to the redundant block BRD0, the latch L1 corresponding to the redundant block BRD1, and the output of the latch La are latched L0 Alternatively, selection means for selectively adding to L1 is provided.

Here, as shown in FIG. 3, each of the storage units K0 and K1 includes a non-volatile memory cell 11 having a floating gate and configured similarly to the memory array 4, and the latches La, L0, and L1 are illustrated in FIG. As shown in FIG. The storage units K0 and K1 are areas K0-A and K1-A where block addresses are written, areas K0-E and K1-E where enable bits are written, and areas K0-D where disable bits are written. , K1-D are provided. Each of the latches La, L0, and L1 is a latch having the same number of bits as the storage unit K0 (or K1). Similarly, the areas La-A, L0-A, L1-A, and enable bits in which block addresses are written Are written in areas La-E, L0-E and L1-E, and areas La-D, L0-D and L1-d in which disable bits are written.

Next, the operation of the above-described semiconductor memory will be described.
First, when the power is turned on, data in the storage unit K0 in the BRD information storage memory 9 is read and written in the latch La, and then data in the latch La is written in the latch L0. Next, the data in the storage unit K1 is read and written in the latch La, and then the data in the latch La is written in the latch L1.

  Next, when a read command and an address are input from the external circuit to the interface circuit 1 and supplied to the control circuit 3 via the CUI 2, the control circuit 3 first stores the memory block indicated by the address. It is checked whether the address is stored in the storage unit K0 or K1 of the BRD information storage memory 9. This check is performed by checking the areas L0-A and L1-A of the latches L0 and L1. If it is not stored, a read command and an address are output to the decoder 6. Decoder 6 receives a read command and an address, reads data from memory array 4, and outputs the data to control circuit 3 via sense amplifier 8. The control circuit 3 outputs the data read from the memory array 4 to the interface circuit 1.

  On the other hand, when the address of the storage block indicated by the read address supplied to the control circuit 3 is stored in, for example, the latch L0 of the BRD information storage memory 9, the control circuit 3 reads the address, read address, and read of the redundant block BRD0. The command is output to the decoder 6. Decoder 6 receives this command and address, reads data indicated by the read address from redundant block BRD0, and outputs the data to control circuit 3 via sense amplifier 8. The control circuit 3 outputs the data to the interface circuit 1.

  Next, when a write command, write data, and an address are input from the external circuit to the interface circuit 1 and supplied to the control circuit 3 via the CUI 2, the control circuit 3 instructs the address in the same manner as described above. It is checked whether the address of the storage block being stored is stored in the storage unit K0 or K1 of the BRD information storage memory 9. If it is stored, the redundant block is accessed for data writing, and if not stored, the addressed storage block is accessed for writing.

Next, the operation at the time of data erasure of the above-described semiconductor memory will be described with reference to the flowcharts shown in FIGS.
When a command instructing erasure and an address of the erase block are input from the external circuit to the interface circuit 1, the input command and address of the storage block are supplied to the control circuit 3 via the CUI 2. Upon receiving the erase command, the control circuit 3 first checks whether the command is a command for erasing the storage block or a command for erasing the entire chip (step S1 in FIG. 4). If it is neither, proceed to another sequence.
On the other hand, if it is a command for instructing erasing, the power supply circuit 5 is instructed to output an erasing voltage, and the erasing command and the address of the storage block to be erased are output to the decoder 6. The decoder 6 selects a memory cell corresponding to the address. Thereby, the (−) negative voltage output from the power supply circuit 5 is applied to the selected memory cell, and the memory block is erased.

  Next, the control circuit 3 outputs a read signal and the address of the erased storage block to the decoder 6, sequentially reads the data of each memory cell of the erased storage block, and confirms that the erase of each memory cell has been performed correctly ( Verify) (step S2). If it is correctly performed, it is determined whether or not all the storage blocks to be erased have been erased (step S3), and if all have been erased, the process is terminated. If there is a storage block to be erased, the process proceeds to the erase process for the next block.

  If it is determined in step S2 that erasure has not been performed correctly, it is determined whether one of the redundant blocks BRD0 and BRD1 for redundancy is usable (step S4). This determination is made by checking whether or not “1” is written in the enable bits L0-E and L1-E and the disable bits L0-D and L1-D of the latches L0 and L1 of the BRD information storage memory 9. If "1" is written in the enable bits L0-E and L1-E of the latches L0 and L1, it is determined that the redundant block has already been used, and the disable bit L0 When “1” is written in −D and L1-D, it is determined that the redundant block cannot be used. If the redundant blocks BRD0 and BRD1 are both used or unusable, data indicating that erasure is impossible is returned to the interface circuit 1 and the processing is terminated.

On the other hand, if either of the redundant blocks BRD0 and BRD1 is usable, the process proceeds to the Auto redundancy process shown in FIG.
In the auto redundancy process, first, it is determined whether or not the storage block that has not been erased correctly is one of the redundant blocks BRD0 and BRD1 (step S11). If it is either, “1” is written to the disable bit K0-D of the storage unit K0 corresponding to the redundant block (referred to as BRD0) (step S12). Next, the written disable bit K0-D is verified (step S13). In this Verify, first, all data in the storage unit K0 is read based on the Verify level (see FIG. 7), written to the latch La, and then whether or not the disable bit La-D of the latch La is “1”. Is checked (step S14).

If the determination result is “NO”, it is determined whether or not the number of Verify has reached n or more that is set in advance (step S15). If the determination result is “NO”, the process returns to step S12, and the disable bit K0-D is written and verified again (steps S12 to S15). When the number of write / verify reaches n times, the determination in step S15 is “YES”, and the process proceeds to step S16. In step S16, the Reelatch process is performed at a normal read level. That is, the data in the storage unit K0 is read based on the normal read level (see FIG. 7) and stored in the latch La, and then the data in the latch La is transferred to the latch L0. Then, data indicating that erasure is impossible is returned to the interface circuit 1 and the processing is terminated.
Note that the number of times of write / verify is a plurality of times because, as the write characteristics of the flash memory cell, an increase in threshold when writing is performed depends on the write time, and the write characteristics vary depending on the cell. This is because it is preferable to apply a plurality of write pulses for a predetermined time in order to obtain the above.

  Here, the difference between the reading at verify and the normal reading will be described. As an example, when data is written to the memory cell 11 (FIG. 3), the Id (drain current) -Vg (gate voltage) characteristic has a threshold value around 5 V as shown by a curve G1 in FIG. When a curve is formed and erasure is performed, the threshold value is set to be a (−) curve as shown by a curve G2. In the case of normal data reading, the reading is performed with the gate voltage level in the vicinity of the intermediate 3V. On the other hand, in the case of the write verify, the verify voltage is set to 5V. However, if the threshold exceeds 5V, the verify becomes pass, so the threshold is set when the threshold is slightly exceeded. As described above, the read reference level is different between the verify reading and the normal reading. For this reason, in the above process, the data in the storage unit K0 is read out by the Relac process that is normal reading (the gate voltage level is 3 V) and is reset in the latch L0. Since the gate voltage level for reading at verify is as high as 5V, there is a possibility that data (data other than the disable bits K0-D) not written in step S12 may change due to threshold variation. Because there is.

Now, when the processing in steps S12 to S15 is repeated, if Verify is OK (“YES” in step S14), the process proceeds to step S17, the above-described Relatch process is performed, and then the process proceeds to step S18. In step S <b> 18, the address of the storage block (referred to as storage block BLK <b> 2) determined to be unerasable is written into the BRD information storage memory 9. Now, assuming that the redundant block BRD1 is usable, the address of the storage block BLK2 is written in the area K1-A of the storage unit K1. Next, the written data is verified (step S19). That is, each data in the storage unit K1 is read based on the Verify level (see FIG. 7), written to the latch La, and then the data in the area La-A of the latch La matches the address of the storage block BLK2. Is checked.

  If the result of Verify is NG ("NO" at step S20), it is determined whether or not the number of Verify has reached a preset number of times n (step S21). If the determination result is “NO”, the process returns to step S18 to write the address and verify again (steps S18 to S20). When the number of write / verify reaches n times, the determination in step S21 is “YES”, and the process proceeds to the AutoR / D error process of FIG.

On the other hand, when the processing of steps S18 to S21 is repeated and Verify is OK (step S20 is “YES”), the process proceeds to step S22. In step S22, “1” is written to the enable bits K1-E in the storage unit K1. Next, the written data is verified (step S23). That is, each data in the storage unit K1 is read based on the Verify level , written to the latch La, and then it is checked whether the data in the area La-A of the latch La is “1”.

  If the result of Verify is NG ("NO" at step S24), it is determined whether or not the number of Verify has reached a preset number of times n (step S25). If the determination result is “NO”, the process returns to step S22, and the address is written and verified again (steps S22 to S25). When the number of write / verify reaches n times, the determination in step S25 is “YES”, and the process proceeds to the AutoR / D error process of FIG. On the other hand, if Verify is OK (“YES” in step S24), the process proceeds to step S26, where the above-described Reelatch process is performed, and then data indicating that the erase process has been correctly completed is output to the interface circuit 1, and the process is performed. Exit.

Next, AutoR / D error processing will be described with reference to FIG.
When this process proceeds, first, “1” is written to the disable bit K1-D of the storage unit K1 for which address writing or enable bit writing could not be performed (step S31). Next, the written data is verified (step S32). That is, each data in the storage unit K1 is read based on the Verify level , written in the latch La, and then it is checked whether the data in the area La-D of the latch La is “1”.

  If the result of Verify is NG ("NO" at step S33), it is determined whether or not the number of Verify has reached a preset number of times n (step S35). If the determination result is “NO”, the process returns to step S31 to write the address and verify again (steps S31 to S33). When the number of times of writing / Verify reaches n times, the determination in step S35 is “YES”, the Releatch process is performed (step S36), and then data indicating that erasure is impossible is returned to the interface circuit 1. The process ends. Also, if Verify is OK while writing / Verify is repeated ("YES" in step S33), the Relat processing is performed (step S34), and then the erasure is disabled. The indicated data is returned to the interface circuit 1 and the processing is terminated.

  It is possible to write the address, enable bit, and disable bit at once, but in this case, if the battery suddenly drops during reset operation or LVDD (Low Vdd: flash memory writing) When an interruption operation by detecting this voltage and automatically interrupting writing) is entered, it is assumed that only enable bits have been written and other bits have not been written. The process is as follows.

  In the above-described embodiment, the data in the storage units K0 and K1 is written to the latch La and the latches L0 and L1 are not written at the time of Verify. Then, Verify is performed based on the data of the latch La. Then, after verifying, the data in the storage units K0 and K1 is read again at the read level (see FIG. 7), and written to the latches L0 and L1 via the latch La (Relate). This process is for countermeasures against variations in threshold values of the memory cell 11 (FIG. 3). That is, since the reading at verify is performed at the verify level (FIG. 7; a level higher than the read level), data other than the verify target may change when written to the latch La due to variations in threshold. There is. The Relate process prevents this inconvenience.

  The present invention is used for a nonvolatile memory such as a flash memory.

1 is a block diagram showing a configuration of a semiconductor memory according to an embodiment of the present invention. It is a block diagram which shows the internal structure of the BRD information storage memory 9 in the same semiconductor memory. 3 is a diagram showing a memory cell 11 that constitutes storage units K0 and K1 in the BRD information storage memory 9 and a CMOS latch 12 that constitutes a latch La. FIG. It is a flowchart for demonstrating operation | movement of the embodiment. It is a flowchart for demonstrating operation | movement of the embodiment. It is a flowchart for demonstrating operation | movement of the embodiment. 3 is a diagram illustrating characteristics of a memory cell 11. FIG.

Explanation of symbols

1 ... interface circuit 2 ... CPI
DESCRIPTION OF SYMBOLS 3 ... Control circuit 4 ... Memory array 6 ... Decoder 8 ... Sense amplifier 9 ... BRD information storage memory 11 ... Memory cell 12 ... Latch BLK0-BLK15 ... Memory block BRD0, BRD1 ... Redundant block D ... Selection means K0, K1 ... Memory | storage part La, L0L1 ... Latch

Claims (1)

A memory array having a plurality of storage blocks, a first redundant block, a second redundant block ;
An information storage memory having a first storage unit for storing data relating to the usage state of the first redundant block, and a second storage unit for holding data relating to the usage state of the second redundant block ;
In response to a command for erasing a storage block from an external circuit, an erasing operation is performed on the selected first storage block among the plurality of storage blocks,
Performing a confirmation operation to confirm whether the erasure operation has been performed correctly;
If the data in the first storage block is not correctly erased based on the result of the confirmation operation, a signal indicating disable is written to the first storage unit when the first storage block is the first redundant block. Perform a first write operation;
A second storage unit that can use the address of the first storage block after the first write operation is correctly performed or based on the result of the confirmation operation, when the first storage block is not the first redundant block Perform a second write operation to write to
Erasing means for executing a third write operation for writing a signal indicating an enable bit to the second storage unit after the second write operation is correctly performed ;
When a write / read command and an address are received from an external circuit and an address corresponding to the address received from the external circuit is stored in the first storage unit or the second storage unit, the first storage unit or the When the redundant block corresponding to the address stored in the second storage unit is accessed and the address corresponding to the address received from the external circuit is not stored in the first storage unit or the second storage unit, the external circuit Write / read means for accessing the storage block indicated by the address received from
Semiconductor memory having a.

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