JP4873975B2 - Alarm - Google Patents

Description

  The present invention relates to an alarm device that detects, for example, a fire and issues an alarm. This is to ensure that the signal input from the interlocked alarm device can be received.

For example, an alarm provided with an interlocking circuit that can be interlocked by wired or wireless connection so that a fire that occurs in one room in a house can be alarmed by light emission, ringing, etc. in another room There is a vessel. Here, it is assumed that a wired connection is made. The interlock circuit includes an interlock input circuit that detects a signal from another alarm device and an interlock output circuit that transmits a signal to the other alarm device. As the interlock input circuit, it is determined whether the signal is transmitted (whether the interlock input is made) by determining whether the connected wiring (hereinafter referred to as the interlock wiring) is conductive or non-conductive. Some discriminate (see, for example, Patent Document 1).
JP 2003-058968 A

  By the way, the alarm device generally has a run mode with high power consumption and a sleep mode with low power consumption for the purpose of reducing the power consumption as much as possible and extending the battery life. The run mode is activated, and processing such as state determination is performed during that time. The interlocking input determination is performed in the run mode, that is, every predetermined cycle.

  Here, for example, when a periodic noise source such as commercial power supply noise is superimposed on the interlocking wiring, the high / low state in which the voltage becomes higher or lower may periodically fluctuate. For this reason, there is a possibility that the discrimination cannot be accurately performed depending on the detection timing at the time of linked input discrimination. In some cases, it is not judged that a fire has occurred in other devices (no linked input is made). It may also happen that the alarm is sounded. This is the same even if the discrimination process is always performed.

  Accordingly, an object of the present invention is to provide an alarm device that can prevent erroneous determination of interlocking input and reliably perform interlocking input determination.

An alarm device according to the present invention is an alarm device that is connected to another device via an interlock wiring, performs an interlock input determination process, and determines an interlock input by another device. When a presence or absence is detected, a control circuit is provided that determines whether or not an interlocking input is present, and the control circuit varies the time interval for detecting the interlocking input multiple times .

Moreover, the control circuit of the alarm device according to the present invention changes the time interval for detecting the interlocked input multiple times from a long time interval to a short time interval.

  According to the present invention, the control circuit detects the presence / absence of the interlocking input a plurality of times in succession to determine the determination result, so that erroneous detection is performed even if noise is superimposed on the interlocking wiring. Without being generated, it is possible to determine the interlocking input more reliably and prevent an erroneous alarm or the like.

  Further, according to the present invention, if the interlocking wiring is in a conductive state, it is detected that there is an interlocking input, and if the interlocking wiring is in a non-conducting state, it is detected that there is no interlocking input. The determination can be easily detected based on the voltage.

  Further, according to the present invention, it is possible to reduce the power consumption by performing the interlocking input determination process every predetermined time, setting the mode for performing the process and the mode for not performing the process.

  In addition, according to the present invention, since the time interval for detecting a plurality of interlocking inputs is made different in the control circuit, erroneous detection is performed in synchronization with periodic noise. Can be prevented.

  Further, according to the present invention, when it is determined that the same detection as the determination result has been performed, the interlocking input determination process is ended, so that the processing time can be shortened without prolonging the time until determination, Further, power consumption can be prevented.

  Further, according to the present invention, since the detection time interval is changed from a long time interval to a short time interval, for example, detection of the same state in noise having a long periodicity is not performed many times. As a result, the number of detections can be reduced, and as a result, the time for the linked input determination process can be shortened.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of an alarm device according to Embodiment 1 of the present invention. Here, the alarm device in the present embodiment is assumed to be a fire alarm device. In FIG. 1, the fire alarm device includes a battery 100 as a power source, a control circuit 110, a constant voltage circuit 120, a boost / light emission circuit 130, a light receiving amplification circuit 140, a battery voltage detection circuit 150, a power supply voltage abnormality monitoring circuit 160, an inspection / The voice stop circuit 170, the sound ringing circuit 180, the fire / abnormality display circuit 190, the interlock circuit 200, the terminal wiring 205, and the interlock terminal 210 are configured.

  FIG. 2 is a block diagram showing the configuration of the control circuit 110. For example, the control circuit 110 composed of a one-chip microcomputer (microcomputer) or the like includes a calculation unit 111, a RAM (memory) 112, a ROM 113, a timer unit 114, an A / D conversion unit 115, a main oscillation unit 116, a sub oscillation unit 117, and an interface. Part 118.

  The calculation unit 111 is a digital signal input through the A / D conversion unit 115 and data input through the interface unit 118 (for example, data relating to fire detection, battery voltage, power supply voltage monitoring, and interlocking input). Etc.), processing in the control circuit 110 is performed based on data read via the RAM (memory) 112 or the ROM 113. In the present embodiment, processing such as comparison, determination, etc., particularly associated with interlocking input determination processing (whether a signal related to interlocking is transmitted from another device) is performed. This process is performed in the run mode.

  The RAM 112 temporarily stores data such as changes. In particular, in the present embodiment, when the calculation unit 111 determines the presence / absence of the interlock input in the interlock input determination process, an interlock input flag is provided for reference in the subsequent determination of the interlock input determination process. is doing. The ROM 113 stores data (for example, a program processed by the calculation unit 111) that is read and processed by the calculation unit 111.

  The timer unit 114 measures time. In particular, in the present embodiment, the control circuit 110 operates in the run mode every predetermined time, and performs time counting for performing a plurality of interlocking input detections at predetermined time intervals. The A / D converter 115 converts signals input from various circuits and the like into digital data.

  The main oscillating unit 116 and the sub oscillating unit 117 are provided to oscillate clocks having two types of frequencies so that the control circuit 110 can operate in two types of modes. The control circuit 110 operates at the main clock frequency based on the oscillation of the main oscillation unit 116 in the run mode, and operates at the sub clock frequency based on the oscillation of the sub oscillation unit 117 in the sleep mode. The interface unit 118 is provided to transmit / receive a signal including data to / from an external circuit, device, or the like. In the case of an analog signal, the signal may be routed through the A / D converter 115.

  The constant voltage circuit 120 changes the voltage applied by the battery 100 to a constant voltage (here, 2.3 V, for example), and mainly supplies power to the control circuit 110. Based on the signal from the control circuit 110, the booster / light emitting circuit 130 causes an infrared light emitting diode (not shown) to emit light for fire detection. The light receiving amplification circuit 140 amplifies light (scattered light) from the infrared light emitting diode received by a photodiode (not shown). The battery voltage detection circuit 150 detects the voltage applied by the battery 100.

  The power supply voltage abnormality monitoring circuit 160 monitors the power supply voltage of the constant voltage circuit 120 and the boosting / light emitting circuit 130 so that power with an appropriate voltage is supplied. The inspection / audio stop circuit 170 transmits a signal for causing the control circuit 110 to perform an inspection or audio stop process when a switch (not shown) is pressed by the user. The sound ringing circuit 180 is an amplification circuit that sounds a sound (including a buzzer sound) from a speaker (not shown) based on a signal from the control circuit 110. The fire / abnormality display circuit 190 causes a light emitting diode (not shown) to emit light based on a signal transmitted from the control circuit 110 to teach a user a fire or the like. Here, in the present embodiment, the control circuit 110 transmits signals to the sound ringing circuit 180 and the fire / abnormality display circuit 190 even in the sleep mode so that the ringing and abnormal display are not stopped.

  FIG. 3 is a diagram illustrating a circuit configuration centering on the interlocking circuit 200. The alarm device of the present embodiment can be connected to other devices outside the alarm device via the interlocking terminal 210. Hereinafter, the alarm device according to the present embodiment is described as being connected to another device (an interlocking terminal thereof) having the same interlocking circuit 200 and capable of performing the interlocking input determination process via the interlocking wiring 220. To do. In this embodiment, it is assumed that the interlocking circuit 200 and the control circuit 110 constitute interlocking input determination means and perform interlocking input determination processing. The interlocking circuit 200 is connected to the interlocking terminal 210 via the terminal wiring 205, receives an interlocking signal from an external device via the interlocking wiring 220, transmits it to the control circuit 110, and outputs from the control circuit 110. It becomes an interface for transmitting the interlocking signal to other devices.

  The interlocking circuit 200 of the present embodiment is composed of bipolar transistors as switching elements, transistors Q20 and Q21 such as FETs, resistors R82 and R83, and a diode D6. Further, the control circuit 110 and the interlock circuit 200 are connected by three terminals A, B, and C. Here, the terminals A and B serve as output terminals for transmitting a signal from the control circuit 110 side to the interlocking circuit 200 according to the state of the applied voltage. On the other hand, the terminal C becomes an input terminal through which a signal is transmitted from the interlocking circuit 200 to the control circuit 110 side due to a change in applied voltage.

  Next, the operation of the interlock circuit 200 will be described. First, a case where a signal is transmitted from the control circuit 110 to another device will be described. The control circuit 110 normally sets the applied voltage at the terminal B to a low state (voltage lower than the reference). For example, when the amount of light received from the infrared light emitting diode is changed, the control circuit 110 determines that a fire has occurred and transmits a signal, and the applied voltage at the terminal B is set to a high state (a voltage higher than the reference). At this time, a voltage is applied to the base of the transistor Q21 to cause conduction between the collector and the emitter (the potential difference is 0), and between the two terminals of the interlocking terminal 210 (between the interlocking wirings 220) is also conductive. This is the state of the device (interlocking circuit 200) when the signal is transmitted.

  Next, a case where it is detected whether or not a signal is transmitted from another device (hereinafter referred to as interlocking input detection) will be described. For example, when the interlock input is not detected such as in the sleep mode, the applied voltage at the terminal A is in a low state (voltage lower than the reference), but the control circuit 110 tries to detect the interlock input in the run mode, for example. In this case, the applied voltage at the terminal A is set to a high state (voltage higher than the reference).

  At this time, a voltage is applied to the base of the transistor Q20, and the collector-emitter becomes conductive. Here, when the signal is not transmitted from the external (other) device and the interlocking input is not performed, the transistor Q21 on the external device side is non-conductive, so that no current flows and interlocks. The wiring 220 is in a non-conductive state, and the applied voltage at the terminal C is high (here, the battery voltage is 2.3 V). On the other hand, when a signal is transmitted from an external device and an interlocking input is made, the transistor Q21 on the external device side is conductive, so the transistor Q20, resistors R82 and R83, and the diode D6 to the terminal wiring 205 are interlocked. A current flows to the external device side via the terminal 210 and the interlocking wiring 220 (the interlocking wiring 220 becomes conductive). At this time, the voltage relating to the voltage division between the resistor R82 and the resistor R83 becomes the applied voltage at the terminal C. By setting a threshold value (for example, 2.0 V) that can determine that the voltage related to this voltage division (for example, 1.6 V here) is in a low state, the presence / absence of an interlocking input from an external device is determined. Can be detected.

  FIG. 4 is a timing chart relating to the interlocking input determination process of the control circuit 110. Here, in order to reduce power consumption, the control circuit 110 operates in the run mode by a clock operation by the main oscillation unit 116 by a timer interrupt for each predetermined period (for example, every 5 seconds) as a predetermined time. In the present embodiment, the interlocking input determination process is performed during the operation in the run mode. On the other hand, in the case of the sleep mode based on the clock operation by the sub oscillating unit 117, it is assumed that the control circuit 110 performs only a minimum operation including the interlocking input determination process. Here, in the present embodiment, the interlocking input determination process performed by the control circuit 110 is stored in advance in the ROM 113 as a program, for example, and the arithmetic unit 111 executes the program in the ROM 113 to realize the process. Thus, it is assumed that the interlocking input determination process by the control circuit 110 is performed.

  In the present embodiment, in the run mode, the control circuit 110 (interlocking input determining means) performs the interlocking input determining process with one cycle of detecting the presence or absence of the interlocking input continuously a plurality of times (for example, five times). Do. For example, when a detection different from the previous determination result (the state of the interlocking input flag) is detected continuously a plurality of times (for example, when the previous determination result is that there is no interlocking input, it is determined that there is a plurality of times continuously) Or when it is determined that the previous determination result indicates that there is no interlocking input for a plurality of times), whether or not there is an interlocking input is determined.

  Although it is conceivable that the detection timings of the presence / absence of the interlocked input are performed at equal intervals, in the present embodiment, for example, the detection time interval between the first time and the second time (hereinafter referred to as the detection interval) is time T1,2. The detection interval between the third time and the third time is the time T2, the detection interval between the third time and the fourth time is the time T3, and the detection interval between the fourth time and the fifth time is the time T4, and the sampling period (detection period, the base side of the transistor Q20) The timing at which the voltage is applied is different. This is to prevent the period of noise having periodicity from synchronizing with the sampling period. Here, the detection interval is set so that T1> T2> T3> T4. In this embodiment, as will be described later, the interlocked input determination process is finished when it is determined that the same detection as the previous determination result has been made. However, when a long period of noise is superimposed, for example, the noise waveform As the output from the high-side waveform to the low-side waveform inverts, it takes time to reverse the determination of the presence or absence of interlocking input. The shorter the time interval, the greater the number of detections during that time. This is because it takes time for processing (for example, if the time interval is changed from a long one to a short one, the determination of the presence / absence of interlocking input is reversed twice, but the time interval changes from a short one to a long one) Then you have to do it three times). Further, the sampling period is set so that T1 is not multiplied by T4, so that T1 is not multiplied by T3 and T4, so that T1 is not multiplied by T2, T3, and T4 (for example, 2). The reciprocals of 5, 7, 11, 13 (Hz) are 0.33, 0.2, 0.14, 0.9, 0.7 (ms) as detection intervals T1, T2, T3, T4, etc. ). As a result, it is possible to prevent erroneous detection due to noise having a frequency multiplied by the frequency that is the reciprocal of each sampling period. Note that it is most effective to vary the detection intervals in a plurality of detections. However, the detection intervals are not particularly limited, and the same detection intervals may be included.

  FIG. 5 is a flowchart illustrating the interlocking input determination process performed by the control circuit 110. The control circuit 110 performs other processing and the like during the operation in the run mode. Here, it is assumed that only the interlocking input determination processing is performed. First, since the operation is performed in the run mode every predetermined period as described above, it is determined whether or not 5 seconds have passed (S1). If it is determined that 5 seconds have elapsed, the operation is switched to the clock operation by the main oscillation unit 116 and operates in the run mode (S2). It is determined whether or not an interlocking input has been made (S3). Whether or not the interlocking input is made is determined based on whether or not the applied voltage at the terminal C of the interlocking circuit 200 is less than the threshold value of 2.0 V as described above.

  If it is determined that no interlocking input is made, it is determined whether or not the previous (previous) determination result confirms the determination that the interlocking input is present (whether the interlocking input flag is turned on) (S4A). If it is not determined that there is an interlocking input, the interlocking input determination process in the run mode is terminated, the clock operation by the sub oscillation unit 117 is switched, and the sleep mode is entered (S14).

  If it is determined that there is an interlocking input, it is determined whether the interlocking input detection is the first detection (S5A). If it is the first detection, after waiting for T1 time (S6A), it is determined whether or not an interlocking input is made (S3). Here, if it is not the first detection, it is determined whether it is the second detection (S7A). If it is the second detection, after waiting for T2 time (S8A), it is determined whether or not an interlocking input is made (S3). If it is not the second detection, it is determined whether it is the third detection (S9A). If it is the third detection, after waiting for T3 time (S10A), it is determined whether or not an interlocking input is made (S3). Further, if it is not the third detection, it is determined whether or not it is the fourth detection (S11A). If it is the fourth detection, after waiting for T4 time (S12A), it is determined whether or not an interlocking input is made (S3). If it is not the fourth detection, it is determined that it is detected that the interlocking input has not been made five times (steady), the interlocking input flag is turned off (S13A), and the run mode is determined. In step S14, the interlocked input determination process is terminated, the clock operation is switched to the sub oscillation unit 117, and the sleep mode is entered. For example, even if the detection of the steady state is confirmed at this time, the ringing by the sound ringing circuit 180 and the fire / abnormality display circuit 190 until the switch (not shown) in the inspection / voice stop circuit 170 is pressed. Do not stop the abnormal display.

  On the other hand, if it is determined in S3 that an interlocking input has been made, it is determined whether or not the immediately preceding (previous) determination result is a determination that the interlocking input is present (S4B). If it is determined that there is an interlocking input, the interlocking input determination process in the run mode is terminated, and the process shifts to the sleep mode (S14).

  If it is not determined that there is an interlocking input, it is determined whether the interlocking input detection is the first detection (S5B). If it is the first detection, after waiting for T1 time (S6B), it is determined whether or not an interlocking input is made (S3). If it is not the first detection, it is determined whether it is the second detection (S7B). If it is the second detection, after waiting for T2 time (S8B), it is determined whether or not an interlocking input is made (S3). If it is not the second detection, it is determined whether it is the third detection (S9B). If it is the third detection, after waiting for T3 time (S10B), it is determined whether or not an interlocking input is made (S3). Further, if it is not the third detection, it is determined whether or not it is the fourth detection (S11B). If it is the fourth detection, after waiting for T4 time (S12B), it is determined whether or not an interlocking input is made (S3). If the detection is not the fourth time, the interlocking input has been made five times continuously. Therefore, it is determined that the interlocking input has been detected, and the interlocking input flag is turned on (S13B). Then, the interlocked input determination process in the run mode is terminated, the clock operation is switched to the sub oscillation unit 117, and the sleep mode is entered (S14). For example, at this time, the control circuit 110 transmits a signal to the sound ringing circuit 180 and the fire / abnormality display circuit 190 in a process different from the interlocking input determination process to cause the ringing and the abnormal display.

  As described above, according to the alarm device of the first embodiment, the control circuit 110 receives the interlock input based on the applied voltage at the terminal between the two circuits by the interlock input discriminating means of the control circuit 110 and the interlock circuit 200. When it is detected multiple times (5 times) continuously whether or not it has been made, it is determined that it has been detected that linked input has been made or has not been done. For example, even if noise is superimposed on the interlocking wiring 220, it is possible to determine the interlocking input (signal transmission from another device) more reliably without causing erroneous detection. In addition, if the interlock input is not performed or the state where the interlock input is not performed does not continue five times, the process shifts to the sleep mode according to the determination of S4A (or S4B). Consumption can be prevented and the life of the battery 100 can be extended.

  Furthermore, since the detection timing (detection interval) is made different, the period of noise having periodicity and the detection interval (cycle) are not synchronized, and the presence / absence of interlocking input can be determined. In the alarm device of the present embodiment, when the presence / absence of the interlocking input is reversed, the interlocking input determination process is terminated. At this time, the time between the first detection and the next detection is lengthened and gradually shortened. As a result, the number of detections in the same waveform (one high-side waveform or low-side waveform) in noise having a long periodicity can be reduced, and the time for the interlocking input determination process can be shortened.

Embodiment 2. FIG.
Although the power source of the alarm device in the above-described embodiment is the battery 100, the alarm device is not limited to the battery, and may be configured by another power source. In addition, here, the control circuit 110 performs the interlocking input determination process in the run mode, but it can also be applied to, for example, an alarm device that does not change the mode. Alternatively, it may be determined by continuously detecting from when it is determined that there is an interlocking input. Furthermore, in the above-described embodiment, the fire alarm has been described. However, for example, the present invention can be applied to an alarm device for other purposes including gas leakage and intrusion.

It is a block diagram showing the structure of the alarm device which concerns on embodiment of this invention. 2 is a block diagram showing a configuration of a control circuit 110. 2 is a diagram illustrating a circuit configuration centering on an interlocking circuit 200. FIG. It is a figure which shows the timing chart regarding the interlocking input discrimination | determination process of the control circuit. It is a figure showing the flowchart which shows the interlocking input discrimination | determination process by the control circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Battery 110 Control circuit 111 Operation part 112 RAM
113 ROM
114 Timer Unit 115 A / D Converter 116 Main Oscillator 117 Sub Oscillator 118 Interface Unit 120 Constant Voltage Circuit 130 Boosting / Light Emitting Circuit 140 Photodetection Amplifier 150 Battery Voltage Detection Circuit 160 Power Supply Voltage Abnormality Monitoring Circuit 170 Inspection / Audio Stop Circuit 180 Sound ringing circuit 190 Fire / abnormality display circuit 200 Interlocking circuit 205 Terminal wiring 210 Interlocking terminal 220 Interlocking wiring Q20, Q21 Transistor R82, R83 Resistor D6 Diode

Claims (2)

It is an alarm device that is connected to other devices via interlock wiring, performs interlock input determination processing, and determines the interlock input by the other devices,
When detecting the presence or absence of the interlocking input multiple times in succession, a control circuit for determining whether the interlocking input is present or not ,
The alarm circuit characterized in that the control circuit varies a time interval for detecting the plurality of interlocking inputs . Wherein the control circuit, the alarm of claim 1, wherein the continue to the short time interval the time interval for detecting the plurality of interlocking input from a long time interval.

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