JP4871921B2 - Data processing system and program development system - Google Patents

Description

  The present invention relates to a DMA (Direct Memory Access) control device, and more particularly to a control device that directly transfers data between memories or between memories or external devices without using an arithmetic processing unit such as a CPU in SoC (System on a Chip). It is.

  In recent years, as information devices have become more sophisticated and multifunctional, the amount of data processed by SoC (Systems on a Chip) mounted on these devices has also increased. In order to cope with such increasing data processing, in recent SoCs, a plurality of data processing units such as external peripheral device control units and CPUs such as display control and CD / HDD control perform data processing in parallel. A plurality of data processing units are connected so as to hang on the above bus. A DRAM is connected to the bus via an MCU (Memory Controller Unit) in order to temporarily store data, programs, display display data, and the like in the arithmetic processing of the CPU. The DRAM and the bus I / F may be narrowed down to one because the cost increases if each DRAM is placed in each data processing unit. Is going.

  On the other hand, in SoC, there is a DMA controller that directly transfers data between memories or between memories or external peripheral devices without using an arithmetic processing unit such as a CPU. A DMA controller is also connected to the bus. There are two types of data transfer methods in the DMA controller. One is called cycle steal mode, in which every time a transfer in one data transfer unit is completed, the right to occupy the bus is passed to another data processing unit. The other is called a burst mode. Once the DMA controller has taken the bus occupation right, the transfer is continued without releasing the bus occupation right until the transfer end condition is satisfied. The data transfer method of the DMA controller and the data transfer unit (data transfer amount per unit) in the cycle steal mode can be changed by setting a register in the DMA controller by the user program. is there.

  As an access arbitration method when an access request from the DMA controller and an access request from another data processing unit are simultaneously generated for the same DRAM, a high priority is given to the access request from the DMA controller. There is a method in which a lower priority is given to the request than the DMA controller, and the access request is arbitrated according to this priority. By using this arbitration method, it is possible to speed up access from the DMA controller, but when there are many access requests from the DMA controller, the access request from the low priority CPU is kept waiting for a long time, As a result, the performance of the entire system is degraded.

  Further, when accessing the DRAM, precharge processing for storing data and access destination address designation processing are performed first, and accordingly, it takes overhead time. Therefore, if the data transfer unit per time is reduced, an overhead time is required several times, and the transfer efficiency is lowered.

  As an invention for solving this problem, there is Patent Document 1 or Patent Document 2 that describes means for dynamically adjusting the data transfer amount. Japanese Patent Application Laid-Open No. 2004-228561 monitors the bus load due to DRAM access from the DMA controller, and restricts DRAM access from the CPU based on the result. On the other hand, Patent Document 2 monitors a bus load caused by a part of DRAM access from a DMA controller, and controls another DRAM access from the DMA controller based on the result.

JP 2003-256355 A JP 2003-178020 A

  On the other hand, there is a cache memory as a device for reducing the number of DRAM accesses from the CPU. Since the storage capacity of the cache memory has been increasing year by year due to improvements in semiconductor technology, the number of DRAM accesses from the CPU continues to decrease year by year due to the cache memory. At present, DRAM access from the CPU is replaced with DRAM access from the DMA controller. It is a fraction of that. In the above situation, if the CPU access is limited by detecting the bus load factor from the number of DMA accesses, there is a problem that when the number of DMA accesses is large, the CPU cannot be accessed at all and processing is delayed.

  As a countermeasure for this problem, a study was made of dynamically adjusting the data transfer amount by manipulating the register of the DMA controller with a user program. When the cache memory is adopted, before the CPU accesses the DRAM, it is checked whether the access destination data is in the cache memory, which is a temporary storage device in the CPU, and only when a cache miss occurs. Access to the DRAM is performed. Since whether or not to make a cache miss depends on the execution result of the program, it cannot be estimated from the user program. Therefore, it is difficult to dynamically adjust the transfer amount from the user program using the register of the DMA controller.

  An object of the present invention is to provide a data processing system capable of actively suppressing memory access from being biased to one of a CPU and a DMA control device.

  Another object of the present invention is to provide a development environment for a data processing system that can actively suppress the bias of memory access to one of a CPU and a DMA controller.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the bus arbitration circuit that arbitrates the bus occupation right between the CPU or the DMA control device in accessing the memory, the bus arbitration device periodically measures the bus load caused by the access to the memory from the CPU, and the bus load Information is transmitted to the DMA controller. The DMA control device performs control to reduce the data transfer amount of the data transfer control based on the bus load information received from the bus arbitration device. According to this, the bus occupation time by the DMA control device can be dynamically changed according to the bus load measured periodically.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to actively suppress the memory access from being biased to one of the CPU and the DMA control device.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A data processing system according to the present invention arbitrates a bus occupation right between a DMA controller having a register in which a data transfer amount and a data transfer method are set, and a CPU or the DMA controller in accessing a memory. A bus arbitration circuit. The bus arbitration device includes a bus load monitoring circuit that periodically measures a bus load caused by access from the CPU to the memory and transmits the bus load information to the DMA control device. The DMA controller performs control to reduce the data transfer amount by data transfer control when the bus load information received from the bus load monitoring circuit exceeds a predetermined bus load.

  When the data transfer amount is controlled by the DMA controller on the assumption that the memory access from the CPU is a fraction of the memory access from the DMA controller, the memory from the CPU When the bus load due to access is high, the memory access performance from the DMA controller is only slightly reduced, and the memory access from the CPU becomes possible if necessary, and when the bus load due to memory access from the CPU is small The memory access efficiency from the DMA controller increases.

  Thereby, it is possible to actively suppress the memory access from being biased to one of the CPU and the DMA control device. Therefore, when executing a program in which the DRAM access frequency from the CPU varies, the overall processing efficiency can be increased.

  [2] In the data processing system according to item 1, the control for reducing the data transfer amount by the data transfer control is a control for reducing the data transfer amount at one time in the cycle steal mode.

  [3] In the data processing system according to item 1, the control for reducing the data transfer amount by the data transfer control is a control for changing the data transfer control mode from the burst mode to the cycle steal mode.

  [4] In the data processing system according to item 1, the bus load monitoring circuit measures the number of memory accesses from the CPU in a predetermined time, and obtains a signal indicating whether the number of accesses is equal to or greater than a threshold value as the bus load information.

  [5] In the data processing system according to item 1, the bus arbitration device further includes a buffer for temporarily accumulating memory access requests from the CPU and transmitting a free storage capacity to the bus monitoring circuit. At this time, the bus load monitoring circuit transmits, as the bus load information, information indicating whether or not the integrated value of the buffer free capacity of the buffer at a certain time is equal to or greater than a threshold value to the DMA controller.

  [6] In the data processing system according to item 1, the CPU includes a cache memory that transmits a cache miss signal to the bus arbitration circuit when a cache miss hit occurs. At this time, the bus load monitoring circuit measures the number of occurrences of the cache miss signal in a predetermined time, and transmits information indicating whether the number of occurrences of the cache miss signal is equal to or greater than a threshold value to the DMA controller as the bus load information.

  [7] In the data processing system according to item 1, the CPU outputs a value of a program counter indicating an address of an instruction to be executed to the bus arbitration circuit. At this time, the bus load monitoring circuit stores the start value and range of the program counter in a routine or task with a small number of memory accesses from the CPU as a lookup table, and the input value of the program counter hits the table. The information regarding whether or not it has been transmitted is transmitted to the DMA controller as the bus load.

  [8] A program development system that supports development of a program using the data processing system according to item 4 as a target device includes a builder that converts a source code of a program operating on the target device into an execution format, and the program execution format. And an uploader for transferring onto the target device. The builder measures the number of memory accesses in the target device a plurality of times based on a simulator that simulates the target device and executes a program, and the execution result by the simulator, and stores memory from the CPU in the bus load monitoring circuit of the target device And a profiler that obtains the threshold of the number of accesses and the measurement cycle so that the program execution time is minimized. The uploader outputs a threshold value and a measurement cycle of the number of memory accesses from the CPU obtained by the profiler together with a program. As a result, the data processing system according to item 4 can use the threshold value and the measurement cycle of the memory access frequency that are adaptive to the execution of the program generated by the program development system.

  [9] A program development system for supporting development of a program using the data processing system according to item 5 as a target device, a builder for converting a source code of a program operating on the target device into an execution format, and the program execution format And an uploader for transferring the data to the target device. The builder simulates the target device and executes a program, and based on the execution result of the simulator, measures the number of memory accesses in the target device a plurality of times, and the buffer free capacity in the bus load monitoring circuit of the target device A profiler that obtains the threshold value of the integrated value and the measurement cycle so as to minimize the program execution time. The uploader outputs the threshold value and the measurement cycle of the integral value of the buffer free space obtained by the profiler together with the program. As a result, the data processing system according to item 5 can use the threshold value of the integral value of the buffer free space and the measurement cycle that are adaptive to the execution of the program generated by the program development system.

  [10] A program development system that supports development of a program using the data processing system according to item 6 as a target device, a builder for converting a source code of a program operating on the target device into an execution format, and the program execution format And an uploader for transferring the data to the target device. The builder measures the number of memory accesses in the target device a plurality of times based on the execution result of the simulator by simulating the target device and executing the program, and the number of cache misses in the bus load monitoring circuit of the target device And a profiler that calculates the program execution time to minimize the program execution time. The uploader outputs a threshold value and a measurement cycle of the cache miss number obtained by the profiler together with a program. As a result, the data processing system according to item 6 can use a threshold value and a measurement cycle for the number of cache misses that are adaptive to the execution of the program generated by the program development system.

  [11] A program development system that supports development of a program using the data processing system according to item 7 as a target device, a builder for converting a source code of a program operating on the target device into an execution format, and the program execution format And an uploader for transferring onto the target device. The builder measures the number of memory accesses in the target device a plurality of times based on the execution result of the simulator by simulating the target device and executing the program, and from the CPU in the bus load monitoring circuit of the target device. And a profiler for obtaining a look-up table indicating a start value and a range of a program counter in a routine or task having a low memory access frequency. The uploader outputs the look-up table obtained by the profiler together with the program. As a result, the data processing system according to item 7 can use a look-up table indicating a start value and a range of a program counter that is adaptive to the execution of the program generated by the program development system.

2. Details of Embodiments Embodiments will be further described in detail. DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments for carrying out the invention, and the repetitive description thereof will be omitted.

Embodiment 1
FIG. 1 illustrates a data processing system according to the first embodiment of the present invention. The data processing system 1 may be a single chip such as a data processor or a microcomputer, or may be an on-board multi-chip system. The data processing system 1 is illustrated with a development environment 2 as its program development system, and the data processing system 1 is also referred to as a target device 1 for convenience.

  The target device 1 includes a CPU 11, a DMA controller (DMAC) 12, a DRAM 14, a bus arbitration circuit 13, a program I / F 16, and a program dedicated RAM (Random Access Memory) 15. The DRAM 14 is not particularly limited, but is a synchronous DRAM that operates in clock synchronization.

  The target device 1 receives the program S05 from the development environment 2 via the program interface (program I / F) 16, stores the program S05 in the program dedicated RAM 15 or DRAM 14, and the CPU 11 reads the program S05 from the program dedicated RAM 15 or DRAM 14. The program S05 is executed. In the figure, the program is read from the program dedicated RAM 15. The CPU 11 and the DMA control device 12 are connected to the DRAM 14 via the bus 17 and the bus arbitration circuit 13. The bus arbitration circuit 13 performs arbitration of the bus occupation right in the CPU 11 or the DMA control device 12. The bus 17 is assumed to be an address and data bus. Although not particularly shown, it was understood that the cache memory was included in the block of the CPU 11.

  The development environment 2 includes an OS (operating system) 24 mounted on a host PC (personal computer) 25, and includes a builder 22 and an uploader 23 that operate on the OS 24, and a program 21 that is executed by the builder 22. The program 21 refers to a source program corresponding to the program S05 operating on the target device 1, and is converted into an execution format program S05 by the builder 22, and transferred to the target device 1 by the uploader 23. The target device 1 stores the program S05 transferred by the uploader 23 in the program dedicated RAM 15 or DRAM 14 via the program I / F 16.

  The present embodiment is characterized in that the bus arbitration circuit 13 includes a bus load monitoring circuit 131. The bus load monitoring circuit 131 monitors the bus load depending on the number of DRAM accesses from the CPU 11 and transmits a signal S03 regarding whether or not to change the data transfer amount to the DMA controller 12. The DMA controller 12 has a register for designating the data transfer amount, and sets a value related to the data transfer amount in the register according to the number of accesses per unit time. The register setting items are 32 bytes for C1, 64 bytes for C2, and 32 bytes / 64 bytes automatic switching for C3.

  FIG. 2 is a detailed view of the DMA controller 12. The DMA controller 12 includes various registers 124, a register control circuit 121, various control circuits 122, and a bus I / F 123. The various registers 124 accumulate information related to operation settings of the DMA control device 12. The register control circuit 121 reads and writes information in various registers 124. The various control circuits 122 control the behavior of the DMA control device 12, a request priority control unit that determines the priority of the DMA access request S02, an activation control unit that starts and ends DMA transfer, and DMA transfer A number control unit for counting or resetting the number of times is included.

  In the present invention, in response to a DMA transfer size designation request, the register control circuit 121 writes information relating to DMA transfer size designation to various registers 124. The various control circuits 122 read the contents of various registers 124 and various signals from the bus 17 in accordance with the DMA transfer request, and transmit a DMA access request S02 to the bus via the bus I / F 123 to each device.

  FIG. 3 is a detailed view of the various registers 124. The various registers 124 include a DMA control register 1241 that stores setting information related to the DMA transfer mode and transfer size, and a DMA transfer source / transfer destination setting that stores the address of the data transferred by the DMA transfer and the address of the transfer destination. Register 1242, DMA operation register 1243 for storing channel priority and DMA transfer status during DMA transfer, external devices such as USB (Universal Serial Bus) and SCI / F (Serial Communication Interface) It comprises a DMA extended resource register 1244 that designates a transfer request source or a transfer request destination when performing DMA transfer, and a DMA transfer number register 1245 that designates the number of DMA transfers. The DMA control register 1241 includes a DMA transfer size designation bit 12411, a DMA transfer mode designation bit 12412, other setting bits 12415, a reservation bit 12416, and the like. By changing the DMA transfer size designation bit, it is possible to select one of transfer size candidates in the cycle steal mode. Further, it is possible to select one of the cycle steal mode and the burst mode as the transfer mode by changing the DMA transfer mode designation bit.

  The present invention is characterized in that the DMA control register 1241 has a DMA transfer mode automatic switching bit 12414 and a DMA transfer size automatic switching bit 12413 in addition to the DMA transfer mode specifying bit 12412 and the DMA transfer size specifying bit 12411. By setting the DMA transfer mode automatic switching bit 12414 to 1, the value of the DMA transfer mode designated by the DMA transfer mode designation request S33 is used instead of the DMA transfer mode designated by the register write content S09 (about this) This will be described later with reference to FIG. 21). Also, by setting the DMA transfer size automatic switching bit 12413 to 1, the DMA transfer size value designated by the DMA transfer size designation request S03 is used instead of the DMA transfer size designated by the register write content S09.

  Further, the register control circuit 121 receives the DMA transfer size designation request S03, and the register control circuit 121 writes the register write contents including the DMA transfer size designation bit 12411 to the DMA control register 1241, so that the DMA transfer size designation bit 12411 is obtained. The changed value is written to. Thereafter, the various control circuits 122 read the register contents from the various registers 124 and read the DMA transfer size designation bit 12411 from the value, thereby transferring the data corresponding to the transfer size in the DMA in the cycle steal mode.

  FIG. 4 is a detailed diagram of the register control circuit 121. In addition to the conventional register control circuit 1212, the register control circuit 121 includes a register write content generation unit 1211, a DEMUX (demultiplexer) circuit 1213 that decomposes the register write content S 07 into each set content, and a MUX that synthesizes each set content. (Multiplexer) circuit 1214 is formed.

  In the present invention, when the register write content S07 is generated by the conventional register control circuit 1212, the register control circuit 121 decomposes the register write content S07 into each set content by the DEMUX circuit 1213. The register write content generation unit 1211 generates a new DMA transfer size designation bit from the DMA transfer size designation request S03 and the DMA transfer size designation bit S071 among the set contents.

  When the DMA transfer size designation request S03 is not input, the register write content generation unit outputs the DMA transfer size designation bit S071 disassembled from the DEMUX as a new DMA transfer size designation bit. If the DMA transfer size designation request S03 is input, the DMA transfer size is determined from the contents of the DMA transfer size designation request S03, the DMA transfer size designation bit to be written to the register is set, and a new DMA transfer size designation bit is set. Output. The MUX circuit 1214 synthesizes a new DMA transfer size designation bit and other setting contents decomposed by the DEMUX, and writes them in various registers 124 as register write contents S09.

  FIG. 5 is a detailed diagram of the bus arbitration circuit 13.

  An access request from the DMA controller 12 to the DRAM 14 (hereinafter referred to as a DMA access request S02) and an access request from the CPU 11 to the DRAM 14 (hereinafter referred to as a CPU access request S01) are stored in dedicated queue buffers 132 to 133, respectively. . The priority determination circuit 134 outputs a selection signal S13 from each access request S01 to S02 output from the queue buffers 132 to 133. The selection signal S13 here indicates which of the DMA access request S02 and the CPU access request S01 is to be output with priority. The selector 135 outputs either the DMA access request S02 or the CPU access request S01 according to the selection signal S13.

  In the present invention, the bus arbitration circuit 13 includes a bus load monitoring circuit 131. The bus load monitoring circuit 131 outputs a DMA transfer size designation request S03 from the clock signal S12 and the CPU access request S01.

  FIG. 6 is a detailed diagram of the bus load monitoring circuit 131. The counter 13102 increments the value by 1 when the clock signal S12 has passed one clock cycle. The conditional counter 13101 increments the value by 1 when the clock signal has passed one clock cycle and the CPU access request S01 is detected. The cycle storage memory 13107 stores a CPU access measurement cycle value S19. The value S19 of the periodic storage memory is generated by the development environment 2, transmitted together with the program S05 by the uploader 23 in the development environment 2, and transferred to the bus load monitoring circuit 131 in the bus arbitration circuit 13 via the program I / F16. . The comparator 13104 compares the value S15 of the counter with the value S19 of the cycle storage memory, and outputs a CPU access cycle signal S17 if the counter value S15 becomes equal to or greater than the CPU access measurement cycle S19. Reset the value. Thus, the CPU access measurement cycle can be measured by the counter 13102, and the time S14 when the CPU access request is detected within the CPU access measurement cycle can be measured by the conditional counter 13101. If the time S14 when the CPU access request is detected is smaller than the threshold value S18, the comparator 13103 determines that the CPU access request S01 is small, and the DMA transfer size designation request S16 when the CPU access request S01 is small, for example, 0/1. Output 1 in the signal. The sample & hold circuit 13105 reads the signal S17 of the CPU access measurement cycle, holds the value of the DMA transfer size designation request S16 for the next CPU access measurement cycle, and outputs it. Here, in the DMA transfer size designation request S16, 0 is a DMA transfer size of 32 bytes, and 1 is a DMA transfer size of 64 bytes. The threshold value S18 is generated by the development environment 2, transmitted by the uploader 23 together with the program S05, and transferred to the bus load monitoring circuit 131 in the bus arbitration circuit 13 via the program I / F16.

  FIG. 18 is a detailed diagram of the builder 22, and FIG. 19 is a calculation processing flow by the builder 22 of the DRAM access count threshold S18 and the measurement cycle S19 from the CPU in the bus load monitoring circuit 131. The builder 22 includes a compiler 221 that converts the program 21 from various languages such as C language and Java (registered trademark) language into machine language, and a linker 222 that connects the program 21 converted into machine language by the compiler 221 into an execution format. The simulator 223 executes the contents of the linker 222 on the PC 25 in a pseudo manner, and the profiler 224 measures the CPU access load from the program execution result on the simulator 223. Here, it is assumed that the simulator 223 has a function of simulating the cache memory 112 similar to that of the target device 1, and the profiler 224 can count the number of occurrences of cache misses during program execution on the simulator 223.

  The builder 22 first compiles the program 21 with the compiler 221 (F06), and creates a program execution format by linking with the linker 222 (F07). Next, the program is executed by the simulator 223 using the program execution format. The profiler 224 measures the number of cache misses in the program and the bus cycle interval of DRAM access from the DMA (F10, F11). In the figure, the symbol referred to by LP means that the process (F10) sandwiched between them is repeated a plurality of times. As for the bus cycle interval for DRAM access from the DMA, if a fixed bus cycle interval is accessed by the register of the DMA controller 12 by a program (F08), the bus cycle interval for DRAM access from the DMA is obtained from the register setting. (F09). The profiler 224 sets the DRAM access time interval from the DMA to the measurement cycle S19 (dT) of the DRAM access count from the CPU (F12).

The profiler 224 measures the program execution bus cycle T excluding the latency due to DRAM access (F10), obtains an average value from the number of cache misses and sets it as the number N of CPU access requests (F13). The profiler 224 calculates the threshold value n of the number of DRAM accesses from the CPU by the following formula (F14).
n = ceil (N × dT / T) (N <T−T / dT)
n = dT−1 (N ≧ T−T / dT)
Here, the function ceil (x) is a function for rounding up the decimal point of x. When n = 0, the CPU priority is completely given, and when n = dT, the DMA priority is given, and the meaning of switching the DMA transfer size is lost, so 1 ≦ n ≦ dT−1.

  The compiler 221 compiles a source file in which a routine for transferring the threshold value S18 and the measurement cycle S19 of the DRAM access count from the CPU 11 and the threshold value S18 and the measurement cycle S19 to the bus load monitoring circuit 131 is written. Link with other routines to create an executable file.

  As described above, the threshold S18 and the measurement cycle S19 of the DRAM access count from the CPU 11 in the bus load monitoring circuit 131 are calculated by the builder 22 and transferred to the target device 1, whereby the CPU priority is determined by the number of DRAM accesses from the CPU 11 in the program. Or DMAC priority can be determined.

  Since the number of DRAM accesses from the CPU 11 is basically smaller than the number of DRAM accesses from the DMAC 12, the threshold S18 of the number of DRAM accesses from the CPU 11 may be set to 1.

  FIG. 26 is a detailed diagram of the DRAM access request S04, which corresponds to the DMA access request S02 and the CPU access request S01. The breakdown of the access request S04 is the same as the known one, and is composed of an access request source identifier S041, an access destination memory address S042, an access size S043, and a read / write distinction S044. In some cases, write data S045 is also included. The bus load monitoring circuit 131 determines whether the access request data S01 has been sent and measures the bus load.

  FIG. 27 is a first operation timing chart of the DRAM 14. The upper part shows an operation timing chart T01 of the DRAM 14 when the transfer size is fixed to 32 bytes according to a known technique, and the lower part shows an operation timing chart T02 of the DRAM 14 when the transfer size is automatically switched according to the present invention. In the figure, HD means an initial operation required for setting a row address for DRAM 14 access, DMA 32B is a memory operation of DRAM 14 in a 32-byte cycle steal mode by DMAC, and DMA 64B is a memory of DRAM 14 in a 64-byte cycle steal mode by DMAC. Means movement.

  HD indicates an overhead time T03 for DRAM 14 access, DMA 32B indicates a time T04 required for 32-byte access, and DMA 64B indicates a time T05 required for 64-byte access. The initial value of the DMA transfer size in the present invention is 32 bytes.

  In the lower time chart of the present invention, after confirming that the CPU access is small in the CPU access measurement period T10, the DMA transfer amount is increased to 64 bytes from the DMA transfer amount switching timing T06. Although the DMA data transfer time itself takes twice as long as 32 bytes fixed, the overhead time due to HD is the same for both 32-byte access and 64-byte access. When it is performed twice, the access time can be shortened by the overhead time for 64-byte access.

  FIG. 28 is a second operation timing chart of the DRAM 14. The upper part shows a time chart T16 of the DRAM 14 when the transfer size is fixed to 64 bytes according to a conventional known technique, and the lower part shows a time chart T02 of the DRAM 14 when the transfer size is automatically switched according to the present invention. The initial value of the DMA transfer size in the present invention is 64 bytes. In the figure, CPU means the memory operation of the DRAM 14 by the CPU, and the meanings of HD, DMA 32B, and DMA 64B are the same as those in FIG.

  In the lower time chart of the present invention, after confirming that there are many CPU accesses in the CPU access measurement period T10, the DMA transfer amount is reduced to 32 bytes from the DMA transfer amount switching timing T06. When the 64 bytes are fixed, the CPU access is delayed as much as the DMA access is not completed. In the present invention, the DMA access time is the sum of the overhead time and the 32 byte access time. CPU access can be performed faster by the value obtained by subtracting the 32-byte access time from the 64-byte access time.

<< Embodiment 2 >>
FIG. 7 is a detailed diagram of the bus arbitration circuit 13 in the second embodiment of the present invention. In the present invention, the bus monitoring system in the bus load monitoring circuit 131 is different from the first embodiment. The queue buffer 133 on the CPU access request side outputs the buffer free capacity S20, and the bus load monitoring circuit 131 outputs the DMA transfer size designation request S03 from the clock signal S12 and the buffer free capacity S20. The bus load monitoring circuit 131 monitors the bus load related to CPU access by using the free capacity S20 of the queue buffer 133 that stores the CPU access request S01 instead of the CPU access request S01. For example, the write pointer and the read pointer in the queue buffer 133 are in an empty state (no stored data), the values match, the write pointer is incremented for each write, the read pointer is incremented for each read, and the read pointer is the value of the write pointer. Assuming that the buffer free capacity S20 is not overtaken, the difference between the value of the read pointer and the value of the read pointer is the buffer free space S20.

  FIG. 8 is a detailed diagram of the bus load monitoring circuit 131 of FIG. The integrator 13108 integrates the buffer free space S20 only during the CPU access measurement period S23. The comparator 13103 determines that the CPU access request S01 is small if the time integral value S21 of the buffer free capacity is larger than the threshold value S22, and the DMA transfer size designation request S16 when the CPU access request S01 is small, for example, in the 0/1 signal 1 is output. The sample & hold circuit 13105 reads the CPU access cycle signal S17, holds the DMA transfer size designation request value S16 for the next CPU access measurement cycle S23, and outputs it.

Note that the calculation processing by the builder 22 of the measurement interval S23 of the buffer free space time integral value in the bus load monitoring circuit 131 is the same as the calculation in the measurement cycle S19 of the DRAM access count from the CPU in the first embodiment. The threshold S22 (n) of the free capacity time integration value is obtained by the following calculation formula.
n = dtx-dT (dT <dtx <M (dT + 1))
Here, dtx is a desired value as the longest bus cycle number of DRAM access from the CPU, and M is a buffer maximum capacity. When n = 0, the CPU priority is completely given, and when n = MdT, the DMA priority is given, and the meaning of switching the DMA transfer size is lost. Therefore, 1 ≦ n <MdT.

  Since the number of DRAM accesses from the CPU is basically smaller than the number of DRAM accesses from the DMA, the threshold S22 of the buffer free capacity time integration value may be set to 1.

<< Embodiment 3 >>
FIG. 9 shows a data processing system (target device) 1 according to a third embodiment of the present invention together with its development environment 2. The difference from the first and second embodiments is that the CPU 11 outputs a cache miss signal S24 in addition to the CPU access request S01 to the bus load monitoring circuit 131 in the bus arbitration circuit 13, and the bus load monitoring circuit 131 The bus load is calculated from the signal S24 and a DMA transfer size designation request S03 is output. The bus load monitoring circuit 131 monitors the bus load related to CPU access by using the cache miss signal S24 instead of the CPU access request S01.

  FIG. 10 is a detailed view of the CPU 11 in FIG. The CPU core 111 makes a cache access request S25 to the cache memory 112, and the cache memory 112 transmits the in-cache data S26 to the CPU core 111 according to the content of the request S25. When a cache miss occurs, the cache memory 112 transmits a CPU access request S01 to the DRAM 14. The cache memory 112 has a function of outputting debug data S27 including a cache miss signal S24.

  In the third embodiment, the cache-related debugging data S27 output from the cache memory 112 is decomposed into each data by the DEMUX circuit 113, and the data is synthesized by the MUX circuit 114. At the same time, the cache miss signal S24 is monitored by the bus load. Transmit to the circuit 131.

  FIG. 11 is a detailed diagram of the bus arbitration circuit 13 in the third embodiment. The difference from the first and second embodiments is that the input of the bus load monitoring circuit 131 is not the CPU access request S01 or the buffer free capacity S20 but the cache miss signal S24.

  FIG. 12 is a detailed diagram of the bus load monitoring circuit 131 in the third embodiment. The difference from the first embodiment is that the conditional counter 13111 increments the value by 1 when the clock signal has passed one clock cycle and the cache miss signal S24 is 1.

  The comparator 13103 determines that the CPU access request S01 is small if the time when the cache miss signal S24 is 1 is smaller than the threshold value S29, and the DMA transfer size designation request S16 when the CPU access request S01 is small, for example, 0 / 1 in one signal is output only for the next CPU access measurement cycle S30. The sample & hold circuit 13105 reads the CPU access cycle signal S17, holds the DMA transfer size designation request value S16 for the next CPU access measurement cycle S30, and outputs it.

  The calculation processing by the builder 22 of the cache miss frequency threshold S29 and the measurement cycle S30 in the bus load monitoring circuit 131 is the same as the calculation of the DRAM access frequency threshold S18 from the CPU and the measurement cycle S19 in the first embodiment. It's okay.

<< Embodiment 4 >>
FIG. 13 illustrates a data processing system (target device) 1 according to a fourth embodiment of the present invention together with its development environment 2. The difference from the first to third embodiments is that the CPU 11 outputs the program counter value S31 in addition to the CPU access request S01 to the bus load monitoring circuit 131 in the bus arbitration circuit 13, and the bus load monitoring circuit 131 is programmed. The bus load is calculated from the counter value S31 and a DMA transfer size designation request S03 is output. The bus load monitoring circuit 131 monitors the bus load related to CPU access by using the value S31 of the program counter instead of the CPU access request S01.

  FIG. 14 is a detailed view of the CPU 11 in the fourth embodiment. A significant difference from the third embodiment is that the CPU-related debugging data S32 output from the CPU core 111 is decomposed into data groups by the DEMUX circuit 115, and the data group is synthesized by the MUX circuit 116, and at the same time, the data group Is transmitted to the bus load monitoring circuit 131.

  FIG. 15 is a detailed diagram of the bus arbitration circuit 13 in the fourth embodiment. Unlike the first to third embodiments, the bus load monitoring circuit 131 monitors the bus load related to CPU access by using the program counter value S31 instead of the CPU access request S01 and the clock signal S12. It is in place.

  FIG. 16 is a detailed diagram of the bus load monitoring circuit 131 in the fourth embodiment, and FIG. 17 is a processing flow of the bus load monitoring circuit 131 in the fourth embodiment. The bus load monitoring circuit 131 includes a lookup table 13114. The look-up table 13114 describes a program counter start value 1311141 and a range 131142 in a routine or thread having a high CPU access load in a program operating on the system. If the program counter value S31 is within the range 131142 from the program counter start value 1311141, it is determined that the CPU access request is small, and a DMA transfer size designation request when the CPU access request is small, for example, 1 in the 0/1 signal is set. , And output until the program counter S31 comes out of the range 131142.

  FIG. 20 is a flowchart of processing for creating the lookup table 13114 by the builder 22 in the fourth embodiment. The builder 22 first compiles the program 21 with the compiler 221 (F06), and creates the execution format of the program by linking with the linker 222 (F07). Next, the program is executed by the simulator 223 using the program execution format. The profiler 224 counts the number of cache miss occurrences in units of routines or threads in the program, and measures the start value 1311141 and the range 131142 of the program counter (F10). The simulator and profiler execute the program by changing the program parameters multiple times and measure the number of cache misses. An average value is obtained from the number of times of cache misses and is set as the number of CPU access requests (F22). The profiler 224 sorts the number of CPU access requests of the routine or task in ascending order, extracts the program counter start value 1311141 and the range 131142 in the routine or task with less CPU access, and creates the contents of the lookup table 13114. The profiler 224 converts the contents of the lookup table 13114 into a program source file, and rewrites the program source file to run a routine for transferring the contents of the lookup table 13114 to the bus load monitoring circuit 131 at the initialization of the program (F23). ).

  The compiler 221 compiles the source file in which the lookup table 13114 is written and the source file in which the routine for transferring the contents of the lookup table 13114 to the bus load monitoring circuit 131 is written (F15). 13114 is linked with another routine (F16), and an execution file is created.

  As described above, the look-up table 13114 is installed in the bus load monitoring circuit 131 and the value S31 of the program counter is read to increase the DMA transfer size and transfer efficiency with respect to, for example, a data read / write routine with a memory with a low CPU load. In a calculation routine with a high CPU load, it is possible to reduce the DMA transfer size and speed up memory access in the CPU.

<< Embodiment 5 >>
FIG. 21 illustrates a data processing system (target device) 1 according to a fifth embodiment of the present invention together with its development environment 2. The difference from the first to fourth embodiments is that in order to increase the DMA transfer efficiency, the bus load monitoring circuit 131 outputs a DMA transfer mode designation request S33 instead of the DMA transfer size designation request S03, and the DMA controller 12 Is to change the DMA transfer mode. In short, if the CPU access is low, that is, if the predetermined threshold is not exceeded, the DMA transfer mode is set to the burst mode, and if the CPU access is high, that is, if the predetermined threshold is exceeded, the DMA transfer mode is set to the cycle steal mode. Since the control method in this case can be classified very easily from the above description, a detailed description thereof will be omitted.

Embodiment 6
FIG. 22 illustrates a data processing system (target device) 1 according to the sixth embodiment of the present invention together with its development environment 2. The difference from the first to fifth embodiments is that the bus load monitoring circuit 131 outputs both the DMA transfer size designation request S03 and the DMA transfer mode designation request S33 in order to increase the DMA transfer efficiency. Changing the DMA transfer size and DMA transfer mode.

  FIG. 23 is a detailed diagram of the bus arbitration circuit 13 in the sixth embodiment. The difference from the first to fifth embodiments is that one bus load monitoring circuit is provided for each of the DMA transfer mode designation request and the DMA transfer size designation request. The DMA transfer mode can improve the DMA transfer efficiency compared to the DMA transfer size, but there is a risk of hindering the DRAM access from the CPU. Therefore, the DMA transfer mode designation request threshold is set for the DMA transfer size designation request. The DMA transfer mode designation request measurement cycle is set higher than the threshold and longer than the DMA transfer size designation request measurement cycle. Specifically, the DMA transfer mode designation request threshold and the measurement cycle are set to integer multiples of the DMA transfer size designation request threshold.

<< Embodiment 7 >>
FIG. 24 illustrates a data processing system (target device) 1 according to a seventh embodiment of the present invention together with its development environment 2. The difference from the first to sixth embodiments is that the CPU outputs a program counter value S31 in addition to the CPU access request S01, and the bus load monitoring circuit receives a DMA transfer size designation request S03 and a DMA transfer mode designation request. Both S33 are output, and the DMA transfer size and the DMA transfer mode in the DMA controller 12 are changed.

  FIG. 25 is a processing flow of the bus load monitoring circuit 131 in the seventh embodiment of the present invention. If the program counter value S31 is within the range 131142 from the program counter start value 131114 (F02), it is determined that the CPU access request S01 is small, and the DMA transfer size designation request S03 when the CPU access request S01 is small, for example, 0 1 in signal / 1 is output until the program counter value is out of range (F04 to F05). Further, if the value S03 of the program counter is in the top nth of the lookup table 13114 (F19), the lookup table 13114 is sorted in ascending order of the CPU access request S01. If the CPU access request S01 is small, the DMA transfer mode designation request S33, for example, 1 in the 0/1 signal is output until the program counter goes out of the range. Here, when the value of the DMA transfer mode designation request S07 is 0, the cycle steal mode is indicated, and when it is 1, the burst mode is indicated.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  The present invention can be widely applied not only to a microcomputer or data processor equipped with a DMAC but also to various SoCs. The development environment as a program development system is not limited to being constructed on a PC, but can be constructed on an engineering workstation or the like. The memory accessed by the CPU or DMAC is not limited to DRAM, and may be other memory.

1 is an overall view of a data processing system according to a first embodiment of the present invention. 1 is a detailed view of a data processing system according to a first embodiment of the present invention. FIG. 3 is a detailed view of various registers in the first embodiment of the present invention. FIG. 2 is a detailed diagram of a register control circuit according to the first embodiment of the present invention. FIG. 2 is a detailed diagram of a bus arbitration circuit in the first embodiment of the present invention. FIG. 3 is a detailed diagram of a bus load monitoring circuit according to the first embodiment of the present invention. It is a detailed diagram of the bus arbitration circuit in the second embodiment of the present invention. It is a detailed diagram of a bus load monitoring circuit in the second embodiment of the present invention. It is a whole view of the data processing system which is the 3rd Embodiment of this invention. It is a detailed view of CPU in the 3rd Embodiment of this invention. It is a detailed diagram of the bus arbitration circuit in the third embodiment of the present invention. It is a detailed diagram of the bus load monitoring circuit in the third embodiment of the present invention. It is a whole data processing system which is the 4th Embodiment of this invention. It is a detailed view of CPU in the 4th Embodiment of this invention. It is a detailed figure of the bus arbitration circuit in the 4th Embodiment of this invention. It is a detailed diagram of a bus load monitoring circuit in the fourth embodiment of the present invention. It is a processing flow of the bus load monitoring circuit in the 4th Embodiment of this invention. It is detail drawing of the builder in the 1st Embodiment of this invention. It is a calculation processing flow by the builder 22 of the threshold value S18 of DRAM access frequency in the 1st Embodiment of this invention, and the measurement period S19. It is the look-up table creation processing flow by the builder in the 4th Embodiment of this invention. FIG. 10 is an overall view of a data processing system according to a fifth embodiment of the present invention. It is a whole data processing system which is the 6th Embodiment of this invention. It is a detailed view of the bus load monitoring circuit in the sixth embodiment of the present invention. FIG. 10 is an overall view of a data processing system according to a seventh embodiment of the present invention. It is a processing flow of the bus load monitoring circuit in the 7th Embodiment of this invention. It is a detailed view of an access request to the DRAM in the first embodiment of the present invention. 3 is a first time chart of the DRAM according to the first embodiment of the present invention. 6 is a second time chart of the DRAM according to the first embodiment of the present invention.

Explanation of symbols

1 Target device 11 CPU
111 CPU Core 112 Cache 113 Cache Demultiplexer 114 Cache Multiplexer 115 CPU Core Demultiplexer 116 CPU Core Multiplexer 12 DMA Controller (DMAC)
121 Register Control Circuit 1211 Register Write Content Generation Unit 1212 Conventional Register Control Circuit 1213 Demultiplexer 1214 Multiplexer 122 Various Control Circuits 123 Bus I / F
124 Various registers 125 DMA controller internal bus 13 Bus arbitration circuit 131 Bus load monitoring circuit 13101 Conditional counter 13102 Timer counter 13103 Comparator for DMA transfer size determination 13104 Comparator for timer signal generation 13105 Sample & hold circuit 13106 CPU access Request number threshold storage memory 13107 CPU access request number measurement cycle storage memory 13108 Buffer free capacity time integrator 13109 Buffer free capacity time integration threshold storage memory 13110 Buffer free capacity time integration value measurement cycle storage memory 13111 Conditional counter for number of cache miss signals 13112 Cache miss signal count threshold storage memory 13113 Cache miss signal measurement cycle storage memory 13114 Look-up table 1311 1 Program counter start value 131,151 program counter range 132 queue for DMA queue buffer 133 CPU buffer 134 the priority decision circuit 135 selector 14 DRAM
15 Program dedicated RAM
16 Program I / F
17 Bus 2 Development Environment 21 Program 22 Builder 221 Compiler 222 Linker 223 Simulator 224 Profiler 23 Uploader 24 OS
25 PC
S01 CPU access request S02 DMA access request S03 DMA transfer size designation request S04 DRAM access S041 Access request source identifier S042 Access destination address S043 Access size S044 Read / write discriminator S045 Write data S05 Program execution format S06 In-program instruction S07 Register write Contents S071 DMA transfer size designation bit S08 Various signals S09 Register contents (after reflecting DMA transfer size designation request)
S10 Various register initialization signals S11 Register contents S12 Clock signal S13 Selection signal S14 CPU access request count S15 Timer counter signal S16 DMA transfer size designation request continuous value S17 Timer signal S18 CPU access request count threshold signal S19 CPU access request count measurement cycle Signal S20 CPU queue buffer free capacity S21 CPU queue buffer free capacity time integration value S22 CPU queue buffer free capacity time integration threshold S23 CPU queue buffer free capacity time integrated value measurement cycle S24 Cache miss signal S25 Cache access request S26 Cache Internal data S27 Cache-related debugging data S28 Number of cache miss signals S29 Cache miss signal number threshold S30 Cache miss signal number measurement cycle S31 Program counter value S32 CPU-related debugging data S33 DMA transfer mode designation request C1 DMA transfer size setting 32 bytes C2 DMA transfer size 64 bytes setting C3 DMA transfer size 32 bytes / 64 bytes automatic switching setting C4 DMA transfer cycle steal mode setting C5 DMA transfer burst mode setting C6 DMA transfer cycle steal / burst automatic switching mode setting C7 DMA transfer amount / transfer method automatic switching mode setting F01 Program counter start value + range calculation processing F02 Program counter value judgment processing F03 Lookup table full text read completion judgment Process F04 DMA transfer size 0 designation process F05 DMA transfer size 1 designation process F06 Program compilation process F07 Program link process F08 DM A access interval determination processing F09 Processing for obtaining DMA access interval from register set value F10 Simulation execution processing F11 Processing for obtaining DMA access interval from profiler measurement result F12 CPU access measurement interval calculation processing F13 CPU access request count average value calculation processing F14 CPU access Request threshold calculation process F15 Program recompilation process F16 Program relink process F17 Program upload process F18 Lookup table creation process F19 Lookup table rank determination process F20 DMA transfer mode 0 setting process F21 DMA transfer mode 1 setting process F22 CPU access count calculation Processing T01 Time chart when DMA transfer size is fixed to 32 bytes T02 Time chart when DMA transfer size is automatically switched T03 D RAM access overhead time T04 Time required for 32-byte DRAM access by DMA T05 Time required for 64-byte DRAM access by DMA T06 DMA transfer amount switching timing boundary line T07 DMA transfer amount switching timing boundary mark T08 Transfer at DMA transfer size automatic switching Boundary line indicating completion T09 Boundary line indicating transfer completion when DMA transfer size is fixed to 32 bytes T10 Arrow indicating CPU access measurement period T11 Access time difference between DMA transfer size automatic switching and fixed time T12 DRAM access from CPU Time T13 Boundary line indicating completion of CPU access during DMA transfer size automatic switching T14 Boundary line indicating CPU access completion when DMA transfer size is fixed T15 CP between DMA transfer size automatic switching and fixed time Access time difference T16 DMA transfer size 64-byte fixed at the time chart

Claims (11)

In a data processing system having a DMA control device having a register in which a data transfer amount and a data transfer method are set, and a bus arbitration circuit for arbitrating a bus occupation right between the CPU or the DMA control device in accessing a memory,
The bus arbitration device includes a bus load monitoring circuit that periodically measures a bus load due to access to the memory from the CPU and transmits the bus load information to the DMA control device,
The data processing system, wherein the DMA controller performs control to reduce a data transfer amount by data transfer control when the bus load information received from the bus load monitoring circuit exceeds a predetermined bus load.   2. The data processing system according to claim 1, wherein the control for reducing the data transfer amount by the data transfer control is a control for reducing a single data transfer amount in the cycle steal mode.   2. The data processing system according to claim 1, wherein the control for reducing the data transfer amount by the data transfer control is control for changing a data transfer control mode from a burst mode to a cycle steal mode.   2. The data processing system according to claim 1, wherein the bus load monitoring circuit measures the number of memory accesses from the CPU in a predetermined time and obtains a signal indicating whether the number of accesses is equal to or greater than a threshold value as the bus load information. The bus arbitration device further includes a buffer that temporarily accumulates memory access requests from the CPU and transmits a free storage capacity to the bus monitoring circuit;
2. The data processing system according to claim 1, wherein the bus load monitoring circuit transmits, as the bus load information, information indicating whether or not an integrated value of the buffer free capacity of the buffer at a certain time is equal to or greater than a threshold value to the DMA controller. . The CPU includes a cache memory that transmits a cache miss signal to the bus arbitration circuit when a cache miss hit occurs.
2. The bus load monitoring circuit measures the number of occurrences of a cache miss signal in a predetermined time, and transmits information indicating whether the number of occurrences of a cache miss signal is equal to or greater than a threshold to the DMA controller as the bus load information. Data processing system. The CPU outputs a value of a program counter indicating an address of an instruction to be executed to the bus arbitration circuit,
The bus load monitoring circuit stores a start value and a range of a program counter in a routine or task with a small number of memory accesses from the CPU as a lookup table, and whether or not the input value of the program counter hits the table The data processing system according to claim 1, wherein the information regarding is transmitted to the DMA controller as the bus load. A program development system that supports development of a program using the data processing system according to claim 4 as a target device,
A builder for converting a source code of a program operating on the target device into an execution format;
An uploader for transferring the program execution format onto the target device,
The builder simulates a target device and executes a program;
Based on the execution result by the simulator, the number of memory accesses in the target device is measured a plurality of times, and the threshold value and the measurement cycle of the number of memory accesses from the CPU in the bus load monitoring circuit of the target device are minimized. A profiler that seeks to be
The program uploading system, wherein the uploader outputs a threshold value and a measurement cycle of the number of memory accesses from the CPU obtained by the profiler together with a program. A program development system that supports development of a program using the data processing system according to claim 5 as a target device,
A builder for converting a source code of a program operating on the target device into an execution format;
An uploader for transferring the program execution format onto the target device,
The builder simulates a target device and executes a program;
Based on the execution result by the simulator, the number of times of memory access in the target device is measured a plurality of times, and the threshold value and the measurement cycle of the integral value of the buffer free capacity in the bus load monitoring circuit of the target device are minimized. A profiler that seeks to be
The program development system, wherein the uploader outputs a threshold value and a measurement cycle of the integral value of the buffer free space obtained by the profiler together with a program. A program development system that supports development of a program using the data processing system according to claim 6 as a target device,
A builder for converting a source code of a program operating on the target device into an execution format;
An uploader for transferring the program execution format onto the target device,
The builder simulates a target device and executes a program;
Based on the execution result by the simulator, the number of memory accesses in the target device is measured a plurality of times, and the threshold for the number of cache misses and the measurement cycle in the bus load monitoring circuit of the target device are set so that the program execution time is minimized. A profiler for which
The program uploading system, wherein the uploader outputs a threshold value and a measurement cycle of the cache miss number obtained by the profiler together with a program. A program development system for supporting development of a program using the data processing system according to claim 7 as a target device,
A builder for converting a source code of a program operating on the target device into an execution format;
An uploader for transferring the program execution format onto the target device,
The builder simulates a target device and executes a program;
Based on the execution result by the simulator, the number of memory accesses in the target device is measured a plurality of times, and the start value and range of the program counter in a routine or task with a small number of memory accesses from the CPU in the bus load monitoring circuit of the target device And a profiler for obtaining a look-up table indicating
The uploader is a program development system that outputs a lookup table obtained by the profiler together with a program.

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