JP4867652B2 - Detection apparatus and method, and reception apparatus - Google Patents

Description

  The present invention relates to a detection apparatus and method and a reception apparatus, and more particularly to a detection apparatus and method and a reception apparatus that can detect a frequency error of a carrier wave more accurately.

  In recent years, a modulation scheme called an orthogonal frequency division multiplexing (OFDM) scheme has been used as a scheme for transmitting digital signals. This OFDM system is a system that prepares a number of orthogonal carriers within the transmission band, assigns data to the amplitude and phase of each carrier, and performs digital modulation using PSK (Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). .

  In the OFDM system, signals are transmitted in symbol units called OFDM symbols (hereinafter also simply referred to as symbols). An example of the OFDM symbol is shown in FIG.

  In FIG. 1, the range of the arrow described as “OFDM symbol” indicates a section occupied by one OFDM symbol. Further, as described as “guard interval” and “effective symbol” in FIG. 1, the OFDM symbol includes a guard interval (a section from A to B in FIG. 1) and an effective symbol (B in FIG. 1). To C). The guard interval is obtained by copying the waveform of the portion after the effective symbol (the hatched portion in FIG. 1) by a predetermined ratio and adding it to the position immediately before the effective symbol. By adding this guard interval, it is possible to remove the influence of the multipath by performing appropriate signal processing on the receiving apparatus side for a multipath shorter than the guard interval.

  Due to these characteristics, the OFDM system is often applied to terrestrial digital broadcasting that is strongly affected by multipath interference. As terrestrial digital broadcasting adopting such an OFDM scheme, there are standards such as DVB-T (Digital Video Broadcasting-Terrestrial) and ISDB-T (Integrated Services Digital Broadcasting-Terrestrial).

For example, in mode 3 of the ISDB- _TSB standard, 512 carriers are included in the effective symbol, and the interval between the carriers is 125 / 126≈0.992 kHz. Data is modulated on 433 carriers out of 512 carriers in the effective symbol. The guard interval is a signal having a time length of any ratio of 1/4, 1/8, 1/16, and 1/32 of the effective symbol.

In the OFDM system, generally, a transmission unit called an OFDM transmission frame configured by a plurality of consecutive OFDM symbols is defined. For example, in the ISDB- _TSB standard, one OFDM transmission frame is composed of 204 OFDM symbols.

  By the way, in the OFDM system, an error (hereinafter referred to as a carrier frequency error) may occur in the frequency of the carrier wave between the transmission side and the reception side. Here, the carrier frequency error will be described with reference to FIGS. 2 represents the frequency of the carrier wave before being modulated by the carrier frequency in the transmission device, FIG. 3 represents the frequency of the carrier wave modulated by the carrier frequency fc in the transmission device, and FIG. It represents the frequency of the carrier wave after being demodulated. Δf represents the frequency interval of the carrier wave.

  Each carrier wave of the OFDM signal is modulated by the transmission device with the carrier frequency fc and transmitted to the reception device. When the receiving apparatus can demodulate the received signal accurately with the carrier frequency fc, each carrier can be returned to the state shown in FIG. However, there are many cases where it is not possible to accurately demodulate at the carrier frequency fc due to the performance of the receiving device, and in this case, each carrier is demodulated at the frequency of the carrier frequency fc + carrier frequency error fe. As a result, as shown in FIG. 4, each carrier wave is demodulated at a position shifted by the carrier frequency error fe.

  Therefore, conventionally, it has been proposed to detect and correct a carrier frequency error using a pilot signal inserted in an OFDM signal (see, for example, Patent Document 1).

  Pilot signals are inserted for synchronization and demodulation of receiving devices such as CP (Continual Pilot), SP (Scattered Pilot), TMCC (Transmission and Multiplexing Configuration Control), TPS (Transmission Parameter Signaling), and AC (Auxiliary Control). Or a signal inserted into a plurality of carriers in an effective symbol in order to transmit control information, additional information, etc. The phase and amplitude of the pilot signal, the number of pilot signals included in the effective symbol, And the arrangement pattern of the insertion position is determined in advance by the standard.

For example, when the carrier modulation scheme is QPSK in mode 3 of the ISDB- _TSB standard, TMCC pilot signals and AC pilot signals are included in 12 of the 512 carriers included in one effective symbol. Yes. For example, in the segment of segment No. 0, the TMCC pilot signals are arranged at the 101st, 131st, 286th, and 349th numbers as indicated by the index number of the carrier within the 433 ranges in which the signal is modulated. AC pilot signals are arranged at Nos. 7, 89, 206, 209, 226, 244, 377, and 407, respectively.

  Here, an example of a conventional carrier frequency error detection method will be described with reference to FIGS.

  A range 11 in FIG. 5 indicates a range of effective carrier frequency on the transmission side. A solid line arrow in the range 11 indicates a carrier wave including a data signal such as an image and a sound, and a dotted line arrow indicates a carrier wave including a pilot signal. When a carrier frequency error occurs on the receiving side, the effective carrier frequency range is shifted by the carrier frequency error, and the carrier frequency including the pilot signal included therein is also shifted by the carrier frequency error.

  In the conventional method, within the predetermined frequency range, for example, as shown in the ranges 12 to 16 in FIG. 5, the effective carrier frequency range is shifted by the carrier frequency interval Δf while the carrier frequency is changed. A correlation value representing a correlation between a pilot signal and a signal included in a carrier wave (hereinafter referred to as a virtual pilot carrier wave) corresponding to the position of the pilot signal when shifted is calculated, and the carrier frequency is calculated based on the calculated correlation value. An error is required. Hereinafter, the frequency for shifting the carrier wave is referred to as an offset frequency.

  FIG. 6 shows an example of the relationship between the offset frequency and the correlation value. The horizontal axis in FIG. 6 represents the correlation value, and the vertical axis represents the offset frequency. When the offset frequency and the carrier frequency error match, the pilot value is actually included in the virtual pilot carrier, and the correlation value increases. On the other hand, when the offset frequency and the carrier frequency error do not match, the virtual pilot carrier includes a data signal whose phase and amplitude vary almost randomly, and thus the correlation value becomes small. Therefore, as shown by an arrow P1 in FIG. 6, an offset frequency that has a larger correlation value than other offset frequencies appears. As a result, the offset frequency that maximizes the correlation value is detected as a carrier frequency error.

  However, since the total number of TMCC pilot signals and AC pilot signals included in one symbol is very small, 3 in mode 1 and 12 in mode 3, the correlation value is calculated only for one symbol. The value peak may not appear clearly. Therefore, in the invention described in Patent Document 1, it has been proposed to accurately detect a carrier frequency error by cumulatively adding correlation values over several symbols (hereinafter also referred to as cumulative addition). Accordingly, as shown in FIG. 7, the peak value of the correlation value clearly appears as the number of symbols to which the correlation value is cumulatively added, and the carrier frequency error can be detected with high accuracy.

JP 2004-304453 A

  However, in the invention described in Patent Document 1, since the reliability of the correlation value is not verified, in other words, the reliability of the detection result of the carrier frequency error is not verified. When trying to synchronize with a difficult channel, the offset frequency at which the correlation value is maximized is detected, and the carrier frequency error may be erroneously detected.

  The present invention has been made in view of such a situation, and makes it possible to detect a carrier frequency error more accurately.

A detection apparatus according to a first aspect of the present invention is a detection apparatus for detecting a frequency error of a carrier wave of an OFDM signal, and for each offset frequency included in the first frequency range, the carrier wave frequency is only the offset frequency. Correlation value calculating means for calculating a correlation value representing a correlation between a signal included in a carrier wave corresponding to the position of the pilot signal when shifted and the pilot signal; a maximum value of the correlation value; a second largest value; Reliability detection means for detecting the reliability of the correlation value based on the difference or ratio, and the offset frequency at which the reliability is equal to or greater than a predetermined threshold and the correlation value is maximized as the frequency error. and a frequency error detection means is provided for detecting the correlation value calculation means, in a range of the first frequency, the reliability is greater than or equal to the threshold value the If the offset frequency is not detected, the correlation value is calculated for each offset frequency included in the second frequency range wider than the first frequency range, and the frequency error detecting means Within the frequency range, the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximized is detected as the frequency error.

  The correlation value calculating means accumulates and adds the correlation values by one OFDM symbol until the reliability reaches a predetermined threshold or more, and the reliability detection means accumulates the correlation value by one OFDM symbol. Each time it is added, the reliability is detected based on the difference or ratio between the maximum value of the accumulated correlation value and the second largest value, and the frequency error detection means The offset frequency at which the cumulatively added correlation value becomes maximum can be detected as the frequency error when the threshold value is exceeded.

  The correlation value calculating means cumulatively adds the correlation values for a predetermined number of first OFDM symbols, and the reliability detecting means has the correlation value calculated for the first OFDM symbol number cumulatively added. The reliability is detected based on the difference or ratio between the maximum value and the second largest value, and the frequency error detection means causes the reliability of the correlation value to be cumulatively added for the first number of OFDM symbols. The offset frequency at which the degree is equal to or greater than the threshold and the correlation value cumulatively added by the number of the first OFDM symbols is maximized can be detected as the frequency error.

  When the correlation frequency calculation means does not detect the offset frequency at which the reliability with respect to the correlation value cumulatively added for the number of the first OFDM symbols is equal to or greater than the threshold, the first OFDM symbol number The correlation values for the second number of the second OFDM symbols are cumulatively added, and the reliability detection means causes the maximum value and the second largest value of the correlation values cumulatively added for the number of the second OFDM symbols. The reliability is detected based on a difference or ratio between the frequency error detection means, and the frequency error detection means has the reliability for the correlation value cumulatively added for the second number of OFDM symbols equal to or greater than the threshold, and The offset frequency that maximizes the correlation value cumulatively added for the second number of OFDM symbols can be detected as the frequency error.

  The frequency error detecting means can determine that the frequency of the carrier wave cannot be synchronized when the reliability is less than a predetermined threshold.

A detection method or program according to a first aspect of the present invention is a detection method for detecting a frequency error of a carrier wave of an OFDM signal or a program for causing a computer to execute a process of detecting a frequency error of a carrier wave of an OFDM signal . For each offset frequency included in the frequency range, the correlation value representing the correlation between the pilot signal and the signal included in the carrier corresponding to the position of the pilot signal when the frequency of the carrier is shifted by the offset frequency And the reliability of the correlation value is detected based on the difference or ratio between the maximum value of the correlation value and the second largest value, the reliability is equal to or greater than a predetermined threshold value, and the correlation value There detecting the offset frequency with the maximum as the frequency error in the range of the first frequency, the reliability is the threshold value or less If the offset frequency is not detected, the correlation value is calculated for each offset frequency included in the range of the second frequency wider than the range of the first frequency, and within the range of the second frequency And detecting the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximized as the frequency error .

The receiving apparatus according to the second aspect of the present invention is a receiving apparatus that receives an OFDM signal. For each offset frequency included in the predetermined frequency range, for each offset frequency included in the first frequency range, A correlation value calculating means for calculating a correlation value representing a correlation between a signal included in a carrier wave corresponding to a position of a pilot signal when the frequency of the carrier wave is shifted by the offset frequency and the pilot signal; Based on the difference or ratio between the maximum value and the second largest value, reliability detection means for detecting the reliability of the correlation value, the reliability is equal to or greater than a predetermined threshold value, and the correlation value is maximum And a frequency error detecting means for detecting the offset frequency as the frequency error , wherein the correlation value calculating means is in the first frequency range. When the offset frequency at which the reliability is equal to or higher than the threshold is not detected, the correlation value is calculated for each offset frequency included in the second frequency range wider than the first frequency range, The frequency error detecting means detects, as the frequency error, the offset frequency at which the reliability is not less than a predetermined threshold and the correlation value is maximum within the range of the second frequency.

In the first aspect of the present invention, for each offset frequency included in the first frequency range, the frequency of the carrier is included in the carrier corresponding to the position of the pilot signal when the frequency is shifted by the offset frequency. A correlation value representing a correlation between a signal and the pilot signal is calculated, and a reliability of the correlation value is detected based on a difference or ratio between a maximum value of the correlation value and a second largest value, and the reliability Is detected as the frequency error , and in the range of the first frequency, the offset frequency at which the reliability is equal to or higher than the threshold is detected. If not, the correlation value is calculated for each offset frequency included in the second frequency range wider than the first frequency range. Is, within the range of the second frequency, the reliability becomes higher than a predetermined threshold value, and the offset frequency by the correlation value is maximized is detected as the frequency error.

In the second aspect of the present invention, for each offset frequency included in the range of the first frequency, the frequency of the carrier is included in the carrier corresponding to the position of the pilot signal when shifted by the offset frequency. A correlation value representing a correlation between a signal and the pilot signal is calculated, and a reliability of the correlation value is detected based on a difference or ratio between a maximum value of the correlation value and a second largest value, and the reliability Is detected as the frequency error , and in the range of the first frequency, the offset frequency at which the reliability is equal to or higher than the threshold is detected. If not, the correlation value is calculated for each offset frequency included in the second frequency range wider than the first frequency range. Is, within the range of the second frequency, the reliability becomes higher than a predetermined threshold value, and the offset frequency by the correlation value is maximized is detected as the frequency error.

  As described above, according to the first aspect or the second aspect of the present invention, the frequency error of the carrier wave can be detected. In particular, according to the first aspect or the second aspect of the present invention, the frequency error of the carrier wave can be detected more accurately.

  Embodiments of the present invention will be described below. Correspondences between constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is to confirm that the embodiments supporting the present invention are described in the detailed description of the invention. Accordingly, although there are embodiments that are described in the detailed description of the invention but are not described here as embodiments corresponding to the constituent elements of the present invention, It does not mean that the embodiment does not correspond to the configuration requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

The detection device according to the first aspect of the present invention (for example, the broadband carrier frequency error detection circuit 125 in FIG. 9) is a detection device that detects a frequency error of a carrier wave of an OFDM (Orthogonal Frequency Division Multiplexing) signal. For each offset frequency included in the range, a correlation value representing the correlation between the pilot signal and the signal included in the carrier corresponding to the position of the pilot signal when the frequency of the carrier is shifted by the offset frequency is calculated. Correlation value calculating means (for example, pilot correlation operation circuits 205-1 to 205- (2n + 1) in FIG. 9) and the correlation based on the difference or ratio between the maximum correlation value and the second largest value. A reliability detection means for detecting the reliability of the value (for example, the reliability detection circuit 210 in FIG. 9); Frequency error detection means (for example, error detection circuit 211 in FIG. 9) that detects the offset frequency at which the correlation value is maximized as the frequency error , and the correlation value calculation means includes the first frequency. If the offset frequency at which the reliability is equal to or higher than the threshold is not detected in the range, the correlation value is calculated for each offset frequency included in the second frequency range wider than the first frequency range. The frequency error detecting means calculates and detects, as the frequency error, the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximum within the range of the second frequency.

A detection method or program according to the first aspect of the present invention is a detection method for detecting a frequency error of a carrier wave of an OFDM signal or a program for causing a computer to execute a process of detecting a frequency error of a carrier wave of an OFDM signal. For each offset frequency included in the first frequency range, the correlation between the pilot signal and the signal included in the carrier corresponding to the position of the pilot signal when the frequency of the carrier is shifted by the offset frequency A correlation value is calculated (for example, steps S101 to S105 in FIG. 12 and step S153 in FIG. 15), and the reliability of the correlation value is based on the difference or ratio between the maximum value of the correlation value and the second largest value. (For example, step S156 in FIG. 15), the reliability is equal to or higher than a predetermined threshold value, and the correlation There detecting the offset frequency with the maximum as the frequency error in (e.g., step S158 in FIG. 15), the first range of frequencies, the offset frequencies the reliability is equal to or greater than the threshold value is not detected In this case, the correlation value is calculated for each offset frequency included in the second frequency range wider than the first frequency range, and the reliability is equal to or higher than a predetermined threshold within the second frequency range. And detecting the offset frequency that maximizes the correlation value as the frequency error .

A receiving apparatus according to the second aspect of the present invention (for example, receiving apparatus 101 in FIG. 8) is a receiving apparatus that detects a frequency error of a carrier wave of an OFDM signal, and for each offset frequency included in the first frequency range. Correlation value calculation means for calculating a correlation value representing the correlation between the pilot signal and a signal included in the carrier wave corresponding to the position of the pilot signal when the frequency of the carrier wave is shifted by the offset frequency (for example, FIG. 9). Pilot correlation calculation circuits 205-1 to 205- (2n + 1)) and the reliability detection for detecting the reliability of the correlation value based on the difference or ratio between the maximum value of the correlation value and the second largest value. Means (for example, the reliability detection circuit 210 in FIG. 9) and the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximized. Frequency error detection means (for example, the error detection circuit 211 in FIG. 9) that detects the wave number error, and the correlation value calculation means has the reliability that is equal to or higher than the threshold value in the first frequency range. When the offset frequency is not detected, the correlation value is calculated for each offset frequency included in the second frequency range wider than the first frequency range, and the frequency error detecting means Within the frequency range, the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximized is detected as the frequency error.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 8 is a block diagram showing an embodiment of the receiving apparatus 101 to which the present invention is applied. The receiving apparatus 101 includes an antenna 111, a tuner 112, a band pass filter (BPF) 113, an A / D (Analog / Digital) conversion circuit 114, a DC (Direct Current) cancellation circuit 115, a digital orthogonal conversion circuit 116, and a carrier frequency error correction. Circuit 117, FFT operation circuit 118, FFT window phase error correction circuit 119, equalization circuit 120, deinterleave / error correction circuit 121, transport stream generation circuit 122, timing synchronization circuit 123, narrowband carrier frequency error detection circuit 124, A broadband carrier frequency error detection circuit 125, a numerically controlled oscillation circuit (NCO) 126, a frame synchronization circuit 127, a transmission control information decoding circuit 128, and a TS clock generation circuit 129 are configured.

  The antenna 111 receives a digital broadcast broadcasted by a broadcast station and supplies the digital broadcast to the tuner 112 as an RF (Radio Frequency) signal.

  The tuner 112 includes a multiplier 112 a and a local oscillator 112 b, converts the RF signal supplied from the antenna 111 to an IF (Intermediate Frequency) signal, and supplies the IF signal to the BPF 113.

  The BPF 113 filters the IF signal supplied from the tuner 112 and supplies it to the A / D conversion circuit 114.

  The A / D conversion circuit 114 A / D converts the IF signal supplied from the BPF 113 and supplies the digitized IF signal to the DC cancellation circuit 115.

  The DC cancellation circuit 115 removes the DC component of the IF signal supplied from the A / D conversion circuit 114 and supplies the IF signal from which the DC component has been removed to the digital quadrature demodulation circuit 116.

  The digital orthogonal demodulation circuit 116 orthogonally demodulates the IF signal supplied from the DC cancellation circuit 115 with a carrier signal having a predetermined carrier frequency to generate a baseband OFDM signal (hereinafter also referred to as an OFDM time domain signal). The OFDM time domain signal generated by the digital quadrature demodulation circuit 116 is a complex signal composed of an I-channel signal with a real axis component and a Q-channel signal with an imaginary axis component. The digital orthogonal demodulation circuit 116 supplies the generated OFDM time domain signal to the carrier frequency error correction circuit 117.

  The carrier frequency error correction circuit 117 multiplies the OFDM time domain signal supplied from the digital quadrature demodulation circuit 116 by the carrier frequency error correction signal supplied from the NCO 126 to obtain the carrier frequency error component of the OFDM time domain signal. Remove. The carrier frequency error correction circuit 117 supplies the OFDM time domain signal from which the carrier frequency error component has been removed to the FFT operation circuit 118, the timing synchronization circuit 123, and the narrowband carrier frequency error detection circuit 124.

  The FFT operation circuit 118 performs an FFT operation on the OFDM time domain signal supplied from the carrier frequency error correction circuit 117 based on the FFT operation start timing instruction from the timing synchronization circuit 123, and is orthogonally modulated to each carrier wave. The extracted data is extracted, and the extracted data is supplied to the FFT window phase error correction circuit 119. The signal output from the FFT operation circuit 118 is a so-called frequency domain signal after being subjected to FFT. Therefore, hereinafter, the signal after the FFT calculation is referred to as an OFDM frequency domain signal.

  The FFT window phase error correction circuit 119 is a phase rotation component generated due to a shift between the actual boundary position of the OFDM symbol and the start timing of the FFT calculation range with respect to the OFDM frequency domain signal supplied from the FFT calculation circuit 118. Perform the correction. That is, the FFT window phase error correction circuit 119 corrects the phase of a deviation that occurs with an accuracy of a sampling period or less. Specifically, the OFDM frequency domain signal output from the FFT operation circuit 118 is complex-multiplied with the phase correction signal of the complex signal supplied from the timing synchronization circuit 123 to perform phase rotation correction. The OFDM frequency domain signal subjected to phase rotation correction is supplied to an equalization circuit 120, a broadband carrier frequency error detection circuit 125, a frame synchronization circuit 127, and a transmission control information decoding circuit 128.

  The equalization circuit 120 identifies a pilot signal based on the OFDM symbol number supplied from the frame synchronization circuit 127, and uses the identified pilot signal to perform phase equalization and amplitude equalization of the OFDM frequency domain signal. The OFDM frequency domain signal subjected to phase equalization and amplitude equalization is supplied to the deinterleave / error correction circuit 121.

  The deinterleave / error correction circuit 121 detects information modulated on each carrier wave of the OFDM frequency domain signal supplied from the equalization circuit 120 according to the modulation method, performs demapping processing, etc. Is decrypted. Thereafter, the deinterleave / error correction circuit 121 performs error correction processing on the decoded data and supplies the OFDM demodulated data to the transport stream generation circuit 122.

The transport stream generation circuit 122 multiplexes a predetermined data signal with respect to the OFDM demodulated data supplied from the deinterleave / error correction circuit 121 based on the timing defined by the broadcasting system, and also deinterleave / error. Smoothing processing is performed so that intermittent OFDM demodulated data supplied from the correction circuit 121 is smoothed and output continuously using the TS clock supplied from the TS clock generation circuit 129, and MPEG-2 transport is performed. Output stream (TS). Note that the predetermined data signal to be multiplexed with respect to the OFDM demodulated data is, for example, a null packet that is not transmitted by the OFDM signal in the ISDB- _TSB standard.

  The timing synchronization circuit 123 specifies the boundary position of the OFDM symbol based on the OFDM time domain signal supplied from the carrier frequency error correction circuit 117 and obtains the timing at which the FFT operation circuit 118 should perform the FFT operation. The timing is notified to the FFT arithmetic circuit 118. Further, the timing synchronization circuit 123 estimates a clock frequency error resulting from the difference between the data generation clock frequency of the OFDM time domain signal and the clock frequency of the receiving apparatus 101, and corrects the clock frequency error signal indicating this estimated value to the FFT window phase error correction. This is notified to the circuit 119 and the TS clock generation circuit 129. Further, the timing synchronization circuit 123 notifies the control circuit 202 of the broadband carrier frequency error detection circuit 125 described later of the boundary position of the identified OFDM symbol.

  The narrowband carrier frequency error detection circuit 124 is based on the OFDM time domain signal supplied from the carrier frequency error correction circuit 117 and has a narrowband carrier frequency with an accuracy of ± 1/2 or less of the carrier frequency interval (eg, 0.992 kHz). The error is detected, and the detected narrow band carrier frequency error is supplied to the NCO 126.

  The broadband carrier frequency error detection circuit 125 detects a broadband carrier frequency error with accuracy of the carrier frequency interval (eg, 0.992 kHz) based on the OFDM frequency domain signal supplied from the FFT window phase error correction circuit 119, and detects the detected broadband. A carrier frequency error is supplied to the NCO 126.

  The NCO 126 adds the narrowband carrier frequency error supplied from the narrowband carrier frequency error detection circuit 124 and the wideband carrier frequency error supplied from the wideband carrier frequency error detection circuit 125, and the carrier frequency error obtained by addition is added. Accordingly, a carrier frequency error correction signal whose frequency increases or decreases is generated, and the generated carrier frequency error correction signal is supplied to the carrier frequency error correction circuit 117. The carrier frequency error correction signal is a complex signal.

  The frame synchronization circuit 127 detects a synchronization word included in a predetermined position of the OFDM transmission frame based on the OFDM frequency domain signal supplied from the FFT window phase error correction circuit 119, and identifies the start timing of the OFDM transmission frame Then, based on the start timing of the specified OFDM transmission frame, the OFDM symbol number is calculated and supplied to the equalization circuit 120.

  Based on the OFDM frequency domain signal supplied from the FFT window phase error correction circuit 119, the transmission control information decoding circuit 128 decodes transmission control information such as TMCC or TPS that has been modulated to a predetermined carrier position. The transmission control information decoding circuit 128 supplies the decoded transmission control information to, for example, a system controller (not shown). The system controller controls demodulation and playback processing using the supplied transmission control information.

  The TS clock generation circuit 129 uses the clock frequency error signal supplied from the timing synchronization circuit 123 to generate a TS clock synchronized with the received OFDM signal, and sends the generated TS clock to the transport stream generation circuit 122. Supply.

  FIG. 9 shows a detailed configuration example of the wideband carrier frequency error detection circuit 125 of FIG. The broadband carrier frequency error detection circuit 125 includes a differential demodulation circuit 201, a control circuit 202, a pilot signal position generation circuit 203, 2n (n is an integer of 2 or more) delay units 204-1 to 204-2n, 2n + 1 (n Is an integer greater than or equal to 2) pilot correlation calculation circuits 205-1 to 205- (2n + 1), counter 206, selector 207, peak value detection circuit 208, frequency error storage circuit 209, reliability detection circuit 210, And it is comprised so that the error detection circuit 211 may be included.

  The differential demodulation circuit 201 is configured to include an angle conversion circuit 221, a first-in first-out memory (FIFO) 222, and a subtraction circuit 223. The angle conversion circuit 221 of the differential demodulation circuit 201 is an angle on the plane formed by the I axis and the Q axis of the OFDM frequency domain signal that is a complex signal supplied from the FFT window phase error correction circuit 119 of FIG. And an angle signal based on the obtained angle is supplied to the FIFO 222 and the subtraction circuit 223.

  The FIFO 222 delays the angle signal supplied from the angle conversion circuit 221 by one symbol length and supplies it to the subtraction circuit 223. The subtraction circuit 223 subtracts the angle delayed by the FIFO 222 from the angle obtained by the angle conversion circuit 221 based on the angle signal supplied from the angle conversion circuit 221 and the angle signal supplied from the FIFO 222. Differential demodulation is performed, and the differential demodulation result is supplied to pilot correlation arithmetic circuits 205-1 to 205- (2n + 1).

  When notified from the timing synchronization circuit 123 of the symbol start position of the OFDM frequency domain signal, the control circuit 202 sets the symbol start position of the OFDM frequency domain signal to the pilot signal position generation circuit 203 and the cumulative addition circuits 233-1 to 233. -(2n + 1) is notified as appropriate.

  In addition, the control circuit 202 sets the number of symbols to be cumulatively added by the cumulative addition circuits 233-1 to 233- (2n + 1), and at the timing when the pilot correlation calculation circuit 205-1 has finished the cumulative addition of the set number of symbols. A flag (hereinafter referred to as a first cumulative addition end flag) is generated, and the generated first cumulative addition end flag is notified to the counter 206, the selector 251 and the selector 271. The control circuit 202 generates a flag (hereinafter referred to as a second cumulative addition end flag) at the timing when the cumulative addition of the number of symbols set by the last pilot correlation calculation circuit is completed, and the generated second Is notified to the reliability detection circuit 210.

  Further, the control circuit 202 sets a range in which the wide band carrier frequency error is detected, that is, a range in which the offset frequency is shifted (hereinafter also referred to as an offset range). Since the offset range is set in units of carrier frequency interval Δf, the range can be expressed as −R × Δf to R × Δf (R is a natural number). At this time, the value of R is referred to as an offset range amount. The control circuit 202 notifies the pilot signal position generation circuit 203 and the error detection circuit 211 of the offset range amount R corresponding to the set offset range.

  In addition, the control circuit 202 applies the offset range −R × Δf to the phase correction circuits 231-1 to 231- (2n + 1) of the pilot correlation calculation circuits 205-1 to 205- (2n + 1) according to the set offset range. Within R × Δf, different offset frequencies are set at intervals of Δf. Specifically, the offset frequency fs = −R × Δf is set in the phase correction circuit 231-1, and the offset frequency fs = − (R−n + 1) × Δf is set in the phase correction circuit 231-n. The offset frequency fs = − (R−n) × Δf is set in the phase correction circuit 231− (n + 1), and the offset frequency fs = − (R−n−1) is set in the phase correction circuit 231− (n + 2). ) × Δf is set, and the offset frequency fs = − (R−2n) × Δf is set in the phase correction circuit 231- (2n + 1).

  For example, when R = n is set, the offset frequency fs = −n × Δf is set in the phase correction circuit 231-1, and the offset frequency fs = −Δf is set in the phase correction circuit 231-n. Then, the offset frequency fs = 0 is set in the phase correction circuit 231- (n + 1), the offset frequency fs = Δf is set in the phase correction circuit 231- (n + 2), and the phase correction circuit 231- (2n + 1). Is set to an offset frequency fs = n × Δf.

  When the control circuit 202 notifies the symbol start position of the OFDM frequency domain signal, the pilot signal position generation circuit 203 inserts a pilot signal into the input OFDM frequency domain signal based on the symbol start position. A flag (hereinafter referred to as a cumulative addition execution flag) is generated at a position to be processed, and the generated cumulative addition execution flag is used as the cumulative addition circuit 233-1 of the pilot correlation calculation circuit 205-1 and the delay unit 204- 1 is notified. The pilot signal position generation circuit 203 generates a cumulative addition execution flag when the offset frequency fs is fs = −R × Δf.

  When the cumulative addition execution flag is supplied, the delay units 204-1 to 204-2n having the delay amount 1 output the supplied cumulative addition execution flag with a delay of one operation.

  The pilot correlation calculation circuit 205-1 includes a phase correction circuit 231-1, a likelihood conversion circuit 232-1, and a cumulative addition circuit 233-1. The phase correction circuit 231-1 corrects the phase of the angle signal supplied from the differential demodulation circuit 201 based on the set offset frequency and guard interval length, and the phase-corrected angle signal is converted into a likelihood conversion circuit 232. -1. A detailed description of phase correction by the phase correction circuit 231-1 will be described later.

  The likelihood conversion circuit 232-1 takes the maximum value (for example, 1) when the angle signal supplied from the phase correction circuit 231-1 is 0 degrees (0 radians) and 180 degrees (2π radians). In the case of degrees (π / 2 radians) and 270 degrees (3π / 2 radians), likelihood conversion is performed so as to take the lowest value (for example, −1). The likelihood conversion circuit 232-1 supplies the calculated value obtained by the likelihood conversion to the cumulative addition circuit 233-1.

  When the cumulative addition execution flag is input, the cumulative addition circuit 233-1 performs cumulative addition of the calculated values supplied from the likelihood conversion circuit 232-1 and appropriately adds the calculated values (hereinafter referred to as the cumulative addition value). Output to the selector 207.

  The phase correction circuits 231-2 (not shown) to 231- (2n + 1) of the pilot correlation calculation circuits 205-2 (not shown) to 205- (2n + 1) are the phase correction circuits 231 of the pilot correlation calculation circuit 205-1. As in -1, the phase of the angle signal supplied from the differential demodulation circuit 201 is corrected based on the offset frequency and the guard interval length, and the phase-corrected angle signal is converted into a likelihood conversion circuit 232-2 (not shown). To 232- (2n + 1). However, the phase correction circuits 231-2 to 231- (2n + 1) are set with different offset frequencies, and perform phase correction based on the different offset frequencies set for each.

  In addition, the likelihood conversion circuits 232-2 to 232- (2n + 1) and the cumulative addition circuits 233-2 to 233- (2n + 1) of the pilot correlation calculation circuits 205-2 to 205- (2n + 1) respectively perform pilot correlation calculation. Since operations similar to those of the likelihood conversion circuit 232-1 and the cumulative addition circuit 233-1 of the circuit 205-1 are executed, description thereof will be omitted as appropriate.

  When the first cumulative addition end flag is supplied from the control circuit 202, the counter 206 starts counting and counts from 1 to 2R + 1. The counter 206 notifies the selector 207 and the selector 271 of the counted value for each count. The pilot correlation calculation circuits 205-1 to 205- (2n + 1) have different timings for cumulative addition in accordance with the set offset frequencies, so that the output of the counter 206 and each pilot correlation calculation circuit 205- The timing of the end of cumulative addition from 1 to 205- (2n + 1) is synchronized.

  In accordance with the value supplied from the counter 206, the selector 207 sequentially reads and reads the cumulative addition value from the cumulative addition circuits 233-1 to 233- (2n + 1) of the pilot correlation calculation circuits 205-1 to 205- (2n + 1). The accumulated addition value is supplied to the selector 251, the selector 253, and the comparison circuit 255 of the peak value detection circuit 208.

  That is, the selector 207 reads the cumulative addition value stored in the cumulative addition circuit 233-1 when 1 is supplied from the counter 206, and thereafter, when 2 is sequentially supplied from the counter 206, the selector 207 accumulates. When the cumulative addition value stored in the addition circuit 233-2 (not shown) is read and 2R + 1 is supplied from the counter 206, the cumulative addition value stored in the accumulation circuit 233- (2R + 1) is read and read. The accumulated addition value is supplied to the selector 251, the selector 253, and the comparison circuit 255 of the peak value detection circuit 208.

  The peak value detection circuit 208 includes a selector 251, a register 252, a selector 253, a register 254, and a comparison circuit 255. In other words, the peak value detection circuit 208 is the maximum value and the second largest value of cumulative addition values supplied from the selector 207. The peak value and the second peak value of the cumulative addition value supplied from the selector 207 are detected.

  Under the control of the comparison circuit 255, the selector 251 and the selector 253 are selected from among the value stored in the register 252, the value stored in the register 254, and the cumulative addition value newly supplied from the selector 207. Two of the larger values are selected and stored in the register 252 and the register 254. Further, when the first cumulative addition end flag is supplied from the control circuit 202, the selector 251 and the selector 253 reset the value stored in the register 252 and the value stored in the register 254, respectively. The comparison circuit 255 also includes a value newly stored from the selector 207 among the value stored in the register 252, the value stored in the register 254, and the cumulative addition value newly supplied from the selector 207. When the added value is the maximum, an enable signal is supplied to the selector 271 of the frequency error storage circuit 209.

  The frequency error storage circuit 209 includes a selector 271 and a register 272, and stores the value supplied from the counter 206 when the largest cumulative addition value is output from the selector 207, as an estimated value of the broadband carrier frequency error.

  That is, when a value is input from the counter 206, the selector 271 selects one of the value input from the counter 206 and the value stored in the register 272 and stores the selected value in the register 272. Specifically, the selector 271 stores the value input from the counter 206 in the register 272 when the enable signal is input from the comparison circuit 255, and the register 272 when the enable signal is not input from the comparison circuit 255. The value supplied from 272 is stored again in the register 272. Further, the selector 271 resets the value stored in the register 272 when the first cumulative addition end flag is supplied from the control circuit 202.

  This makes it possible to specify the pilot correlation calculation circuit that has calculated the largest cumulative addition value among the pilot correlation calculation circuits 205-1 to 205- (2n + 1), and consequently to specify the wideband carrier frequency error. Can do. The frequency error storage circuit 209 is

  The reliability detection circuit 210 receives the value stored in the register 252 and the register 254 at the timing when the second cumulative addition end flag is supplied from the control circuit 202, that is, the maximum value of the cumulative addition value and the second value. A large value is read, and the reliability of the cumulative value is detected based on the difference or ratio between the maximum cumulative value and the second largest value. The reliability detection circuit 210 compares the reliability of the detected cumulative addition value with a predetermined threshold value and notifies the control circuit 202 and the error detection circuit 211 of the comparison result.

  The error detection circuit 211 reads the value stored in the register 272 of the frequency error storage circuit 209 when the reliability of the cumulative addition value supplied from the reliability detection circuit 210 is equal to or greater than a predetermined threshold value. The error detection circuit 211 detects a broadband carrier frequency error based on the read value. The error detection circuit 211 supplies the detected broadband carrier frequency error to the NCO 126 in FIG. If the reliability of the cumulative addition value supplied from the reliability detection circuit 210 is less than a predetermined threshold value, it is determined that the carrier frequency cannot be synchronized, and the NCO 126 is notified that synchronization is not possible.

  Next, the reception process of the reception apparatus 101 will be described with reference to the flowchart of FIG.

  In step S <b> 1, the tuner 112 converts the RF signal received by the antenna 111 into an IF signal and supplies the IF signal to the BPF 113.

  In step S <b> 2, the BPF 113 filters the IF signal supplied from the tuner 112 and supplies it to the A / D conversion circuit 114.

  In step S <b> 3, the A / D conversion circuit 114 performs A / D conversion on the IF signal supplied from the BPF 113 and supplies the digitized IF signal to the DC cancellation circuit 115.

  In step S4, the DC cancellation circuit 115 removes the DC component of the IF signal supplied from the A / D conversion circuit 114, and supplies the IF signal from which the DC component has been removed to the digital quadrature demodulation circuit 116.

  In step S5, the digital quadrature demodulation circuit 116 performs quadrature demodulation on the IF signal. Specifically, the digital quadrature demodulation circuit 116 orthogonally demodulates the IF signal supplied from the DC cancellation circuit 115 with a carrier signal having a carrier frequency to generate a baseband OFDM signal, that is, an OFDM time domain signal. The generated OFDM time domain signal is supplied to the carrier frequency error correction circuit 117.

  In step S6, the carrier frequency error correction circuit 117 removes the carrier frequency error component from the OFDM time domain signal. Specifically, the carrier frequency error correction circuit 117 complex-multiplies the OFDM time domain signal supplied from the digital quadrature demodulation circuit 116 with the carrier frequency error correction signal supplied from the NCO 126 to obtain the carrier wave of the OFDM signal. The OFDM signal from which the frequency error component has been removed and the carrier frequency error component has been removed is supplied to the FFT operation circuit 118, the timing synchronization circuit 123, and the narrowband carrier frequency error detection circuit 124.

  In step S7, the timing synchronization circuit 123 obtains FFT calculation timing and clock frequency error. Specifically, the timing synchronization circuit 123 specifies the boundary position of the OFDM symbol based on the OFDM time domain signal supplied from the carrier frequency error correction circuit 117, and determines the timing at which the FFT operation circuit 118 should perform the FFT operation. The obtained timing is notified to the FFT operation circuit 118, and a clock frequency error value resulting from the difference between the data generation clock frequency of the OFDM time domain signal and the clock frequency of the receiving apparatus 101 is obtained, and this is corrected by the FFT window phase error correction. This is notified to the circuit 119 and the TS clock generation circuit 129.

  In step S8, the FFT operation circuit 118 performs an FFT operation on the OFDM time domain signal. Specifically, the FFT operation circuit 118 performs an FFT operation on the OFDM time domain signal supplied from the carrier frequency error correction circuit 117 based on the instruction of the FFT operation start timing from the timing synchronization circuit 123, and Data orthogonally modulated to the carrier wave is extracted, and the extracted data, that is, the OFDM frequency domain signal is supplied to the FFT window phase error correction circuit 119.

  In step S9, the FFT window phase error correction circuit 119 corrects the phase rotation component of the OFDM frequency domain signal. Specifically, the FFT window phase error correction circuit 119 multiplies the OFDM frequency domain signal supplied from the FFT operation circuit 118 by the phase correction signal that is a complex signal supplied from the timing synchronization circuit 123. Then, the phase rotation component is corrected, and the corrected OFDM frequency domain signal is supplied to the equalization circuit 120, the broadband carrier frequency error detection circuit 125, the frame synchronization circuit 127, and the transmission control information decoding circuit 128.

  The transmission control information decoding circuit 128 decodes the transmission control information modulated to a predetermined carrier position based on the OFDM frequency domain signal supplied from the FFT window phase error correction circuit 119, For example, it is supplied to a system controller (not shown).

  In step S10, the frame synchronization circuit 127 calculates an OFDM symbol number. Specifically, the frame synchronization circuit 127 detects a synchronization word included in a predetermined position of the OFDM transmission frame based on the OFDM frequency domain signal supplied from the FFT window phase error correction circuit 119, and detects the OFDM transmission frame. Is determined, an OFDM symbol number is calculated based on the start timing of the specified OFDM transmission frame, and this is supplied to the equalization circuit 120.

  In step S11, the equalization circuit 120 performs phase equalization and amplitude equalization of the OFDM frequency domain signal. Specifically, the equalization circuit 120 identifies a pilot signal based on the OFDM symbol number supplied from the frame synchronization circuit 127, and uses the identified pilot signal to equalize the phase of the OFDM frequency domain signal. The OFDM frequency domain signal subjected to phase equalization and amplitude equalization is supplied to the deinterleave / error correction circuit 121.

  In step S12, the deinterleave / error correction circuit 121 decodes the data and performs error correction processing. Specifically, the deinterleave / error correction circuit 121 detects information modulated on each carrier wave according to the modulation method, performs demapping processing, etc., decodes the data, and decodes the decoded data. Is subjected to error correction processing, and OFDM demodulated data is supplied to the transport stream generation circuit 122.

  In step S13, the TS clock generation circuit 129 generates a TS clock. Specifically, the TS clock generation circuit 129 uses the clock frequency error signal supplied from the timing synchronization circuit 123 to generate a TS clock synchronized with the received OFDM signal, and transports the generated TS clock. This is supplied to the stream generation circuit 122.

  In step S14, the transport stream generation circuit 122 generates and outputs a transport stream, and the reception process ends. Specifically, the transport stream generation circuit 122 multiplexes a predetermined data signal with respect to the OFDM demodulated data supplied from the deinterleave / error correction circuit 121 based on the timing defined by the broadcasting system. The smoothing process is performed so that the intermittent OFDM demodulated data supplied from the deinterleave / error correction circuit 121 is smoothed using the TS clock supplied from the TS clock generation circuit 129 and continuously output. Outputs MPEG-2 transport stream (TS).

  As described above, the reception process of the reception apparatus 101 is executed.

  In step S6 of FIG. 10, the carrier frequency error correction circuit 117 removes the carrier frequency error component of the OFDM time domain signal supplied from the digital quadrature demodulation circuit 116. For this purpose, the carrier frequency error supplied from the NCO 126 is removed. An error correction signal is used. Next, processing until the carrier frequency error correction signal is generated and supplied to the carrier frequency error correction circuit 117, that is, carrier frequency error correction signal generation processing will be described with reference to the flowchart of FIG.

  In step S51, the narrowband carrier frequency error detection circuit 124 detects a narrowband carrier frequency error. Specifically, the narrowband carrier frequency error detection circuit 124 has an accuracy of ± 1/2 or less of the carrier frequency interval (eg, 0.992 kHz) based on the OFDM time domain signal supplied from the carrier frequency error correction circuit 117. The narrow-band carrier frequency error is detected, and the detected narrow-band carrier frequency error is supplied to the NCO 126.

  In step S52, the broadband carrier frequency error detection circuit 125 executes broadband carrier frequency error detection processing. Details of the broadband carrier frequency error detection process will be described later with reference to FIG. 15. In this process, the broadband carrier frequency error detection circuit 125 is based on the OFDM frequency domain signal supplied from the FFT window phase error correction circuit 119. Then, a wide band carrier frequency error with an accuracy of the carrier frequency interval (for example, 0.992 kHz) is detected, and the detected wide band carrier frequency error is supplied to the NCO 126.

  In step S53, the NCO 126 generates a carrier frequency error correction signal, and the carrier frequency error correction signal generation process ends. Specifically, the NCO 126 adds the narrowband carrier frequency error supplied from the narrowband carrier frequency error detection circuit 124 and the wideband carrier frequency error supplied from the wideband carrier frequency error detection circuit 125, and adds them. A carrier frequency error correction signal whose frequency increases or decreases according to the generated carrier frequency error is generated, and the generated carrier frequency error correction signal is supplied to the carrier frequency error correction circuit 117.

  The carrier frequency error correction signal generation process is executed as described above.

  Next, details of the broadband carrier frequency error detection processing by the broadband carrier frequency error detection circuit 125 will be described. The broadband carrier frequency error detection circuit 125 detects a broadband carrier frequency error by a pilot correlation calculation process of FIG. 12 described later and a broadband carrier frequency error detection process of FIG.

  First, the pilot correlation calculation process of the receiving apparatus 101 will be described with reference to the flowchart of FIG. Moreover, FIG. 13 and FIG. 14 are referred suitably.

  In step S101, the differential demodulation circuit 201 of the wideband carrier frequency error detection circuit 125 performs angle conversion on the OFDM frequency domain signal to perform differential demodulation. Specifically, the angle conversion circuit 221 of the differential demodulation circuit 201 is on the plane formed by the I axis and the Q axis of the complex signal supplied from the FFT window phase error correction circuit 119, that is, the OFDM frequency domain signal. An angle signal based on the obtained angle is supplied to the FIFO 222 and the subtraction circuit 223. The FIFO 222 delays the angle signal supplied from the angle conversion circuit 221 by one symbol length and supplies it to the subtraction circuit 223. The subtraction circuit 223 subtracts the angle delayed by the FIFO 222 from the angle obtained by the angle conversion circuit 221 based on the angle signal supplied from the angle conversion circuit 221 and the angle signal supplied from the FIFO 222. Differential demodulation is performed, and an angle signal as a result of the differential demodulation is supplied to pilot correlation arithmetic circuits 205-1 to 205- (2n + 1).

  FIG. 13A shows I channel data and Q channel data decomposed into respective carrier frequency components by FFT calculation on a phase plane for each symbol. Da (n−1) and Db (n−1) indicate data signals whose carrier frequencies after FFT of the (n−1) th OFDM symbol are Da and Db, respectively, and Da (n) and Db ( n) shows data signals whose carrier frequencies after FFT of the nth OFDM symbol are Da and Db, respectively. Pa (n-1), Pb (n-1), and Pc (n-1) are pilot signals whose carrier frequencies after FFT of the (n-1) th OFDM symbol are Pa, Pb, and Pc, respectively. In the figure, Pa (n), Pb (n), and Pc (n) indicate pilot signals whose carrier frequencies after FFT of the nth OFDM symbol are Pa, Pb, and Pc, respectively.

  FIG. 13B shows the angle signal after differential demodulation by the differential demodulation circuit 201 on the phase plane, and dDa and dDb are the (n−) th (n−) th carrier frequencies of Da and Db, respectively. 1) A differential demodulated signal of the nth symbol and the nth symbol. Further, dPa, dPb, and dPc are the (n−1) -th symbol, n-th symbol, and differential demodulated signals having carrier frequencies of Pa, Pb, and Pc, respectively.

  Returning to FIG. 12, in step S102, the phase correction circuits 231-1 to 231- (2n + 1) convert the angle signal supplied from the differential demodulation circuit 201 based on the preset offset frequency and guard interval ratio. to correct. This process will be described with reference to FIG.

  FIG. 14 shows the relationship between the offset frequency and the guard interval ratio. In FIG. 14, the horizontal axis is the time axis.

  In FIG. 14, the range of Ts indicated by an arrow represents one symbol length. The range of Tu indicated by the arrow represents the effective symbol length. A range of Tg indicated by an arrow represents a guard interval length. Note that the ratio of the guard interval length to the effective symbol length is set to, for example, 1/4, 1/8, 1/16, or 1/32. In FIG. Let G be the ratio to the length. Then, the guard interval length Tg is expressed by the following formula (1).

  Tg = G × Tu (1)

  In FIG. 14, the range of the FFT window indicated by the arrow represents the range of the FFT window, which is the range of signals that are subjected to the FTT operation by the FTT operation circuit 118. In FIG. 14, the range of the FFT window is the same as the range of the effective symbol Tu, but it is not necessarily the same as the range of the effective symbol Tu.

  In FIG. 14, the value of N represents the value of N when the offset frequency fs is expressed as offset frequency fs = N × Δf using the carrier frequency interval Δf, and is hereinafter referred to as an offset frequency amount. That is, when N = 1, the offset frequency fs = Δf, when N = 2, the offset frequency fs = 2 × Δf, and when N = 3, the offset frequency fs = 3 × Δf.

  In FIG. 14, the top waveform represents the waveform when the offset frequency amount N = 1 and the guard interval ratio G = 1/4, and the second waveform from the top represents the offset frequency amount N = 2 and the guard interval. The waveform when the ratio G = 1/4 is represented, the third waveform from the top represents the waveform when the offset frequency amount N = 3 and the guard interval ratio G = 1/4, and the waveform at the bottom is The waveform is shown when the offset frequency amount N = 1 and the guard interval ratio G = 1/8.

  First, paying attention to the top waveform in FIG. 14, the phase is 0 at the start position of the (n−1) th symbol, but the phase is rotated by π / 2 at the start position of the nth symbol. Therefore, at the start position of the (n + 1) -th symbol, the phase is further rotated by π / 2 and becomes π.

  Looking at the second waveform from the top in FIG. 14, the phase is 0 at the start position of the (n−1) th symbol, but the phase is rotated by π at the start position of the nth symbol, and π Thus, at the start position of the (n + 1) th symbol, the phase is further rotated by π to 2π.

  Looking at the third waveform from the top in FIG. 14, the phase is 0 at the start position of the (n−1) th symbol, but the phase is rotated by 3π / 2 at the start position of the nth symbol. 3π / 2, and at the start position of the (n + 1) -th symbol, the phase is further rotated by 3π / 2 to 3π.

  Looking at the bottom waveform in FIG. 14, the phase is 0 at the start position of the (n−1) th symbol, but the phase is rotated by π / 4 at the start position of the nth symbol, At the start position of the (n + 1) th symbol, the phase is further rotated by π / 4 to become π / 2, and at the end position of the (n + 1) th symbol, the phase is further increased by π The phase is rotated by / 4 to be 3π / 4.

  That is, when the carrier wave is shifted by the offset frequency, the phase is rotated by 2π × G × N for each symbol based on the offset frequency amount N and the guard interval ratio G.

  Therefore, the phase correction circuits 231-1 to 231- (2n + 1) correct this phase rotation.

  As described above, different offset frequencies are set in the phase correction circuits 231-1 to 231- (2n + 1). Further, the guard interval ratio G is set in the phase correction circuits 231-1 to 231- (2n + 1) based on the received OFDM signal.

  The phase correction circuits 231-1 to 231- (2n + 1) correspond to the phase rotation amount according to the phase rotation amount (= 2π × G × N) obtained based on the offset frequency fs and the guard interval ratio G set for each of them. The phase of the angle signal is corrected.

  FIG. 13C shows an angle signal whose phase is corrected by the amount of phase rotation from the phase of FIG. 13B on the phase plane, and dDa, dDb and dPa, dPb, dPc are dDa, dDb, and Corresponds to dPa, dPb, dPc.

As described above, the pilot signals Pa, Pb, and Pc are signals having a constant phase. For example, in the case of the ISDB- _TSB standard, the pilot signal is differentially BPSK modulated, so that the phase difference between consecutive symbols is 0 degrees (0 radians) or 180 degrees (π radians). Therefore, as a result of phase correction by the amount of phase rotation, the differential demodulated signal of the pilot signal converges to a value on the I axis. In FIG. 13C, the phase of the differential demodulated signals dPa and dPb of the pilot signal moves to 0 degrees (0 radians), and the phase of the differential demodulated signal dPc of the pilot signal moves to 180 degrees (π radians). ing.

  On the other hand, since the data signals Da and Db have almost random phases in each symbol, the phases become almost random for each data even after differential demodulation. Therefore, even after the phase correction by the amount of phase rotation, the phase of the differential demodulated signal of the data signal is distributed almost randomly as indicated by dDa and dDb in FIG. 13C.

  The phase correction circuits 231-1 to 231- (2n + 1) correct the phase of the angle signal based on the set offset frequency fs and then convert the corrected angle signal into likelihood conversion circuits 232-1 to 232-. (2n + 1).

  Returning to FIG. 12, in step S103, the likelihood conversion circuits 232-1 to 232- (2n + 1) convert the angle signals supplied from the phase correction circuits 231-1 to 231- (2n + 1) to 0 degrees (0 radians). In the case of 180 degrees (2π radians), the maximum value (for example, 1) is taken, and in the case of 90 degrees (π / 2 radians) and 270 degrees (3π / 2 radians), the minimum value (for example, -1) is taken. Likelihood conversion is performed.

  FIG. 13D represents the position of the signal on the phase plane after likelihood conversion. As shown in FIG. 13D, the signal is converted to a maximum value of 1 for 0 radians (0 degrees) and π radians (180 degrees), π / 2 radians (90 degrees), and 3π / 2. In the case of radians (270 degrees), it is converted to -1 which is the lowest value.

  As described above, since the phase of the differential demodulated signal of the pilot signal converges to approximately 0 degrees or 180 degrees, the likelihood for the pilot signal becomes a value close to +1 or +1. On the other hand, since the phase of the differential demodulated signal of the data signal is distributed almost randomly, the likelihood for the data signal is distributed almost randomly within the range of +1 to -1.

  The likelihood conversion circuits 232-1 to 232- (2n + 1) supply the likelihood obtained by converting the angle signal to the cumulative addition circuits 233-1 to 233- (2n + 1).

  Returning to FIG. 12, in step S104, the cumulative addition circuits 233-1 to 233- (2n + 1) are supplied with the cumulative addition execution flag from the pilot signal position generation circuit 203 or the delay units 204-1 to 204-2n. If the cumulative addition execution flag is supplied from the pilot signal position generation circuit 203 or the delay units 204-1 to 204-2n, the process proceeds to step S105.

  In step S105, the cumulative addition circuits 233-1 to 233- (2n + 1) cumulatively add the likelihoods supplied from the likelihood addition circuits 232-1 to 232- (2n + 1). Thereafter, the process returns to step S101, and the processes after step S101 described above are repeated.

  In step S104, when the cumulative addition circuits 233-1 to 233- (2n + 1) determine that the cumulative addition execution flag is not supplied from the pilot signal position generation circuit 203 or the delay units 204-1 to 204-2n. The process of step S105 is skipped, the process returns to step S101, and the processes after step S101 described above are repeated.

  The pilot correlation calculation process is executed as described above. Note that the processing of step S104 is executed by each of the cumulative addition circuits 233-1 to 233-2n + 1. When a cumulative addition execution flag is supplied to a certain cumulative addition circuit, the cumulative addition circuits are cumulatively transmitted to other cumulative addition circuits. The addition execution flag may not be supplied. In that case, the cumulative addition circuit to which the cumulative addition execution flag has been supplied proceeds to step S105 and cumulatively adds the likelihood, and the cumulative addition circuit to which the cumulative addition execution flag has not been supplied skips the processing of step S105. The supplied likelihood is discarded.

  Next, the details of the broadband carrier frequency error detection processing in step S52 of FIG. 11 will be described with reference to the flowchart of FIG. The process of FIG. 15 is executed in parallel with the pilot correlation calculation process of FIG. 12 described above.

  Hereinafter, it is assumed that the offset range amount R is set to n = n and the offset range is set to −n × Δf to n × Δf. In the following description, it is assumed that the offset frequency is set in each of the phase correction circuits 231-1 to 231-(2n + 1) within the range from −n × Δf to n × Δf and at intervals of Δf. .

  In step S151, the control circuit 202 notifies the symbol start position. Specifically, when the timing synchronization circuit 123 is notified of the symbol start position of the OFDM frequency domain signal, the control circuit 202 determines the symbol start position of the OFDM frequency domain signal, the packet signal position generation circuit 202, and the cumulative addition. The circuits 233-1 to 233- (2n + 1) are notified.

  In step S152, the cumulative addition circuits 233-1 to 233- (2n + 1) reset the stored cumulative addition value.

  In step S153, the pilot signal position generation circuit 203 sets the generation timing of the cumulative addition execution flag and generates the cumulative addition execution flag. Specifically, pilot signal position generation circuit 203 sets the timing when offset frequency fs = −n × Δf. The pilot signal position generation circuit 203 generates and outputs a cumulative addition execution flag based on the set timing. Here, the generation timing of the cumulative addition execution flag will be described with reference to FIG.

  An example of the arrangement of pilot signals is shown on the right side of “OFDM frequency domain signal” in FIG. That is, a plurality of upward arrows shown on the right side of “OFDM frequency domain signal” in FIG. 16 represent pilot signals and data signals modulated on a plurality of carriers of the OFDM frequency domain signal. Of these arrows, solid arrows represent data signals, and dotted arrows represent pilot signals. In the example shown in FIG. 16, the pilot signals are arranged at the ninth, eleventh, seventeenth, and twenty-first positions from the left. Hereinafter, the ninth pilot signal from the left is referred to as pilot signal a, the eleventh pilot signal as pilot signal b, the 17th pilot signal as pilot signal c, and the 21st pilot signal as pilot signal d.

  As described above, the pilot signal arrangement pattern in a plurality of OFDM frequency domain signals is determined in advance by the standard, and the pilot signal position generation circuit 203 modulates the pilot signal arrangement pattern, that is, the pilot signal is modulated. The index number of the carrier wave being stored is stored in advance. Therefore, pilot signal position generation circuit 203 generates a cumulative addition execution flag based on the stored arrangement. In this case, the pilot signal position generation circuit 203 generates a cumulative addition execution flag so as to coincide with the appearance position of the pilot signal when the offset frequency fs = −n × Δf.

  On the right side of the description of “fs = −n × Δf” in FIG. 16, a cumulative addition execution flag generated when the offset frequency fs = −n × Δf and a first cumulative addition end flag described later are shown. ing. Hereinafter, as shown in FIG. 16, the cumulative addition execution flag is referred to as a cumulative addition execution flag a, a cumulative addition execution flag b, a cumulative addition execution flag c, and a cumulative addition execution flag d in order from the left side.

  Timing for generating the cumulative addition execution flags a to d corresponds to the arrangement of pilot signals stored in advance in the pilot signal position generation circuit 203, and the cumulative addition execution flags a to d are delayed by a delay unit. Thus, the signals are supplied to the cumulative addition circuits 233-1 to 233- (2n + 1) at different timings. In other words, the cumulative addition execution flag generated by the pilot signal position generation circuit 203 is supplied to the cumulative addition circuit 233-1 at the generated timing, delayed by one operation, and the cumulative addition circuit 233-2 (not shown) ), Further delayed by one operation, and supplied to the cumulative addition circuit 233-3 (not shown). The cumulative addition execution flag generated by the pilot signal position generation circuit 203 is supplied to the cumulative addition circuit 233- (2n + 1) after being delayed by 2n operations.

  The cumulative addition execution flag a generated by the pilot signal position generation circuit 203 is first supplied to the cumulative addition circuit 233-1 and also supplied to the delay unit 204-1. At this time, as described above, the cumulative addition circuit 233-1 determines in step S104 that the cumulative addition execution flag has been supplied, and in step S105, the cumulative addition circuit 233-1 accumulates the likelihood supplied from the likelihood conversion circuit 232-1. to add. That is, the likelihood supplied from the likelihood conversion circuit 232-1 is based on the assumption that the frequency of each carrier is shifted by the offset frequency fs = −n × Δf by the phase correction circuit 231-1. It is calculated on the basis of the angle-corrected angle signal, assuming that the error is −n × Δf. Accordingly, the pilot correlation calculation circuit 205-1 corrects the phase, converts the likelihood based on the assumption that the frequency of each carrier wave is shifted by the offset frequency fs = −n × Δf, and sets the pilot signal at the appearance position of the pilot signal. The corresponding likelihood is cumulatively added.

  By the way, the cumulative addition execution flag a generated by the pilot signal position generation circuit 203 is delayed by one operation by the delay unit 204-1 and then “fs = − (n−1) × Δf” in FIG. Are supplied to the cumulative adder circuit 233-2 (not shown) and to the delay device 204-2 (not shown) at the timing shown on the right side of FIG. As shown in FIG. 16, the cumulative addition flag a is shifted to the right by the carrier frequency interval (Δf).

  At this time, similarly to the cumulative addition circuit 233-1, the cumulative addition circuit 233-2 determines in step S104 that the cumulative addition execution flag has been supplied, and in step S105, the likelihood conversion circuit 232-2 (not shown). ) Is cumulatively added. The likelihood supplied from the likelihood conversion circuit 232-2 is assumed that the frequency of each carrier is shifted by the offset frequency fs = − (n−1) × Δf by the phase correction circuit 231-2 (not shown). That is, it is calculated based on the phase-corrected angle signal, assuming that the broadband carrier frequency error is − (n−1) × Δf. Therefore, the pilot correlation calculation circuit 205-2 (not shown) corrects the phase based on the assumption that the frequency of each carrier is shifted by the offset frequency fs = − (n−1) × Δf, and converts the likelihood. Then, the likelihood corresponding to the appearance position of the pilot signal is cumulatively added.

  Similarly, the cumulative addition execution flag a is delayed by the delay unit and supplied to the cumulative addition circuit. The cumulative addition circuit is supplied from the likelihood conversion circuit at the timing when the cumulative addition execution flag a is supplied. The added likelihood is accumulated.

  As a result, the pilot correlation calculation circuit 205-n performs phase correction, likelihood conversion, and correspondence to the appearance position of the pilot signal based on the assumption that the frequency of each carrier wave is shifted by the offset frequency fs = −Δf. The pilot correlation calculation circuit 205- (n + 1) corrects the phase based on the assumption that the frequency of each carrier is not shifted, converts the likelihood, and corresponds to the appearance position of the pilot signal. The pilot correlation calculation circuit 205- (n + 2) performs phase correction, likelihood conversion, and pilot conversion based on the assumption that the frequency of each carrier is shifted by the offset frequency fs = Δf. The likelihood corresponding to the appearance position of the signal is accumulated, and the pilot correlation calculation circuit 205- (2n + 1) shifts the frequency of each carrier by an offset frequency fs = n × Δf. Based on the assumption that that, the phase correction, and the likelihood conversion, cumulatively adds the likelihood corresponding to the occurrence position of the pilot signal.

  After generating the cumulative addition execution flag a, the pilot signal position generation circuit 203 generates the next cumulative addition execution flag b at a predetermined timing based on the arrangement of the pilot signals stored in advance, and performs the cumulative addition execution. The flag b is supplied to the cumulative addition circuit 233-1 and the delay unit 204-1. Also in the cumulative addition execution flag b, the same processing as in the case of the cumulative addition execution flag a described above is executed.

  Thereafter, the cumulative addition execution flags c and d are also generated by the pilot signal position generation circuit 203 at a predetermined timing in the same manner as described above, and processing similar to the above is performed based on these cumulative addition execution flags c and d. Executed.

  The accumulated value obtained by accumulating the likelihoods is obtained by adding a signal included in the carrier corresponding to the position of the pilot signal when the frequency of the carrier is shifted by the offset frequency fs, that is, a signal included in the virtual pilot carrier, and a pilot signal. And the correlation. Therefore, when the offset frequency fs matches the actual wideband carrier frequency error and the pilot signal is actually included in the virtual pilot carrier, the cumulative addition value for the offset frequency, that is, the likelihood of only the pilot signal is accumulated. The added cumulative value becomes a larger value than the cumulative added value for other offset frequencies, that is, the cumulative value obtained by adding the likelihood of only the data signal.

  In step S154, the control circuit 202 determines whether the cumulative addition for the set number of symbols has been executed. Specifically, the control circuit 202 sets the number of symbols X to which the cumulative addition circuits 233-1 to 233- (2n + 1) cumulatively add likelihood by the cumulative addition number control process described later with reference to the flowchart of FIG. is doing. Therefore, the control circuit 202 executes the cumulative addition for the set number of symbols X when the last cumulative addition execution flag d in the symbol is generated, that is, when all the cumulative addition execution flags for one symbol are generated. It is determined whether or not the flag is output from the pilot signal position generation circuit 203. When the cumulative addition execution flag for the set number of symbols X has not been output from the pilot signal position generation circuit 203, the control circuit 202 determines that the cumulative addition for the set number of symbols has not been executed, The process proceeds to step S155.

  In step S155, the symbol start position is notified in the same manner as in step S151, and the process returns to step S153. After that, until it is determined in step S154 that the cumulative addition for the set number of symbols has been executed, the processes of steps S153 to S155 are repeatedly executed, and the likelihood for the preset number of symbols is added to the cumulative addition circuit 233. −1 to 233− (2n + 1) are cumulatively added.

  In step S154, when the cumulative addition execution flag for the set number X of symbols is output from the pilot signal position generation circuit 203, the control circuit 202 determines that the cumulative addition for the set number of symbols has been executed, The process proceeds to step S156.

  In step S156, the peak value detection circuit 208 detects the reliability of the cumulative addition value. Specifically, the control circuit 202 generates a first cumulative addition end flag, and supplies the first cumulative addition end flag to the counter 206, the selector 251, the selector 253, and the selector 271. The selector 251 resets the value stored in the register 252. In addition, the selector 253 resets the value stored in the register 254. Further, the selector 271 resets the value stored in the register 272.

  The counter 206 starts counting and supplies the counted value 1 to the selector 207 and the selector 271. Thereafter, the counter 206 counts from 2 to 2n + 1 at a predetermined timing.

  Based on the value supplied from the counter 206, the selector 207 selects the value accumulated in the cumulative addition circuit corresponding to the value supplied from the counter 206 among the cumulative addition circuits 233-1 to 233- (2n + 1). The processing of reading and supplying the read cumulative addition value to the selector 251, the selector 253, and the comparison circuit 255 is started.

  That is, when 1 is supplied from the counter 206, the selector 207 reads the cumulative addition value stored in the cumulative addition circuit 233-1 and sends the read cumulative addition value to the selector 251, the selector 253, and the comparison circuit 255. When the counter 206 is supplied with 2 from the counter 206, the cumulative addition value stored in the cumulative addition circuit 233-2 (not shown) is read, and the read cumulative addition value is selected by the selector 251, the selector 253, and the comparison circuit 255. When the counter 206 is supplied with 3, the cumulative addition value stored in the cumulative addition circuit 233-3 (not shown) is read, and the read cumulative addition value is selected by the selector 251, the selector 253, and the comparison circuit. 255.

  Similarly, when n is supplied from the counter 206, the selector 207 reads the cumulative addition value stored in the cumulative addition circuit 233-n, and uses the read cumulative addition value as the selector 251, the selector 253, and the comparison circuit. When n + 1 is supplied from the counter 206, the cumulative addition value stored in the cumulative addition circuit 233- (n + 1) is read, and the read cumulative addition value is selected by the selector 251, the selector 253, and the comparison circuit 255. When n + 2 is supplied from the counter 206, the cumulative addition value stored in the cumulative addition circuit 233- (n + 2) is read and the read cumulative addition value is sent to the selector 251, the selector 253, and the comparison circuit 255. When 2n + 1 is supplied from the counter 206, the cumulative value stored in the cumulative addition circuit 233- (2n + 1) Read the value, and supplies the read accumulated sum selector 251, a selector 253, and the comparison circuit 255.

  The timing at which the selector 207 reads the cumulative addition values from the cumulative addition circuits 233-1 through 233- (2n + 1) is set by the cumulative addition circuits 233-1 through 233- (2n + 1) based on the cumulative addition execution flags, respectively. This is the timing at which the likelihoods corresponding to the number X of symbols are accumulated. Therefore, the cumulative addition value read by the selector 207 is a cumulative addition value based on the cumulative addition execution flag for the set number of symbols X.

  When the cumulative addition value is supplied from the selector 207, the comparison circuit 255 compares the cumulative addition value supplied from the selector 207, the value stored in the register 252, and the value stored in the register 254. When the cumulative addition value supplied from the selector 207 is the maximum, the comparison circuit 255 outputs an enable signal to the selector 253 and the selector 271 when the value stored in the register 252 is greater than or equal to the value stored in the register 254. When the value stored in the register 252 is less than the value stored in the register 254, an enable signal is output to the selector 251 and the selector 271.

  When the cumulative addition value supplied from the selector 207 is the second largest, the comparison circuit 255 sends an enable signal to the selector 253 when the value stored in the register 252 is equal to or greater than the value stored in the register 254. When the value stored in the register 252 is less than the value stored in the register 254, an enable signal is output to the selector 251.

  Further, the comparison circuit 255 does not output an enable signal when the cumulative addition value supplied from the selector 207 is minimum.

  Based on the presence / absence of an enable signal from the comparison circuit 255, the selector 251 selects the larger one of the value stored in the register 252 and the cumulative addition value newly supplied from the selector 207 and supplies the selected value to the register 252. To do. That is, when the enable signal is supplied from the comparison circuit 255, the selector 251 selects the cumulative addition value supplied from the selector 207 and stores it in the register 252, and when the enable signal is not supplied from the comparison circuit 255, The value stored in the register 252 is selected and stored in the register 252 again.

  Further, the selector 253 selects the larger one of the value stored in the register 254 and the cumulative addition value newly supplied from the selector 207 based on the presence / absence of the enable signal from the comparison circuit 255. To supply. That is, when the enable signal is supplied from the comparison circuit 255, the selector 253 selects and stores the cumulative addition value supplied from the selector 207 in the register 254, and when the enable signal is not supplied from the comparison circuit 255, The value stored in the register 254 is selected and stored in the register 254 again.

  As a result, the maximum value and the second largest value of the cumulative addition value are stored in the registers 252 and 254.

  The frequency error storage circuit 209 starts storing the value supplied from the counter 206 when the supply of the counted value from the counter 206 is started. That is, values are sequentially supplied from the counter 206 to the selector 271 of the frequency error storage circuit 209. When a value is supplied from the counter 206, the selector 271 stores the value supplied from the counter 206 in the register 272 when the enable signal is supplied from the comparison circuit 255 of the peak value detection circuit 208, and the peak value detection circuit When the enable signal is not supplied from the 208 comparison circuit 255, the value supplied from the register 272 is stored again in the register 272. As a result, the value output from the counter 206 at the timing when the cumulative addition value takes the maximum value is stored in the register 272.

  The control circuit 202 supplies the second cumulative addition end flag to the reliability detection circuit 210 at the timing when the counter 206 finishes counting, that is, at the timing when the counter 206 outputs 2n + 1. The reliability detection circuit 210 reads the values stored in the registers 252 and 254, that is, the maximum value of the cumulative addition value and the second largest value. The reliability detection circuit 210 detects the reliability of the cumulative addition value based on the difference or ratio between the maximum value of the cumulative addition value and the second largest value. For example, the reliability detection circuit 210 detects the difference or ratio between the maximum value of the cumulative addition value and the second largest value as the reliability of the cumulative addition value as it is.

  The reliability of this cumulative addition value is such that the greater the difference or ratio between the maximum value of the cumulative addition value and the second largest value, that is, the signal included in the virtual pilot carrier at the offset frequency at which the cumulative addition value is maximum. The larger the difference between the correlation with the pilot signal and the correlation between the signal included in the virtual pilot carrier at another offset frequency and the pilot signal, the larger the value is set. That is, the reliability of the cumulative addition value indicates the reliability with respect to detecting the offset frequency at which the cumulative addition value is maximized as a wideband carrier frequency error.

  In step S157, the reliability detection circuit 210 determines whether the reliability of the cumulative addition value is greater than or equal to a predetermined threshold value. If the error detection circuit 211 determines that the reliability of the cumulative addition value is greater than or equal to the predetermined threshold, the process proceeds to step S158.

  In step S158, the error detection circuit 211 detects a broadband carrier frequency error, and the broadband carrier frequency error detection process ends. Specifically, the reliability detection circuit 210 notifies the control circuit 202 and the error detection circuit 211 that the reliability of the cumulative addition value is equal to or greater than a predetermined threshold value. The error detection circuit 211 reads the value stored in the register 272 of the frequency error storage circuit 209. The error detection circuit 211 uses a value obtained by subtracting the offset range amount R + 1 from the read value and Δf, that is, the offset frequency set for the pilot correlation calculation circuit 205 that maximizes the cumulative addition value. Detect as carrier frequency error. In other words, the offset frequency at which the reliability of the cumulative addition value is greater than or equal to a predetermined threshold and the cumulative addition value is maximum is detected as a wideband carrier frequency error. For example, when the read value is 1, that is, when the cumulative addition value read from the cumulative addition circuit 233-1 is the maximum, −R × Δf is detected as the broadband carrier frequency error, and the read value is n. In some cases, that is, when the cumulative addition value read from the cumulative addition circuit 233-n is the maximum, (n−R−1) × Δf is detected as the broadband carrier frequency error. The error detection circuit 211 supplies the detected wideband carrier frequency error to the NCO 126.

  If it is determined in step S157 that the reliability of the cumulative addition value is less than the predetermined threshold, the process proceeds to step S159.

  In step S159, the error detection circuit 211 notifies that synchronization is not possible, and the broadband carrier frequency error detection process ends. Specifically, the reliability detection circuit 210 notifies the control circuit 202 and the error detection circuit 211 that the reliability of the cumulative addition value is less than a predetermined threshold value. The error detection circuit 211 determines that the frequency of the carrier wave cannot be synchronized due to, for example, a broadband carrier frequency error that exceeds the offset range, the electric field strength is weak, or the pilot signal cannot be detected due to noise or the like, The NCO 126 is notified that synchronization is not possible.

  As described above, the broadband carrier frequency error detection process is executed.

  As described above, the likelihoods corresponding to the preset number of symbols X are cumulatively added, and the cumulative addition value obtained by cumulatively adding the likelihood of only the pilot signal is added to the likelihood of only the data signal. It can be much larger than the cumulative addition value. Therefore, the cumulative addition value of only the pilot signal can be accurately detected as the maximum value. In addition, by detecting the reliability of the accumulated value, the wideband carrier frequency error in a state where the carrier frequency cannot be synchronized, such as when the wideband carrier frequency error exceeds the offset range or the pilot signal cannot be detected due to noise or the like. Is prevented from being erroneously detected. As a result, the broadband carrier frequency error can be detected more accurately.

  Next, a process in which the control circuit 202 sets the number X of symbols to which the likelihood is cumulatively added, that is, a cumulative addition number control process will be described with reference to the flowchart of FIG.

In step S181, the control circuit 202 acquires the number of pilot signals included in one OFDM symbol of the received OFDM signal. For example, in the ISDB-T _SB standard, the total number of TMCC pilot signal and AC pilot signal included in 1OFDM symbol, when the modulation scheme is either QPSK, 16QAM, and 64QAM, 3 present in the mode 1, There are 6 in mode 2 and 12 in mode 3. The control circuit 202 specifies the number of pilot signals included in one OFDM symbol according to the standard or mode of the received OFDM signal. For example, the standard or mode of the received OFDM signal may be input by the user from an operation unit (not shown).

  In step S182, the control circuit 202 sets the number of symbols X to which the likelihood should be accumulated based on the number of pilot signals included in one OFDM symbol acquired in step S181. That is, the control circuit 202 holds the number of pilot signals (Pn) to which the likelihood is to be accumulated in advance, and the number of pilot signals included in the OFDM symbol of the number of symbols X is the reference number Pn. The number of symbols X is set so as to be as described above. Here, assuming that the number of pilot signals included in one OFDM symbol acquired in step S181 is Sn, the control circuit sets the number of symbols X so as to satisfy Equation (2).

  Sn × X> Pn (2)

  As described above, the number X of symbols to which the likelihood is added is set. The control circuit 202 repeats the processing from step S153 to step S155 in FIG. 15 by the set number of symbols X, thereby accumulating the likelihoods by the amount that can accurately detect the carrier frequency error. be able to.

  By the way, if the reference number Pn is set to be small, the number of symbols X to be cumulatively added is reduced and the possibility of erroneously detecting a broadband carrier frequency error is increased. Therefore, the reference number Pn is set to a value larger than an appropriate value. It is possible. However, if the reference number Pn is set to be large, the detection time of the wideband carrier frequency error becomes longer accordingly.

  Therefore, in order to shorten the detection time, it is conceivable to stop the cumulative addition when the reliability of the cumulative addition value is equal to or higher than a predetermined threshold value and detect a broadband carrier frequency error. Here, with reference to the flowchart of FIG. 18, wideband carrier frequency error detection in the case where the cumulative addition is stopped and the wideband carrier frequency error is detected when the reliability of the cumulative value exceeds a predetermined threshold value. Processing will be described.

  The processing of steps S201 to S203 is the same as the processing of steps S151 to S153 of FIG. 15 described above, and the description thereof will be omitted, but will be omitted, but by these processings, cumulative addition of one symbol for each offset frequency is performed. A value is calculated.

  In step S204, the reliability of the cumulative addition value is detected in the same manner as in step S156 in FIG. That is, in this case, the reliability of the cumulative addition value for one symbol is detected.

  In step S205, as in the above-described process in step S157 of FIG. 15, it is determined whether the reliability of the cumulative addition value is greater than or equal to a predetermined threshold value. That is, in this case, it is determined whether the reliability of the cumulative addition value for one symbol is greater than or equal to a predetermined threshold value. If it is determined that the reliability of the cumulative addition value is less than the predetermined threshold, the process proceeds to step S206.

  In step S206, it is determined whether the cumulative addition for the set number of symbols has been executed in the same manner as the processing in step S154 of FIG. If it is determined that the cumulative addition for the set number of symbols has not been executed, the process proceeds to step S207.

  In step S207, the symbol start position is notified in the same manner as in step S155 of FIG. Thereafter, the process returns to step S203, and in step S205, it is determined that the reliability of the cumulative addition value is equal to or greater than a predetermined threshold value, or in step S206, it is determined that the cumulative addition for the set number of symbols has been executed. Steps S203 through S207 are repeatedly executed until it is done. In other words, the accumulated value is accumulated one symbol at a time until the reliability of the accumulated value becomes equal to or higher than a predetermined threshold value or until the accumulation of the set number of symbols is executed.

  If it is determined in step S205 that the reliability of the cumulative addition value is greater than or equal to a predetermined threshold, the process proceeds to step S208.

  In step S208, a broadband carrier frequency error is detected in the same manner as in step S158 of FIG. 15 described above, and the broadband carrier frequency error detection process ends. That is, before performing the cumulative addition for the set number of symbols, the broadband carrier frequency error is detected when the reliability of the cumulative addition value is equal to or greater than a predetermined threshold.

  In step S206, when it is determined that the cumulative addition for the set number of symbols has been executed, that is, when the cumulative addition for the set number of symbols is executed, the reliability of the cumulative addition value is a predetermined threshold value. If not, the process proceeds to step S209.

  In step S209, similar to the process in step S159 of FIG. 15 described above, it is notified that synchronization is not possible, and the wideband carrier frequency error detection process ends.

  In this way, the detection of the broadband carrier frequency error can be speeded up.

  FIG. 19 shows an example of the transition of the cumulative addition value in the broadband carrier wave frequency error detection process of FIG. The horizontal axis direction in FIG. 19 indicates the cumulative addition value, and the vertical axis direction indicates the offset frequency. The leftmost graph shows an example of the distribution of cumulative addition values for one symbol, the second graph from the left shows an example of cumulative addition values for two symbols, and the third graph from the left. The graph shows an example of cumulative addition values for three symbols, and the leftmost graph shows an example of the distribution of cumulative addition values for four symbols.

  For example, as shown in FIG. 19, in the cumulative addition values for 1 to 3 symbols, the difference between the maximum value and the second largest value is small, so in step S205, the reliability of the cumulative addition value is a predetermined value. It is determined that it is less than the threshold, and no broadband carrier frequency error is detected. On the other hand, when the likelihoods for four symbols are cumulatively added, the difference between the maximum value and the second largest value is increased, and in step S205, it is determined that the reliability of the cumulative value is greater than or equal to a predetermined threshold value. A broadband carrier frequency error is detected. Therefore, for example, when the number of symbols to be accumulated is set to 5 symbols or more, the detection of the broadband carrier frequency error can be speeded up.

  Further, by using the reliability, an erroneous offset frequency is detected as a wideband carrier frequency error at a stage where the number of symbols to be cumulatively added is small, for example, at a stage when the cumulative addition value for one symbol in FIG. 19 is obtained. It is prevented.

  In the above description, the number of symbols to be cumulatively added and the offset range are fixed, but may be variable according to the situation. Here, with reference to the flowcharts of FIG. 20 and FIG. 21, the wideband carrier frequency error detection processing when the number of symbols to be added and the offset range are made variable will be described.

  In step S251, the control circuit 202 sets the number of symbols to be added and sets the offset range to be narrow. Hereinafter, in step S251, the number of symbols to be accumulated is set to one half of the number of symbols X set by the above-described accumulation number control process of FIG. 15, and the offset range is set to (−n / 2). An example where xΔf to (n / 2) × Δf, that is, the offset range amount R = n / 2 is set will be described.

  The control circuit 202 notifies the pilot signal position generation circuit 203 of the set offset range amount R. Further, the control circuit 202 sets an offset frequency in the position correction circuits 231-1 to 231- (n + 1) according to the set offset range. That is, the offset frequency is set in each of the position correction circuits 231-1 to 231- (n + 1) within the range of (−n / 2) × Δf to (n / 2) × Δf and at an interval of Δf.

  The processing of steps S252 to S257 is the same as the processing of steps S151 to S156 of FIG. 15 described above, and the details of the processing will be repeated and will be omitted, but by these processing, the pilot signal position generation circuit 203 is processed. From the above, the cumulative addition execution flag is generated so as to coincide with the appearance position of the pilot signal when the offset frequency fs = (− n / 2) × Δf. Further, (n + 1) pieces of (n + 1) pieces set at intervals of Δf within the range of (−n / 2) × Δf to (n / 2) × Δf by the pilot correlation calculation circuits 205-1 to 205- (n + 1). An accumulated value obtained by accumulating the likelihood corresponding to the offset frequency for X / 2 symbols is calculated. Further, the reliability of the calculated cumulative addition value is detected.

  In step S258, it is determined whether or not the reliability of the cumulative addition value is greater than or equal to a predetermined threshold, as in the process of step S157 of FIG. 15 described above. If it is determined that the reliability of the cumulative addition value is equal to or greater than the predetermined threshold, the process proceeds to step S259.

  In step S259, a broadband carrier frequency error is detected in the same manner as in step S158 of FIG. 15 described above, and the broadband carrier frequency error detection process ends. In this case, compared with the broadband carrier frequency error detection processing of FIG. 15, the broadband carrier frequency error can be detected with a small number of symbols and within a narrow offset range, and the broadband carrier frequency error detection is speeded up. can do.

  If it is determined in step S258 that the reliability of the cumulative addition value is less than the predetermined threshold value, that is, the cumulative addition value for the set number of symbols within the currently set offset range, If the frequency error cannot be detected, the process proceeds to step S260.

  In step S260, the control circuit 202 widens the offset range. For example, the control circuit 202 sets the offset range from −n × Δf to n × Δf. The control circuit 202 notifies the pilot signal position generation circuit 203 of the set offset range amount. Further, the control circuit 202 sets an offset frequency in the position correction circuits 231-1 to 231- (2n + 1) according to the set offset range.

  The processing of steps S261 to S266 is the same as the processing of steps S151 to S156 of FIG. 15 described above, and the details of the processing will be repeated and will be omitted, but these processing sets the settings in step S260. For each offset frequency within the offset range, the cumulative addition value for the number of symbols set in step S251 is calculated, and the reliability of the cumulative addition value is detected.

  In step S267, it is determined whether the reliability of the cumulative addition value is equal to or greater than a predetermined threshold, as in the process of step S157 of FIG. 15 described above. If it is determined that the reliability of the cumulative addition value is equal to or greater than the predetermined threshold, the process proceeds to step S259, where a broadband carrier frequency error is detected, and the broadband carrier frequency error detection process ends.

  In step S267, when it is determined that the reliability of the cumulative addition value is less than the predetermined threshold value, that is, within the currently set offset range, the cumulative addition value for the set number of symbols indicates the wideband carrier wave. If the frequency error cannot be detected, the process proceeds to step S268.

  In step S268, the control circuit 202 increases the number of symbols to be accumulated. For example, the control circuit 202 sets the number of symbols to be cumulatively added to the number of symbols X set by the above-described cumulative addition number control process of FIG.

  The processing of steps S269 to S274 is the same as the processing of steps S151 to S156 of FIG. 15 described above, and the details of the processing will be repeated and will be omitted. However, these processings set in step S260. For each offset frequency within the offset range, the cumulative addition value for the number of symbols set in step S268 is calculated, and the reliability of the cumulative addition value is detected.

  In step S275, it is determined whether the reliability of the cumulative addition value is greater than or equal to a predetermined threshold, as in the process of step S157 of FIG. If it is determined that the reliability of the cumulative addition value is equal to or greater than the predetermined threshold, the process proceeds to step S259, where a broadband carrier frequency error is output, and the broadband carrier frequency error detection process ends.

  If it is determined in step S275 that the reliability of the cumulative addition value is less than the predetermined threshold, the process proceeds to step S276.

  In step S276, it is notified that synchronization is not possible by the same process as in step S159 of FIG. 15 described above, and the broadband carrier frequency error detection process ends.

  In this way, the number of symbols to be accumulated is increased stepwise, and the offset range is expanded stepwise. For example, when receiving a radio channel with a good reception environment or a reception device with good reception accuracy. In an environment where the frequency error of the carrier wave is small, such as when it is used, the broadband carrier frequency error can be detected at a stage where the number of symbols to be added is small and within a narrow offset range. The speed can be increased.

  In addition, the number of symbols to be accumulated and the offset range are made variable, and when the reliability of the accumulated value exceeds a predetermined threshold, the accumulation is stopped and a broadband carrier frequency error is detected. It may be. Here, referring to the flowcharts of FIG. 22 and FIG. 23, the number of symbols to be cumulatively added and the offset range are made variable, and the cumulative addition is performed when the reliability of the cumulative addition value exceeds a predetermined threshold. The broadband carrier frequency error detection process when the broadband carrier frequency error is detected will be described.

  The processing from step S301 to step S304 is the same as the processing from step S251 to S254 in FIG. 20 described above, and the description thereof will be repeated and will be omitted. However, by these processing, within the offset range set in step S301. For each offset frequency, an accumulated value for one symbol is calculated.

  In step S305, the reliability of the cumulative addition value is detected in the same manner as in step S204 in FIG. That is, in this case, the reliability of the cumulative addition value for one symbol is detected.

  In step S306, it is determined whether the reliability of the cumulative addition value is equal to or greater than a predetermined threshold, as in the process of step S205 in FIG. That is, in this case, it is determined whether the reliability for one symbol is equal to or greater than a predetermined threshold. If it is determined that the reliability of the cumulative addition value is less than the predetermined threshold, the process proceeds to step S307.

  In step S307, as in the above-described process in step S206 of FIG. 18, it is determined whether the cumulative addition for the set number of symbols has been executed. If it is determined that the cumulative addition for the set number of symbols has not been executed, the process proceeds to step S308.

  In step S308, the symbol start position is notified in the same manner as in step S207 in FIG. Thereafter, the process returns to step S304, and in step S306, it is determined that the reliability of the cumulative addition value is equal to or greater than a predetermined threshold value, or in step S307, it is determined that the cumulative addition for the set number of symbols has been executed. Steps S304 to S308 are repeatedly executed until it is done. In other words, the accumulated value is accumulated one symbol at a time until the reliability of the accumulated value becomes equal to or higher than a predetermined threshold value or until the accumulation of the set number of symbols is executed.

  If it is determined in step S306 that the reliability of the cumulative addition value is equal to or greater than the predetermined threshold, the process proceeds to step S309.

  In step S309, a broadband carrier frequency error is detected as in the above-described process of step S158 in FIG. 15, and the broadband carrier frequency error detection process ends. That is, before performing the cumulative addition for the number of symbols set in step S301, the wideband carrier frequency error is detected when the reliability of the cumulative addition value is equal to or greater than a predetermined threshold. Therefore, compared with the broadband carrier frequency error detection process described above with reference to FIGS. 20 and 21, the detection of the broadband carrier frequency error can be speeded up.

  If it is determined in step S307 that the cumulative addition for the set number of symbols has been executed, that is, within the currently set offset range, If no error is detected, the process proceeds to step S310.

  In step S310, the offset range is widened in the same manner as in step S260 of FIG.

  In step S311, the symbol start position is notified in the same manner as in step S302, and in step S312, the cumulative addition value is reset as in step S303.

  Thereafter, in the same manner as the processing in steps S304 to S308 described above, in step S315, it is determined that the reliability of the cumulative addition value is equal to or greater than a predetermined threshold value, or in step S316, the cumulative addition for the set number of symbols. Steps S313 to S317 are repeatedly executed until it is determined that is executed. In other words, the accumulated value is accumulated one symbol at a time until the reliability of the accumulated value becomes equal to or higher than a predetermined threshold value or until the accumulation of the set number of symbols is executed.

  If it is determined in step S315 that the reliability of the cumulative addition value is equal to or greater than the predetermined threshold value, the process proceeds to step S309. In step S309, a broadband carrier frequency error is detected, and the broadband carrier frequency error detection process ends. To do.

  If it is determined in step S316 that the cumulative addition for the set number of symbols has been executed, that is, within the currently set offset range, If no error has been detected, the process proceeds to step S318.

  In step S318, the number of symbols to be cumulatively added is increased in the same manner as in step S268 of FIG.

  In step S319, the symbol start position is notified in the same manner as in step S302, and in step S320, the cumulative addition value is reset in the same manner as in step S303.

  Thereafter, in the same manner as the processing in steps S304 to S308 described above, in step S323, it is determined that the reliability of the cumulative addition value is equal to or greater than a predetermined threshold value, or in step S324, the cumulative addition for the set number of symbols. Steps S321 to S325 are repeatedly executed until it is determined that is executed. In other words, the accumulated value is accumulated one symbol at a time until the reliability of the accumulated value becomes equal to or higher than a predetermined threshold value or until the accumulation of the set number of symbols is executed.

  If it is determined in step S323 that the reliability of the cumulative addition value is equal to or greater than the predetermined threshold value, the process proceeds to step S309. In step S309, a broadband carrier frequency error is detected, and the broadband carrier frequency error detection process ends. To do.

  In step S324, when it is determined that the cumulative addition for the set number of symbols has been executed, that is, within the currently set offset range, the cumulative value for the set number of symbols has the wideband carrier frequency. If no error is detected, the process proceeds to step S326.

  In step S326, it is notified that synchronization is not possible by the same process as in step S159 of FIG. 15 described above, and the broadband carrier frequency error detection process ends.

  As described above, the wideband carrier frequency error can be accurately detected. In addition, according to the broadband carrier frequency error detection processing of FIG. 18 and FIGS. 20 to 23, the detection of the broadband carrier frequency error can be speeded up.

  In addition, by making the number of symbols to be added and the offset range variable, it is possible to avoid differences in received channels, radio wave environments, receivers, receiver peripheral temperature, receiver deterioration over time, etc. Accordingly, it is possible to realize speeding up of broadband carrier frequency error detection.

  Note that the method of calculating the cumulative addition value, that is, the correlation value with the pilot signal, described above is an example, and other methods may be used.

  The circuit configuration of the wideband carrier frequency error detection circuit shown in FIG. 9 is an example, and the circuit configuration of the wideband carrier frequency error detection circuit in the embodiment of the present invention is limited to the circuit configuration shown in FIG. It does not mean to be done.

  In addition, if the number of symbols to be added and the offset range are made variable, the number of symbols and the offset range when a wideband carrier frequency error is detected are stored for each received channel, and then that channel is received. By using the stored value in this case, the detection of the broadband carrier frequency error can be further speeded up.

  Further, the detected broadband carrier frequency error may be stored for each channel. As a result, the channel synchronization in the case of re-receiving the channel once received can be further accelerated. With the spread of one-segment broadcasting (one-segment broadcasting) and the like, the number of channels increases, the opportunity to receive channels from broadcasting stations in different regions increases, and the number of channels receiving no broadband carrier frequency error is increasing. Even so, since the detection of the broadband carrier frequency error is accelerated as described above, it is possible to prevent the synchronization of the channel from being greatly delayed as compared with the case where the broadband carrier frequency error is stored. .

  Further, in the processing of FIGS. 20 to 23, the example in which the offset range and the number of symbols to be cumulatively added are changed to two stages, but more stages may be provided.

  The present invention can be applied to devices that receive and demodulate OFDM signals, such as television receivers, tuners, mobile phones, and PDAs (Personal Digital Assistants).

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software executes various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a program recording medium in a general-purpose personal computer or the like.

  FIG. 24 is a block diagram showing an example of the configuration of a personal computer 400 that executes the above-described series of processing by a program. A CPU (Central Processing Unit) 401 executes various processes according to a program stored in a ROM (Read Only Memory) 402 or a recording unit 408. A RAM (Random Access Memory) 403 appropriately stores programs executed by the CPU 401 and data. These CPU 401, ROM 402, and RAM 403 are connected to each other via a bus 404.

  An input / output interface 405 is also connected to the CPU 401 via the bus 404. Connected to the input / output interface 405 are an input unit 406 made up of a keyboard, mouse, microphone, etc., and an output unit 407 made up of a display, a speaker, and the like. The CPU 401 executes various processes in response to commands input from the input unit 406. Then, the CPU 401 outputs the processing result to the output unit 407.

  The recording unit 408 connected to the input / output interface 405 includes, for example, a hard disk, and stores programs executed by the CPU 401 and various data. A communication unit 409 communicates with an external device via a network such as the Internet or a local area network.

  A program may be acquired via the communication unit 409 and stored in the recording unit 408.

  The drive 410 connected to the input / output interface 405 drives a removable medium 411 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, and drives the program or data recorded therein. Get etc. The acquired program and data are transferred to and stored in the recording unit 408 as necessary.

  As shown in FIG. 24, a program recording medium for storing a program that is installed in a computer and is ready to be executed by the computer includes a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only). Memory, DVD (Digital Versatile Disc), a magneto-optical disk, a removable medium 411 which is a package medium made of a semiconductor memory, a ROM 402 where a program is temporarily or permanently stored, and a recording unit 408 It is comprised by the hard disk etc. which comprise. The program is stored in the program recording medium using a wired or wireless communication medium such as a local area network, the Internet, or digital satellite broadcasting via a communication unit 409 that is an interface such as a router or a modem as necessary. Done.

  In the present specification, the step of describing the program stored in the program recording medium is not limited to the processing performed in time series in the order described, but is not necessarily performed in time series. Or the process performed separately is also included.

  Furthermore, the embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.

It is a figure explaining the structure of an OFDM signal. It is a figure explaining a carrier frequency error. It is a figure explaining a carrier frequency error. It is a figure explaining a carrier frequency error. It is a figure explaining the detection process of the conventional broadband carrier wave frequency error. It is a figure explaining the detection process of the conventional broadband carrier wave frequency error. It is a figure explaining the detection process of the conventional broadband carrier wave frequency error. It is a block diagram which shows one Embodiment of the receiver which applied this invention. FIG. 9 is a block diagram illustrating in detail the broadband carrier frequency error detection circuit of FIG. 8. It is a flowchart explaining the reception process of a receiver. It is a flowchart explaining the carrier wave frequency error correction signal generation process of a receiver. It is a flowchart explaining the pilot correlation calculation process of a receiver. It is a figure explaining phase correction. It is a figure explaining a phase error. 12 is a flowchart for explaining the first embodiment of the broadband carrier frequency error detection processing in step S52 of FIG. 11; It is a figure explaining the timing which a cumulative addition circuit accumulates likelihood. It is a flowchart explaining the cumulative addition number control process of a receiver. 12 is a flowchart for explaining a second embodiment of the broadband carrier frequency error detection process in step S52 of FIG. It is a figure which shows the example of a cumulative addition value. 12 is a flowchart for explaining a third embodiment of the broadband carrier frequency error detection processing in step S52 of FIG. 11; 12 is a flowchart for explaining a third embodiment of the broadband carrier frequency error detection processing in step S52 of FIG. 11; 12 is a flowchart for explaining a fourth embodiment of the broadband carrier frequency error detection processing in step S52 of FIG. 11; 12 is a flowchart for explaining a fourth embodiment of the broadband carrier frequency error detection processing in step S52 of FIG. 11; And FIG. 11 is a block diagram illustrating an example of a configuration of a personal computer.

Explanation of symbols

  101 receiver, 117 carrier frequency error correction circuit, 118 FFT operation circuit, 119 FFT window phase error correction circuit, 124 narrow band carrier frequency error detection circuit, 125 wide band carrier frequency error detection circuit, 126 numerical control oscillation circuit, 201 differential Demodulation circuit, 203 control circuit, 203 pilot signal position generation circuit, 204-1 to 204-2n delay unit, 205-1 to 205- (2n + 1) pilot correlation operation circuit, 206 counter, 207 selector, 208 peak value detection circuit, 209 frequency error storage circuit, 210 reliability detection circuit, 211 error detection circuit, 221 angle conversion circuit, 222 FIFO, 223 subtraction circuit, 231-1 to 231- (2n + 1) phase correction circuit, 232-1 to 232- (2n + 1) Likelihood conversion circuit, 233-1 through 233- (2n + 1) cumulative addition circuit, 251 a selector, 252 register, 253 selector, 254 register, 255 comparator circuit, 271 a selector, 272 register

Claims (8)

In a detection device for detecting a frequency error of a carrier wave of an OFDM (Orthogonal Frequency Division Multiplexing) signal,
For each offset frequency included in the first frequency range, the correlation between the pilot signal and the signal included in the carrier corresponding to the position of the pilot signal when the frequency of the carrier is shifted by the offset frequency Correlation value calculating means for calculating a correlation value;
Reliability detection means for detecting the reliability of the correlation value based on the difference or ratio between the maximum value of the correlation value and the second largest value;
The reliability is greater than or equal to a predetermined threshold value, and, viewed contains a frequency error detecting means for detecting the offset frequency of the correlation value is maximized as said frequency error,
In the first frequency range, the correlation value calculating means detects a second frequency range wider than the first frequency range when the offset frequency with the reliability equal to or higher than the threshold is not detected. Calculate the correlation value for each offset frequency included therein,
The frequency error detecting means detects the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximum within the range of the second frequency as the frequency error . The correlation value calculation means accumulates and adds the correlation value by one OFDM symbol until the reliability is equal to or higher than a predetermined threshold.
Each time the correlation value is cumulatively added for one OFDM symbol, the reliability detection means calculates the reliability based on a difference or ratio between the cumulatively added maximum value of correlation values and the second largest value. Detect
The detection apparatus according to claim 1, wherein the frequency error detection unit detects, as the frequency error, the offset frequency at which the accumulated correlation value becomes maximum when the reliability becomes equal to or higher than the threshold. The correlation value calculation means cumulatively adds the correlation values for a predetermined number of first OFDM symbols,
The reliability detection means detects the reliability based on a difference or ratio between a maximum value of the correlation value cumulatively added for the first OFDM symbol number and a second largest value,
The frequency error detecting means has the reliability of the correlation value cumulatively added for the number of first OFDM symbols equal to or greater than the threshold value, and the correlation value cumulatively added for the number of first OFDM symbols is The detection apparatus according to claim 1, wherein the offset frequency that is maximized is detected as the frequency error. The correlation value calculating means, when the offset frequency at which the reliability with respect to the correlation value cumulatively added for the first OFDM symbol number is not more than the threshold is not detected, from the first OFDM symbol number. Cumulatively add the correlation values for the number of many second OFDM symbols,
The reliability detection means detects the reliability based on a difference or ratio between a maximum value of the correlation value cumulatively added for the number of the second OFDM symbols and a second largest value,
The frequency error detecting means has the reliability of the correlation value cumulatively added for the second OFDM symbol number equal to or higher than the threshold value, and the correlation value cumulatively added for the second OFDM symbol number The detection apparatus according to claim 3 , wherein the offset frequency that is maximized is detected as the frequency error. The detection device according to claim 1, wherein the frequency error detection unit determines that the frequency of the carrier wave cannot be synchronized when the reliability is less than a predetermined threshold. In the detection method for detecting the frequency error of the carrier wave of the OFDM signal,
For each offset frequency included in the first frequency range, the correlation between the pilot signal and the signal included in the carrier corresponding to the position of the pilot signal when the frequency of the carrier is shifted by the offset frequency Calculate the correlation value,
Detecting the reliability of the correlation value based on the difference or ratio between the maximum value of the correlation value and the second largest value;
Detecting the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximized as the frequency error ;
In the first frequency range, when the offset frequency having the reliability equal to or higher than the threshold is not detected, each offset frequency included in the second frequency range wider than the first frequency range. Calculating the correlation value;
A detection method comprising a step of detecting, as the frequency error, the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximum within the range of the second frequency . In a program that causes a computer to execute processing for detecting a frequency error of a carrier wave of an OFDM signal,
For each offset frequency included in the first frequency range, the correlation between the pilot signal and the signal included in the carrier corresponding to the position of the pilot signal when the frequency of the carrier is shifted by the offset frequency Calculate the correlation value,
Detecting the reliability of the correlation value based on the difference or ratio between the maximum value of the correlation value and the second largest value;
Detecting the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximized as the frequency error ;
In the first frequency range, when the offset frequency having the reliability equal to or higher than the threshold is not detected, each offset frequency included in the second frequency range wider than the first frequency range. Calculating the correlation value;
A program comprising a step of detecting, as the frequency error, the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximum within the range of the second frequency . In a receiving apparatus that receives an OFDM signal,
For each offset frequency included in the first frequency range, the correlation between the pilot signal and the signal included in the carrier corresponding to the position of the pilot signal when the frequency of the carrier is shifted by the offset frequency Correlation value calculating means for calculating a correlation value;
Reliability detection means for detecting the reliability of the correlation value based on the difference or ratio between the maximum value of the correlation value and the second largest value;
The reliability is greater than or equal to a predetermined threshold value, and, viewed contains a frequency error detecting means for detecting the offset frequency of the correlation value is maximized as said frequency error,
In the first frequency range, the correlation value calculating means detects a second frequency range wider than the first frequency range when the offset frequency with the reliability equal to or higher than the threshold is not detected. Calculate the correlation value for each offset frequency included therein,
The frequency error detection means is a receiving device that detects the offset frequency at which the reliability is equal to or higher than a predetermined threshold and the correlation value is maximum within the second frequency range as the frequency error .

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