JP4860058B2 - D / A conversion circuit and semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor formed using a semiconductor. The present invention also relates to a D / A conversion (digital / analog conversion) circuit (DAC) using the capacitor. The present invention also relates to a semiconductor device using this DAC.
[0002]
[Prior art]
In recent years, research and development of thin film transistors (TFTs) using a polycrystalline silicon film formed on a glass substrate as an active layer has been actively conducted. A TFT using a polycrystalline silicon film has a mobility that is two orders of magnitude higher than that of a TFT using an amorphous silicon film. Therefore, even if the gate width of the TFT is reduced to a small size, the current value necessary for circuit operation can be obtained. Enough can be secured. Therefore, it is possible to realize a system-on-panel in which a pixel portion of a matrix type flat panel display and a driving circuit thereof are integrally formed on the same substrate.
[0003]
Realization of the system-on-panel enables cost reduction by reducing the assembly process and inspection process of the display, and also enables miniaturization and high definition of the flat panel display.
[0004]
[Problems to be solved by the invention]
The challenge for further miniaturization and higher definition of flat panel displays is the realization of a DAC capable of high-speed operation and having a small occupied area on the substrate.
[0005]
There are various types of DACs. Typical examples include a capacitive division type and a resistance division type. The capacitive division type DAC can operate at a high speed in a relatively small area as compared with the resistance division type.
[0006]
FIG. 16 is a circuit diagram illustrating an example of a general capacity division type DAC. 16 is an n-bit digital signal D. ₀ ~ D _n-1 N switches SW controlled by each bit of ₀ ~ SW _n-1 And n capacitors C, 2C,..., 2 connected to each switch ^n-1 C (C is a constant) and reset switch SW _R And have.
[0007]
In addition, the DAC shown in FIG. _A ), Power supply B (voltage V _B ) Is given voltage. The power sources A and B are kept at different voltages. Note that the voltage in this specification means a potential difference from a ground potential unless otherwise specified. Voltage V of analog signal output from DAC _OUT Is given to the output line.
[0008]
Capacity C _L Is the output V _OUT Is the load capacity of the signal line connected to.
[0009]
Switch SW ₀ ~ SW _n-1 A digital signal of a corresponding bit is input to each of the above. Then, based on 0 or 1 information of the input digital signal, it is selected whether a voltage is applied from the power source A or a voltage from the power source B to one electrode (first electrode) of each capacitor.
[0010]
The operation of the DAC shown in FIG. 16 will be described step by step. The operation of the DAC shown in FIG. _R And writing period T _A It is divided and explained. The operation in each period of the DAC shown in FIG. 16 will be described with reference to FIG.
[0011]
First, the reset period T _R Middle, reset switch SW _R By means of the voltage V of the power supply B _B Is applied to one electrode (second electrode) of all capacitors. Also, the switch SW is switched by a digital signal. ₀ ~ SW _n-1 And the other electrode (first electrode) of all capacitors is supplied with voltage from the same power source. Here, it is assumed that the voltage V from the power source B _B Is given. An equivalent circuit diagram of the DAC immediately before the end of the reset period is shown in FIG. C _T Means the combined capacity of all capacities.
[0012]
Reset period T _R After completion, writing period T _A Is started. Writing period T _A Then, according to the information that the digital signal of each bit has, the switch SW ₀ ~ SW _n-1 And the voltage V from the power source A or the power source B is applied to the first electrode of each capacitor. _A Or voltage V _B Is given. Then, the electric charge is charged to n capacitors, and then enters a steady state. An equivalent circuit diagram at this time is shown in FIG. C _A Is the voltage V _A Means the combined capacity of the given capacity, C _B Is the voltage V _B Means the combined capacity of the given capacity.
[0013]
The reset period T described above _R And writing period T _A By repeating this operation, it is possible to convert a digital signal into an analog signal.
[0014]
However, if the number of bits of a digital signal to be handled is increased in order to increase the definition of the flat panel display, it becomes difficult to suppress the area occupied by the substrate even in the case of a capacitive division type DAC.
[0015]
In order to suppress the occupied area, when the capacity of the capacitive division type DAC is designed to be simply reduced, the area and the capacity value of the capacity corresponding to the least significant bit are reduced. The capacitance is slightly shifted due to a shift of a mask or the like at the time of formation, a rounding of patterning, an unexpected parasitic capacitance, or the like. Therefore, if the capacity is designed to be reduced, the ratio of the deviation corresponding to the capacity value of the capacity corresponding to the least significant bit increases, and it becomes difficult to form a capacity-divided DAC with good linearity.
[0016]
In addition, when the number of bits of the corresponding digital signal is increased, the resistance division type DAC is not only suppressed in area but also has a high output resistance, which makes high-speed operation difficult.
[0017]
In view of the problems described above, in order to further reduce the size and increase the definition of flat panel displays, it is possible to reduce the area even when the number of bits of a digital signal is increased, and the linearity is capable of high-speed operation. The production of a good DAC is an issue.
[0018]
[Means for Solving the Problems]
The inventor formed a capacitor having three electrodes, a first electrode, a second electrode, and a third electrode, which were stacked with an insulating film serving as a dielectric interposed therebetween, and used the capacitor for the DAC.
[0019]
Specifically, the plurality of capacitors included in the D / A conversion circuit includes a first electrode, a first dielectric in contact with the first electrode, a second electrode in contact with the first dielectric, A second dielectric in contact with the second electrode; and a third electrode in contact with the second dielectric. The second electrode overlaps with the first electrode and the third electrode, and the second electrode has an opening in a portion overlapping with the first electrode and the third electrode. In the opening of the second electrode, a contact hole is formed in the first dielectric and the second dielectric, and the first electrode and the third electrode are connected via the contact hole. Yes.
[0020]
With the above configuration, the capacitance value can be increased while suppressing the area occupied by the capacitor on the substrate. Therefore, the ratio of the deviation of the capacitance value caused by the rounding of patterning, the unexpected parasitic capacitance, etc. in the entire capacitance is reduced, and the linearity of the capacitive division type DAC can be kept good.
[0021]
Further, the first electrode and the third electrode are electrically connected, and the second electrode is connected to the output side of the DAC. With the above configuration, since the second electrode is sandwiched between the first electrode and the third electrode, the second electrode connected to the output line is not easily affected by the parasitic capacitance, and the linearity of the DAC is kept good. Can do.
[0022]
According to the above configuration, the present invention can be driven at high speed, can occupy a relatively small area on the substrate, and can form a DAC corresponding to a digital signal having a high number of bits without losing linearity.
[0023]
Further, by forming a plurality of capacitors (unit cells) having the above-described configuration, electrically connecting the first electrode or the third electrode of the plurality of unit cells to each other, and electrically connecting the second electrodes to each other, One capacitor having a desired capacitance value can be easily formed. Therefore, the DAC having the capacity of the present invention is relatively easy to design.
[0024]
The configuration of the present invention is shown below.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows the configuration of a unit cell of the present invention. 1A is a top view of a unit cell, FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A, and FIG. 1C is BB ′ of FIG. 1A. FIG.
[0026]
In the capacitor of the present invention, the first dielectric 102 is formed in contact with the first electrode 101 having conductivity, and the second electrode 103 having conductivity is formed in contact with the first dielectric 102. A second dielectric 104 is formed in contact with the second electrode 103, and a conductive third electrode 105 is formed in contact with the second dielectric 104.
[0027]
An opening 106 is formed in the second electrode 103, and the first electrode 101 and the third electrode are formed in the opening 106 through contact holes formed in the first dielectric 102 and the second dielectric 104. 105 is connected. At this time, the first electrode 101 and the third electrode 105 are not in contact with the second electrode 103 and are electrically separated from each other.
[0028]
The first dielectric 102 and the second dielectric 105 are made of an insulating material. The first electrode 101, the second electrode 103, and the third electrode 105 are made of a conductive material.
[0029]
Note that the capacitor of the present invention includes a capacitor formed by overlapping the first electrode 101, the first dielectric 102, and the second electrode 103, the second electrode 103, the second dielectric 105, and the first electrode. A capacitor formed by overlapping of the three electrodes 105 can be used together.
[0030]
With the above configuration, the capacitance value can be increased while suppressing the area occupied by the capacitor on the substrate. Further, the first electrode and the third electrode are electrically connected, the first electrode and the third electrode are connected to the signal input side, and the second electrode is connected to the output side, so that the first electrode and the third electrode are connected. Since the second electrode is sandwiched between the second electrodes, the second electrode connected to the output side is not easily affected by the parasitic capacitance between the second electrode and the circuit element.
[0031]
Next, a capacitor formed using a plurality of unit cells of the present invention will be described with reference to FIG. 2A is a top view of a capacitor formed of a plurality of unit cells, FIG. 2B is a cross-sectional view taken along the line CC ′ of FIG. 2A, and FIG. Sectional drawing in DD 'of A) is shown.
[0032]
The unit cell structure of the capacitor shown in FIG. 2 is the same as that shown in FIG. 1, and a first dielectric 202 is formed in contact with the first electrode 201 having conductivity. A second electrode 203 is formed in contact with the first dielectric 202. A second dielectric 204 is formed in contact with the second electrode 203, and a conductive third electrode 205 is formed in contact with the second dielectric 204.
[0033]
An opening 206 is formed in the second electrode 203, and the first electrode 201 and the third electrode are connected through contact holes formed in the first dielectric 202 and the second dielectric 204 in the opening 206. 205 is connected. Note that the first electrode 201 and the third electrode 205 are not in contact with the second electrode 203 and are electrically separated from each other.
[0034]
The first dielectric 202 and the second dielectric 205 are made of an insulating material. The first electrode 201, the second electrode 203, and the third electrode 205 are made of a conductive material.
[0035]
And the 2nd electrode 203 which each unit capacity has is electrically connected mutually. Specifically, the second electrodes 203 included in each unit capacitor are all included in one conductive film and are electrically equivalent.
[0036]
In FIG. 2, the third electrodes 205 included in each of the plurality of unit cells are electrically connected to each other at a node 207 to form one capacitor.
[0037]
Note that a capacitance is expected to be formed by the node 207, the second dielectric 204, and the film including the second electrode 203, and the capacitance value is taken into account to design the capacitance. Also good.
[0038]
The DAC having the capacitance shown in FIGS. 1 and 2 can increase the capacitance value while suppressing the area occupied by the substrate of the capacitance. The ratio of the generated capacitance value deviation is reduced, and the linearity can be kept good.
[0039]
In addition, the first electrode and the third electrode are electrically connected, the first electrode and the third electrode are connected to the signal input side, and the second electrode is connected to the DAC output side. Since the second electrode is sandwiched between the three electrodes, the second electrode connected to the output line is hardly affected by the parasitic capacitance, and the linearity of the DAC can be kept good.
[0040]
According to the above configuration, the present invention can be driven at high speed, can occupy a relatively small area on the substrate, and can form a DAC corresponding to a digital signal having a high number of bits without losing linearity.
[0041]
Further, by forming a plurality of capacitors (unit cells) having the above-described configuration, electrically connecting the first electrode or the third electrode of the plurality of unit cells to each other, and electrically connecting the second electrodes to each other, One capacitor having a desired capacitance value can be easily formed. Therefore, the DAC having the capacity of the present invention is relatively easy to design.
[0042]
【Example】
Examples of the present invention will be described below.
[0043]
Example 1
In this embodiment, a structure of a DAC formed using the capacitor of the present invention will be described.
[0044]
FIG. 3 shows a circuit diagram of the DAC of this embodiment. The DAC of this embodiment can convert an 8-bit digital signal into an analog signal.
[0045]
The capacitive division type DAC shown in FIG. 3 has each bit D of an 8-bit digital signal. ₀ ~ D ₇ 8 switches SW whose operation is controlled by ₀ ~ SW ₇ And eight capacitors C in which the voltage applied by each switch is controlled ₀ , C ₁ ..., C ₇ And reset switch SW _R And have. Further, the DAC shown in FIG. 3 is supplied with the voltage V by the power source A, the power source B and the power source R, respectively. _A , Voltage V _B , Voltage V _R Is given. Voltage V _A And voltage V _B The value of is different. In addition, the voltage V of the analog signal output from the DAC _OUT Is given to the output line.
[0046]
Capacity C ₀ , C ₁ ..., C ₇ The capacitance values of C are ₀ = C, C ₁ = 2C, ..., C ₇ = 2 ⁷ Represented by C.
[0047]
Switch SW ₀ ~ SW ₇ A digital signal of a corresponding bit is input to each of the above. Then, according to 0 or 1 information of the input digital signal, the voltage V is applied to the electrode of each capacitor by the power source A. _A Or the voltage V by the power source B _B Is selected.
[0048]
FIG. 4 shows eight capacitors C when the DAC shown in the circuit diagram of FIG. 3 is formed using the unit cell of the present invention. ₀ , C ₁ ..., C ₇ The top view of is shown. FIG. 4 does not show the first dielectric 302 and the second dielectric 304 in order to clarify the position where the second electrode is provided.
[0049]
Capacity C ₂ ..., C ₇ Are unit cells 1, 2, ... 2 ^Five It has one by one. And capacity C ₂ ..., C ₇ In each of the above, the third electrodes of the unit cells are connected to each other via nodes.
[0050]
Capacity C ₀ Has a capacity value of ¼ of the unit cell, and the capacity C ₁ Has a capacity value that is 1/2 that of a unit cell. Capacity C ₀ And capacity C ₁ An enlarged view of is shown in FIG.
[0051]
FIG. 5A shows the capacity C ₀ And C ₁ 5B is a cross-sectional view taken along the line EE ′ of FIG. 5A, and FIG. 5C is a cross-sectional view taken along the line FF ′ of FIG. 5A.
[0052]
Capacitance C shown in FIG. ₀ And C ₁ The first dielectric 302 is formed in contact with the first electrode 301 having conductivity. A second electrode 303 is formed in contact with the first dielectric 302. A second dielectric 304 is formed in contact with the second electrode 303, and a conductive third electrode 305 is formed in contact with the second dielectric 304.
[0053]
The first electrode 301 and the third electrode 305 are connected at the contact hole 308. In FIG. 5, the area where the first electrode and the third electrode overlap is the capacitance C ₀ ¼ of unit cell, capacity C ₁ In this case, it is ½ of the unit cell.
[0054]
The first dielectric 302 and the second dielectric 305 are made of an insulating material. The first electrode 301, the second electrode 303, and the third electrode 305 are made of a conductive material.
[0055]
FIG. 6 shows a top view of the switch of the DAC of the present embodiment shown in FIG. In FIG. 6, as in FIG. 4, the first dielectric 302 and the second dielectric 304 are not shown in order to clarify the wiring arrangement and the TFT position.
[0056]
In this embodiment, as shown in FIG. _Four ~ Switch SW ₇ Uses a transmission gate having an n-channel TFT and a p-channel TFT.
[0057]
Furthermore, in this embodiment, as shown in FIG. _Four ~ Switch SW ₇ The channel width of the TFT of the switch SW ₀ ~ Switch SW _Three Is larger than the channel width of the TFT of the. And switch SW _Four ~ Switch SW ₇ The larger the corresponding capacitance value, the larger the channel width. Increasing the channel width increases the current capability of the TFT and increases the speed of charge charge. The larger the capacitance value, the larger the amount of charge to be charged. Therefore, it is preferable that the charge charge speed is high.
[0058]
In the present embodiment, the DAC that converts an 8-bit digital signal into an analog signal has been described. However, the present invention is not limited to this, and the number of bits can be set arbitrarily.
[0059]
(Example 2)
In this embodiment, an example of a manufacturing process in the case where the capacitor and the TFT used in the DAC of the present invention and the TFT and the storage capacitor of the pixel portion of the liquid crystal display are formed over the same substrate will be described. Note that FIGS. 7 to 10 show only the process of forming the p-channel TFT and the n-channel TFT included in the reset switch of the DAC, but all the transistors used in the present invention are shown in FIGS. It can be created based on the steps shown.
[0060]
In FIG. 7A, a substrate 901 includes polyethylene terephthalate (PET), polyethylene in addition to a glass substrate such as barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass. A plastic substrate having no optical anisotropy such as naphthalate (PEN) or polyethersulfone (PES) can be used. A quartz substrate may be used. In the case of using a glass substrate, it is possible to prevent the substrate from being deformed in the subsequent steps if heat treatment is performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point.
[0061]
In order to prevent impurity diffusion from the substrate 901, a base film 902 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 901 on which a TFT is formed with a thickness of 10 to 200 nm. To do. The base film may be formed of one layer of the insulating film or a plurality of layers.
[0062]
The semiconductor layers 903 to 906 are formed from a semiconductor film having crystallinity obtained by crystallizing a semiconductor film having an amorphous structure by a laser annealing method, a thermal annealing method, a rapid thermal annealing method (RTA method), or the like. Alternatively, a crystalline semiconductor film formed by sputtering, plasma CVD, thermal CVD, or the like may be used. Alternatively, the semiconductor layers 903 to 906 having crystallinity can be formed by a crystallization method using a catalytic element in accordance with the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652. In the crystallization step, it is preferable to first release hydrogen contained in the amorphous semiconductor film, and heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the amount of contained hydrogen to 5 atom% or less. When it is made rough, the film surface can be prevented from being rough. In any case, the crystalline semiconductor film thus formed is selectively etched to form crystalline semiconductor layers 903 to 906 at predetermined positions. (Fig. 7 (A))
[0063]
Alternatively, an SOI (Silicon On Insulators) substrate in which a single crystal silicon layer is formed over the substrate 901 may be used. Several types of SOI substrates are known depending on their structures and fabrication methods. Typically, SIMOX (Separation by Implanted Oxygen), ELTRAN (Epitaxial Layer Transfer: registered trademark of Canon Inc.) substrate, Smart- Cut (registered trademark of SOITEC) or the like can be used. Of course, other SOI substrates can also be used.
[0064]
Next, in order to form a DAC capacitor and a pixel storage capacitor, a mask 907 is formed, and the semiconductor layer 903 and a part of the semiconductor layer 906 (a region to be a storage capacitor) are doped with phosphorus, an impurity region 908, 909 is formed (FIG. 7B). The concentration of phosphorus in the impurity regions 908 and 909 is 1 × 10 ¹³ ~ 1x10 ¹⁵ atoms / cm ^Three (Typically 5 × 10 ¹³ ~ 5x10 ¹⁴ atoms / cm ^Three ).
[0065]
Next, after removing the mask 907 and forming an insulating film 910 covering the semiconductor layer, a part of the insulating film 910 located over the region 909 serving as a storage capacitor of the pixel is removed by patterning. (Fig. 7 (C))
[0066]
Next, thermal oxidation is performed to form a gate insulating film 911. By this thermal oxidation, the final gate insulating film thickness was 80 nm. Note that a portion of the gate insulating film 911 located over the impurity region 909 serving as a storage capacitor is formed to be thinner than other regions. (Fig. 7 (D))
[0067]
Next, a channel doping process for adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the TFT was performed over the entire surface or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, diborane (B ₂ H ₆ Boron was added by ion doping with plasma excitation without mass separation. Of course, an ion implantation method that performs mass separation may be used.
[0068]
Next, a conductive film is formed and patterned to form gate electrodes 912 to 914 and capacitor wirings 915 and 916 (FIG. 8A). Here, a stacked structure of a silicon film doped with phosphorus (film thickness 150 nm) and tungsten silicide (film thickness 150 nm) was used.
[0069]
Note that the gate electrodes 912 to 914 and the capacitor wirings 915 and 916 may be formed as a single layer, or may have a stacked structure including a plurality of layers of two or more layers as necessary. For example, an element selected from tungsten (W), tantalum (Ta), titanium (Ti), and molybdenum (Mo), an alloy containing the element, or an alloy film combining the elements is used. In addition, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), molybdenum nitride (MoN) which are nitrides of these elements, tungsten silicide which is silicide, tantalum silicide, titanium silicide, molybdenum silicide, etc. A stacked structure may be formed.
[0070]
Next, phosphorus is added to the semiconductor layers 904 to 906 at a low concentration in a self-aligning manner using the gate electrodes 912 to 914 as a mask (FIG. 8B). The concentration of phosphorus in this low concentration region is 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three , Typically 3 × 10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three Adjust so that Note that in this step, phosphorus is also added to part of the impurity regions 908 and 909 to which phosphorus is added in the previous step of FIG. Through the above steps, impurity regions 921 to 927 are formed.
[0071]
Next, a mask 931 is formed and phosphorus is added at a high concentration to form high concentration impurity regions 934 to 939 (FIG. 8C). The phosphorus concentration in this high concentration impurity region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three ) So that it is within the range. Note that the impurity regions 938 and 939 are not uniform in impurity concentration in the process of FIGS. 7A and 8B, but the impurity concentration added in the process of FIG. Since the concentration of the impurity added by the process of FIG. 7A and FIG. 8B is higher, the final impurity concentration falls within the above range. Note that among the impurity regions 921 to 927, a region covered with the mask 931 has a low impurity concentration and functions as an LDD region.
Then, after the impurity element is added, the mask 931 is removed.
[0072]
Next, a mask 943 is formed so as to cover the semiconductor layers 903, 904, and 906, and boron is added to the semiconductor layer 905 with a high concentration using the gate electrode 913 as a mask (FIG. 9A). The impurity regions 944 and 945 formed here are diborane (B ₂ H ₆ ) Using an ion doping method. The concentration of the impurity element imparting p-type in the impurity regions 944 and 945 is 2 × 10 ²⁰ ~ 2x10 ^{twenty one} atoms / cm ^Three To be.
[0073]
However, the impurity regions 944 and 945 contain an impurity element imparting n-type in detail. However, by making the concentration of the impurity element imparting p-type in these impurity regions 944 and 945 be 1.5 to 3 times the concentration of the impurity element imparting n-type, No problem arises because it functions as a source region and a drain region.
[0074]
Next, after the mask 943 is removed, a passivation film 946 that covers the gate electrodes 912 to 914 and the capacitor wirings 915 and 916 is formed. Here, a silicon oxide film was formed with a thickness of 70 nm. Next, a heat treatment step for activating the n-type or p-type impurity element added to the semiconductor layer at each concentration is performed. Here, heat treatment was performed at 850 ° C. for 30 minutes.
[0075]
Next, a first interlayer insulating film 947 made of an organic resin material is formed. Here, an acrylic resin film having a thickness of 400 nm was used (FIG. 9B). Next, after forming a contact hole reaching the semiconductor layer, a capacitor electrode 950, a connection wiring 951, source wirings 952 to 954, and drain wirings 955 and 956 are formed. In this embodiment, the capacitor electrode 950, the connection wiring 951, the source wirings 952 to 954, and the drain wirings 955 and 956 are continuously formed by sputtering using a Ti film of 100 nm, a Ti film containing 300 nm, and a Ti film of 150 nm. A laminated film having a three-layer structure was formed (FIG. 9C).
[0076]
Next, after performing a hydrogenation process, a second interlayer insulating film 957 made of acrylic is formed. Then, a contact hole is formed in the second interlayer insulating film 957 so as to reach the capacitor electrode 950, the connection wiring 951, and the drain wiring 955, and a light-shielding conductive film is formed so as to cover the second interlayer insulating film 957. The film is formed with a thickness of. Then, by patterning, a reset wiring 958 connected to the capacitor electrode 950, a connection wiring 959 that electrically connects the connection wiring 951 and the drain wiring 955, and a light shielding layer 960 that overlaps the channel formation region of the TFT in the pixel portion are formed. It forms (FIG. 10 (A)).
[0077]
Next, a third interlayer insulating film 961 is formed. Then, a contact hole reaching the drain wiring 956 is formed in the second interlayer insulating film 957 and the third interlayer insulating film 961. Next, after forming a 100 nm transparent conductive film (here, indium tin oxide (ITO) film), patterning is performed to form a pixel electrode 962 in contact with the drain wiring 956 (FIG. 10B).
[0078]
After the above steps, an alignment film, a color filter, and the like are formed, and the liquid crystal is sealed between the counter substrate and the liquid crystal display is completed.
[0079]
Needless to say, the present embodiment is an example and is not limited to the steps of the present embodiment. For example, as each insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an organic resin material (polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like) film can be used.
[0080]
In FIG. 10B, 971 is a DAC capacitor of the present invention, 972 is a reset switch, 973 is a pixel TFT (pixel TFT), and 974 is a pixel storage capacitor. In the capacitor 971, the semiconductor layer 903 including the impurity region 908 and the high concentration impurity region 934 is the first electrode, the gate insulating film 911 is the first dielectric, the capacitor wiring 915 is the second electrode, the passivation film 946, and the first interlayer insulating film. 947 corresponds to the second dielectric, and the capacitor electrode 950 corresponds to the third electrode.
[0081]
The reset switch 972 includes an n-channel TFT 975 and a p-channel TFT 976. The n-channel TFT 975 includes an active layer 904, a gate insulating film 911, and a gate electrode 912. The active layer 904 includes a source region 977, a drain region 978, LDD regions 979 and 980, and a channel formation region 981. The p-channel TFT 976 includes an active layer 905, a gate insulating film 911, and a gate electrode 913. The active layer 905 includes a source region 982, a drain region 983, and a channel formation region 984.
[0082]
The pixel TFT 973 includes an active layer 906, a gate insulating film 911, and a gate electrode 914. The active layer 906 includes a source region 985, a drain region 986, LDD regions 987 and 988, and a channel formation region 989.
[0083]
Note that the pixel storage capacitor 974 includes a capacitor wiring 916 and an impurity region 909 which is a part of the semiconductor layer 906, where the gate insulating film 911 is thinner than the other portions. Yes.
[0084]
Note that the capacity of the present invention is not limited to the configuration shown in this embodiment. Further, the capacitor of the present invention is not used only for a liquid crystal display, but can be used for any kind of semiconductor device.
[0085]
This embodiment can be implemented by freely combining with the first embodiment.
[0086]
(Example 3)
In this embodiment, an example of a DAC formed using the capacitor of the present invention will be described with reference to circuit diagrams.
[0087]
The DAC shown in FIG. 11 has n bits (D ₀ ~ D _n-1 ) Digital signals. D ₀ Is LSB and D _n-1 Is the MSB. In addition, an n-bit digital signal is converted into the lower m bits (D ₀ ~ D _m-1 ) And upper (nm) bits (D _m ~ D _n-1 ) And think.
[0088]
As shown in FIG. 11, the DAC of the present invention has an n-bit digital signal (D ₀ ~ D _n-1 N switches (SW) controlled by each bit of ₀ ~ SW _n-1 ) And each switch (SW ₀ ~ SW _n-1 ) Connected to capacitors (C, 2C,..., 2 ^m-1 C, C, 2C, ... 2 ^nm-1 C) and two reset switches (SW _R 1 and SW _R 2). These capacities are integral multiples of the unit capacity C.
[0089]
Further, the DAC of the present invention has another capacity (C) in addition to the above capacity. The other capacitor (C) is electrically connected to one electrode of each capacitor corresponding to the lower m bits and one electrode of each capacitor corresponding to the upper (nm) bits. Is formed using an electrode that is equivalent to.
[0090]
Capacity C _L Is the output V _OUT Is the load capacity of the signal line connected to. In addition, the ground power supply is V _G And However, V _G May be any constant power source.
[0091]
The DAC in FIG. 11 includes a power supply H (voltage V _H ), Power supply L (voltage V _L ), Offset power supply (voltage V _B ), Power source A (voltage V _A ) Is connected. V _H > V _L And V _H <V _L In the case of _OUT Outputs an analog signal of opposite phase. Here, V _H > V _L The output in the case of _H <V _L In this case, the output is the inverted phase.
[0092]
Switch (SW ₀ ~ SW _n-1 ) Is an input digital signal (D ₀ ~ D _n-1 ) Is 0 (Lo), it is connected to the power supply L, and when the input digital signal is 1 (Hi), it is connected to the power supply H. Reset switch SW _R 1 is a capacity (C, 2C,..., 2) corresponding to the upper (nm) bits. ^nm-1 V to C) _B Controls the charging of charges from. Also, reset switch SW _R 2 is a capacity corresponding to the lower m bits (C, 2C,..., 2 ^m-1 V to C) _A Controls the charging of charges from.
[0093]
Reset switch SW _R One end of 2 may be connected to the power source L so that the voltage from the power source A is not supplied.
[0094]
Next, a circuit diagram of a DAC having a configuration different from that in FIG. 11 is shown in FIG. The conventional DAC of FIG. 12 has an n-bit digital signal (D ₀ ~ D _n-1 N switches (SW) controlled by each bit of ₀ ~ SW _n-1 ) And each switch (SW ₀ ~ SW _n-1 ) Connected to capacitors (C, 2C,..., 2 ^m-1 C, C, 2C, ... 2 ^nm-1 C) and two reset switches (SW _R 1 and SW _R 2). In the DAC of FIG. 12, the capacitor C is connected to the circuit on the lower bit side, and the capacitance value of the capacitor connecting the circuit corresponding to the lower bit and the circuit corresponding to the upper bit is different. 11 is different from the DAC of FIG.
[0095]
Also in the DAC of FIG. ₀ ~ SW _n-1 ) Is an input digital signal (D ₀ ~ D _n-1 ) Is 0 (Lo), it is connected to the power supply L, and when the input digital signal is 1 (Hi), it is connected to the power supply H.
[0096]
This embodiment can be implemented by being freely combined with Embodiment 1 or Embodiment 2.
[0097]
Example 4
Next, the structure of a liquid crystal display using the DAC of the present invention will be described with reference to FIGS.
[0098]
FIG. 13 is a block diagram showing the configuration of the liquid crystal display. The liquid crystal display illustrated in FIG. 13 includes a pixel portion 9003, a source signal line driver circuit 9001, and a gate signal line driver circuit 9002.
[0099]
The pixel portion 9003 has a plurality of pixels 9004. The source signal line driver circuit 9001 includes a shift register circuit 9001-1, a latch circuit A 9001-2, a latch circuit B 9001-3, and a D / A conversion circuit 9001-4. The gate signal line driver circuit 9002 includes a shift register circuit 9002-1 and a buffer circuit 9002-1.
[0100]
The capacitor of the present invention can be used for the D / A conversion circuit 9001-4.
[0101]
FIG. 14 shows a circuit diagram of the pixel 9004. The pixel 9004 includes one source signal line 9005 and one gate signal line 9006. The pixel 9004 is provided with a pixel TFT 9007, a liquid crystal cell 9008 in which liquid crystal is sandwiched between the counter electrode and the pixel electrode, and a capacitor 9009.
[0102]
A gate electrode of the pixel TFT 9004 is connected to the gate signal line 9006. One of a source region and a drain region of the pixel TFT 9004 is connected to the source signal line 9005, and the other is connected to a pixel electrode and a capacitor 9009 included in the liquid crystal cell 9008.
[0103]
The capacitor 9009 is provided to hold the potential of the pixel electrode when the pixel TFT 9007 is in a non-selected state (off state).
[0104]
A counter potential is applied to the counter electrode of the liquid crystal cell 9008.
[0105]
A clock signal (CK) and a start pulse (SP) are input to the shift register circuit 9001-1 included in the source signal line driver circuit 9001. The shift register circuit 9001-1 sequentially generates timing signals based on the clock signal (CK) and the start pulse (SP), and sequentially supplies the timing signals to the latch circuit A 9001-2.
[0106]
The latch circuit A9001-2 has a plurality of latches that store digital signals. When the timing signal is input, the latch circuit A 9001-2 sequentially captures and holds the digital signal in each latch.
[0107]
The time until the writing of digital signals to all the latches of the latch circuit A9001-2 is completed is called a line period. Actually, a period obtained by adding a horizontal blanking period to the line period may be called a line period.
[0108]
After the end of one line period, a latch signal (Latch Signal) is supplied to the latch circuit B9001-3. At this moment, digital signals written and held in the latch circuit A 9001-2 are sent all at once to the latch circuit B 9001-3, and are written and held in all the latches of the latch circuit B 9001-3.
[0109]
Based on the timing signal from the shift register circuit 9001-1, the digital signal is sequentially written again to the latch circuit A9001-2 that has finished sending the digital signal to the latch circuit B9001-3.
[0110]
During the second line period, the digital signals written and held in the latch circuit B9001-3 are sequentially input to the D / A conversion circuit 9001-4.
[0111]
In the D / A conversion circuit 9001-4, the digital signal is converted into an analog video signal (analog signal) and supplied to the source signal line 9005.
[0112]
On the other hand, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register circuit 9002-1 in the gate signal line driver circuit 9002, a selection signal for controlling switching of the pixel TFT 9007 is generated. The selection signal is buffered and amplified in the buffer circuit 9002-2 and input to the gate signal line 9006.
[0113]
The pixel TFT 9004 is turned on by a selection signal input to the gate signal line 9006, and an analog signal input to the source signal line is input to the pixel electrode included in the liquid crystal cell 9008 through the pixel TFT.
[0114]
The liquid crystal is driven by the potential of the analog signal input to the pixel electrode, the amount of transmitted light is controlled, and a part of the image (an image corresponding to the pixel) is displayed on the pixel.
[0115]
When a part of the image is displayed in all the pixels, one image is displayed in the pixel portion 9003.
[0116]
One image is displayed by performing the above operation in each pixel.
[0117]
This embodiment can be implemented by freely combining with the first to third embodiments.
[0118]
(Example 5)
The semiconductor device having a DAC of the present invention can be used for various electronic devices.
[0119]
As an electronic device using the DAC of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook personal computer, a game machine, a mobile phone An information terminal (mobile computer, cellular phone, portable game machine, electronic book, etc.), an image playback device equipped with a recording medium (specifically, a recording medium such as a Digital Versatile Disc (DVD) is played back and the image is displayed. And a device equipped with a display that can be used. Specific examples of these electronic devices are shown in FIGS.
[0120]
FIG. 15A illustrates a display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The DAC of the present invention can be used for the display portion 2003 or other control circuits. The display devices include all information display devices for personal computers, for receiving TV broadcasts, for displaying advertisements, and the like.
[0121]
FIG. 15B illustrates a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The DAC of the present invention can be used for the display portion 2102 or other control circuits.
[0122]
FIG. 15C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The DAC of the present invention can be used for the display portion 2203 or other control circuits.
[0123]
FIG. 15D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The DAC of the present invention can be used for the display portion 2302 or other control circuits.
[0124]
FIG. 15E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the DAC of the present invention can be used for these display portions A, B 2403, 2404 or other control circuits. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0125]
FIG. 15F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The DAC of the present invention can be used for the display portion 2502 or other control circuits.
[0126]
FIG. 15G shows a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . The DAC of the present invention can be used for the display portion 2602 or other control circuits.
[0127]
Here, FIG. 15H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The DAC of the present invention can be used for the display portion 2703 or other control circuits.
[0128]
In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving images are increasing. The DAC of the present invention is useful because it can operate at high speed, can convert a digital signal having a high number of bits into an analog signal, and can ensure the linearity of the analog signal to be output.
[0129]
As described above, the applicable range of the DAC of the present invention is so wide that the DAC can be used for electronic devices in various fields. Moreover, the electronic device of the present embodiment may use any of the DAC configurations shown in the first to fourth embodiments.
[0130]
【Effect of the invention】
According to the above configuration, the present invention can be driven at high speed, can occupy a relatively small area on the substrate, and can form a DAC corresponding to a digital signal having a high number of bits without losing linearity.
[0131]
Further, by forming a plurality of capacitors (unit cells) having the above-described configuration, electrically connecting the first electrode or the third electrode of the plurality of unit cells to each other, and electrically connecting the second electrodes to each other, One capacitor having a desired capacitance value can be easily formed. Therefore, the DAC having the capacity of the present invention is relatively easy to design.
[Brief description of the drawings]
1A and 1B are a top view and a cross-sectional view of a capacitor of the present invention.
FIG. 2 is a top view and a cross-sectional view of a capacitor according to the present invention.
FIG. 3 is a circuit diagram of a DAC using a capacitor of the present invention.
FIG. 4 is a top view of the capacity of the DAC of the present invention.
FIG. 5 is a top view of the capacity of the DAC of the present invention.
FIG. 6 is a top view of a switch included in the DAC of the present invention.
7A and 7B are diagrams showing a capacitor of the present invention and a TFT manufacturing process.
FIG. 8 is a diagram showing a capacitor of the present invention and a process for producing a TFT.
FIGS. 9A and 9B illustrate a capacitor of the present invention and a TFT manufacturing process. FIGS.
FIGS. 10A and 10B are diagrams showing a capacitor of the present invention and a TFT manufacturing process. FIGS.
FIG. 11 is a circuit diagram of a DAC using a capacitor of the present invention.
FIG. 12 is a circuit diagram of a DAC using a capacitor of the present invention.
FIG. 13 is a block diagram showing the structure of a liquid crystal display using the DAC of the present invention.
FIG. 14 is a circuit diagram of a pixel of a liquid crystal display.
FIG. 15 is a diagram of a semiconductor device using a DAC of the present invention.
FIG. 16 is a circuit diagram of a general capacitive division type DAC.
FIG. 17 is a diagram showing an operation of a general capacity division type DAC.

Claims (4)

A semiconductor device having a D / A conversion circuit having a plurality of capacitors and a thin film transistor over a substrate having an insulating surface,
The D / A conversion circuit has a plurality of capacitors,
The plurality of capacitors include a first electrode, a first dielectric in contact with the first electrode, a second electrode in contact with the first dielectric, and a second dielectric in contact with the second electrode. Each having a body and a third electrode in contact with the second dielectric,
The second electrode overlaps the first electrode and the third electrode,
The second electrode has an opening in a portion overlapping the first electrode and the third electrode,
Contact holes are formed in the first dielectric and the second dielectric in the opening of the second electrode,
The first electrode and the third electrode are connected via the contact hole;
The second electrodes of the plurality of capacitors are all electrically connected,
A part of the first electrode and the third electrode respectively included in the plurality of capacitors are electrically connected,
A potential of the second electrode is applied to a circuit subsequent to the D / A conversion circuit;
The thin film transistor includes a semiconductor film which is formed simultaneously with the first electrodes, a first dielectric gate insulating formed simultaneously with the film, a gate electrode formed simultaneously with the second electrodes, the first 3 electrodes and has a source electrode and a drain electrode formed at the same time,
A semiconductor device comprising an interlayer insulating film formed simultaneously with the second dielectric. A semiconductor device having a D / A conversion circuit having a plurality of capacitors and a thin film transistor over a substrate having an insulating surface,
The D / A conversion circuit has a plurality of capacitors,
The plurality of capacitors include a first electrode, a first dielectric in contact with the first electrode, a second electrode in contact with the first dielectric, and a second dielectric in contact with the second electrode. Each having a body and a third electrode in contact with the second dielectric,
The second electrode overlaps the first electrode and the third electrode,
The second electrode has an opening in a portion overlapping the first electrode and the third electrode,
Contact holes are formed in the first dielectric and the second dielectric in the opening of the second electrode,
The first electrode and the third electrode are connected via the contact hole;
The first electrode and the third electrode of each of the plurality of capacitors are electrically connected, and the first to nth capacitors are formed by the connection,
The ratio of the capacitance values of the first to n-th capacitors is represented by 2 ⁰ : 2 ¹ : 2 ² :...: 2 ⁽ⁿ⁻²⁾ : 2 ⁽ⁿ⁻¹⁾ ,
The second electrodes of the plurality of capacitors are all electrically connected,
A potential of the second electrode is applied to a circuit subsequent to the D / A conversion circuit;
The thin film transistor includes a semiconductor film which is formed simultaneously with the first electrodes, a first dielectric gate insulating formed simultaneously with the film, a gate electrode formed simultaneously with the second electrodes, the first 3 electrodes and has a source electrode and a drain electrode formed at the same time,
A semiconductor device comprising an interlayer insulating film formed simultaneously with the second dielectric. In claim 1 or claim 2,
Each of the plurality of capacitors has the same capacitance value. In any one of Claims 1 thru | or 3 ,
A semiconductor device comprising a display device, a digital still camera, a notebook personal computer, a mobile computer, a DVD player, a head mounted display, a video camera, or a mobile phone.

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