JP4843744B1 - Integrated circuit device and electronic apparatus - Google Patents

Abstract

An object of the present invention is to provide an integrated circuit device capable of scalable adjustment of graphics processing performance and capable of constructing an optimum system according to target processing performance. .
The present invention is basically based on the knowledge that the number of integrated circuits corresponding to a target performance can be cascaded to expand or reduce the graphics processing performance in a scalable manner. An embodiment of the present invention is for communication between a first integrated circuit (1), a second integrated circuit (2), and a first integrated circuit (1) and a second integrated circuit (2). A bus (4) and an input / output bus (5) for outputting the operation result of the first integrated circuit (1) to the second integrated circuit (2) are included.
[Selection] Figure 1

Description

  The present invention relates to an integrated circuit device capable of executing graphics processing, and an electronic device mounted with the integrated circuit device. More specifically, the present invention relates to an integrated circuit device that can expand graphics processing performance in a scalable manner by cascading a plurality of integrated circuits, and an electronic device on which the integrated circuit device is mounted.

  Conventionally, it is known to perform graphics processing using an integrated circuit such as an LSI (Large Scale Integration). FIG. 6 shows a conventional graphics processing system using an integrated circuit alone. In a conventional system, image data is input via an input interface from a medium such as a CGROM that stores image data such as stream data or a drawing command, or a camera (imaging device) that acquires image data. The The input image data is developed in the VRAM or system memory by the CPU, and image processing is executed by the image engine. The processed image data subjected to the image processing is output to a display device such as a liquid crystal display (LCD) via the output interface.

  Further, as conventional techniques for connecting and mounting a plurality of graphic processors in order to improve graphics processing performance, for example, Japanese Patent Laid-Open No. 2000-222590 (Patent Document 1) and Japanese Patent Laid-Open No. 2007-179225. The invention disclosed in (Patent Document 2) is known.

  The invention disclosed in Patent Document 1 relates to an image processing apparatus that performs drawing processing in parallel by a plurality of graphics processors. In the present invention, the processing load in each graphics processor is calculated from the attribute data and the graphics command input to the graphics processor, and the graphics processor for which the load exceeds a predetermined threshold is drawn. Is to stop.

  The invention disclosed in Patent Document 2 relates to an information processing apparatus capable of switching graphics chips having different drawing processing capabilities in accordance with a user's purpose of use. In the present invention, a built-in graphic chip having a relatively low processing capability is built in the chip, and an external graphics chip having a relatively high processing capability is provided outside the chip. The user can select whether the image processing is performed in the built-in graphics chip or the external graphics chip via the graphics changeover switch.

JP 2000-222590 A JP 2007-179225 A

  By providing a plurality of graphics chips as in the technologies disclosed in Patent Document 1 and Patent Document 2 described above, the graphics processing performance is basically improved according to the number of installed graphics chips. It is possible to make it.

  However, in the conventional invention, since the circuit is constructed so as to obtain a certain target performance, a graphics chip is added to the circuit once assembled or a graphics chip is added from the assembled circuit. It was difficult to remove. For this reason, the graphics processing performance of the circuit could not be adjusted in a scalable manner according to the changing target performance. In other words, for example, if the target drawing performance or video / still image decoding performance is high, it is possible to satisfy the target performance by increasing the circuit scale, but it is difficult to reduce the circuit scale once manufactured. For this reason, when image processing that does not require such high performance is performed, the assembled circuit scale becomes redundant.

  Further, for example, it is theoretically possible to improve the graphics processing performance by providing two or more independent integrated circuits as shown in FIG. 6 and constructing a system for each of them. However, when the same system is assembled in parallel, it is necessary to provide peripheral devices for each integrated circuit, which increases the system cost in manufacturing.

  For this reason, at present, there is a demand for a technique that can expand or reduce the graphics processing performance of an image processing system in a scalable manner and can construct an optimum system according to the target processing performance.

Therefore, as a result of intensive investigations on means for solving the problems of the conventional invention, the inventor of the present invention has implemented a number of integrated circuits according to the target performance and cascaded them to perform graphics processing. It was found that an integrated circuit device capable of scalable or scalable performance can be obtained. The inventor has conceived that the problems of the prior art can be solved based on the above knowledge, and has completed the present invention.
Specifically, the present invention has the following configuration.

The present invention relates to an integrated circuit device for performing graphics processing.
The integrated circuit device of the present invention is for communication that connects a first integrated circuit (1), a second integrated circuit (2), and the first integrated circuit (1) and the second integrated circuit (2). A bus (4) and an input / output bus (5) for outputting the operation result of the first integrated circuit (1) to the second integrated circuit (2) are included.
Here, the first integrated circuit (1) is:
A first central processing unit (11);
A first input interface (12) for inputting image data;
Based on the control of the first central processing unit (11), a part of the image data input to the first input interface (12) via the communication bus (4) is converted into a second integrated circuit ( A first communication interface (13) for forwarding to 2);
A first image engine (14) for image processing image data based on control of the first central processing unit (11);
The first output interface (15) for outputting the first processed image data processed by the first image engine (14) to the second integrated circuit (2) via the input / output bus (5). And).
The second integrated circuit (2)
A second communication interface (23) for receiving part of the image data transferred from the first integrated circuit (1) via the communication bus (4);
A second image engine (24) for image-processing a part of the image data received by the second communication interface (23) based on the control of the first central processing unit (11);
A second input interface to which the first processed image data output from the first integrated circuit (1) is input via the input / output bus (5);
A second output interface that integrates and outputs the first processed image data input to the second input interface (22) and the second processed image data processed by the second image engine (24). (25).

  In the present invention, the first integrated circuit (1) and the second integrated circuit (2) are connected as described above. The first integrated circuit (1) and the second integrated circuit (2) basically have the same graphics processing performance and the same circuit configuration. Two times the graphics processing performance can be obtained. Also, by removing the interfaces (communication bus (4) and input / output bus (5)) that connect the first integrated circuit (1) and the second integrated circuit (2), the graphics can be changed according to the target performance. The processing performance can be expanded or reduced in a scalable manner. Further, since the peripheral device (for example, CGROM) can be shared and used by connecting the first integrated circuit (1) and the second integrated circuit (2) as described above, the system cost is reduced. The increase of can be minimized. Furthermore, in the present invention, the central control of the entire integrated circuit device is performed by one central processing unit (CPU), so that it is not necessary to perform communication between the integrated circuits, and centralized control is possible. Therefore, for example, software used for graphics processing can be easily developed.

  In the present invention, the communication interface for transferring image data from the first integrated circuit (1) to the second integrated circuit (2) and the calculation result of the first integrated circuit (2) are used as the second interface. An input / output interface for outputting to the integrated circuit (2) is provided separately. Therefore, the first central processing unit (11) of the first integrated circuit (1) uses the bus used to control the second integrated circuit (2), and the first integrated circuit (2). The bus for outputting the calculation result to the second integrated circuit (2) can be separated. For this reason, it is possible to avoid the problem of mutual communication interference between the first integrated circuit (1) and the second integrated circuit (2), and it is possible to further increase the speed of image processing.

In the present invention, the first integrated circuit (1) is connected to the first system memory (10), and the second integrated circuit (2) is connected to the second system memory (20). Is preferred.
That is, in the first integrated circuit (1), the image data input to the first input interface (12) is transferred to the first system memory (10) based on the control of the first central processing unit (11). And image processing is performed in the first image engine (14).
Similarly, in the second integrated circuit (2), part of the image data received by the second communication interface (23) is stored in the second system memory based on the control of the first central processing unit (11). (20) and image processing is performed in the second image engine (24).

  Thus, in the present invention, it is preferable that the first integrated circuit (1) and the second integrated circuit (2) each have the system memory (10, 20) independently. When performing image processing, the image engine executes image processing on the image data expanded in the system memory using the storage space of the system memory. In the present invention, image processing is performed in parallel by the first image engine (14) and the second image engine (24), but when the two image engines perform image processing using a common system memory, , Access to the system memory becomes frequent, and as a result, there is a concern that the graphics processing may be delayed. Therefore, in a preferred embodiment of the present invention, the above problem is solved by connecting an independent system memory to each integrated circuit.

  The present invention preferably further includes an interrupt bus (6) for performing interrupt processing in the first integrated circuit (1) and the second integrated circuit (2).

  In the present invention, an image processing end signal is sent from the second integrated circuit (2) to the first central processing unit (11) of the first integrated circuit (1) via the interrupt bus (6). Interrupt processing to transmit Thereby, the first central processing unit (11) can know the completion of the processing in the second integrated circuit (2) without degrading the processing performance. For this reason, graphics processing can be efficiently performed based on the control of the first central processing unit (11). In the present invention, since the communication bus (4), the input / output bus (5), and the interrupt bus (6) are separately provided, the first integrated circuit (1) and the second bus The problem of mutual communication interference between the integrated circuits (2) can be avoided.

An integrated circuit device according to another embodiment of the present invention includes a first integrated circuit (1), a second integrated circuit (2), a third integrated circuit (3), and a first integrated circuit ( The communication bus (4) for connecting 1) to the second integrated circuit (2) and the third integrated circuit (3), and the operation result of the first integrated circuit (1) to the second integrated circuit (2 The first input / output bus (5a) for outputting to the second integrated circuit (2) and the second input / output bus for outputting the operation result of the second integrated circuit (2) to the third integrated circuit (3) (5a).
The first integrated circuit (1)
A first central processing unit (11);
A first input interface (12) for inputting image data;
Based on the control of the first central processing unit (11), part of the image data input to the first input interface (12) via the communication bus (4) is converted into the second integrated circuit (2 And a first communication interface (13) for transferring to the third integrated circuit (3);
A first image engine (14) for image processing image data based on control of the first central processing unit (11);
The first output for outputting the first processed image data processed by the first image engine (14) to the second integrated circuit (2) via the first input / output bus (5a). An interface (15) is provided.
The second integrated circuit (2)
A second communication interface (23) for receiving part of the image data transferred from the first integrated circuit (1) via the communication bus (4);
A second image engine (24) for image-processing a part of the image data received by the second communication interface (23) based on the control of the first central processing unit (11);
A second input interface (22) to which the first processed image data output from the first integrated circuit (1) is input via the first input / output bus (5a);
The integrated data obtained by integrating the first processed image data input to the second input interface (22) and the second processed image data image-processed by the second image engine (24) is input to the second input interface (22). And a second output interface (25) for outputting to the third integrated circuit via the output bus (5b).
The third integrated circuit (3)
A third communication interface (33) for receiving part of the image data transferred from the first integrated circuit (1) via the communication bus (4);
A third image engine (34) for image-processing a part of the image data received by the third communication interface (33) based on the control of the first central processing unit (11);
A third input interface (32) to which the integrated data output from the second integrated circuit (2) is input via the second input / output bus (5b);
A third output interface (35) for integrating and outputting the integrated data input to the third input interface (32) and the third processed image data processed by the third image engine (34); It comprises.

  In the present invention, the first integrated circuit (1), the second integrated circuit (2), and the third integrated circuit (3) are connected as described above. The first integrated circuit (1), the second integrated circuit (2), and the third integrated circuit basically have the same graphics processing performance and the same circuit configuration. By connecting, it is possible to obtain a graphics processing performance three times as high as usual. In addition, these integrated circuits (1-3) can be easily increased or decreased via the interfaces (communication bus (4) and input / output bus (5)). Processing performance can be expanded or reduced in a scalable manner.

  Another embodiment of the present invention is a computer on which the above-described integrated circuit device is mounted.

  Another embodiment of the present invention is a game machine on which the above-described integrated circuit device is mounted.

FIG. 1 is a block diagram showing a circuit configuration of a main part in the embodiment of the present invention. FIG. 2 is a block diagram showing a circuit configuration of a main part in another embodiment of the present invention. FIG. 3 is a block diagram showing a circuit configuration of a main part in another embodiment of the present invention. FIG. 4 is a block diagram showing a circuit configuration of the computer according to the embodiment of the present invention. FIG. 5 is a block diagram showing a circuit configuration of the game machine according to the embodiment of the present invention. FIG. 6 is a block diagram showing a circuit configuration of a conventional integrated circuit.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. The present invention is not limited to the embodiments described below, but includes those appropriately modified by those skilled in the art from the following embodiments.

(1. First embodiment)
FIG. 1 is a block diagram showing a circuit configuration of a main part in the first embodiment of the present invention. In the embodiment shown in FIG. 1, the first integrated circuit (1) and the second integrated circuit (2) are a communication bus (4), an input / output bus (5), and an interrupt bus (6). ) Are connected to each other via a signal, and signals can be exchanged. As shown in FIG. 1, the first integrated circuit (1) and the second integrated circuit (2) have substantially the same circuit configuration, and each of them has a central processing unit (hereinafter also referred to as CPU). ), Image engine, VRAM, and other interfaces. Therefore, each of the first integrated circuit (1) and the second integrated circuit (2) functions independently as an integrated circuit for graphics processing even if they are not connected to each other. In the embodiment shown in FIG. 1, information processing and device control are performed by the first central processing unit (11) in the first integrated circuit (1), and the first central processing unit (11) Based on the control, graphics processing is executed.

(1-1. First integrated circuit)
First, the circuit configuration of the first integrated circuit (1) will be described.
The first integrated circuit (1) includes a first central processing unit (11), a first input interface (12), a first communication interface (13), a first image engine (14), a first It includes an output interface (15), a first system memory interface (16), a first VRAM (17), and a second interrupt interface (18).

  The first central processing unit (11) is a device for controlling information processing and device control in the entire system and controlling a program for executing graphic processing. In the non-volatile memory 101, for example, display control data corresponding to each command read by the first central processing unit (11), images such as character / background data, stream data, drawing commands, and display control programs are displayed. Data is stored. Then, the first central processing unit (11) reads out these image data via the input interface (12), and performs a classification process on the apparatus that processes the information. An example of the nonvolatile memory 101 is a CGROM. Further, the nonvolatile memory 101 may be an EEPROM or a flash memory. Further, the first central processing unit (11) may acquire image data from an image sensor (102) such as a camera. The first central processing unit (11) may be provided with a RAM constituting a work area.

  The first central processing unit (11) distributes a part of the image data to the first image engine (14) in the first integrated circuit (1) in the separation process, and other parts of the image data are described later. To the second image engine (24) in the second integrated circuit (2). For example, the first central processing unit (11) may distribute the image data according to the area when displayed on the display device, or may distribute the image data for each RGB. At this time, the first central treatment unit (11) may calculate the necessary processing amount of the input image data and perform the sorting process based on the drawing possibility of the image engine. Further, for example, the background image data is processed in the first image engine (14), and the character image data is processed in the second image engine (24). It is good. Further, for example, when displaying a stereoscopic image, for example, the image for the left eye is processed in the first image engine (14), and the image for the right eye is processed in the second image engine (24). Also good.

The first input interface (12) is an interface for acquiring image data. The first input interface (12) has, for example, a ROM interface to which image data stored in the CGROM (101) is input, and a CAM interface for acquiring image data from an image sensor (102) such as a camera. . The first input interface may be a parallel connection type or a serial connection type. As described above, the data input to the first input interface (12) is transmitted to the first central processing unit (11).
In the embodiment shown in FIG. 1, since the image data stored in the CGROM (101) is input via the ROM interface, the CAM interface is not used. For this reason, the CAM interface is displayed with light ink.

The first communication interface (13) includes a first central processing unit (11) that performs main control and a second central processing unit (21) of the second integrated circuit (2) under the control. It is a means for connecting via a communication bus (4). The communication interface (13) is, for example, USB (Universal Serial Bus standard), PCI (Peripheral).
This is an interface for connecting a general-purpose high-speed bus of Component Interconnect (PCI) standard, PCIe (PCI Express) standard, SCSI (Small Computer System Interface) standard, and serial SCSI standard.

  The first image engine (14) is a device for image processing the image data sorted by the first central processing unit (11) based on a command from the first central processing unit (11). . Image data such as stream data and drawing commands sorted by the first central processing unit (11) is developed in the first system memory (10) and the first VRAM (16), and the first image engine. By (14), 3D graphics processing rendering and video moving image decoding processing are executed. The first image engine (14) analyzes the input image data, performs predetermined image processing according to the analysis result, and records the processed image in the first system memory (10).

  The first output interface (15) outputs the processed image data processed by the first image engine (14) to the second integrated circuit (2) via the input / output bus (5). Is an interface for. The first output interface (15) is formed in accordance with a standard corresponding to the second input interface in the second integrated circuit (2) described later. For example, an interface that can output processed image data to the liquid crystal display (103) even when the first integrated circuit (1) is used alone is adopted as the first output interface (15). Is preferred. An example of the first output interface (15) is an LCD parallel RGB output interface.

  The first system memory interface (16) is an interface for connecting the first integrated circuit (1) and the system memory (DDR) (10).

  The first VRAM (17) and the first system memory (10) are storage devices that function as a work space for the first central processing unit (11) and the first image engine (14). The first central processing unit (11) develops the image data acquired via the first input interface (12) in the first VRAM (17) and the first system memory (10). The first image engine (14) processes image data using the first VRAM (17) and the first system memory (10).

  The first interrupt interface (18) is an interface for receiving an interrupt signal from the second integrated circuit (2) via the interrupt bus (6). In the interrupt processing, an interrupt signal is sent from the second integrated circuit (2) to the first central processing unit (11) of the first integrated circuit (1), and the second integrated circuit (2). The completion of the graphics processing at is communicated. When the interrupt process is performed, the first central processing unit (11), for example, interrupts the process being performed at that time and performs the process according to the signal received from the second integrated circuit (2). Also good.

(1-2. Second Integrated Circuit)
Next, the circuit configuration of the second integrated circuit (2) will be described.
As shown in FIG. 1, the second integrated circuit (2) includes a second central processing unit (21), a second input interface (22), a second communication interface (23), and a second image. An engine (24), a second output interface (25), a second system memory interface (26), a second VRAM (27), and a second interrupt interface (28) are included.

  Thus, the second integrated circuit (2) preferably has the same circuit configuration as the first integrated circuit (1) described above. The second integrated circuit (2) may be a duplicate of the first integrated circuit (1). That is, the first central processing unit (11), the first input interface (12), the first communication interface (13), the first image engine (14), the first of the first integrated circuit (1). The output interface (15), the first system memory interface (16), the first VRAM (17), and the second interrupt interface (18) are respectively connected to the second integrated circuit (2). Central processing unit (21), second input interface (22), second communication interface (23), second image engine (24), second output interface (25), second system memory interface (26), the second VRAM (27), and the second interrupt interface (28). However, as a matter of course, the second integrated circuit (2) may have a configuration different from that of the first integrated circuit (1).

  As shown in FIG. 1, the first communication interface (11) of the first integrated circuit (1) and the second communication interface (21) of the second integrated circuit (2) are connected to a communication bus ( It is connected via 4). The first output interface (13) of the first integrated circuit (1) and the second input interface (23) of the second integrated circuit (2) are connected via an input / output bus (5). It is connected. Furthermore, the first interrupt interface (18) of the first integrated circuit (1) and the second interrupt interface (28) of the second integrated circuit (2) are connected via the interrupt bus (6). Connected.

In the present embodiment, an existing CAM interface that acquires image data from an image sensor such as a camera is used as the second input interface (23) in the second integrated circuit (2). Therefore, data transfer can be performed between the first integrated circuit (1) and the second integrated circuit (2) via the input / output bus (5) without providing new transfer means.
In this embodiment, since the ROM interface in the second input interface is not used, it is displayed with light ink.

  As described above, when the first integrated circuit (1) and the second integrated circuit (2) are connected, any integrated circuit is set as a master and any integrated circuit is set as a slave. It is decided whether to function. In the embodiment shown in FIG. 1, the first integrated circuit (1) in which the CGROM 101 is connected to the input interface (12) functions as the main integrated circuit. In the second integrated circuit (2), which is a subordinate integrated circuit, the function of the second central processing unit (12) is stopped, and information processing and device control are controlled by the first central processing unit (11). Is set to follow.

  The second integrated circuit (2) shares the CGRM (101) with the first integrated circuit (1). Therefore, a part of the image data input from the CGRM (101) to the first integrated circuit (2) is controlled by the first central processing unit (11). The second VRAM or the second system memory (20) is expanded. The second integrated circuit (2) processes part of the image data received from the first integrated circuit (1) by the second image engine (24), and completes the processing by the first central processing unit. To (11). Then, the second integrated circuit (2) integrates and synthesizes the processed image data output from the first integrated circuit (1) and the processed image data processed by the second image engine, and the LCD monitor ( 103).

  Since the description of each configuration in the second integrated circuit (2) is the same as the configuration in the first integrated circuit (1) described above, the description in the first integrated circuit (1) is cited here. And omit it.

(1-3. Processing flow)
The processing flow in the embodiment of the present invention will be described below.
In FIG. 1, in order to describe the processing flow of the embodiment of the present invention, one image data is divided into upper and lower parts, the upper part is subjected to image processing in the first integrated circuit (1), and the lower part The second integrated circuit (2) performs image processing, and finally, the two processed image data are integrated and output to the LCD monitor (103).
An example of graphic processing in the two integrated circuits is not limited to this. For example, when performing image processing for a stereoscopic display, the first integrated circuit (1) processes the image data for the left eye, and the second integrated circuit (2) processes the image data for the right eye. Also good. Further, the image data of the background portion may be processed in the first integrated circuit (1), and the image data of the character portion may be processed in the second integrated circuit (2).

  First, stream data and image data such as drawing commands stored in the CGROM (101) are input to the first integrated circuit (1) via the first input interface (12).

  When the image data is input, the first integrated circuit (1) performs a classification process in the first central processing unit (11). In the classification process, the image data for the first integrated circuit (1) is developed in the first system memory (10). On the other hand, the image data for the second integrated circuit is output from the first communication interface (13) and input to the second communication interface (23) via the communication bus (4). When the image data is input, the second integrated circuit (2) develops the image data in the second system memory (20).

  Thus, since the first integrated circuit (1) and the second integrated circuit (2) can share and use peripheral devices (particularly, the non-volatile memory 101 such as CGROM), the system cost can be reduced. The increase can be minimized.

  Thereafter, the first central processing unit (11) activates the first image engine (14) and at the same time through the communication between the first communication interface (13) and the second communication interface (23). The second image engine (24) of the two integrated circuits (2) is activated.

  The activated first image engine (14) and second image engine (24) execute image processing using the system memory (10, 20) and VRAM (17, 27), respectively. In each image engine (14, 24), for example, 3D graphics rendering processing and video moving image decoding processing are executed.

  Thus, the first image engine (1) and the second image engine (2) perform image processing in parallel. For this reason, the embodiment of the present invention can obtain a graphic processing performance twice as high as that of a conventional apparatus that performs image processing in a single integrated circuit shown in FIG. 6, for example.

  When the image processing is completed in each image engine (14, 24), the processed image data after the image processing is stored in the first system memory (10) and the second system memory (20), respectively. The second image engine (24) notifies the first central processing unit (11) of the end of the image processing via the interrupt bus (6). Therefore, the first central processing unit (11) can recognize the end of the image processing in the second integrated circuit (2) by the interrupt notification.

  As described above, in the embodiment of the present invention, the overall control of the entire system can be performed by the first central processing unit (11) mounted on the first integrated circuit (1). Communication in the network can be minimized.

  Thereafter, the first central processing unit (11) controls the processed image data stored in the first system memory (10) by controlling the first output interface (15), and the second integrated circuit (2). To the second input interface (22).

  At this time, for example, an LCD parallel RGB output interface can be used as the first output interface (15). As the second input interface (22), for example, a Camera parallel RGB input interface can be used. The first output interface (15) and the second input interface (22) are used as an interface for outputting image data to an LCD monitor or an interface for acquiring image data even when the integrated circuit is a single unit. It functions. Therefore, according to the embodiment of the present invention, the existing image data output interface and the existing image data acquisition interface can be used as an interface for data transfer between integrated circuits. Therefore, high-throughput data transfer can be performed between integrated circuits without providing new data transfer means. That is, according to the present invention, the communication between integrated circuits can be performed using the existing interface without providing a dedicated interface for communication between the integrated circuits, so that an increase in circuit scale can be avoided. .

  When the second integrated circuit (2) receives the processed image data processed by the first integrated circuit (1) through the second input interface (22), the second integrated circuit (2) receives the processed image data as the second integrated circuit (2). Store in system memory (20). For this reason, on the second system memory (20), the processed image data (first processed image data) in the first integrated circuit (1) and the processed image data (first processed image data (2)) (Second processed image data) is developed.

  The first central processing unit (11) controls the second output interface (25) via communication in the communication bus (4) and is expanded on the second system memory (20). The first processed image data and the second processed image data are integrated and combined. The integrated data synthesized and synthesized is output to the LCD monitor (103) via the second output interface (25).

  As described above, according to the embodiment of the present invention, CGROM or the like can be shared between two integrated circuits, and it is necessary to newly provide communication means (such as a bus) between the integrated circuits. Therefore, it is possible to double the graphic processing performance while minimizing the increase in BOM cost.

(2. Second Embodiment)
Hereinafter, the second embodiment of the present invention will be described with reference to FIGS.
FIG. 2 shows an embodiment in which a first integrated circuit (1), a second integrated circuit (2), and a third integrated circuit (3) are cascade-connected to each other.
As shown in FIG. 2, in this embodiment, the first integrated circuit is a main circuit (Master), and the second integrated circuit (2) and the third integrated circuit (3) are subordinate (Slave). ).

  Each configuration of the first integrated circuit (1) and the second integrated circuit (2) is the same as that in the embodiment in FIG.

  In the present embodiment, the second integrated circuit (2) and the third integrated circuit (3) are connected to the first integrated circuit (1). As shown in FIG. 2, the third integrated circuit includes a third central processing unit (31), a third input interface (32), a third communication interface (33), and a third image engine (34). ), A third output interface (35), a third system memory interface (36), a third VRAM (37), and a third interrupt interface (38). These configurations are the same as those in the first integrated circuit (1) and the second integrated circuit (3) described above. For this reason, the third integrated circuit (3) preferably has the same circuit configuration as the first integrated circuit (1) and the second integrated circuit (2) described above. The third integrated circuit (3) may be a duplicate of the first integrated circuit (1) or the second integrated circuit (2). However, as a matter of course, the third integrated circuit (3) may include a different configuration from the first integrated circuit (1) and the second integrated circuit (2).

  In the present embodiment, as shown in FIG. 2, the second integrated circuit is connected to the first integrated circuit (1) via the communication bus (4) such as PCIe or PCI having a plurality of lanes. The circuit (2) and the third integrated circuit (3) are connected. That is, the first integrated circuit (1) and the main circuit (Master) are used, and the second integrated circuit (2) and the third integrated circuit (3) are used as a subordinate circuit (Slave). Done. Therefore, in the present embodiment, for example, one image is divided into three, the upper stage portion is subjected to image processing in the first integrated circuit (1), and the middle portion is subjected to image processing in the second integrated circuit (2). In the third integrated circuit (3), the lower stage can be image-processed.

  In the present embodiment, the first central processing unit (11) mounted on the first integrated circuit (1) is connected to the second integrated circuit (2) via the communication on the communication bus (4). The second image engine (24), the second output interface (25), the third image engine (34) of the third integrated circuit (3), and the third output interface (35) are controlled. Thus, in this embodiment, the first central processing unit (11) controls the governance of the entire system. The second integrated circuit (2) and the third integrated circuit (3) also have a second central processing unit (21) and a third central processing unit (31), respectively. The function is stopped.

  The first integrated circuit (1), the second integrated circuit (2), and the third integrated circuit (3) share the CGROM (101). When image data is input from the CGROM (101) to the first integrated circuit (1), the first central processing unit (11) converts the image data into the first integrated circuit (1) and the second integrated circuit (1). The integrated circuit (2) and the third integrated circuit (3) are separated and developed in the respective system memories (10, 20, 30).

  Thereafter, the first central processing unit (11) activates the first image engine (14) and at the same time, the second image engine (24) and the third image via the communication bus (4). The engine (34) is started. Then, the image processing is executed in parallel by the three image engines (14, 24, 34).

  When the image processing is completed in the second image engine (24) and the third image engine (34), an interrupt notification is transmitted to the first central processing unit (11) via the interrupt bus (6). The

  The first processed image data processed in the first integrated circuit (1) is sent from the first output interface (15) through the first input / output bus (5a) to the second input interface ( 22).

  The first processed image data is stored in the second system memory (20) and then integrated with the second processed image data processed in the second integrated circuit (2). The integrated data is sent from the second output interface (25) to the third integrated circuit (3) via the second input / output bus (5b).

  The third integrated circuit (3) acquires the integrated data output from the second integrated circuit (2) through the third input interface. The first central processing unit (11) controls the third input interface (32) via the communication bus (4) and stores the integrated data in the system memory (30). Then, the first central processing unit (11) controls the third output interface (35) via the communication bus (4), and the third data generated by the integrated data and the third image engine 34. The processed image data are integrated and synthesized and output to the LCD monitor (103).

  In this way, three times the graphic processing performance can be obtained by cascading three integrated circuits as compared with the case where the integrated circuits are used alone. Further, as shown in FIG. 2, each integrated circuit can share and use peripheral devices (CGROM, etc.), so that even if the number of integrated circuits increases, the increase in system cost is minimized. It can be.

  In the present invention, the number of integrated circuits to be connected is not limited to two or three, but may be four or more. In this case, n times of graphic processing performance can be obtained by n cascade connections. Therefore, the graphic processing performance can be adjusted in a scalable manner by appropriately increasing or decreasing the number of integrated circuits to be connected according to the required performance.

  Further, as shown in FIG. 3, in the second integrated circuit (2) and the third integrated circuit (3), the connection with the system memory can be omitted. For example, when the capacity of the VRAM (27, 37) incorporated in the second integrated circuit (2) and the third integrated circuit (3) is sufficiently larger than the image processing capacity, the second image engine (24 ) And the third image engine (34) can be transferred directly to the output interface (25, 35) without going through the system memory, the system memory becomes unnecessary, further saving the system cost. Is possible.

(3. Computer)
FIG. 4 is a block diagram showing an embodiment (computer) of the present invention. This embodiment relates to a computer based on computer graphics (such as a graphic computer). As shown in FIG. 4, the computer includes a central processing unit (CPU) 102, a geometry calculation unit such as a geometry calculation circuit 103, a rendering unit such as a renderer 104, a texture generation unit such as a texture generation circuit 105, and an illumination processing circuit 107. An illumination processing unit such as a display circuit 108, a display information generation unit such as a display circuit 108, a frame buffer 109, and a monitor 110. These elements are connected by a bus or the like and can transmit data to each other. In addition, the storage unit may include a main memory (not shown), various tables, a work memory 111 serving as a work area, and a texture memory 112 that stores textures. The hardware constituting each unit is connected through a bus, for example. The storage unit may be configured by a RAM such as a VRAM, a CR-ROM, a DVD, or a hard disk.

  A central processing unit (CPU) 102 is a device for controlling a program for generating an image. The work memory 111 may store data used by the CPU 102 and a display list. Then, the CPU 102 may read a program stored in the main memory and perform a predetermined process. However, the predetermined processing may be performed only by hardware processing. For example, the CPU 102 reads polygon data as world coordinate three-dimensional object data from the work memory 111 and outputs the polygon data to the geometry calculation circuit 103. Specifically, those having a main processor, a coprocessor, a data processor, four arithmetic operation circuits, or a general-purpose operation circuit as appropriate. These are connected by a bus, for example, so that signals can be exchanged. In addition, a data expansion processor for expanding compressed information may be provided.

  The CPU 102 reads polygon data from the work memory 111 and outputs the polygon data to the geometry calculation circuit 103. The geometry calculation circuit 103 performs processing such as coordinate conversion of the input polygon data into data of a viewpoint coordinate system with the viewpoint as the origin. The geometry calculation circuit 103 outputs the processed polygon data to the renderer 104. The renderer 104 converts polygon unit data into pixel unit data. The renderer 104 and the texture generation circuit 105 generate a texture color in units of pixels based on the texture data stored in the texture memory 112. The texture generation circuit 105 outputs pixel unit data having texture color information to the illumination processing circuit 107. The illumination processing circuit 107 shades a polygon having texture color information using a normal vector, barycentric coordinates, and the like in units of pixels. The illumination processing circuit 107 outputs the shaded image data to the display circuit 108. The display circuit 108 writes the image data input from the illumination processing circuit 107 to the frame buffer 109 and reads the image data written to the frame buffer 109 to obtain display image information. At the same time, 2D / 3D synthesis processing can be performed by using information such as an edge buffer. The display circuit 108 outputs display image information to the monitor 110. The monitor 110 displays a computer graphics image according to the input display image information.

(4. Game console)
FIG. 5 is a block diagram of an embodiment (game machine) according to the present invention. The embodiment represented by this block diagram can be suitably used particularly as a portable, home or business game machine. Therefore, in the following, it will be described as a game machine. Note that the game machine shown in the figure may include at least the processing unit 200 (or may include the processing unit 200 and the storage unit 270, or the processing unit 200, the storage unit 270, and the information storage medium 280). These blocks (for example, the operation unit 260, the display unit 290, the sound output unit 292, the portable information storage device 294, and the communication unit 296) can be arbitrary constituent elements.

  When the system is turned on, part or all of the information stored in the information storage medium 280 is transferred to the storage unit 270, for example. A game processing program is stored in, for example, the main memory 272, and various data are stored in the texture storage unit 276, a table (not shown), or the like.

  Operation information from the operation unit 260 is transmitted to the processing unit 200 via, for example, a serial interface or a bus (not shown), and sound processing and various image processing are performed. The sound information processed by the sound processing unit 250 is transmitted to the sound output unit 292 via the bus and released as sound. Save information stored in a portable information storage device 294 such as a memory card is also transmitted to the processing unit 200 via a serial interface or bus (not shown), and predetermined data is read from the storage unit 270.

  The image processing unit 210 performs various types of image processing in accordance with instructions from the game processing unit 220. Specifically, the geometry calculation unit 232 performs various geometry calculations (three-dimensional coordinate calculation) such as coordinate conversion, clipping processing, perspective conversion, or light source calculation. Then, the object data (object vertex coordinates, vertex texture coordinates, luminance data, etc.) after the geometry processing (after perspective transformation) is stored and saved in the main memory 272 of the storage unit 270, for example. Next, the drawing unit 240 draws the object in the frame buffer 274 based on the object data after the geometry calculation (after perspective transformation) and the texture stored in the texture storage unit 276.

  The information stored in the frame buffer 274 is transmitted to the display unit 290 via the bus and rendered. In this way, it functions as a game machine having computer graphics.

  The embodiment of the present invention is not limited to the above-described computer or game machine, and can be applied to various electronic devices that execute computer graphics processing.

  ADVANTAGE OF THE INVENTION According to this invention, the integrated circuit device which can adjust graphics processing performance scalable can be provided. Therefore, the present invention can be suitably used in the computer industry.

DESCRIPTION OF SYMBOLS 1 1st integrated circuit 2 2nd integrated circuit 3 3rd integrated circuit 4 Communication bus 5 Input / output bus 5a 1st input / output bus 5b 2nd input / output bus 6 Interrupt bus 10 1st System memory 11 first central processing unit 12 first input interface 13 first communication interface 14 first image engine 15 first output interface 16 first system memory interface 17 first VRAM
18 First interrupt interface 20 Second system memory 21 Second central processing unit 22 Second input interface 23 Second communication interface 24 Second image engine 25 Second output interface 26 Second system memory Interface 27 Second VRAM
28 second interrupt interface 30 third system memory 31 third central processing unit 32 third input interface 33 third communication interface 34 third image engine 35 third output interface 26 third system memory Interface 27 Third VRAM
28 Third interrupt interface

Claims (6)

An integrated circuit device for performing graphics processing,
A first integrated circuit (1) capable of independent graphics processing ;
A second integrated circuit (2) capable of graphics processing independently ;
A communication bus (4) connecting the first integrated circuit (1) and the second integrated circuit (2);
An input / output bus (5) for outputting a calculation result of the first integrated circuit (1) to the second integrated circuit (2);
The first integrated circuit (1) includes:
A first central processing unit (11);
A first input interface (12) for inputting image data including stream data and a drawing command ;
Based on the control of the first central processing unit (11), a part of the image data input to the first input interface (12) via the communication bus (4) is converted into the second A first communication interface (13) for transferring to the integrated circuit (2) of
A first image engine (14) that performs image processing on the image data based on control of the first central processing unit (11);
A first output for outputting the first processed image data image-processed by the first image engine (14) to the second integrated circuit (2) via the input / output bus (5). An interface (15),
The second integrated circuit (2) is:
A second central processing unit (21) according to the control of the first central processing unit (11) in a connected state with the first integrated circuit (1);
A second communication interface (23) for receiving part of the image data transferred from the first integrated circuit (1) via the communication bus (4);
A second image engine (24) for image-processing a part of the image data received by the second communication interface (23) based on the control of the first central processing unit (11);
A second input interface (22) to which the first processed image data output from the first integrated circuit (1) is input via the input / output bus (5);
The second processed image data input to the second input interface (22) and the second processed image data processed by the second image engine (24) are integrated and output. An output interface (25) ,
When the first integrated circuit (1) is used alone, the first output interface (15) is a processed image obtained by performing graphics processing on the display device with the first integrated circuit (1). An output interface that can output data,
The integrated circuit device, wherein the second input interface (22) is an input interface capable of directly inputting the image data when the second integrated circuit (2) is used alone .
The first integrated circuit (1) is connected to a first system memory (10),
The image data input to the first input interface (12) is developed in the first system memory (10) based on the control of the first central processing unit (11), and the first data is input to the first input interface (12). The image is processed in the image engine (14),
The second integrated circuit (2) is connected to a second system memory (20),
Part of the image data received by the second communication interface (23) is developed in the second system memory (20) based on the control of the first central processing unit (11), and the second The integrated circuit device according to claim 1, wherein image processing is performed in the second image engine (24).
The integrated circuit device according to claim 1, further comprising an interrupt bus (6) for performing interrupt processing in the first integrated circuit (1) and the second integrated circuit (2).
An integrated circuit device for performing graphics processing,
A first integrated circuit (1) capable of independent graphics processing ;
A second integrated circuit (2) capable of graphics processing independently ;
A third integrated circuit (3) capable of graphics processing alone ;
A communication bus (4) for connecting the first integrated circuit (1) to the second integrated circuit (2) and the third integrated circuit (3);
A first input / output bus (5a) for outputting a calculation result of the first integrated circuit (1) to the second integrated circuit (2);
A second input / output bus (5b) for outputting the operation result of the second integrated circuit (2) to the third integrated circuit (3),
The first integrated circuit (1) includes:
A first central processing unit (11);
A first input interface (12) for inputting image data including stream data and a drawing command ;
Based on the control of the first central processing unit (11), a part of the image data input to the first input interface (12) via the communication bus (4) is converted into the second An integrated circuit (2) and a first communication interface (13) for transferring to the third integrated circuit (3);
A first image engine (14) that performs image processing on the image data based on control of the first central processing unit (11);
A first processed image data image-processed by the first image engine (14) is output to the second integrated circuit (2) via the first input / output bus (5a). 1 output interface (15),
The second integrated circuit (2) is:
A second central processing unit (21) according to the control of the first central processing unit (11) in a connected state with the first integrated circuit (1);
A second communication interface (23) for receiving part of the image data transferred from the first integrated circuit (1) via the communication bus (4);
A second image engine (24) for image-processing a part of the image data received by the second communication interface (23) based on the control of the first central processing unit (11);
A second input interface (22) to which the first processed image data output from the first integrated circuit (1) is input via the first input / output bus (5a);
The first processed image data input to the second input interface (22) and the second processed image data image-processed by the second image engine (24) are integrated, and the integrated data is A second output interface (25) for outputting to the third integrated circuit via a second input / output bus (5b),
The third integrated circuit (3) is:
A third central processing unit (31) according to the control of the first central processing unit (11) in a connected state with the first integrated circuit (1) and the second integrated circuit (2);
A third communication interface (33) for receiving part of the image data transferred from the first integrated circuit (1) via the communication bus (4);
A third image engine (34) for image-processing a part of the image data received by the third communication interface (33) based on the control of the first central processing unit (11);
A third input interface (32) to which the integrated data output from the second integrated circuit (2) is input via the second input / output bus (5b);
A third output interface (3) for integrating and outputting the integrated data input to the third input interface (32) and the third processed image data processed by the third image engine (34). and 35), comprising a,
When the first integrated circuit (1) and the second integrated circuit (2) are used alone, the first output interface (15) and the second output interface (25) are display devices. On the other hand, an output interface capable of outputting processed image data subjected to graphics processing by the first integrated circuit (1) and the second integrated circuit (2),
When the second integrated circuit (2) and the third integrated circuit (3) are used alone, the second input interface (22) and the third input interface (32) are the images. An integrated circuit device that is an input interface capable of directly inputting data .
5. A computer on which the integrated circuit device according to claim 1 is mounted.
  A game machine on which the integrated circuit device according to any one of claims 1 to 4 is mounted.

Images