JP4837144B2 - Semiconductor memory device and control method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device using a flash memory and a control method thereof, and more particularly to control of a compaction search.

  In general, a nonvolatile memory, for example, a flash memory cannot be overwritten when data is written. Therefore, it is necessary to erase data once and then write data. When such data writing and erasing are repeated, the divided unnecessary areas remain without being erased. The process of erasing unnecessary areas and collecting used areas into a continuous area is called compaction or garbage collection. A conventional garbage collection process of a semiconductor memory device is described in Patent Document 1, for example.

  Data D is written to the address (A, a) of the memory unit based on a write request from the host. Thereafter, there is a write request from the host to the frame at address (A, a) again, and a new version of data D-1 is written to the frame where no data is written, for example, the data portion at address (B, m). . In the pointer portion of the address (A, a), “B, m” is written as the link destination address. Thereafter, when there is a write request from the host to the address (A, a), the data D-2 is written to the frame in which no data is written, for example, the data portion of the address (C, n), as described above. In the pointer portion of the address (B, m), “C, n” is written as the link destination address.

  When garbage collection is performed in such a state, the frame at the address (B, m) merely indicates a link relationship and has no meaning as data. Therefore, garbage collection erases the frame “B, m”.

  In this process, first, the frame data at the address (A, a) is saved in the buffer unit, and the pointer is rewritten to C, n on the buffer. At the same time, the data at addresses (B, m) and (A, a) are erased. Thereafter, the data at the address (A, a) with the rewritten pointer is written to the same address in the memory unit. As a result, the link destination of the address (A, a) is directly (C, n), and the frame of the address (B, m) is a frame into which data can be written.

  However, when rewriting control is performed according to the pointer portion in this way, it is necessary to follow the link destination in response to a write request from the host, which is time consuming. A table part comprising a part and a logical address part is provided. The instruction address part is a part indicating an address instructed by the host when accessing data from the host to the nonvolatile memory. The valid bit part is a part indicating whether or not data is stored in the memory block of the corresponding memory part. The logical address part is a part that logically converts an address instructed by the host and determines the address of the memory block in the memory part.

  The garbage collection control means has a preset threshold value, and when there is a write request from the host, the added value of the number of data written blocks and the number of memory blocks for executing the write request with reference to the table section is the threshold value. If the sum exceeds the threshold, garbage collection of the memory unit is executed. As the threshold value, an appropriate value such as a value indicating 90% of the alternative area of the memory unit is set. Since garbage collection is performed based on the threshold value in this way, it is possible to prevent the garbage collection process from being executed while a write request from the host is being executed.

  Furthermore, in Patent Document 1, the garbage collection control means has a timer function. The usage status of the memory block in the memory unit 16 is monitored with reference to the table unit 19, and when the status of the memory block does not exceed the threshold value, the memory block is written and a timer is set to determine the status of the memory block. When the threshold value exceeds the threshold value, the memory part is garbage collected and the timer is reset. The timer is in a set state and has a function of executing garbage collection after the predetermined time has elapsed. By periodically performing garbage collection in this way, it is possible to prevent the garbage collection process from having to be executed while the write request from the host is being executed.

JP-A-6-222985 (paragraphs 0011-0015, 0028, 0039, 0050)

  The apparatus described in Patent Document 1 periodically performs garbage collection. In order to perform garbage collection, the garbage collection control means needs to look up the address of the frame in which no data is written with reference to the table portion, and the ratio of the time of this search processing to the entire garbage collection processing is Big was the problem.

  An object of the present invention is to provide a semiconductor memory device that can efficiently search for a compaction candidate.

  A semiconductor memory device according to an aspect of the present invention is a semiconductor memory device including a nonvolatile memory and a controller connected to the nonvolatile memory, and the controller determines a compaction candidate for the nonvolatile memory. Main memory for storing candidate information for requesting, request issuing means for issuing an access request for candidate information in the main memory, delay means for delaying an access request issued by the request issuing means, and the delay Access means for accessing the candidate information in the main memory based on the access request delayed by the means;

  According to one aspect of the present invention, since the access request for the compaction candidate information in the main memory is executed with a delay, it is possible to prevent access to the main memory for the compaction candidate information from being concentrated within a unit time. The original access of the main memory for data transfer is not hindered by the access for the compaction target candidate information, and the performance degradation of the semiconductor memory device can be prevented.

1 is a diagram of a semiconductor memory device according to an embodiment of the present invention. It is a figure which shows the effective page management bitmap table for a compaction search. It is a flowchart which shows the compaction search which concerns on embodiment of this invention. It is a figure which shows the mode of the delay circuit which delays an access request and its confirmation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing an overall configuration of the semiconductor memory device of the first embodiment. The embodiment includes a plurality of semiconductor nonvolatile memories, for example, NAND flash memories 10 ₀ , 10 ₁ ... 10 _n and a flash memory controller 12. Each flash memory 10 ₀ , 10 ₁ ... 10 _n is composed of, for example, 2 to 16 memory chips. The flash memory controller 12 includes a flash memory I / F 30 connected to the flash memories 10 ₀ , 10 ₁ ... 10 _n . If the flash memory ₁₀ 0, ₁₀ 1 ... _{10 n} are accessible in parallel, not shown flash memory I / F30 also provided n pieces are connected respectively to the flash memory ₁₀ 0, ₁₀ 1 ... _{10 n} The The flash memory I / F 30 individually controls the flash memories 10 ₀ , 10 ₁ ... 10 _n regarding operation modes such as program, read, and erase.

The flash memory controller 12 includes a CPU 22, a main memory 24, a command processor 40, a data processor 42, an arbitration circuit 28, and a compaction search engine 36. These components are connected to the CPU bus 20. The main memory 24 is composed of DRAM and includes an in-block effective page management bitmap table 26 and a compaction candidate management table 25 for compaction processing of the flash memories 10 ₀ , 10 ₁ ... 10 _n .

An external ROM 14 is also connected to the CPU bus 20 of the flash memory controller 12. The ROM 14 includes firmware 16. The firmware 16 uses the CPU 22 to issue a read command and a write command to the flash memories 10 ₁ , 10 ₂ ,... 10 _n by an I / O command access to the flash memory I / F 30.

The flash memory I / F 30 receives an instruction from the CPU 22 and performs data transfer between the NAND flash memories 10 ₁ , 10 ₂ ,... 10 _n and the main memory 24.

  It is assumed that the firmware 16 operates by transferring the content programmed in the ROM 14 to the temporary storage unit in the CPU 22 or the main memory 24 when the system power supply is activated.

The intra-block valid page management bitmap table 26 is configured as shown in FIG. The NAND flash memory 10 ₁ , 10 ₂ ,... 10 _n has a bit map configuration for indicating whether each page is valid (Valid) or invalid (Invalid). The entire NAND flash memory 10 ₁ , 10 ₂ ,... 10 _n is divided into predetermined bytes, for example, 2112 bytes, and one page is formed for each of them, and predetermined pages, for example, 64 pages form one block. Valid indicates that there is data written in the page and that the data is valid. “Invalid” indicates that nothing has been written in the page, or data previously written in the page has become invalid (when data has been overwritten).

The valid / invalid state of the intra-block valid page management bitmap table 26 is updated when writing to the NAND flash memories 10 ₁ , 10 ₂ ,... 10 _n occurs. Here, the write operation from the firmware 16 is performed using a logical block address (LBA). Therefore, when data is actually written to the NAND flash memories 10 ₁ , 10 ₂ ,... 10 _n , the logical address is converted into a physical address (block address, page address) and data is written.

The NAND flash memories 10 ₁ , 10 ₂ ,..., 10 _n prevent the lifetime from being drastically reduced by performing writing to the same cell, so even if data is written multiple times with the same LBA, Performs a compaction process that newly writes data to pages with different physical addresses and invalidates the data stored in pages with previously written physical addresses. In order to carry out this valid / invalid management, an intra-block valid page management bitmap table 26 exists.

  Therefore, while the system is operating while performing such a write operation, it is essential that a block with a small number of valid pages (that is, a block targeted for compaction processing) is generated. .

  The firmware 16 uniquely counts the number of valid pages in the block, and if the valid number is equal to or less than a certain number, the block is entered in the compaction candidate management table 25 as one of compaction targets, and one of the blocks in the block Is applied to the compaction process. Compaction processing is an operation that collects valid page data in multiple blocks to be compacted, moves them to another block, invalidates the source page, and creates an empty block in which nothing is written. .

A compaction search engine 36 is provided as dedicated hardware for counting the number of in-block valid pages indicated by the in-block valid page management bitmap table 26. The firmware 16 periodically or uniquely operates the engine 36 to access the intra-block valid page management bitmap table 26 in the main memory 24 and count the number of valid pages in the block to search and specify the compaction target. , Added to the compaction candidate management table 25. Therefore, during the search operation may access to the main memory 24 is temporarily centralized, NAND-type flash memory ₁₀ 1, ₁₀ 2, ... inhibit a memory access required for data transfer between the 10 _n or CPU 22, Data provision speed performance for users may be degraded.

  In the present embodiment, the compaction search engine 36 delays the access request REQ1 to the main memory 24 issued to search the intra-block valid page management bitmap table 26 via the delay circuit 32, and the request request REQC is sent to the arbitration circuit 28. Supply. In addition to the request REQC, the arbitration circuit 28 receives an access request REQA to the main memory 24 issued from the flash memory I / F 30 and an access request REQB to the main memory 24 issued from the CPU 22. Arbitration (arbitration) is performed to determine a request to give the right to use the bus among the three requests. As a result of the arbitration, access requests to which the right to use the bus is given are executed in order. When the bus use right is given and the access to the main memory 24 is completed, confirmation ACKC, ACKA, and ACKB are returned to the delay circuit 32, the flash memory I / F 30, and the CPU 22.

  Similarly to the request PRQ1, the delay circuit 32 also delays the confirmation ACKC (the delay time may be the same as or different from the delay time for the request) and transmits it to the compaction search engine 36 as the confirmation AKC1. The delay time of the delay circuit 32 is adjusted by a delay time adjustment circuit 34 in which an adjustment value is set by the CPU 22. The CPU 22 can detect the access frequency of the main memory 24 by a command managed by the firmware 16. For this reason, the delay time is adjusted according to the access frequency of the main memory 24. Alternatively, the access frequency of the main memory may be detected by directly monitoring the bus line 20 with hardware (not shown) without using a command managed by the firmware 16.

The flash memory controller 12 also includes a command processor 40 and a data processor 42. The command processor 40 gives a read command and a write command from the CPU 22 to the NAND flash memories 10 ₁ , 10 ₂ ,... 10 _n . The data processor 42 processes read data and write data of the NAND flash memories 10 ₁ , 10 ₂ ,... 10 _n .

  FIG. 3 is a flowchart showing the compaction search process. In block # 12, the CPU 22 activates a compaction search engine 36 for performing a compaction search. At startup, the compaction search engine 36 is provided with a search start address and a search data size. The compaction search engine 36 reads the data in the area of the main memory 24 designated by these. That is, here, the initial value of the search start address is the first address of the valid page management bitmap table 26 in the main memory 24, and the search data size is the size of the valid page management bitmap table 26. The CPU 22 can start the compaction search even while user data transfer and data transfer related to the NAND flash are being executed.

  In block # 14, the CPU 22 detects the access frequency of the main memory 24 by a command managed by the firmware 16, and sets the access frequency information in the delay time adjustment circuit 34. It is determined in block # 16 whether or not the access frequency is more crowded than the reference frequency. When the access is more congested than the reference frequency, the delay time is lengthened in block # 18, and conversely, when the access is vacant than the reference frequency, the delay time is shortened in block # 20. For this reason, when the access is congested, the delay time of the delay circuit 32 becomes long, and when the access is free, the delay time becomes short. The delay time for the request REQ1 may be different from the delay time for the confirmation ACKC or may be the same.

In block # 22, the compaction search engine 36 asserts an access request REQ1 to the main memory 24. After a delay time T ₀ from the assertion of the access request REQ1, the access request REQC to the arbitration circuit 28 is asserted in block # 24. Therefore, the longer the delay time T _0, the execution frequency of the access request REQ1 to the main memory 24 from the compaction search engine 36 is reduced.

The arbitration circuit 28 receives an access request REQA to the main memory 24 issued from the flash memory I / F 30 in block # 26, an access request REQB to the main memory 24 issued from the CPU 22, and an access issued from the delay circuit 32. General arbitration (arbitration of bus use right) is performed with the request REQC (a request in which the access request REQ1 issued from the compaction search engine 36 is delayed by time T ₀ ). If the access request REQC has the right to use the bus, the data in the valid page management bitmap table 26 is accessed in block # 28, and candidate information for determining a compaction candidate (a block in which the number of valid pages in the block is a certain number or less (Effective / invalid information of each page for finding). Note that the size of data by one access in block # 28 is, for example, 16 bytes. In one compaction search, the data in the valid page management bitmap table 26 is accessed 16 bytes at a time.

When the reading of the data (compaction candidate information) in the valid page management bitmap table 26 is completed, the arbitration circuit 28 asserts a confirmation ACCC at block # 30. Delay circuit 32 asserts a confirmation ACK1 to compaction search engine 36 in block # 32 after a delay time _{T 1} since the asserted confirmation ACKC. The read compaction candidate information is sent to the compaction search engine 36 together with the confirmation ACK1. The compaction candidate information is entered into the compaction candidate management table 25 by the compaction search engine 36.

  In block # 34, it is determined whether or not a search for the search data size has been performed. If not, the process returns to block # 14, and the next 16 bytes of the valid page management bitmap table 26 are searched. The above process is repeated until a search for the specified search data size is performed. Thereby, compaction candidate information (for example, a block having a certain number or less of valid pages in a block) is stored in the compaction candidate management table 25.

  Compaction processing itself, that is, reading compaction candidate information from the compaction candidate management table 25, collecting valid page data in the compaction candidate block, moving it to another block, invalidating the source page, and freeing the compaction candidate block The process of making a block can be performed at a different timing after the search. By performing the search in advance, the compaction process can be performed efficiently.

FIG. 4 is a diagram for explaining the delay operation of the delay circuit 32. Be an access request REQ1 is asserted for the compaction search from the delay circuit 32 is compaction search engine 36, immediately without asserting a request REQC, it asserts a request REQC delayed by a predetermined delay time T _0. Similarly, confirmation is asserted by the arbitration circuit 28 ACKC be delayed by a predetermined delay time _{T 1,} it is returned to the compaction search engine 36 as a confirmation ACK1. The compaction search engine 36 cannot issue the access request REQ1 for the next compaction search unless it receives the confirmation ACK1 after issuing the access request REQ1.

For this reason, the issuing frequency of the access request REQ1 for compaction search is determined according to the delay times T ₀ and T ₁ . According to the present embodiment, since the delay times T ₀ and T ₁ depend on the access frequency of the main memory, the issue frequency of the access request REQ1 for compaction search is eventually controlled according to the access frequency of the main memory. The Therefore, the compaction search is not concentrated in a certain time, and the main memory access by the CPU or the flash memory is not hindered by the compaction search. Furthermore, the compaction search execution frequency is adjusted according to the access frequency of the main memory, so that the compaction search can be performed during a period when the main memory access is not available, thereby reducing the access performance of the main memory. And compaction processing can be performed efficiently.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment. For example, the example of data in the valid page management bitmap table 26 has been described as candidate information stored in the main memory 24 for determining a compaction candidate. However, the present invention is not limited to this, and information indicating the number of valid pages for each block. You may use itself. The delay circuit 32 also delays the confirmation ACKC asserted by the arbitration circuit 28 together with the access request REQ1 for compaction search from the compaction search engine 36. However, even if only the access request REQ1 is delayed, Since concentration of issuing access requests REQ1 can be prevented, the confirmation ACKC may be passed to the compaction search engine 36 without delay. Furthermore, although the delay time is variable for each issue of the access request REQ1 according to the access frequency of the main memory, it is not always necessary to change for each issue, and may be variable for every fixed time.

  DESCRIPTION OF SYMBOLS 12 ... Flash memory controller, 20 ... CPU bus, 22 ... CPU, 24 ... Main memory, 25 ... Compaction candidate management table, 26 ... In-block effective page management bitmap table, 28 ... Arbitration circuit, 30 ... Flash memory I / F 32 ... Delay circuit 34 ... Delay time adjustment circuit 36 ... Compaction search engine

Claims (11)

Non-volatile memory;
A controller connected to the non-volatile memory;
A semiconductor memory device comprising:
The controller is
A main memory for storing candidate information for determining compaction candidates for the nonvolatile memory;
Request issuing means for issuing a first access request of the main memory for searching the candidate information;
Delay means for delaying the first access request issued by the request issuing means for a first time according to the access frequency of the main memory;
An arbitration circuit that arbitrates access requests;
An access means for accessing candidate information in the main memory based on the first access request delayed by the delay means for the first time when the arbitration circuit grants the right to the first access request;
A semiconductor memory device comprising: The controller further comprises confirmation issuing means for issuing an end confirmation of access by the access means,
2. The semiconductor memory device according to claim 1, wherein the end confirmation issued by the confirmation issuing means is delayed by a second time according to the access frequency of the main memory via the delay means and returned to the request issuing means. The controller further comprises detection means for detecting the access frequency of the main memory,
When the access frequency detected by the detection means is crowded from a predetermined frequency, the first and second times of the delay means are lengthened, and the access frequency detected by the detection means is not crowded than the predetermined frequency 2. The semiconductor memory device according to claim 1, wherein said first and second times of said delay means are shortened.   The semiconductor memory device according to claim 2, wherein the first time and the second time are different times.   The semiconductor memory device according to claim 2, wherein the first time and the second time are the same time. The nonvolatile memory includes a plurality of flash memories,
The semiconductor memory device according to claim 1, wherein the controller includes a plurality of interfaces capable of accessing the plurality of flash memories in parallel. A method for controlling a semiconductor memory device comprising: a nonvolatile memory; and a main memory for storing candidate information for determining a compaction candidate for the nonvolatile memory,
Issuing a first access request of the main memory for retrieving the candidate information;
Delaying the issued first access request for a first time according to the access frequency of the main memory;
Arbitrating access requests,
When the arbitration grants the right to the first access request, accessing the candidate information in the main memory based on the first access request delayed by the first time;
A control method comprising: Issuing an end confirmation of the first access;
8. The control method according to claim 7, further comprising returning the issued end confirmation to the issuer of the first access request with a second time delay in accordance with the access frequency of the main memory. Detecting the access frequency of the main memory,
When the detected access frequency is crowded than a predetermined frequency, the first and second times are lengthened, and when the detected access frequency is not crowded than the predetermined frequency, the first and second times are shortened. Item 8. The control method according to Item 7.   The control method according to claim 8, wherein the first time and the second time are different times.   The control method according to claim 8, wherein the first time and the second time are the same.

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