JP4833010B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device including a light receiving unit in which a plurality of pixel units each having a photodiode that generates an amount of electric charge corresponding to an amount of incident light is arranged.

The solid-state imaging device includes a light receiving unit in which a plurality of pixel units each having a photodiode are two-dimensionally arranged, and outputs a digital value corresponding to the amount of charge generated in the photodiode of each pixel unit. A conversion circuit may also be provided. In such a solid-state imaging device, the number of pixels is steadily increasing, and high-speed imaging is required. Such an increase in the number of pixels and an increase in imaging speed generally lead to an increase in power consumption of the solid-state imaging device.
Special table 2002-505002

  By the way, depending on the application of the solid-state imaging device, there is a case where it is desired to suppress an increase in power consumption, or rather, it is desired to reduce power consumption. For example, when it is desired to drive the solid-state imaging device with a battery for a long time, or when it is desired to suppress heat generation due to the structure of the device including the solid-state imaging device. The present invention has been made to solve the above-described problems, and provides a solid-state imaging device capable of suppressing an increase in power consumption even when increasing the number of pixels and increasing the imaging speed. For the purpose.

  The solid-state imaging device according to the present invention includes (1) a photodiode that generates an amount of charge according to the amount of incident light, and a voltage value according to the amount of charge accumulated in the parasitic capacitance formed at the gate terminal. Amplifying transistor to be output, a transfer transistor for transferring the charge generated in the photodiode to the gate terminal of the amplifying transistor, a discharging transistor for initializing the charge in the parasitic capacitance portion, and a voltage output from the amplifying transistor A plurality of pixel portions each having a selection transistor for selectively outputting a value, and charges generated in the photodiodes in each of the plurality of pixel portions are accumulated in the parasitic capacitance portion in a period indicated by the charge accumulation operation control signal (2) After the charge accumulation operation in each of the plurality of pixel units, the light is output from the selection transistor in each of the plurality of pixel units. An output unit that outputs a digital value corresponding to the voltage value to be output; and (3) an amplifier having a first input terminal, a second input terminal, and an output terminal. The input terminal is connected, the second input terminal of the amplifier is connected to a bias potential for initializing the charges of the parasitic capacitance portions of each of the plurality of pixel portions, and a plurality of signals are output based on an output signal from the output terminal of the amplifier. And an incident light total amount monitoring unit that outputs an incident light total amount signal indicating the total amount of light incident on the photodiodes of each pixel portion. The solid-state imaging device according to the present invention receives a total incident light amount signal output from the incident light total amount monitoring unit, and a plurality of pixels of the light receiving unit when the total incident light amount represented by the incident light total amount signal is larger than a threshold value. It is preferable to further include a control unit that generates a charge storage operation control signal for instructing the charge storage operation to each unit.

  In the solid-state imaging device according to the present invention, each pixel unit included in the light receiving unit is of an APS (Active Pixel Sensor) type, and includes a photodiode, an amplification transistor, a transfer transistor, a discharge transistor, and a selection transistor. have. In addition, the first input terminal of the amplifier included in the total incident light amount monitoring unit is connected to the discharging transistor of each of the plurality of pixel units. The second input terminal of the amplifier is connected to a bias potential for initializing the charge of the parasitic capacitance portion formed at the gate terminal of the amplification transistor of each of the plurality of pixel portions. Since the first input terminal of the amplifier is in an imaginary short relationship with the second input terminal, it has the same bias potential. Accordingly, in each pixel portion, when the discharge transistor and the transfer transistor are in the ON state, the potential of the gate terminal of the amplification transistor is reset and the charge generated in the photodiode is stored in the incident light total amount monitoring portion. Input to the first input terminal of the amplifier.

  Based on the output signal from the output terminal of the amplifier of the total incident light amount monitoring unit, an incident light total amount signal representing the total amount of light incident on the photodiodes of each of the plurality of pixel units is obtained. Then, when the total incident light amount represented by the total incident light amount signal is larger than the threshold value, a charge accumulation operation control signal for instructing the charge accumulation operation to each pixel unit of the light receiving unit is generated. In the light receiving portion, the charge generated in the photodiode in each pixel portion during the period indicated by the charge accumulation operation control signal is accumulated in the parasitic capacitance portion of the gate terminal of the amplifying transistor, and then from the selection transistor in each pixel portion. A digital value corresponding to the output voltage value is output from the output unit.

  In the solid-state imaging device according to the present invention, the incident light total amount monitoring unit includes a capacitance element and a switch provided between the first input terminal and the output terminal of the amplifier, a voltage value output from the output terminal of the amplifier, and a reference It is preferable that the circuit further includes a comparison circuit that compares the voltage values with each other and outputs a signal representing the comparison result as an incident light total amount signal, and the switch is controlled to be opened and closed according to the level of the incident light total amount signal. In this case, the incident light total amount signal output from the comparison circuit is a pulse signal having a pulse repetition frequency corresponding to the amount of light incident on the light receiving unit.

  In the solid-state imaging device according to the present invention, the total incident light amount monitoring unit further includes a capacitive element and a switch provided between the first input terminal and the output terminal of the amplifier, and the switch is controlled to be opened and closed at a constant period. It is preferable to output an output signal from the output terminal as an incident light total amount signal. In this case, the incident light total amount signal output from the amplifier is a triangular wave signal having a peak value corresponding to the amount of incident light to the light receiving unit.

  In the solid-state imaging device according to the present invention, the total incident light amount monitoring unit further includes a resistor provided between the first input terminal and the output terminal of the amplifier, and the output signal from the output terminal of the amplifier is input to the total amount of incident light. It is preferable to output as a signal. In this case, the incident light total amount signal output from the amplifier has a voltage value corresponding to the amount of incident light to the light receiving unit.

  The solid-state imaging device according to the present invention can suppress an increase in power consumption even when increasing the number of pixels or increasing the imaging speed.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

  FIG. 1 is a configuration diagram of a solid-state imaging device 1 according to the present embodiment. The solid-state imaging device 1 shown in this figure includes a light receiving unit 10, an incident light total amount monitoring unit 20, a row selecting unit 30, a column selecting unit 40, a voltage holding unit 50, an output unit 60, and a control unit 70. In this figure, wiring between elements is omitted or simplified.

The light receiving unit 10 is for capturing an image of incident light _, and includes pixel units P _{1,1 to} P _{M, N} that are two-dimensionally arranged in M rows and N columns. The pixel portion P _{m, n} is located in the m-th row and the n-th column. The M × N pixel units P _{1,1 to} P _{M, N} have a common configuration, and generate a charge corresponding to the amount of incident light, and a charge storage unit that stores the charge. And have. The light receiving unit 10 accumulates charges generated by the photodiodes in each of the M × N pixel units P _{1,1 to} P _{M, N} during a period indicated by the charge accumulation operation control signal output from the control unit 70. Accumulate by part. In other periods, the light receiving unit 10 outputs the charges generated by the photodiodes in each of the M × N pixel units P _{1,1 to} P _{M, N} to the incident light total amount monitoring unit 20. M and N are integers of 2 or more, m is an integer of 1 to M, and n is an integer of 1 to N.

The incident light total amount monitoring unit 20 outputs an incident light total amount signal indicating the total amount of light incident on the photodiodes of the pixel units P _{1,1 to} PM _{, N.} The incident light total amount monitoring unit 20 includes an amplifier A ₂₀ having an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the amplifier A ₂₀ is connected to each of the pixel portions P _{1,1 to} P _{M, N.} The non-inverting input terminal of the amplifier A ₂₀ is connected to a bias potential Vb1. The incident light total amount monitoring unit 20 outputs an incident light total amount signal based on the output signal from the output terminal of the amplifier A ₂₀ . Details of the incident light total amount monitoring unit 20 will be described later with reference to FIG.

The row selection unit 30 sequentially designates each row in the light receiving unit 10 under the control of the control unit 70, and each of the N pixel units P _{m, 1 to} P _{m, N in the} designated m-th row. A voltage value corresponding to the amount of charge stored in the charge storage unit is output to the voltage holding unit 50. The row selection unit 30 includes an M-stage shift register circuit, and each row in the light receiving unit 10 can be sequentially specified by an output bit of each stage of the shift register circuit.

The voltage holding unit 50 includes N holding circuits H _{1 to} H _N having a common configuration. The holding circuit H _n is connected to the _M pixel units P _{1, n to} P _{M, n} in the n-th column in the light receiving unit 10 _, and is output from any one of these pixel units P _{m, n.} The input voltage value is input, and the input voltage value is held and output. The holding circuit H _n can hold a voltage value representing a signal component on which a noise component is superimposed, and can also hold a voltage value representing a noise component.

The column selection unit 40 sequentially designates _N holding circuits H _{1 to} H _N included in the voltage holding unit 50, and outputs the voltage value held by the designated nth holding circuit H _n as an output unit. 60. The column selection unit 40 includes N stages of shift register circuits, and N holding circuits H _{1 to} H _N can be sequentially specified by output bits of each stage of the shift register circuit.

After the charge accumulation operation in each of the pixel units P _{m, 1 to} P _{m, N} , the output unit 60 performs digital values corresponding to voltage values output from the pixel units P _{m, 1 to} P _{m, N} (hereinafter, “ Pixel data ”). Further, the output unit 60 outputs the total incident light amount signal output from the incident light total amount monitoring unit 20 during the period when the pixel data is not output. The output unit 60 includes a difference calculation circuit 61, an AD conversion circuit 62, and a switch SW ₆₃ .

The difference arithmetic circuit 61 and processes the input voltage value output from the holding circuits H _n, and outputs a voltage value which is the processing result to the AD converter 62. The AD conversion circuit 62 receives the voltage value output from the difference calculation circuit 61, AD converts the input voltage value, and outputs a digital value (pixel data) as a result of the AD conversion. The switch SW _{63 also} receives pixel data output from the AD conversion circuit 62 and also receives an incident light total amount signal output from the incident light total amount monitoring unit 20, and is controlled by the control unit 70 to be a pixel. Either the data or the incident light total amount signal is selectively output to the common output signal line Lout.

The control unit 70 controls the overall operation of the solid-state imaging device 1. For example, the control unit 70 controls a row selection operation in the row selection unit 30, a column selection operation in the column selection unit 40, a data holding operation in the voltage holding unit 50, an AD conversion operation and an output signal selection operation in the output unit 60. . Further, the control unit 70 inputs the incident light total amount signal output from the incident light total amount monitoring unit 20, and when the total incident light amount represented by the incident light total amount signal is larger than the threshold value, the pixel unit P _m, A charge accumulation operation control signal for instructing a charge accumulation operation for each of _{1 to} P _{m, N} is generated.

The charge accumulation operation control signal for instructing the charge accumulation operation for each of the pixel portions P _{m, 1 to} P _{m, N of the} light receiving unit 10 may be directly supplied from the control unit 70 to the light receiving unit 10. A charge accumulation operation is instructed together with control signals (Reset (m) signal, Trans (m) signal and Hold (m) signal, which will be described later) provided to the gate terminals of the respective transistors included in each pixel unit P _{m, n.} There may be. Alternatively, a charge accumulation operation control signal is supplied from the control unit 70 to the row selection unit 30, and based on the charge accumulation operation control signal, a control applied to the gate terminal of each transistor included in each pixel unit _{Pm, n.} A signal may be generated.

2, the incident light amount monitoring unit 20 included in the solid-state imaging device 1 according to the present embodiment, a diagram showing a circuit configuration of each pixel unit P _{m, n} and the holding circuit H _n. In this drawing, the pixel portion P _{m, n} is representatively shown among the M × N pixel portions P _{1,1 to} PM _{, N} , and is representative of the N holding circuits H _{1 to} H _N. holding circuit H _n and is the shown. One total incident light amount monitoring unit 20 is provided for the M × N pixel units P _{1,1 to} P _{M, N.} In addition, one holding circuit H _n is provided for _M pixel portions P _{1, n to} P _{M, n} in each column.

The incident light total amount monitoring unit 20 includes an integration circuit 21 and a comparison circuit 22. The integrating circuit 21 includes an amplifier A ₂₀ , a capacitive element C ₂₀ and a switch SW ₂₀ . Inverting input terminal of the amplifier A ₂₀ is connected to the drain terminal of the pixel portions P _{1, 1} to P _{M, N} each discharge transistor T1 through the wire LRESET. The non-inverting input terminal of the amplifier A ₂₀ is connected to a bias potential Vb1. The bias potential Vb1 is a potential that can initialize the charge of the parasitic capacitance portion formed at the gate terminal of the amplifying transistor T3 of each of the pixel portions _{P1,1 to} PM _{, N.} Between the inverting input terminal and the output terminal of the amplifier A _20, parallel-connected capacitor elements C ₂₀ and switch SW ₂₀ are provided with each other. The comparison circuit 22 compares the voltage value output from the output terminal of the amplifier A ₂₀ with the reference voltage value Vref, and outputs a signal representing the comparison result as an incident light total amount signal. The switch SW ₂₀ is controlled to open and close in accordance with the level of the incident light total amount signal.

In the incident light total amount monitoring unit 20, when the switch SW ₂₀ is open, the charges input from the pixel units P _{1, 1 to} P _{M, N} to the inverting input terminal of the amplifier A ₂₀ via the wiring Lreset are capacitive elements. will be accumulated in the C _20, the voltage value corresponding to the accumulated charge amount is output from the output terminal of the amplifier a _20. The voltage value output from the output terminal of the amplifier A ₂₀ is compared with the reference voltage value Vref by the comparison circuit 22, and a signal indicating the comparison result is output as the incident light total amount signal.

According charge in the capacitor C ₂₀ is accumulated, finally, the magnitude relationship between the voltage value and the reference voltage value Vref output from the output terminal of the amplifier A ₂₀ is reversed, the level of the incident light amount signal changes Accordingly, the switch SW ₂₀ is closed. When the switch SW ₂₀ is closed, the capacitive element C ₂₀ is discharged, the voltage value output from the output terminal of the amplifier A ₂₀ is initialized, and the voltage value output from the output terminal of the amplifier A ₂₀ and the reference voltage value Vref Are reversed again, the level of the incident light total amount signal changes again, and the switch SW ₂₀ is opened accordingly. Thus, the incident light amount signal level becomes time varying pulse signal, the repetition frequency of the pulses represents the rate of charge flow into the inverting input terminal of the amplifier A ₂₀ (current value).

The pixel portion P _{m, n} is of the APS system and includes a photodiode PD and five MOS transistors T1 to T5. As shown in this figure, the discharge transistor T1, the transfer transistor T2, and the photodiode PD are sequentially connected in series, and the inverting input terminal of the amplifier A ₂₀ of the incident light total amount monitoring unit 20 is the drain of the transistor T1. The anode terminal of the photodiode PD is grounded.

  The amplification transistor T3 and the selection transistor T4 are connected in series, the reference voltage Vb2 is input to the drain terminal of the transistor T3, and the source terminal of the transistor T4 is connected to the wiring Vline (n). A connection point between the transistor T1 and the transistor T2 is connected to the gate terminal of the transistor T3 through the transistor T5. A constant current source is connected to the wiring Vline (n).

The Reset (m) signal is input to the gate terminal of the transistor T1, the Trans (m) signal is input to the gate terminal of the transistor T2, the Address (m) signal is input to the gate terminal of the transistor T4, and Hold (m ) Signal is input to the gate terminal of the transistor T5. These Reset (m) signal, Trans (m) signal, Address (m) signal, and Hold (m) signal are output from the row selection unit 30 under the control of the control unit 70, and N pixels in the m-th row. It is input in common to the parts P _{m, 1 to} P _{m, N.}

With respect to the entire pixel units P _{1,1 to} P _{M, N} , the operation sequence is distinguished in the following three ways. That is,
1) Incident light quantity monitoring period (before time t1 in FIG. 4)
2) Charge accumulation operation period (times t1 to t3 in FIG. 4)
3) Reading output period (after time t3 in FIG. 4)
It is. Among these, for the above 1) and 2), all the pixel portions P _{1,1 to} P _{M, N} start and end simultaneously. As for 3), the operation is sequentially repeated from the first row to the M-th row in units. The following description will be made on the premise of the operating principles 1) to 3).

The non-inverting input terminal of the amplifier A ₂₀ of the incident light amount monitoring unit 20, the bias potential Vb1 for initializing the electric charge of the parasitic capacitance section formed in the gate terminal of the amplifying transistor T3 are input, the amplifier inverting input terminal of the a _20, since the relationship of imaginary short with respect to the non-inverting input terminal, and also a bias potential Vb1. Therefore, when the Reset (m) signal and the Trans (m) signal are at a high level, the junction capacitance portion (charge storage portion) of the photodiode PD is discharged, and further, the Hold (m) signal is also at a high level. The charge of the parasitic capacitance portion formed at the gate terminal of the transistor T3 is discharged. During the incident light quantity monitoring period of 1) above, the Reset (m) signal and the Trans (m) signal are always at a high level, and the photocurrent of the entire photodiode is collectively collected through the inverting input terminal of the amplifier A _{20 to} the capacitive element C. Continue to flow to ₂₀ .

  After that, when the charge accumulation operation period of 2) is entered and the Reset (m) signal, Trans (m) signal, and Hold (m) signal of all the pixel portions become low level, the charge generated in the photodiode PD is It accumulates in the junction capacitor. At the end of the charge accumulation operation period, the Trans (m) signal and the Hold (m) signal are simultaneously set to the high level only for a short period, and the charge in the photodiode is instantaneously transferred to the gate capacitance of the transistor T3.

Thereafter, when each row readout period of 3) is entered, if the Hold (m) signal of the N pixel portions of the selected row is at a low level and the Address (m) signal is at a high level, the pixel portion A noise component is output from P _{m, n} to the wiring Vline (n). When the Trans (m) signal, Hold (m) signal, and Address (m) signal of the N pixel portions in the selected row become high level, the charge accumulated in the junction capacitance portion of the photodiode PD is reduced. A voltage value corresponding to the amount is output as a signal component to the wiring Vline (n).

The holding circuit H _n includes two capacitive elements C ₁ and C ₂ , and four switches SW ₁₁ , SW ₁₂ , SW ₂₁ , and SW ₂₂ . In the holding circuit _{H n,} the switch _{SW 11} and the switch _{SW 12} is provided between the serially connected to the wiring Vline (n) and the wiring Hline_s, one terminal of the capacitance _{C 1,} the switch _{SW 11} and the switch is connected to the connection point between the SW _12, the other end of the capacitive element C ₁ is grounded. The switch SW ₂₁ and the switch SW ₂₂ are connected in series and are provided between the wiring Vline (n) and the wiring Hline_n, and one end of the capacitor C ₂ is between the switch SW ₂₁ and the switch SW _22. is connected to the connection point, the other end of the capacitive element C ₂ is grounded.

In the holding circuit H _n, the switch SW ₁₁ is opened and closed according to the level of set_s signal supplied from the control unit 70. The switch SW ₂₁ opens and closes according to the level of the set_n signal supplied from the control unit 70. The set_s signal and the set_n signal are input in common to the _N hold circuits H _{1 to} H _N. The switches SW ₁₂ and SW ₂₂ open and close according to the level of the hshiht (n) signal supplied from the control unit 70.

In the hold circuit H _n , the noise component output from the pixel unit P _{m, n} to the wiring Vline (n) when the set_n signal changes from the high level to the low level and the switch SW ₂₁ is opened is the capacitance thereafter. It is held as a voltage value out_n (n) by the element C _2. set_s signal pixel unit P _m when the switch SW ₁₁ is opened in turn to a low level from the high _level, the signal component being output from the _n to the wiring Vline (n) is, thereafter, the voltage value by the capacitance element C ₁ out_s held as (n). When the hshiht (n) signal becomes high level, the switch SW ₁₂ is closed, the voltage value out_s (n) held by the capacitive element C ₁ is output to the wiring Hline_s, and the switch SW ₂₂ is closed. , the voltage value has been held by the capacitor element C ₂ out_n (n) is output to the wiring Hline_n. A difference between the voltage value out_s (n) and the voltage value out_n (n) represents a voltage value corresponding to the amount of charge generated in the photodiode PD of the pixel portion Pm _{, n} .

FIG. 3 is a diagram illustrating a circuit configuration of the difference calculation circuit 61 included in the solid-state imaging device 1 according to the present embodiment. As shown in this figure, the difference calculation circuit 61 includes an amplifier _A 64 _{to A 66,} switches _SW 64, _{SW 65,} and includes a resistor _R 1 to R _4. The inverting input terminal of the amplifier A ₆₆ is connected to the output terminal of the buffer amplifier A ₆₄ via the resistor R ₁ and is connected to its own output terminal via the resistor R ₃ . The non-inverting input terminal of the amplifier A ₆₆ is connected to the output terminal of the buffer amplifier A ₆₅ via the resistor R ₂ and is connected to the ground potential via the resistor R ₄ . The output terminal of the amplifier A ₆₆ is connected to the input terminal of the pixel AD conversion circuit 62. The input terminal of the buffer amplifier A ₆₄ is connected to the _N holding circuits H _{1 to} H _N via the wiring Hline_s, and is connected to the ground potential via the switch SW ₆₄ . The input terminal of the buffer amplifier A ₆₅ is connected to the _N holding circuits H _{1 to} H _N via the wiring Hline_n, and is connected to the ground potential via the switch SW ₆₅ .

The switches SW ₆₄ and SW ₆₅ of the difference calculation circuit 61 are controlled by the hreset signal to open and close. When the switch SW ₆₄ is closed, the voltage value input to the input terminal of the buffer amplifier A ₆₄ is reset. When the switch SW ₆₅ is closed, the voltage value input to the input terminal of the buffer amplifier A ₆₅ is reset. When the switch _SW 64, _{SW 65} is open, the wiring from one of the holding circuit _{H n} of the N holding circuits _H 1 _{~H N} Hline_s, the voltage value outputted to the Hline_n out_s (n), out_n (n) is input to the input terminals of the buffer amplifiers A ₆₄ and A ₆₅ . Assuming that the amplification factors of the buffer amplifiers A ₆₄ and A ₆₅ are 1, and the resistance values of the _four resistors R _{1 to} R ₄ are equal to each other, the voltage value output from the output terminal of the difference calculation circuit 61 is This represents a difference in voltage values input through the wiring Hline_s and the wiring Hline_n.

  Next, an example of the operation of the solid-state imaging device 1 according to this embodiment will be described. FIG. 4 is a timing chart showing an example of the operation of the solid-state imaging device 1 according to the present embodiment. The solid-state imaging device 1 operates under the control of the control unit 70. In this figure, in order from the top, (a) intensity of light incident on the solid-state imaging device 1, (b) voltage value output from the integration circuit 21 of the total incident light monitoring unit 20, (c) total incident light monitoring An incident light total amount signal output from the unit 20, (d) a charge accumulation operation control signal output from the control unit 70, and (e) a signal output from the output unit 60 are shown. In this figure, the digital value (pixel data) output from the AD conversion circuit 62 for the m-th row of the light receiving unit 10 is represented as Ddata (m).

The charge accumulation operation control signal output from the control unit 70 is set to a high level for a certain period immediately after the power is turned on to the solid-state imaging device 1. Then, after the charge accumulation operation control signal is changed to a low level, the pixel data for one frame is output from the light receiving unit 10 through the voltage holding unit 50, the difference calculation circuit 61, the AD conversion circuit 62, and the switch SW _63. Is output from. The pixel data output at this time is meaningless, but the charge accumulation operation control signal is set to a high level for a certain period after the power is turned on, so that each pixel unit P _{m, n} of the light receiving unit 10 is set. And other circuits are reset, and normal operation thereafter becomes possible.

In addition, by this reset, the Reset (m) signal, the Trans (m) signal, and the Hold (m) signal supplied from the row selection unit 30 to each pixel unit P _{m, n} are all set to the high level, so that the transistors T1, T2 and T5 are in the on state, the junction capacitance portion (charge storage portion) of the photodiode PD is discharged, and the potential of the gate terminal of the transistor T3 is reset. Further, the switch SW ₂₀ included in the integrating circuit 21 of the incident light total amount monitoring unit 20 is opened after being closed for a certain period.

Thereafter, during a period in which no light is incident on the solid-state imaging device 1, dark current is generated in the photodiode PD included in each pixel unit P _{m, n} of the light receiving unit 10. Its dark current, each pixel unit P _m, via the transistors T1, T2 and wiring Lreset contained in _n, is input to the integration circuit 21 of the incident light amount monitoring unit 20, a charge in the capacitor C ₂₀ is accumulated . As a result, the voltage value output from the integrating circuit 21 gradually increases or increases slowly.

Therefore, the pulse interval of the incident light total amount signal output from the incident light total amount monitoring unit 20 is wide during a period in which no light is incident on the solid-state imaging device 1. Then, in the control unit 70, it is determined that the pulse interval of the incident light total amount signal is wider than a predetermined value, it is determined that no light is incident on the solid-state imaging device 1 (or the incident light amount is smaller than a certain level), charge accumulation operation control device signals is being kept at a low level.

Eventually, when light begins to enter the solid-state imaging device 1, the charge generated in the photodiode PD included in each pixel unit _{Pm, n} of the light receiving unit 10 is converted into the transistor T1, included in each pixel unit _{Pm, n} . through T2 and wiring LRESET, it is input to the integration circuit 21 of the incident light amount monitoring unit 20, a charge in the capacitor C ₂₀ is accumulated. As a result, the voltage value output from the integrating circuit 21 gradually increases, or the rate of increase corresponds to the amount of incident light.

Therefore, when light begins to enter the solid-state imaging device 1, the pulse interval of the incident light total amount signal output from the incident light total amount monitoring unit 20 becomes narrower. Then, the control unit 70 determines that the pulse interval of the incident light total amount signal is narrower than a predetermined value, and determines that light is incident on the solid-state imaging device 1 (or the incident light amount is a certain level or more). , the charge accumulation operation control signal to the time t1 Ru turned to a high level.

Then, during a period from time t1 when the charge accumulation operation control signal changes to high level to time t2 when the charge accumulation operation control signal changes to low level, each pixel unit Pm, n of the light receiving unit 10 receives a Reset (m) signal. and Trans (m) signal and Hold (m) signal is at the low level, the transistors T1, T2, T5 is turned off, the charge generated by the photodiode PD rather accumulated in the junction capacitance portion.

Na us, if it can be predicted in advance the amount of incident light, set charge accumulation time based on the predicted value (i.e., the charge accumulation operation control signal period t ₁ ~t ₂ is a high level) to the proper value Also good.

In the period from time t ₂ to time t ₃ when the charge accumulation operation control signal has changed to low level, the Reset (m) signal and Address (m) signal are at low level in each pixel unit P _{m, n of the} light receiving unit 10. Thus, the transistors T1 and T4 are turned off, and the Trans (m) signal and the Hold (m) signal are at a high level, so that the transistors T2 and T5 are turned on. As a result, the electric charge that has been accumulated in the junction capacitor until then moves to and is held by the gate terminal of the transistor T3 via the transistors T2 and T5. However, since the transistor T4 is in the OFF state, a voltage value corresponding to the charge accumulation amount is not output from each pixel unit Pm _{, n} to the wiring Vline (n).

In the subsequent period from time t ₃ to time t _{4 , N} pixel data Ddata (according to the charge accumulation amount in the _N pixel portions P _{1,1 to} P _{1, N} in the first row of the light receiving unit 10. 1) is output from the output unit 60. Specifically, only in the first row of the light receiving unit 10, the Address (1) signal becomes high level, the transistor T4 is turned on, and the charge accumulation amount in each pixel unit P1 _{, n} in the first row. voltage value corresponding to is output to the wiring Vline (n), it is held by the holding circuit H _n of the voltage holding section 50. Then, voltage values sequentially output from the holding circuits H _n are entered AD conversion to the AD conversion circuit 62 via the differential operation circuit 61, successively the N pixels from the AD conversion circuit 62 via the switch SW ₆₃ Data Ddata (1) is output.

In the subsequent period from time t ₄ to time t _{5 , N} pixel data Ddata (according to the charge accumulation amount in the _N pixel portions P _{2, 1 to} P _{2, N} in the second row of the light receiving unit 10. 2) is output from the output unit 60. Specifically, only in the second row of the light receiving unit 10, the Address (2) signal becomes high level, the transistor T4 is turned on, and the charge accumulation amount in each pixel unit P2 _{, n} in the second row. voltage value corresponding to is output to the wiring Vline (n), it is held by the holding circuit H _n of the voltage holding section 50. Then, voltage values sequentially output from the holding circuits H _n are entered AD conversion to the AD conversion circuit 62 via the differential operation circuit 61, successively the N pixels from the AD conversion circuit 62 via the switch SW ₆₃ Data Ddata (2) is output.

Further, during the period from time t ₅ to time t ₆ , N pieces of pixel data Ddata corresponding to the charge accumulation amount in the N pieces of pixel parts P _{3,1 to} P _{3, N} in the third row of the light receiving unit 10. (3) is output from the output unit 60. Specifically, only in the third row of the light receiving unit 10, the Address (3) signal becomes high level, the transistor T4 is turned on, and the charge accumulation amount in each pixel unit P _{3, n} in the third row voltage value corresponding to is output to the wiring Vline (n), it is held by the holding circuit H _n of the voltage holding section 50. Then, voltage values sequentially output from the holding circuits H _n are entered AD conversion to the AD conversion circuit 62 via the differential operation circuit 61, successively the N pixels from the AD conversion circuit 62 via the switch SW ₆₃ Data Ddata (3) is output.

In the same manner thereafter, N light sources corresponding to the charge accumulation amounts in the N pixel portions P _{m, 1 to} P _{m, N} in the m-th row are sequentially formed from the fourth row to the M-th row of the light receiving unit 10. Pixel data Ddata (m) is output from the output unit 60. In this way, the voltage holding section 50 from the light receiving unit 10, the difference calculation circuit 61, AD converter 62 and through the switch SW ₆₃ of the one frame pixel data Ddata (1) ~Ddata (M) is outputted from the output unit 60 Is done. After one frame of pixel data is output again, the time t ₁ returns to the same state as before.

Thus, in the solid-state imaging device 1 according to the present embodiment, the incident light total amount monitoring unit 20 that monitors the amount of incident light to the light receiving unit 10 is provided, and the total incident light amount output from the incident light total amount monitoring unit 20 is provided. Based on the signal, it is determined whether or not light is incident on the light receiving unit 10 (or whether or not the amount of incident light is a certain level or more). When it is determined that light is incident on the light receiving unit 10 (or the incident light amount is a certain level or more), charge accumulation in each of the pixel units P _{1,1 to} P _{M, N} of the light receiving unit 10 is performed. Pixel data Ddata (1) to Ddata (M) corresponding to the amount are output from the output unit 60. That is, the pixel data reading operation from the light receiving unit 10 to the output unit 60, particularly the AD conversion operation in the AD conversion circuit 62, is only required when light is incident on the light receiving unit 10. Therefore, the solid-state imaging device 1 according to the present embodiment can suppress an increase in power consumption even when increasing the number of pixels and increasing the imaging speed.

  The solid-state imaging device 1 according to the present embodiment can exhibit an effect in the following uses, for example. That is, the solid-state imaging device 1 is provided with a scintillator on the light receiving surface of the light receiving unit 10, so that incident X-rays are converted into visible light by the scintillator, and the visible light is received by the photodiode of the light receiving unit 10. Thus, the incident X-rays can be imaged. The solid-state imaging device 1 provided with such a scintillator is used for X-ray imaging in the oral cavity.

  When the solid-state imaging device 1 is used for X-ray imaging in the oral cavity, the incident period of X-rays to be imaged is extremely short, and the solid-state imaging device 1 must capture the X-rays by capturing the X-ray incident timing. Therefore, the solid-state imaging device 1 detects X-ray incidence by the incident light total amount monitoring unit 20. When the solid-state imaging device 1 detects X-ray incidence, the light receiving unit 10, the voltage holding unit 50, the difference calculation circuit 61, and the AD conversion circuit 62 read out pixel data. By doing so, the solid-state imaging device 1 can capture the X-ray by capturing the X-ray incident timing.

  Thus, when the solid-state imaging device 1 is used for X-ray imaging in the oral cavity, the AD conversion circuit 62 can be stopped before X-ray incidence, and the AD conversion circuit 62 can be operated only at the time of X-ray incidence. That's fine. Therefore, the solid-state imaging device 1 can suppress an increase in power consumption even when increasing the number of pixels and increasing the imaging speed.

  When the solid-state imaging device 1 is used for X-ray imaging in the oral cavity, it is preferable to output the pixel data and the incident light total amount signal to the common output signal line Lout, and these data are used as serial data. It is also preferable to output. In these cases, the number of wirings for outputting these data can be reduced, and the reliability can be improved.

Furthermore, the solid-state imaging device 1 accumulates charges generated by the photodiode PD in the same period in each of the M × N pixel units P _{1,1 to} P _{M, N} of the light receiving unit 10 after detecting light incidence. The pixel data can be sequentially output from the output unit 60 for each pixel unit P _{m, n} after the charge storage. Therefore, even when the temporal change in the amount of incident light is fast, the amount of incident light for the same period can be captured in all the pixel units, and high-accuracy imaging can be performed.

  The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the control unit 70 generates the charge accumulation operation control signal, but an external device that generates the charge accumulation operation control signal based on the incident light total amount signal may be provided separately from the solid-state imaging device. In this case, the incident light total amount signal is output from the output unit of the solid-state imaging device to the external device, a charge accumulation operation control signal is generated by the external device based on the output incident light total amount signal, and the generated charge accumulation is generated. An operation control signal is given from an external device to the solid-state imaging device.

  By doing so, the threshold value can be flexibly adjusted in the external device when detecting the light incidence based on the magnitude comparison between the incident light total amount signal and the threshold value. In addition, the period during which the charge accumulation operation control signal directs charge accumulation (that is, the period during which charges generated by the photodiode in each pixel portion are accumulated by the charge accumulation portion) can be flexibly adjusted in an external device, and a wide range of incidence It can easily cope with the light quantity range.

Further, the incident light total amount monitoring unit 20 may be configured as a modification shown in FIG. 5 or FIG. 5A includes an amplifier A ₂₀ , a capacitive element C _20, and a switch SW ₂₀ . Inverting input terminal of the amplifier A ₂₀ is connected to the drain terminal of the pixel portions P _{1, 1} to P _{M, N} each discharge transistor T1 through the wire LRESET. The non-inverting input terminal of the amplifier A ₂₀ is connected to a bias potential Vb1. The bias potential Vb1 is a potential that can initialize the charge of the parasitic capacitance portion formed at the gate terminal of the amplifying transistor T3 of each of the pixel portions _{P1,1 to} PM _{, N.} Between the inverting input terminal and the output terminal of the amplifier A _20, parallel-connected capacitor elements C ₂₀ and switch SW ₂₀ are provided with each other. The switch SW ₂₀ is controlled by the control unit 70A and opens and closes at a constant cycle. Then, the incident light total amount monitoring unit 20A outputs an output signal from the output terminal of the amplifier A ₂₀ as an incident light total amount signal.

In the incident light total amount monitoring unit 20A, the voltage value output from the output terminal of the amplifier A ₂₀ repeatedly increases and decreases in response to opening and closing of the switch SW _{20 with} a certain period. That is, when the switch SW ₂₀ is closed, the voltage value output from the output terminal of the amplifier A ₂₀ is initialized, and the voltage value output from the output terminal of the amplifier A ₂₀ changes while the switch SW ₂₀ is open. To do. The rate of change in the output voltage value at that time represents the rate of charge flow into the inverting input terminal of the amplifier A ₂₀ (current value). Further, the period during which the switch SW ₂₀ is open is constant, and the period during which the switch SW ₂₀ is closed is also constant. Therefore, the peak value of each triangular wave of the incident light total amount signal output from the output terminal of the amplifier A ₂₀ represents the total amount of light incident on the light receiving unit 10.

Incident light amount monitor unit 20B shown in FIG. 6, an amplifier _{A 20} and the resistor _{R 20.} Inverting input terminal of the amplifier A ₂₀ is connected to the drain terminal of the pixel portions P _{1, 1} to P _{M, N} each discharge transistor T1 through the wire LRESET. The non-inverting input terminal of the amplifier A ₂₀ is connected to a bias potential Vb1. The bias potential Vb1 is a potential that can initialize the charge of the parasitic capacitance portion formed at the gate terminal of the amplifying transistor T3 of each of the pixel portions _{P1,1 to} PM _{, N.} Resistor R ₂₀ is provided between the inverting input terminal of the amplifier A ₂₀ and the output terminal. In the incident light amount monitor unit 20B, a voltage value corresponding to a current value inputted to the inverting input terminal of the amplifier A ₂₀ is output as an incident light amount signal from the output terminal of the amplifier A _20. The incident light total amount signal output from the amplifier A ₂₀ represents the total amount of light incident on the light receiving unit 10.

It is a block diagram of the solid-state imaging device 1 which concerns on this embodiment. Incident light amount monitoring unit 20 included in the solid-state imaging device 1 according to the present embodiment, it is a diagram illustrating a pixel portion P _{m, n} and the holding circuit H _n respective circuit configurations. It is a figure which shows the circuit structure of the difference calculating circuit 61 contained in the solid-state imaging device 1 which concerns on this embodiment. 6 is a timing chart illustrating an example of the operation of the solid-state imaging device 1 according to the present embodiment. It is a figure which shows the circuit structure of the modification of the incident light total amount monitoring part 20 contained in the solid-state imaging device 1 which concerns on this embodiment. It is a figure which shows the circuit structure of the modification of the incident light total amount monitoring part 20 contained in the solid-state imaging device 1 which concerns on this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 10 ... Light-receiving part, 20 ... Total incident light amount monitoring part, 21 ... Integration circuit, 22 ... Comparison circuit, 30 ... Row selection part, 40 ... Column selection part, 50 ... Voltage holding part, 60 ... Output , 61... Difference calculation circuit, 62... AD conversion circuit, 70... Control unit, P _{1,1 to} P _{M, N.}

Claims (5)

Generated by a photodiode that generates an amount of charge corresponding to the amount of incident light, an amplifying transistor that outputs a voltage value corresponding to the amount of charge stored in the parasitic capacitance formed at the gate terminal, and the photodiode A transfer transistor that transfers the generated charge to the gate terminal of the amplification transistor, a discharge transistor that initializes the charge of the parasitic capacitance section, and a selection that selectively outputs a voltage value output from the amplification transistor A plurality of pixel portions each having a transistor for use, and a light receiving portion that accumulates charges generated in the photodiodes in each of the plurality of pixel portions in the parasitic capacitance portion during a period indicated by a charge accumulation operation control signal,
An output unit that outputs a digital value corresponding to a voltage value output from the selection transistor of each of the plurality of pixel units after the charge accumulation operation in each of the plurality of pixel units;
An amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the amplifier is connected to the discharge transistor of each of the plurality of pixel units, and each of the plurality of pixel units The second input terminal of the amplifier is connected to a bias potential for initializing the charge of the parasitic capacitance unit, and the photodiodes of each of the plurality of pixel units are based on an output signal from the output terminal of the amplifier. An incident light total amount monitoring unit for outputting an incident light total amount signal indicating the total amount of light incident on
A solid-state imaging device comprising:   The incident light total amount signal output from the incident light total amount monitoring unit is input, and when the total incident light amount represented by the incident light total amount signal is larger than a threshold value, the charge accumulation operation is performed for each of the plurality of pixel units of the light receiving unit. The solid-state imaging device according to claim 1, further comprising a control unit that generates the charge accumulation operation control signal instructing. The incident light total amount monitoring unit,
A comparison result obtained by comparing the capacitance value and the switch provided between the first input terminal and the output terminal of the amplifier with a voltage value output from the output terminal of the amplifier and a reference voltage value. And a comparison circuit that outputs a signal representing the total incident light amount signal,
The switch is controlled to open and close according to the level of the incident light total amount signal.
The solid-state imaging device according to claim 1. The incident light total amount monitoring unit,
A capacitor and a switch provided between the first input terminal and the output terminal of the amplifier;
The switch is controlled to open and close at regular intervals,
Output an output signal from the output terminal of the amplifier as the total incident light signal,
The solid-state imaging device according to claim 1. The incident light total amount monitoring unit,
A resistor provided between the first input terminal and the output terminal of the amplifier;
Output an output signal from the output terminal of the amplifier as the total incident light signal,
The solid-state imaging device according to claim 1.

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