JP4830108B2 - Program processing apparatus, program processing method, parallel processing program compiler, and recording medium storing parallel processing program compiler - Google Patents

Description

  The present invention relates to a program development technique for realizing a parallel processing system, and more particularly to a compiler technique for realizing a parallel processing system.

  Conventionally, there are mainly two techniques for program development techniques for realizing a parallel processing system. One is a technology that provides a development environment based on an automatic parallel compiler for sequential programs (automatic parallel compiler technology), and the other is a development environment that uses a parallel processing language that is an extension of the sequential processing language. Technology (parallel processing language technology).

  As the former automatic parallel compiler technology, there is an automatic parallel compiler technology for multiprocessors (see, for example, Non-Patent Documents 1, 2, or 3). This is a technique for automatically generating a parallel processing program from a sequential program written in a high-level programming language (mainly Fortran or C language). Specifically, the loop (repetition processing part) is divided, and each divided loop is executed in parallel by different processors, or the processing parts that can be executed in parallel are processed by different processors. Block parallel execution that executes in parallel is the main parallelization technique.

  As an automatic parallel compiler technology, there is an instruction level parallel compiler technology (for example, see Non-Patent Document 4 or 5). It automatically executes execution code for a VLIW (Very Long Instruction Word) type processor (processor having a plurality of arithmetic units) from a sequential program written in a high-level programming language (mainly C language) or a similar language. It is a technology to generate. This execution code is called a horizontal instruction code, and execution instructions for all the arithmetic units are embedded in one instruction. VLIW is one of techniques for increasing the speed of a microprocessor that combines a plurality of instructions that are not dependent on each other and executes them simultaneously.

  As the latter parallel processing language technology, there is a parallel programming language (see, for example, Non-Patent Document 6, 7 or 8). This is a language for directly describing a multiprocessor parallel processing program. Based on a high-level programming language, it has been expanded to explicitly describe parallel execution loops and parallel execution blocks, and many parallel programming languages have been proposed. Non-Patent Document 6 describes VPP Fortran, Non-Patent Document 7 describes HPF (High Performance Fortran), and Non-Patent Document 8 describes Concurrent C.

  In addition, as a parallel processing language technology, there is a message communication system programming technology (see, for example, Non-Patent Document 9 or 10). This is a technology that provides a parallel programming environment (MPI: Message Passing Interface, PVM: Parallel Virtual Machine) in which high-level programming languages (mainly Fortran or C language) are libraryed with inter-processor message communication functions. In this message communication system programming technique, a program is executed in parallel on a plurality of PCs (Personal Computers) or workstations connected via a network. Further, this message communication system programming technique is also used for developing a parallel execution program for a distributed memory type multiprocessor system or a shared memory type multiprocessor system. Non-Patent Document 9 describes MPI (Message Passing Interface), and Non-Patent Document 10 describes PVM (Parallel Virtual Machine).

Okamoto, Goda, Miyazawa, Honda, Kasahara, "Hierarchical Macro Data Flow Processing in OSCAR Multigrain Compiler", Transactions of Information Processing Society of Japan, Vol. 35, No. 4, pp.513-521 (1994) Eigenmann, Hoeflinger, Padua, “On the Automatic Parallelization of the Perfect Benchmarks”, IEEE Trans. On Parallel and Distributed Systems, Vol. 9, No. 1, pp. 5-21 (1998) Hall, Anderson, Amarasinghe, Murphy, Liao, Bugnion, Lam, “Maximizing Multiprocessor Performance with the SUIF Compiler”, IEEE Computer, Vol. 29, No. 12, pp.84-89 (1996) Fisher, “Trace scheduling: A Technique for global Microcode Compaction”, IEEE Trans. Computers, Vol. 30, No. 7, pp.478-490, 1981 Wakabayashi, Tanaka, “Global Scheduling Independent of Control Dependencies Based on Condition Vectors”, Proceedings of 29th ACM / IEEE Conference on Design Automation, pp.112-115, 1992 Hidetoshi Iwashita, "VPP Fortran as seen from HPF", Information Processing, Vol.38, No.2, pp.114-121, February 1997 “HPF Promotion Council (HPFPC)”, [online], [searched on August 10, 2005], Internet <URL: http://www.hpfpc.org/> Gehani, et al, “Concurrent C”, Software, Practice and Experience, Vol.16, No. 9, pp.821-844, 1986 “Message Passing Interface Forum”, [online], [searched August 10, 2005], Internet <URL: http://www.mpi-forum.org/index.html> “PVM”, [online], [Search August 10, 2005], Internet <URL: http://www.csm.ornl.gov/pvm/pvm_home.html>

  However, according to the automatic parallel compiler technology, it is possible to automatically generate a parallel processing program from a sequential program. However, the method for dividing the program and the method for assigning the divided program to the processor are flexible. Since it cannot be changed, the programmer cannot be directly involved in program partitioning, processor allocation, or the like. In addition, application to CMP (Chip MultiProcessor) for server applications is progressing, and scientific calculation with a large calculation load is the main application field, but the application field is limited, for example, system LSI (Large Scale Integration) There is no technology that can be applied to such fields. Here, CMP refers to a technology in which a plurality of processors are integrated on a single chip and coupled by a shared bus.

  The instruction level parallel compiler technology is also applied to circuit design of a dedicated IC (Integrated Circuit), and although it is a practical technology, the parallelism that can be realized is relatively low. Therefore, it cannot be applied to a parallel processing system having a relatively high degree of parallelism.

  Furthermore, the parallel programming language is targeted for a specific field such as a science and technology field, and is used only in a limited field. Therefore, it cannot be applied to a wider range of fields.

  In addition, the message communication system programming technique is also used in the upstream design of the system LSI, but since it is necessary to develop a program for each processor and explicitly describe the communication instruction, The program development efficiency is poor. That is, it is difficult to debug the program, and tuning such as changing the allocation of processing to the processor is difficult.

  Therefore, the present invention has been made in view of the above problems, and an execution for a multiprocessor system to execute high-performance parallel processing by simply adding a simple description to a sequential program by a programmer or the like. The problem is to make it possible to generate code.

The present invention was devised to solve the problem, and the program processing device according to claim 1 is added with a thread description that is a description of an effective range of threads that are units of a program executed by the processor. The parallel processing program is input, the program is divided into each thread, and an execution code is generated for the multiprocessor system. The program processing device includes a storage unit, a processing unit, And the processing unit specifies a start point and an end point of each thread in the parallel processing program input to the storage unit by a reserved keyword or symbol, and the specified start point and end point each operation instruction included in the specified thread area, respectively the operation instruction included in any thread A syntax analysis unit for generating an intermediate language by adding a thread attribute is information for determining whether to enter the intermediate language, extracts the command block input and output data from the intermediate language, the instruction block input Information about single data dependencies, which are dependencies of data generated or referenced by a single operation instruction based on data, and information about data structure dependencies, which are data dependencies between instructions that act on data structures A data dependency extraction unit that generates data dependency branch information including the data, and the intermediate language and the data dependency branch information are input, and based on the data dependency branch information, data connecting different threads from the intermediate language By extracting the dependency branch, the thread output data generation instruction and the thread input reference instruction corresponding to the data dependency branch, the inter-thread data dependency instruction pair is extracted. An inter-thread data dependency extraction unit for generating information, the intermediate word and the inter-thread data dependent instruction pair information are input, and the inter-thread data dependent instruction pair information is input to the intermediate word based on the inter-thread data dependent instruction pair information. A communication command insertion unit that generates a program including the communication command, and a program including the communication command, and inputs the program based on the thread attribute of each command. It is configured to include a program division / code generation unit that divides each thread and converts it into an execution code.

  According to such a configuration, the syntax analysis unit can generate an intermediate language in which a thread attribute is added to each operation instruction included in the thread area from the parallel processing program to which the thread description is added. The data dependency extraction unit extracts instruction block input / output data from the intermediate language generated by the syntax analysis unit, and relates to single data dependency that is dependency of data generated or referenced by a single operation instruction. It is possible to generate data dependency branch information including information and information related to data structure dependency which is data dependency between instructions operating on the data structure. Further, the inter-thread data dependency extraction unit, based on the data dependency branch information extracted by the data dependency extraction unit from the intermediate language generated by the syntax analysis unit, a data dependency branch that connects different threads, It is possible to extract the thread output data generation instruction and the thread input reference instruction corresponding to the data dependency branch and generate the inter-thread data dependency instruction pair information. In addition, the communication command insertion unit generates a program including a communication command by inserting a data communication command depending on the thread into the intermediate language generated by the syntax analysis unit based on the inter-thread data dependent command pair information. Is possible. Further, the program division / code generation unit can divide a program including a communication instruction into each thread based on the thread attribute added to each instruction by the syntax analysis unit, and convert it into an execution code. Therefore, the program processing apparatus can input a parallel processing program to which a thread description is added, and generate an execution code for the multiprocessor system to execute high-performance parallel processing.

Furthermore, the program processing method according to claim 2 inputs a parallel processing program to which a thread description, which is a description about an effective range of a thread that is a unit of a program executed by a processor, is input, and the program is transmitted to each thread. A program processing method by a program processing device that divides and generates an execution code for a multiprocessor system, wherein the program processing device includes a storage unit and a processing unit, and the processing unit includes the storage unit The start point and end point of each thread in the parallel processing program input to is specified by a reserved keyword or symbol, and each calculation instruction included in the thread area specified by the specified start point and end point in, for determining whether each said operation instruction is included in which the thread Generates an intermediate language by adding a thread attributes is broadcast, enter the intermediate language, extracts the command block input and output data from the intermediate language, based on the instruction block output data, by a single operation instruction Generate data dependency branch information including information on single data dependency, which is the dependency of data to be generated or referenced, and data structure dependency, which is data dependency between instructions operating on the data structure; The intermediate language and the data dependency edge information are input, and based on the data dependency edge information, a data dependency edge that connects different threads from the intermediate language, and a thread output data generation instruction corresponding to the data dependency edge And thread input reference instructions are extracted to generate inter-thread data dependent instruction pair information, and the intermediate language and inter-thread data dependent instruction pair are generated. Information is input, and based on the inter-thread data dependence instruction pair information, a communication instruction of data dependent on the thread is inserted into the intermediate language to generate a program including the communication instruction, and the communication A method including inputting a program including an instruction, dividing the program into the threads based on the thread attribute of each instruction, and converting the program into an execution code.

  According to such a method, the processing unit of the program processing device can generate an intermediate language in which a thread attribute is added to each operation instruction included in the thread area from a parallel processing program to which a thread description is added. . In addition, the processing unit of the program processing device extracts instruction block input / output data from the intermediate language, and stores information on single data dependency, which is dependency of data generated or referenced by a single operation instruction, and a data structure. It is possible to generate data dependency edge information including information on data structure dependency that is data dependency between acting instructions. Further, the processing unit of the program processing device outputs, from the intermediate language, a data dependency branch for connecting different threads, a thread output data generation instruction and a thread input reference instruction corresponding to the data dependency branch, based on the data dependency branch information. It is possible to extract and generate inter-thread data dependent instruction pair information. In addition, the processing unit of the program processing device can generate a program including a communication instruction by inserting a communication instruction of data depending on the thread in the intermediate language based on the inter-thread data dependent instruction pair information. is there. Furthermore, the processing unit of the program processing device can divide a program including a communication command into each thread based on a thread attribute added to each command and convert the program into an execution code. Therefore, the program processing apparatus executes such a method to input a parallel processing program to which a thread description is added and generate an execution code for the multiprocessor system to execute high-performance parallel processing. It is possible.

Furthermore, the compiler for parallel processing program according to claim 3, was a parallel processing program compiler for executing a program processing method according to claim 2 to the computer.

According to such a configuration, the parallel processing program compiler can cause the computer to execute the above-described program processing method. Therefore, by incorporating this parallel processing program compiler into a computer and causing the computer to execute the program processing method described above, the multiprocessor system performs high-performance parallel processing by inputting a parallel processing program with an added thread description. It is possible to generate an execution code for execution.

A recording medium according to claim 4 is a recording medium storing the compiler for parallel processing programs according to claim 3 .

According to such a configuration, the parallel processing program compiler stored in the recording medium is incorporated in the computer, and the computer executes the program processing method described above, thereby inputting the parallel processing program to which the thread description is added. The multiprocessor system can generate execution code for executing high-performance parallel processing.

  According to the program processing device of the first aspect, it is possible to input a parallel processing program to which a thread description is added and generate an execution code for the multiprocessor system to execute high-performance parallel processing. is there. Therefore, it becomes possible for the multiprocessor system to generate an execution code for executing high-performance parallel processing only by adding a simple description to the sequential program by a programmer or the like.

Furthermore, according to the program processing method of the second aspect , the program processing device executes the program processing method, thereby inputting the parallel processing program to which the thread description is added, so that the multiprocessor system has a high performance. It is possible to generate an execution code for executing parallel processing. Therefore, it becomes possible for the multiprocessor system to generate an execution code for executing high-performance parallel processing only by adding a simple description to the sequential program by a programmer or the like.

According to the compiler for a parallel processing program according to claim 3 , the thread description is added to the computer by incorporating the compiler for the parallel processing program into the computer and causing the computer to execute the program processing method described above. It is possible to input a parallel processing program and generate an execution code for the multiprocessor system to execute high-performance parallel processing. Therefore, it becomes possible for the multiprocessor system to generate an execution code for executing high-performance parallel processing only by adding a simple description to the sequential program by a programmer or the like.

Furthermore, according to the recording medium of claim 4 , the thread description is added by incorporating the compiler for the parallel processing program stored in the recording medium into the computer and causing the computer to execute the program processing method described above. It is possible to input a parallel processing program and generate an execution code for the multiprocessor system to execute high-performance parallel processing. Therefore, it becomes possible for the multiprocessor system to generate an execution code for executing high-performance parallel processing only by adding a simple description to the sequential program by a programmer or the like.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings (FIGS. 1 to 16).
FIG. 1 is a functional block diagram illustrating an example of functions of the program processing apparatus. As shown in FIG. 1, the program processing apparatus 1A inputs a parallel processing program 50A and outputs a divided program 55A including a communication command. Here, the parallel processing program 50A used in the present embodiment will be described with reference to FIGS.

  The program shown in FIG. 2 is a program described by a programmer or the like, and is an example of a program before adding a thread description. This program is written in C language.

The program shown in FIG. 3 is a program written by a programmer or the like, and is an example of a program (hereinafter also referred to as a parallel processing program) after adding a thread description to the program shown in FIG. Here, the “thread” is a unit of a program executed by one processor, and it is assumed that these threads are processed in parallel by different processors.
This program is described in the extended C language in which a new keyword “THREAD” is added to the C language. A thread name is designated by “(thread name)” following THREAD, and a parenthesis symbol following this An effective range of threads is indicated by a code area (thread area) surrounded by {. A program to which a thread description is added (parallel processing program) refers to a program in which an effective range of threads is described in this way. It should be noted that the processing of a code area not included in any thread is called a “base thread” and is handled in the same way as other threads. In order to generate an execution code from the source code written in the extended C language using an existing C compiler, for example, a preprocessor “#define THREAD (n)” for invalidating the thread declaration is previously set at the top of the program. (Or in the program). By this preprocessor, for example, “THREAD (p1)” is converted into an empty character string, and the parenthesis symbols {...} Following this are interpreted as a scope declaration in a normal C language and processed normally by an existing C compiler. .

Returning to FIG. 1, the description of the program processing apparatus 1A will be continued.
As shown in FIG. 1, the program processing apparatus 1A includes a syntax analysis unit 31, a data dependency extraction unit 32A, an inter-thread data dependency extraction unit 33, a communication instruction insertion unit 35A, and a program division / code generation unit. 39. Hereinafter, each element constituting the program processing apparatus 1A will be described.

(Description of syntax analysis unit 31)
The syntax analysis unit 31 inputs the parallel processing program 50A and analyzes the syntax of the program. Further, an intermediate language is generated from the parallel processing program 50A. The syntax analysis unit 31 recognizes the THREAD keyword added to the reserved word of the extended C language in addition to the well-known syntax analysis function of a normal compiler, and extracts the thread name with “(thread name)” that follows. , It is determined that the code area (thread area) enclosed by the following scope ({...}) is this thread, and a thread attribute (thread attribute) is added to each operation instruction converted to an intermediate language. It has a function. The thread attribute is information for determining in which thread each operation instruction is included. A unique number is assigned to each thread in advance, and this number is assigned to all operation instructions included in the thread. Thread attribute information can be added.

Here, when the thread area has a nested structure, that is, when another thread area exists in a certain thread area, each operation instruction has a thread attribute of the innermost thread area including the thread instruction. To do. For example,
THREAD (p0) {
a = 1;
THREAD (p1) {
b = 2;
}
}
If there is a nested structure (a structure in which the thread p1 is included in the area of the thread p0), the operation b = 2; is included in the thread p0 and the thread p1. At this time, this operation b = 2; has the thread attribute of the innermost thread p1. The thread attribute of the operation a = 1; is the thread p0.
Furthermore, when a function call instruction is included in the thread area, the base thread of the function is assumed to be the same as the thread to which the function call instruction belongs. For example, the instructions on the 21st line (RandomSignal ()) and 25th line (printf ()) of the parallel processing program 50A shown in FIG. 3 are function call instructions in the thread p4 and the thread p5, respectively. Since the processing of the function is executed by the thread that calls them, the base threads of RandomSignal () and printf () are the same as the thread p4 and the thread p5, respectively.
For convenience of explanation, the following description will be given using the parallel processing program 50A as an intermediate language.

(Description of Data Dependency Extractor 32A)
The data dependency extraction unit 32A receives the intermediate language generated by the syntax analysis unit 31 and extracts data dependency. The data dependency extraction unit 32A includes an instruction reference / generation data extraction unit 321, an in-function indirect reference / generation data extraction unit 323, an instruction block extraction unit 324, an instruction block input / output data extraction unit 325A, a data dependency branch A generation unit 326 and an output data generation instruction / input data reference instruction extraction unit 327 are included.

(Description of instruction reference / generated data extraction unit 321)
The instruction reference / generation data extraction unit 321 inputs the intermediate language generated by the syntax analysis unit 31, and generates a reference data list and a generation data list for each instruction in the intermediate language.
The reference data list of each instruction generated by the instruction reference / generated data extraction unit 321 includes all data directly referred to by the instruction. In the case of a unary operation instruction, the reference data list has one reference data. In the case of a function call instruction, all the function call argument data are regarded as reference data.
In addition, the generated data list of each instruction generated by the instruction reference / generated data extraction unit 321 includes data directly generated by the instruction, and there is no data directly generated by a function call instruction of a function having no return value. Instructions other than have one directly generated data.
The reference data list and the generated data list generated by the instruction reference / generated data extraction unit 321 are delivered to the in-function indirect reference / generated data extraction unit 323. Further, the reference data list and the generated data list generated by the instruction reference / generated data extraction unit 321 are appropriately used in the process of extracting the dependency of each instruction.

(Description of function indirect reference / generated data extraction unit 323)
The in-function indirect reference / generated data extraction unit 323 inputs the reference data list and the generated data list generated by the instruction reference / generated data extraction unit 321. If there is a function call instruction, Pointer reference data (hereinafter referred to as indirect dependency data) based on global variables or pointer type function arguments that are referred to or generated is extracted.
In the data dependency analysis of the function call instruction, the data dependency as a normal operation instruction (hereinafter referred to as direct data dependency) must be taken into account. Dependencies that propagate to the function caller (hereinafter referred to as indirect data dependencies) may need to be considered. Examples of direct data dependency include a function call argument (direct reference data) and a function return value (direct generation data). The direct reference data and the direct generation data are used as the instruction reference / generation data extraction unit 321. Exists in the reference data list and generated data list received from.

The indirect reference / generated data extracting unit 323 in the function refers to the reference data list and the generated data list received from the instruction reference / generated data extracting unit 321 and refers to indirect dependent data (other than the function argument) referred to inside the function. (Indirect reference data in function) is extracted and added to the reference data list of each function call instruction. Also, the in-function indirect reference / generated data extraction unit 323 refers to the reference data list and the generated data list received from the instruction reference / generated data extraction unit 321 and is generated (rewritten) inside the function (function return). Function-dependent data (indirectly generated data within a function) other than the value is extracted and added to the generated data list of each function call instruction. The processing of the indirect in-function reference / generated data extraction unit 323 is not particularly different from the processing of extracting known indirect dependency data included in a normal compiler, and thus description thereof is omitted.
The function call instruction reference data list and the generated data list generated by the in-function indirect reference / generated data extraction unit 323 are appropriately used in the process of extracting the dependency of each instruction. As a result, the global data dependency in the parallel processing program 50A can be extracted.

(Description of instruction block extraction unit 324)
The instruction block extraction unit 324 receives the intermediate language generated by the syntax analysis unit 31 and extracts an instruction block from the intermediate language. Here, the instruction block is a block that is generated as a result of dividing the program before and after the branch point, the junction point, and the function call instruction and the thread boundary as a boundary line. Hereinafter, an example of the function of the instruction block extraction unit 324 will be described with reference to FIGS. 3 and 4.

  The instruction block extraction unit 324 finds a repetition statement in the seventh line of the parallel processing program 50A, determines that the program is merged before the conditional expression “t <signalLength”, and extracts a program merge point (merging block) C1. . The instruction block extraction unit 324 determines that the program branches after the conditional expression “t <signalLength” in the seventh line of the parallel processing program 50A, and extracts a program branch point (branch block) B1 (FIG. 4). reference). Further, the instruction block extraction unit 324 extracts the function call instruction D1 “RandomSignal” on the 21st line and the function call instruction D2 “printf” on the 25th line of the parallel processing program 50A (see FIG. 4). Further, the instruction block extraction unit 324 extracts the thread boundaries E1 to E6 immediately before and after the processing by the threads p1 to p5 from the parallel processing program 50A (see FIG. 4).

  FIG. 4 is a program graph showing a result of the instruction block extraction unit 324 extracting an instruction block from the intermediate language generated by the syntax analysis unit 31. Note that a symbol (for example, [p1]) shown on the left of each operation in FIG. 4 indicates a thread name for executing the operation, and [*] indicates the base thread described above. Each operation processing in the intermediate language generated by the parsing unit 31 is divided into binary operation or unary operation (the intermediate variable used when the operation is divided is a temporary variable named “$ xx”. Variable is assigned).

  By the function of the instruction block extraction unit 324 described above, the instruction block extraction unit 324 changes the program branch point B1, the program junction point C1, the function call instruction D1, the function call instruction D2, and the thread boundaries E1 to E6 from the parallel processing program 50A. By extracting, as shown in FIG. 4, the parallel processing program 50A can be divided into instruction blocks A1 to A7. In this way, the instruction block extraction unit 324 can generate information (instruction block information) regarding an instruction block in which an instruction block and a thread are associated with each instruction in the parallel processing program 50A.

  Further, information (instruction block information) regarding the instruction block generated by the instruction block extraction unit 324 is delivered to the instruction block input / output data extraction unit 325A.

(Description of instruction block input / output data extraction unit 325A)
The instruction block input / output data extraction unit 325A receives the intermediate language generated by the syntax analysis unit 31 and the instruction block information extracted by the instruction block extraction unit 324, and uses the instruction block information to generate the intermediate language. Instruction block input data and instruction block output data are extracted. The instruction block input data is data generated in another instruction block among data referred to by each instruction in the instruction block. The instruction block output data is data that is referred to in another block among data generated by each instruction in the instruction block. Hereinafter, an example of the function of the instruction block input / output data extraction unit 325A will be described with reference to FIGS.

  The instruction block input / output data extraction unit 325A finds, for example, a variable sigIn2 on the ninth line of the parallel processing program 50A as data referred to by each instruction in the instruction block. The instruction block input / output data extraction unit 325A refers to the instruction block information extracted by the instruction block extraction unit 324, and determines that the variable sigIn2 is referred to by an instruction in the instruction block A3. The instruction block input / output data extraction unit 325A refers to the instruction block information extracted by the instruction block extraction unit 324, and the reference data list and the generation data list generated by the instruction reference / generation data extraction unit 321. It is determined that this variable sigIn2 is generated in an instruction block (an instruction in the instruction block A1 or an instruction block A4) other than the instruction block A3 to be referred to. As a result, the instruction block input / output data extraction unit 325A can extract the variable sigIn2 as the instruction block input data.

  Further, the instruction block input / output data extraction unit 325A finds, for example, a variable sigOut on the 10th line of the parallel processing program 50A as data generated by each instruction in the instruction block. The instruction block input / output data extraction unit 325A refers to the instruction block information extracted by the instruction block extraction unit 324 and determines that the variable sigOut is generated by an instruction in the instruction block A3. The instruction block input / output data extraction unit 325A refers to the instruction block information extracted by the instruction block extraction unit 324, and the reference data list and the generation data list generated by the instruction reference / generation data extraction unit 321. The variable sigOut is determined to be referenced in an instruction block (instruction block A4) other than the instruction block A3 to be generated. As a result, the instruction block input / output data extraction unit 325A can extract the variable sigOut as the instruction block output data.

  FIG. 5 is a program graph showing the result of the instruction block input / output data extraction unit 325A extracting the instruction block input data and the instruction block output data from the intermediate language generated by the syntax analysis unit 31. As an example, FIG. 5 shows instruction block input data F1, instruction block output data G1, and the like.

  By the function of the instruction block input / output data extraction unit 325A described above, the instruction block input / output data extraction unit 325A uses the instruction block information to receive the instruction block input / output data from the parallel processing program 50A as shown in FIG. Can be extracted. As described above, the instruction block input / output data extraction unit 325A includes information (instruction block) regarding the instruction block input / output data in which the instruction block extracted by the instruction block extraction unit 324 is associated with the input / output data in the instruction block. Input / output data information) can be generated.

  The instruction block information generated by the instruction block extraction unit 324 and the information (instruction block input / output data information) related to the instruction block input / output data generated by the instruction block input / output data extraction unit 325A are generated as data dependency branches. Delivered to part 326.

(Description of Data Dependent Edge Generation Unit 326)
The data dependency branch generation unit 326 includes the intermediate language generated by the syntax analysis unit 31, the instruction block information generated by the instruction block extraction unit 324, and the instruction block input / output generated by the instruction block input / output data extraction unit 325A. Data information is input, and a data dependency branch is generated using the instruction block information and instruction block input / output data information.
A data dependency branch refers to the input / output data of an instruction block when a dependency exists between input data and output data (a relationship in which another block uses the output data of one block as input data). (Vertex) "and connected from the output data node to the input data node. However, when this data dependency relationship separates a branch point or a merge point, a data node is added to the corresponding branch block or merge block so that the data dependency branch passes through this data node. The graph structure of this data dependence branch is a dependency paper proposed by Johnson, Pingali, "Dependence-Based Program Analysis", ACM Conference on Programming Language Design and Implementation, pp. 78-89 (1993). Based on Flow Graph. This Dependence Flow Graph is characterized in that, in the data dependency relationship between the branch point and the merge point described above, a data node is added to the corresponding branch block or merge block, and the data dependency branch passes through this data node. It is a graph structure for expressing data dependency to be performed. Hereinafter, an example of the function of the data dependence edge generation unit 326 will be described with reference to FIGS. 3, 5, and 6.

  FIG. 6 is a program graph showing a result of the data dependency branch generation unit 326 generating a data dependency branch from the intermediate language generated by the syntax analysis unit 31.

The data dependency branch generation unit 326 refers to the instruction block input / output data information generated by the instruction block input / output data extraction unit 325A and finds, for example, sigIn0 as instruction block input data of the instruction block A5. Here, an instruction block that generates sigIn0 (that is, an instruction block having sigIn0 as output data) is searched while tracing back on the program graph from the instruction block A5. During this backward search, the branch block B1 is passed through the T branch branch (the conditional statement of the instruction block A2 is satisfied, that is, the direction in which the program proceeds when “True”), so that branch block B1 Is added with a data node of sigIn0 (T), and the data node and the input data node sigIn0 of the instruction block A5 are connected by the data dependence branch K1. If the search is further continued, since it passes through the merge block C1, a data node of sigIn0 is added to this merge block C1, and a data dependence branch K2 is provided between this data node and the data node sigIn0 (T) of the branch block B1. Connecting. The search from the merge block C1 continues in the direction of the two merge sources to the instruction block A1 and the instruction block A7. Since the instruction block A1 has sigIn0 as output data, this output data node and the data node sigIn0 of the merge block C1 are connected by the data dependence branch K3, and the search in this direction is completed. On the other hand, for the search to the instruction block A7, since it reaches the instruction block A6 having sigIn0 as output data, this output data node and the data node sigIn0 of the merge block C1 are similarly connected by the data dependence branch K4. The entire search is finished.
The output data node sigIn0 added to the branch block B1 is described as sigIn0 (T). This is true when the conditional statement of the instruction block A2 is satisfied (when true). This means that the output data node sigIn0 added to the URL is routed.

  As described above, the data dependence edge generation unit 326 can create a data dependence edge. Further, the instruction block information generated by the instruction block extraction unit 324 is used to grasp the correspondence between the instruction block and the thread, and the instruction block input / output data information generated by the instruction block input / output data extraction unit 325A is used to execute the instruction. By grasping the correspondence between blocks and input / output data nodes, it is possible to generate information (data dependency edge information) related to data dependency edges connecting the nodes. Data dependency edge information will be described with reference to FIG.

In FIG. 7, the data dependency branch generation unit 326 is extracted by the intermediate language generated by the syntax analysis unit 31, the instruction block information extracted by the instruction block extraction unit 324, and the instruction block input / output data extraction unit 325A. It is a table | surface which shows the information (data dependence edge information) regarding a data dependence edge produced | generated using the instruction block input / output data information. The data dependency edge information 100A includes information on the output data node (block name, thread name, and variable name of the output data node), information on the input data node (block name, thread name, and variable name of the input data node), the preceding branch, and Includes trailing branches.
Here, the preceding branch means another data dependency branch whose end point is the start node (instruction block output node) of the data dependency branch. The succeeding branch means another data dependency branch starting from the end point node (instruction block input node) of the data dependency branch. However, the data node added to the branch block or the merge block is regarded as an output node as well as an input node of these blocks. For example, the data dependency branch generation unit 326 finds the data dependency branch “4” as another data dependency branch whose end point is the start node (instruction block output node) of the data dependency branch “5”, and the data dependency branch “5”. "4" is set as the leading branch of "." Similarly, the data dependency branch generation unit 326 finds the data dependency branch “5” as another data dependency branch starting from the end point node (instruction block input node) of the data dependency branch “4”, for example. The data dependency branch “5” is set as the preceding branch of the dependency branch “4”.

  With the function of the data dependency edge generation unit 326 described above, the data dependency edge generation unit 326 uses the instruction block input / output data information extracted by the instruction block input / output data extraction unit 325A, as shown in FIG. The data dependence edge information 100A can be generated from the parallel processing program 50A.

  The data dependency edge information 100A generated by the data dependency edge generation unit 326 is delivered to the output data generation instruction / input data reference instruction extraction unit 327.

(Description of Output Data Generation Instruction / Input Data Reference Instruction Extraction Unit 327)
The output data generation instruction / input data reference instruction extraction unit 327 receives the intermediate language generated by the syntax analysis unit 31 and the data dependency branch information 100A (see FIG. 7) generated by the data dependency branch generation unit 326. The output data generation instruction and the input data reference instruction are extracted. Hereinafter, an example of the function of the output data generation instruction / input data reference instruction extraction unit 327 will be described with reference to FIGS.

The output data generation instruction / input data reference instruction extraction unit 327 refers to the data dependency edge information 100A generated by the data dependency edge generation unit 326, and first, this data in the instruction block on the start point side of each data dependency edge Search for instructions that generate. If the data dependency branch does not have a preceding branch, it means that an instruction (data generation instruction) for generating data related to the data dependency branch exists in the instruction block on the start point side. The corresponding data generation instruction is extracted. If there are a plurality of instructions that generate the same data in the same instruction block, the last instruction to be executed is set as the data generation instruction. Conversely, when the data dependency branch has a preceding branch, it means that an instruction (data generation instruction) for generating data related to the data dependency branch does not exist in the instruction block on the start point side.
Next, an instruction that refers to this data is searched for in the instruction block on the end point side of each data dependency branch. If the data dependency branch does not have a succeeding branch, it means that an instruction (data reference instruction) that refers to data related to the data dependency branch exists in the instruction block on the end point side. The corresponding data reference instruction is extracted. When there are a plurality of instructions that refer to the same data in the same instruction block, the first instruction to be executed among them is set as a data reference instruction. Conversely, if the data dependency branch has a subsequent branch, it means that an instruction (data reference instruction) for referring to data related to the data dependency branch does not exist in the instruction block on the end point side.

  In FIG. 8, the output data generation instruction / input data reference instruction extraction unit 327 uses the intermediate language generated by the syntax analysis unit 31 and the data dependency branch information 100A generated by the data dependency edge generation unit 326. 10 is a table showing information (output data generation instruction / input data reference instruction information) related to an output data generation instruction and an input data reference instruction generated by a data generation instruction search and the data reference instruction search. The output data generation instruction / input data reference instruction information 110A includes, for each data dependency branch, information (block name, thread name and instruction) regarding the data generation instruction in the instruction block on the start point side, data generation instruction symbol, and end point side thereof Information (block name, thread name and instruction) and data reference instruction symbols in the instruction block.

The data generation instruction symbol is obtained by symbolizing information related to the data generation instruction, and is denoted as “data dependency branch number: DEF”. Further, the data reference instruction symbol is information obtained by symbolizing information related to the data reference instruction, and is denoted as “data dependency branch number: USE”.
In FIG. 8, the data dependency branches “6” to “9” shown in FIG. 7 do not exist, but these data dependency branches have neither a data generation instruction nor a reference instruction.

  By the function of the output data generation instruction / input data reference instruction extraction unit 327 described above, the output data generation instruction / input data reference instruction extraction unit 327 uses the data dependency edge information 100A generated by the data dependency edge generation unit 326. As shown in FIG. 8, the output data generation instruction / input data reference instruction information 110A can be generated.

  The data dependency edge information 100A generated by the data dependency edge generation unit 326 and the output data generation instruction / input data reference instruction information 110A generated by the output data generation instruction / input data reference instruction extraction unit 327 are a thread. It is delivered to the inter-data dependency extraction unit 33.

(Description of inter-thread data dependency extraction unit 33)
The inter-thread data dependency extraction unit 33 includes the data dependency edge information 100A (see FIG. 7) generated by the data dependency edge generation unit 326 and the output data generated by the output data generation instruction / input data reference instruction extraction unit 327. The generation instruction / input data reference instruction information 110A (see FIG. 8) is input to extract data dependency between threads. The inter-thread data dependency extraction unit 33 includes a thread input / output data extraction unit 331 and a thread output data generation instruction / thread input data reference instruction extraction unit 332.

(Description of thread input / output data extraction unit 331)
The thread input / output data extraction unit 331 receives the data dependency edge information 100A (see FIG. 7) generated by the data dependency edge generation unit 326, and uses the data dependency edge information 100A (see FIG. 7) to input thread input data. Then, thread output data (thread input / output data) is extracted, and inter-thread data dependency edge information 120A (see FIG. 9) is generated.
The thread input data is data generated in another thread among data referred to by each instruction in the thread. The thread output data is data that is referred to in another thread among data generated by each instruction in the thread. That is, the data dependence branch crossing the thread boundaries E1 to E6 (see FIG. 6) represents the thread input / output data. Hereinafter, an example of the function of the thread input / output data extraction unit 331 will be described with reference to FIGS. 6, 7, and 9.

The thread input / output data extraction unit 331 refers to the data dependency edge information 100A generated by the data dependency edge generation unit 326, and inter-thread data dependency edge information 120A in which an inter-thread data dependency edge is inserted into the data dependency edge information 100A. Is generated. Here, the inter-thread data dependency branch means a data dependency branch connecting data nodes of different threads.
As shown in the data dependency edge information 100A of FIG. 7, the data dependency edges “1” to “10”, “17”, “20”, and “21” indicate that the thread of the output data node and the thread of the input data node are Since they are the same, the inter-thread data dependency branch is not connected from the output data node to the input data node. Also, since the data dependency branches “11” to “16”, “18”, “19”, “22” to “24” have different output data node threads and input data node threads, An inter-thread data dependency branch is connected to the input data node.

  FIG. 9 is a table showing the inter-thread data dependency edge information 120A generated by the thread input / output data extraction unit 331 using the data dependency edge information 100A generated by the data dependency edge generation unit 326. Compared with the data dependence edge information 100A of FIG. 7, a column of “inter-thread data dependence edge” is added, and a value indicating whether or not the data dependence edge is an inter-thread data dependence edge is added to each data dependence edge. Can be set.

  Further, the inter-thread data dependency branch information 120A generated by the thread input / output data extraction unit 331 is delivered to the thread output data generation instruction / thread input data reference instruction extraction unit 332.

(Description of thread output data generation instruction / thread input data reference instruction extraction unit 332)
The thread output data generation instruction / thread input data reference instruction extraction unit 332 includes an inter-thread data dependency branch information 120A (see FIG. 9) generated by the thread input / output data extraction unit 331, and an output data generation instruction / input data reference instruction. The thread input data reference instruction is extracted with reference to the output data generation instruction / input data reference instruction information 110A (see FIG. 8) generated by the extraction unit 327. Here, the thread input data reference instruction is an input data reference instruction related to the inter-thread data dependency branch. Hereinafter, an example of the function of the thread output data generation instruction / thread input data reference instruction extraction unit 332 will be described with reference to FIGS.

  This will be described using the inter-thread data dependency edge information 120A shown in FIG. The thread output data generation instruction / thread input data reference instruction extraction unit 332 uses inter-thread data dependency branches “11” to “16”, “18”, “19”, “22” to “24” as thread input data reference instructions. The respective data reference instructions “11: USE” to “16: USE”, “18: USE”, “19: USE”, and “22: USE” to “24: USE” are extracted. Further, the thread output data generation instruction / thread input data reference instruction extraction unit 332 uses the extracted data dependency branch to generate the output data generation instruction and input data generated by the output data generation instruction / input data reference instruction extraction unit 327. Referring to the reference instruction, a thread output data generation instruction is extracted.

This will be described using the output data generation instruction / input data reference instruction information 110A shown in FIG. The thread output data generation instruction / thread input data reference instruction extraction unit 332 includes the thread input data among the extracted data dependency branches “11” to “16”, “18”, “19”, and “22” to “24”. It is determined whether there is a direct data generation instruction of the reference instruction.
As a result of the determination, the thread output data generation instruction / thread input data reference instruction extraction unit 332 executes the thread input data reference instruction for the data dependency branches “13”, “14”, “16”, “18”, and “19”. Since there is a direct data generation instruction (referring to the output data generation instruction / input data reference instruction information 110A in FIG. 8, the data generation instruction exists on the same line as the data reference instruction), the data generation instruction Extracted as a thread output data generation instruction.
Also, the thread output data generation instruction / thread input data reference instruction extraction unit 332 has no direct data generation instruction of the thread input data reference instruction for the data dependency branches “11”, “12”, and “15”. (If the output data generation instruction / input data reference instruction information 110A in FIG. 8 is referred to, there is no data generation instruction on the same line as the data reference instruction), it is necessary to search for the thread output data generation instruction. This search method will be described with reference to FIG.

FIG. 10 illustrates a thread output data generation instruction search method when the thread output data generation instruction / thread input data reference instruction extraction unit 332 does not include a direct data generation instruction of the thread input data reference instruction. FIG.
When there is no direct data generation instruction of the thread input data reference instruction, the thread output data generation instruction / thread input data reference instruction extraction unit 332 searches for the output data generation instruction in the preceding branch direction. For example, the thread output data generation instruction / thread input data reference instruction extraction unit 332 extracts the leading branch “8” of the data dependence branch “11”. Then, the thread output data generation instruction / thread input data reference instruction extraction unit 332 does not have the data generation instruction symbol of the data dependency branch “8”, and therefore the preceding branch “3” of the data dependency branch “8” and the preceding branch “24” is extracted.
The thread output data generation instruction / thread input data reference instruction extraction unit 332 extracts the data generation instruction symbol “3: DEF” of the data dependency branch “3” extracted as the preceding branch, and the search source data dependency branch “11”. To the generation instruction list (thread input data generation instruction list of thread input data reference instruction).
Further, the thread output data generation instruction / thread input data reference instruction extraction unit 332 extracts the data generation instruction symbol “24: DEF” of the data dependency branch “24” extracted as the preceding branch, and the search source data dependency branch “ 11 ”is added to the generation instruction list (thread output data generation instruction list of the thread input data reference instruction).

  By the thread extraction data generation instruction search method described above, the thread output data generation instruction / thread input data reference instruction extraction unit 332 can generate a thread output data generation instruction list of thread input data reference instructions.

  FIG. 11 shows a thread output data generation instruction / thread input data reference instruction extraction unit 332 that generates a thread output data generation instruction list of thread input data reference instructions, and inter-thread data dependency branch information generated by the thread input / output data extraction unit 331. It is a table | surface which shows the information (inter-thread data dependence instruction pair information) inserted and produced | generated in 120A (refer FIG. 9). As shown in FIG. 11, a plurality of thread output data generation instruction lists of thread input data reference instructions may exist for each data dependency branch.

  Further, the inter-thread data dependency branch information 120A generated by the thread input / output data extraction unit 331 and the inter-thread data dependency instruction pair information 130A generated by the thread output data generation instruction / thread input data reference instruction extraction unit 332 (see FIG. 11) is delivered to the communication command insertion unit 35A.

(Description of communication command insertion unit 35A)
The communication instruction insertion unit 35A includes the intermediate language generated by the syntax analysis unit 31, the inter-thread data dependency branch information 120A (see FIG. 9) generated by the thread input / output data extraction unit 331, and the thread output data generation instruction / The inter-thread data dependent instruction pair information 130A (see FIG. 11) generated by the thread input data reference instruction extraction unit 332 is input, and a communication instruction is inserted into the intermediate language. The communication command insertion unit 35A includes a data transmission command insertion unit 351A and a data reception synchronization command insertion unit 352A.

(Description of Data Transmission Instruction Insertion Unit 351A)
The data transmission instruction insertion unit 351A refers to the thread output data generation instruction list of the thread input data reference instruction in the inter-thread data dependence instruction pair information 130A (see FIG. 11), and the thread of the thread input data reference instruction in the intermediate language A data transmission command is inserted immediately after the output data generation command. Hereinafter, an example of the function of the data transmission command insertion unit 351A will be described with reference to FIG.

For example, the data transmission instruction insertion unit 351A inserts a data transmission instruction immediately after the thread output data generation instruction “13: DEF” corresponding to the thread input data reference instruction “13: USE”. Further, for example, the data transmission command insertion unit 351A sends a data transmission command immediately after each of the thread output data generation commands “3: DEF” and “24: DEF” corresponding to the thread input data reference command “11: USE”. insert.
At this time, the thread “p2” in which the thread input data reference instruction “13: USE” is executed is designated as the destination thread.
The data transmission command insertion unit 351A can insert, for example, an instruction for calling a function for performing data transmission processing of an existing message communication library function for parallel programming into the intermediate language as a data transmission command.
Taking MPI, which is a message programming parallel programming environment, for example, the data transmission instruction insertion unit 351A inserts, for example, an instruction for calling the MPI_Send () function as a function for performing data transmission processing, and uses data as a function call argument. An address, a data size, a data type, a destination thread number (unique number assigned in advance to each thread), and a message tag number (data dependency branch number of a thread input data reference instruction) are set.

(Description of Data Reception Synchronization Command Insertion Unit 352A)
The data reception synchronization instruction insertion unit 352A refers to the thread output data generation instruction list of the thread input data reference instruction in the inter-thread data dependent instruction pair information 130A (see FIG. 11), and determines the thread input data reference instruction in the intermediate language. A data reception synchronization command is inserted immediately before. Hereinafter, an example of the function of the data reception synchronization command insertion unit 352A will be described with reference to FIG.

For example, the data reception synchronization command insertion unit 352A inserts the data reception synchronization command immediately before the thread input data reference command “11: USE”.
The data reception synchronization instruction insertion unit 352A can insert, for example, an instruction for calling a function for performing data reception processing of an existing parallel programming message communication library function into the intermediate language as the data reception synchronization instruction.
Taking MPI, which is a message programming parallel programming environment, as an example, the data reception synchronization instruction insertion unit 352A inserts, for example, an instruction for calling an MPI_Recv () function as a function for performing data reception processing, and as a function call argument, A data address, a data size, a data type, a transmission source thread number (MPI_ANY_SOURCE), and a message tag number (data dependent branch number of a thread input data reference instruction) are set. Note that “MPI_ANY_SOURCE” (“transmission source is an arbitrary thread”) is used as the transmission source thread number in order to correspond to the case where there are a plurality of thread output data generation instructions corresponding to the thread input data reference instruction. It is.

  A program including a communication command generated by inserting a communication command into the intermediate language by the communication command insertion unit 35A is delivered to the program division / code generation unit 39.

(Description of program division / code generation unit 39)
The program division / code generation unit 39 divides a program including the communication instruction generated by the communication instruction insertion unit 35A into thread processing performed by each processor (program division) and converts it into an execution code (machine code) (code generation). To do. As a result, the program division / code generation unit 39 generates a division program 55A (see FIG. 1) including a communication command.
The program dividing function refers to a thread attribute added to each instruction by the syntax analysis unit 31 and divides the program into processes of each thread.
Further, the code generation function is not particularly different from the known code generation function of a normal compiler, and therefore a more detailed description of the code generation function is omitted.

  According to the first embodiment described above, the program processing apparatus 1A analyzes the parallel processing program 50A and generates a divided program 55A including communication instructions applicable to the existing distributed memory system and the existing shared memory system. Is possible.

FIG. 12 is a diagram illustrating an example of a hardware configuration of the program processing apparatus 1A (see FIG. 1).
As shown in FIG. 12, the program processing device 1A is a computer, and includes a central processing unit (processing unit) 10, a main storage device (processing unit) 20, a file device (storage unit) 40, and an input device IN. , And the output device OUT. The file device 40 includes a parallel processing program 50A, and the main storage device 20 includes a parallel processing compiler 30A.

The central processing unit 10 is configured by, for example, a CPU (Central Processing Unit) and the like, and has a function of executing a program stored in the main storage device 20.
The main storage device 20 is composed of, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), and the like, and stores programs, data, and the like executed by the central processing unit 10.
The parallel processing compiler 30A is a program for converting the parallel processing program 50A into a format that can be executed by the multiprocessor system (generating an execution code for the multiprocessor system).
The file device 40 is a device for storing files, and stores a parallel processing program 50A and the like.
The parallel processing program 50A is a program for causing a multiprocessor system to execute parallel processing, and is described by a programmer or the like.
The input device IN is configured by a keyboard, a mouse, and the like, and has a function of inputting an instruction from an operator.
The output device OUT is configured by a display, a printer, or the like, and has a function of outputting characters, images, and the like.

  The central processing unit 10 receives a command from the parallel processing compiler 30 </ b> A stored in the main storage device 20, and reads out the parallel processing program 50 </ b> A stored in the file device 40 to the main storage device 20. The central processing unit 10 obtains data dependency branch information obtained as a result of analyzing the processing order of instructions in the parallel processing program 50A read to the main storage device 20, the data referred to by each instruction, and the data generated by each instruction. 100A (see FIG. 7) and inter-thread data dependent instruction pair information 130A (see FIG. 11) are generated and stored in the main storage device 20. Note that the parallel processing program 50A can be input by the programmer or the like via the input device IN and stored in the file device 40, for example.

  Next, the central processing unit 10 receives the instruction of the parallel processing compiler 30A stored in the main storage device 20, and receives the data dependence branch information 100A (see FIG. 7) and the inter-thread data dependence instruction pair information 130A (see FIG. 11). Referring to the communication command, the communication command is embedded in the parallel processing program 50A stored in the main storage device 20.

  Next, the central processing unit 10 receives a command from the parallel processing compiler 30A stored in the main storage device 20, and divides the parallel processing program 50A in which the communication command is embedded for each thread. The central processing unit 10 stores the divided program 55A including the communication command divided for each thread in the file device 40. Further, the central processing unit 10 can output the program via the output device OUT.

  FIG. 13 is a flowchart showing the operation of the program processing apparatus 1A (see FIG. 1). The operation of the program processing apparatus 1A will be described with reference to FIG. 13 (see FIG. 1 as appropriate).

  As shown in FIG. 13, the syntax analysis unit 31 first performs a process (syntax analysis process) of analyzing the syntax of the parallel processing program 50A (S10). Next, the data dependency extraction unit 32A performs a process of extracting data dependency (data dependency extraction process) using the intermediate language generated as a result of the syntax analysis process (S20). The inter-thread data dependency extraction unit 33 performs processing for extracting data dependency between threads (inter-thread data dependency extraction processing) (S30). Next, the communication command insertion unit 35A performs processing (communication command insertion processing) for generating a program including the communication command by inserting the communication command (S40A). Thereafter, the program division / code generation unit 39 performs a process (program division / code generation process) for dividing the program including the communication instruction and converting the program into an execution code (S50).

  FIG. 14 is a flowchart showing details of the data dependency extraction process S20 (see FIG. 13). The data dependency extraction process S20 (see FIG. 13) will be described with reference to FIG. 14 (see FIG. 1 as appropriate).

  As shown in FIG. 14, first, the instruction reference / generation data extraction unit 321 extracts the reference / generation data of each instruction from the intermediate language (S21). Next, the in-function indirect reference / generated data extraction unit 323 extracts in-function indirect reference / generated data from the intermediate language (S22). Then, the instruction block extraction unit 324 extracts an instruction block from the intermediate language (S23). Next, the instruction block input / output data extraction unit 325A extracts instruction block input / output data from the intermediate language (S24). Then, the data dependence edge generation unit 326 adds a data dependence edge between the instruction block output data and the instruction block input data that inputs the instruction block output data (S25). By this processing, the data dependency edge generation unit 326 can generate the data dependency edge information 100A (see FIG. 7). Thereafter, the output data generation instruction / input data reference instruction extraction unit 327 extracts the output data generation instruction / input data reference instruction (S26). By this processing, the output data generation instruction / input data reference instruction extraction unit 327 can generate the output data generation instruction / input data reference instruction information 110A (see FIG. 8). Through these processes, the data dependency extraction unit 32A generates the data dependency edge information 100A (see FIG. 7) and the output data generation instruction / input data reference instruction information 110A (see FIG. 8) using the intermediate language. Can do.

  FIG. 15 is a flowchart showing details of the inter-thread data dependency extraction processing S30 (see FIG. 13). With reference to FIG. 15 (refer to FIG. 1 as appropriate), the inter-thread data dependency extraction processing S30 (see FIG. 15) will be described.

  As shown in FIG. 15, first, the thread input / output data extraction unit 331 extracts thread input / output data (S31). Thereby, the thread input / output data extraction unit 331 can generate the inter-thread data dependency edge information 120A (see FIG. 9). Next, the thread output data generation instruction / thread input data reference instruction extraction unit 332 extracts a thread output data generation instruction / thread input data reference instruction (S32). Through this process, the thread output data generation instruction / thread input data reference instruction extraction unit 332 can generate the inter-thread data dependent instruction pair information 130A (see FIG. 11). Through these processes, the inter-thread data dependency extraction unit 33 can generate the inter-thread data dependency instruction pair information 130A (see FIG. 11).

  FIG. 16 is a flowchart showing details of the communication command insertion process S40A (see FIG. 13). With reference to FIG. 16 (see FIG. 1 as appropriate), the communication command insertion process S40A (see FIG. 16) will be described.

  As shown in FIG. 16, first, the data transmission instruction insertion unit 351A inserts a data transmission instruction immediately after the thread output data generation instruction of the thread input data reference instruction in the intermediate language (S42A). Next, the data reception synchronization instruction insertion unit 352A inserts the data reception synchronization instruction immediately before the thread input data reference instruction of the thread input data reference instruction in the intermediate language including the data transmission instruction (S43A). Through these processes, the communication command insertion unit 35A can insert a communication command into the intermediate language.

  In the program division / code generation process S50 (see FIG. 13), the program division / code generation unit 39 divides the program including the communication instruction generated by the communication instruction insertion unit 35A into processes performed by each thread (program division). This is a process of converting into an execution code (code generation). As a result, the program division / code generation unit 39 can generate a division program 55A (see FIG. 1) including a communication command. The program partitioning and code generation processing is not particularly different from the known program partitioning and code generation processing of an ordinary compiler, and therefore a more detailed description of the program partitioning and code generation processing is omitted.

(Second Embodiment)
Subsequently, a second embodiment of the present invention will be described with reference to the drawings (FIGS. 17 to 22). The second embodiment relates to the dependency of the data structure. When the data structure is included in the parallel processing program, the dependency between instructions acting on the data structure is extracted and the extraction result is used. The input / output data of the instruction block and the generation of data dependency branch information are extracted, and the output data generation instruction / input data reference instruction is extracted using the data dependency branch information of the instruction block. It differs from the first embodiment in that input data reference command information is generated. Therefore, the parts common to those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The data structure is an aggregate of data composed of a plurality of single data such as array data and C language structure (structure is commonly called “structure”). Here, the single data is a target of information generated / referenced by each instruction (a unit of data on which an operation instruction acts), and is normal “data”. Hereinafter, for convenience of explanation, an object of information generated / referenced by each instruction is referred to as “single data”, and a collection of data composed of a plurality of single data is referred to as “data structure”.

  In the case of single data, it is completely rewritten by the instruction that generates it (assignment instruction), so a simple data dependency is derived from the data generation instruction to the data reference instruction (the data reference instruction depends on the data generation instruction) ). This simple data dependency becomes the operation principle of the data flow machine (data driven control). This data dependency is referred to as single data dependency.

  In the case of a data structure, a single operation instruction accesses only a part (one element in the data structure) (access = “rewrite” or “read”), and specifies the specific data structure element to be accessed. Sometimes this is not possible at compile time. For example, array access by a variable index and pointer reference data correspond to this. For this reason, the dependency (Read-after-write dependency (true dependency) and Write-after-write dependency (output dependency)) in consideration of the ambiguity of access of this data structure is defined as follows.

  The read-after-write dependency means a dependency derived from a “rewrite instruction” for an arbitrary element of the data structure to a “read instruction” for an arbitrary element of the data structure. This is the same property as the data dependency of single data. However, even if the element on which the rewrite instruction operates and the element on which the read instruction operates are not necessarily the same, ”To derive the dependency.

  The write-after-write dependency means a dependency derived from a “rewrite instruction” for an arbitrary element of the data structure to a “rewrite instruction” for an arbitrary element of the data structure.

  There is no Write-after-write dependency for single data dependency. This is because a data generation instruction for a single data completely invalidates (completely rewrites) the data defined by the data generation instruction for the same data executed before, and the data dependency from which these data generation instructions are derived. This is because sex is logically separated.

  For multiple “rewrite commands” for a data structure, such invalidation of rewrite does not necessarily occur (the elements to be rewritten may be different), so it is necessary to store all past rewrite history of the data structure. Arise. Using such means for storing all past rewrite histories, serialization is performed by rewriting instructions between data rewriting instructions. This write-after-write dependency is because the rewrite instruction for the data structure virtually "reads all elements of the data structure" "rewrites one element of the data structure and leaves all other elements as they are. By interpreting that it is composed of two operations of “generating the entire data structure”, it becomes possible to handle the same as normal data dependency (data dependency of single data). The data dependency between instructions that act on the data structure is called data structure dependency.

  In the second embodiment, instruction block input / output data can be extracted from a parallel processing program 50B (see FIG. 17) including a data structure, and data dependency branch information and an output data generation instruction / input data reference instruction can be extracted. It has a configuration.

  FIG. 17 is a functional block diagram illustrating an example of functions of the program processing device according to the second embodiment. As shown in FIG. 17, the program processing apparatus 1B inputs a parallel processing program 50B including a data structure, and outputs a divided program 55B including a communication command. In the second embodiment, the function of the instruction block input / output data extraction unit 325B included in the data dependency extraction unit 32B of the program processing apparatus 1B is the same as the function of the instruction block input / output data extraction unit 325A of the first embodiment. Different. Hereinafter, the function of the instruction block input / output data extraction unit 325B will be described among the elements constituting the program processing apparatus 1B.

  The program shown in FIG. 18 is a parallel processing program written by a programmer or the like, and is an example of a parallel processing program including a data structure. Here, a case where the syntax analysis unit 31 inputs the parallel processing program 50B, analyzes the syntax of the program, and generates an intermediate language will be described. For convenience of explanation, the parallel processing program 50B will be used as an intermediate language as appropriate below.

(Description of instruction block input / output data extraction unit 325B)
The instruction block input / output data extraction unit 325B inputs the intermediate language generated by the syntax analysis unit 31 and the instruction block information extracted by the instruction block extraction unit 324, and determines the dependency between instructions that affect the data structure. Using the instruction block information, the instruction block input data and the instruction block output data are extracted from the intermediate language. Hereinafter, using FIG. 18 to FIG. 20 (refer to FIG. 17 as appropriate), among the functions of the instruction block input / output data extraction unit 325B, the difference from the function of the instruction block input / output data extraction unit 325A in the first embodiment ( Only the function that extracts the dependency between instructions that act on the data structure will be described.

  FIG. 19 is a program graph showing the result of the instruction block input / output data extraction unit 325B extracting the instruction block input data and the instruction block output data from the intermediate language generated by the syntax analysis unit 31. FIG. 19 shows an instruction block input data node F2, an instruction block output data node G2, and the like as an example. The instruction block input / output data extraction method by the instruction block input / output data extraction unit 325B will be described below.

As shown in FIG. 19, the parallel processing program 50B is divided into instruction blocks A11 to A16 by the instruction block extraction unit 324. For example, the instruction “a [0] = 1;” acting on the data structure element on the third line of the parallel processing program 50B shown in FIG.
$ 94: = a [0] ...... (1)
$ 94 = 1 ...... (2)
(Refer to the instruction block A11). The instruction (1) is an operation for calculating the address of the 0th element of the array a and storing it in the intermediate variable $ 94. The instruction (2) is an operation for assigning the right-side expression “1” to the address $ 94. Note that the intermediate variable ($ 94 here) representing the address of the data structure element indicates the element data value stored at the address when quoted by an arbitrary operation instruction (rewrite instruction and read instruction shown below). .

  The instruction block input / output data extraction unit 325B finds, for example, the instruction “$ 94: = a [0]” in the instruction block A11 which calculates the address of the element of the array a and stores it in the intermediate variable $ 94. Also, the instruction block input / output data extraction unit 325B finds the instruction “$ 94 = 1” in the instruction block A11 where the intermediate variable (data structure element address) $ 94 is on the left side of the assignment expression, and this instruction “$ 94 = 1”. Is a rewrite instruction (data structure rewrite instruction) for the array a. Using a similar method, the instruction block input / output data extraction unit 325B finds, for example, the data structure rewrite instruction “$ 95 = b” in the instruction block A12 and the data structure rewrite instruction “$ 103 = $ 101” in the instruction block A14. . In this way, the instruction block input / output data extraction unit 325B can extract the data structure rewriting instruction.

  In addition, the instruction block input / output data extraction unit 325B finds, for example, the instruction “$ 96: = a [i]” to be stored in the intermediate variable $ 96 in the instruction block A13 by calculating the address of the element of the array a. The instruction block input / output data extraction unit 325B finds the instruction “$ 97: = $ 96 + 1” in which the intermediate variable (data structure element address) $ 96 is on the right side of the assignment expression in the instruction block A13. : = $ 96 + 1 ”is determined to be a read instruction (data structure read instruction) for the array a. Using a similar method, the instruction block input / output data extraction unit 325B, for example, reads the data structure read instruction “$ 100: = $ 99-1” in the instruction block A13 and the data structure read instruction “$ 107: = in the instruction block A16. Find printf (“a [i + 1] =% d \ n”, $ 105) ”. In this way, the instruction block input / output data extraction unit 325B can extract the data structure read instruction.

  If there is a dependency derived from the data structure rewrite instruction to the data structure rewrite instruction, the instruction block input / output data extraction unit 325B determines that the dependency is the write-after-write dependency described above. Further, when there is a dependency derived from the data structure rewrite instruction to the data structure read instruction, the dependency is determined to be the above-described read-after-write dependency.

  FIG. 20 is a diagram for explaining the dependency of the data structure extracted by the instruction block input / output data extraction unit 325B. As shown in FIG. 20, for example, the dependency derived from the data structure rewriting instruction “$ 94 = 1” to the data structure rewriting instruction “$ 95 = b” is shown as the Write-after-write dependency. Further, for example, the dependency derived from the data structure rewriting instruction “$ 95 = b” to the data structure reading instruction “$ 97: = $ 96 + 1” is shown as the Read-after-write dependency.

  The instruction block input / output data extraction unit 325B searches for data having a dependency relationship of Write-after-write dependency or Read-after-write dependency in another block, and extracts it as instruction block input / output data. The instruction block input / output data extraction unit 325B refers to the instruction block information extracted by the instruction block extraction unit 324 and determines, for example, that the data structure rewrite instruction “$ 94 = 1” for the array a is in the instruction block A11. To do. Further, the instruction block input / output data extraction unit 325B has a data structure rewrite instruction “$ 95 = b” for the array a in an instruction block (instruction block A12) other than the instruction block A11. It is determined that Write-after-write dependency is shown for “$ 94 = 1”. As a result, the instruction block input / output data extraction unit 325B can extract the array a as the instruction block output data of the instruction block A11. At the same time, the instruction block input / output data extraction unit 325B can extract the array a as the instruction block input data of the instruction block A12. FIG. 19 shows the instruction block output data node G2 and the instruction block input data node F2, respectively. For example, the instruction block output data node G2 and the instruction block input data node F2 are marked with * a <3>, which indicates an arbitrary element of the array a [3].

  By such a method, the instruction block input / output data extraction unit 325B can extract the instruction block input / output data. The instruction block input / output data obtained as a result of the extraction is shown as an instruction block input / output data node added to the program graph of FIG. Thus, the instruction block input / output data extraction unit 325B associates the instruction block extracted by the instruction block extraction unit 324 with the input / output data (including the data structure) in the instruction block. Information about data (instruction block input / output data information) can be generated.

  Also, the instruction block information generated by the instruction block extraction unit 324, the information (instruction block input / output data information) regarding the instruction block input / output data (including the data structure) generated by the instruction block input / output data extraction unit 325B, and Is passed to the data dependency edge generation unit 326.

  FIG. 21 is a table showing data dependency edge information generated by the data dependency edge generation unit 326 (see FIG. 17). The data dependency branch generation unit 326 includes the intermediate language generated by the syntax analysis unit 31, the instruction block information generated by the instruction block extraction unit 324, and the instruction block input / output generated by the instruction block input / output data extraction unit 325B. It is possible to generate data dependency edge information of a data structure by inputting the data information and performing the same process as when generating data dependency edge information of single data. In the second embodiment, the parallel processing program 50B is used. In this case, since the preceding branch and the subsequent branch do not exist, the preceding branch item and the subsequent branch item are omitted from the data dependency branch information 100B. ing.

  FIG. 22 is a table showing output data generation instruction / input data reference instruction information generated by the output data generation instruction / input data reference instruction extraction unit 327 (see FIG. 17). The output data generation instruction / input data reference instruction extraction unit 327 receives the intermediate language generated by the syntax analysis unit 31 and the data dependency branch information 100B (see FIG. 21) generated by the data dependency edge generation unit 326. The output data generation instruction and the input data reference instruction can be extracted by the same processing as that for generating data-dependent branch information of single data.

  According to the second embodiment described above, the program processing apparatus 1B analyzes the parallel processing program 50B including the data structure and divides the communication processing instructions that can be applied to the existing distributed memory system and the existing shared memory system. It is possible to generate the program 55B.

  Further, the hardware configuration of the program processing device 1B is not different from the hardware configuration of the program processing device 1A (see FIG. 1), and thus the description thereof is omitted.

  According to the program processing apparatus according to the first embodiment or the second embodiment described above, the multiprocessor system executes high-performance parallel processing by simply adding a simple description to the sequential program by a programmer or the like. It is possible to generate the execution code.

It is a functional block diagram which shows the function example of the program processing apparatus which concerns on 1st Embodiment. It is an example of the program before the thread description addition according to the first embodiment. It is an example of a program (parallel processing program) after adding a thread description according to the first embodiment. It is a program graph which shows the result of having extracted the instruction block from the intermediate language which concerns on 1st Embodiment. It is a program graph which shows the result of having extracted the instruction block input / output data from the intermediate language according to the first embodiment. It is a program graph which shows the result of having generated the data dependence branch from the intermediate language concerning a 1st embodiment. It is a table | surface which shows the data dependence edge information which concerns on 1st Embodiment. 4 is a table showing output data generation instruction / input data reference instruction information according to the first embodiment. It is a table | surface which shows the data dependence edge information between threads which concerns on 1st Embodiment. It is a figure for demonstrating the search method of the thread output data generation instruction which concerns on 1st Embodiment. It is a table | surface which shows the data dependence instruction pair information between threads which concerns on 1st Embodiment. It is a figure which shows an example of the hardware constitutions of the program processing apparatus which concerns on 1st Embodiment. It is a flowchart which shows operation | movement of the program processing apparatus which concerns on 1st Embodiment. It is a flowchart which shows the flow of the data dependence extraction process which concerns on 1st Embodiment. It is a flowchart which shows the detail of the data dependence extraction process between threads which concerns on 1st Embodiment. It is a flowchart which shows the detail of the communication command insertion process which concerns on 1st Embodiment. It is a functional block diagram which shows the function example of the program processing apparatus which concerns on 2nd Embodiment. It is an example of the parallel processing program which concerns on 2nd Embodiment. It is a program graph which shows the result of having extracted the instruction block input / output data from the intermediate language according to the second embodiment. It is a figure for demonstrating the dependence of the data structure which concerns on 2nd Embodiment. It is a table | surface which shows the data dependence edge information which concerns on 2nd Embodiment. 12 is a table showing output data generation instruction / input data reference instruction information according to the second embodiment.

Explanation of symbols

1A, 1B Program processing device 10 Central processing unit (processing unit)
20 Main storage (processing unit)
30A Parallel processing compiler 31 Syntax analysis unit 32A, 32B Data dependency extraction unit 33 Inter-thread data dependency extraction unit 35A Communication instruction insertion unit 39 Program division / code generation unit 40 File device (storage unit)
50A, 50B Parallel processing program 55A, 55B Divided program including communication instructions 321 Instruction reference / generated data extraction unit 322 Pointer alias analysis unit 323 Indirect reference / generated data extraction unit 324 Instruction block extraction unit 325A, 325B Instruction block input / output Data extraction unit 326 Data dependency branch generation unit 327 Output data generation instruction / input data reference instruction extraction unit 331 Thread input / output data extraction unit 332 Thread output data generation instruction / thread input data reference instruction extraction unit 333 Inter-processor communication instruction insertion unit 341 Inter-thread transfer pointer extraction unit 342 Pointer alias ID operation instruction insertion unit 351A Data transmission instruction insertion unit 352A Data reception synchronization instruction insertion unit 353 Thread activation instruction insertion unit IN input device OUT output device

Claims (4)

Input a parallel processing program to which a thread description, which is a description of the effective range of threads, which is a unit of a program executed by a processor, is input, divide the program into each thread, and generate an execution code for a multiprocessor system A program processing apparatus for performing
The program processing device includes a storage unit and a processing unit,
The processor is
The start point and end point of each thread in the parallel processing program input to the storage unit are specified by reserved keywords or symbols, and are included in the thread area specified by the specified start point and end point A syntax analysis unit that generates an intermediate language to which each operation instruction is added with a thread attribute that is information for determining which thread each operation instruction is included in ;
Single data which is a dependency of data generated or referred to by a single operation instruction based on the instruction block input / output data by inputting the intermediate language, extracting instruction block input / output data from the intermediate language A data dependency extraction unit that generates data dependency branch information including information on dependency and information on data structure dependency that is data dependency between instructions operating on the data structure;
The intermediate language and the data dependency edge information are input, and based on the data dependency edge information, a data dependency edge that connects different threads from the intermediate language, and a thread output data generation instruction corresponding to the data dependency edge And an inter-thread data dependency extraction unit that extracts the thread input reference instruction and generates inter-thread data dependence instruction pair information;
The intermediate language and the inter-thread data dependent instruction pair information are input, and based on the inter-thread data dependent instruction pair information, a data communication instruction depending on the thread is inserted into the intermediate language, A communication command insertion unit for generating a program including the communication command;
Program processing comprising: a program division / code generation unit that inputs a program including the communication instruction, divides the program into the threads based on the thread attribute of each instruction, and converts the program into an execution code. apparatus. Input a parallel processing program to which a thread description, which is a description of the effective range of threads, which is a unit of a program executed by a processor, is input, divide the program into each thread, and generate an execution code for a multiprocessor system A program processing method by a program processing device for performing
The program processing device includes a storage unit and a processing unit,
The processor is
The start point and end point of each thread in the parallel processing program input to the storage unit are specified by reserved keywords or symbols, and are included in the thread area specified by the specified start point and end point An intermediate language is generated by adding a thread attribute that is information for determining which thread each operation instruction is included in to each operation instruction.
Single data which is a dependency of data generated or referred to by a single operation instruction based on the instruction block input / output data by inputting the intermediate language, extracting instruction block input / output data from the intermediate language Generate data dependency branch information including information on dependency and information on data structure dependency which is data dependency between instructions operating on the data structure,
The intermediate language and the data dependency edge information are input, and based on the data dependency edge information, a data dependency edge that connects different threads from the intermediate language, and a thread output data generation instruction corresponding to the data dependency edge And thread input reference instructions are extracted to generate inter-thread data dependent instruction pair information,
The intermediate language and the inter-thread data dependent instruction pair information are input, and based on the inter-thread data dependent instruction pair information, a data communication instruction depending on the thread is inserted into the intermediate language, Generate a program containing communication instructions,
A program processing method comprising: inputting a program including the communication instruction, dividing the program into the threads based on the thread attribute of each instruction, and converting the program into an execution code. Input a parallel processing program to which a thread description, which is a description of the effective range of threads, which is a unit of a program executed by a processor, is input, divide the program into each thread, and generate an execution code for a multiprocessor system A parallel processing program compiler for causing a computer to execute a program processing method for performing
The computer includes a storage unit and a processing unit,
The compiler for the parallel processing program is
The start point and end point of each thread in the parallel processing program input to the storage unit are specified by reserved keywords or symbols, and are included in the thread area specified by the specified start point and end point A process of generating an intermediate language in which a thread attribute, which is information for determining which thread each operation instruction is included in, is added to each operation instruction;
Single data which is a dependency of data generated or referred to by a single operation instruction based on the instruction block input / output data by inputting the intermediate language, extracting instruction block input / output data from the intermediate language Processing for generating data dependency branch information including information on dependency and information on data structure dependency which is data dependency between instructions operating on the data structure;
The intermediate language and the data dependency edge information are input, and based on the data dependency edge information, a data dependency edge that connects different threads from the intermediate language, and a thread output data generation instruction corresponding to the data dependency edge And a thread input reference instruction to generate an inter-thread data dependent instruction pair information;
The intermediate language and the inter-thread data dependent instruction pair information are input, and based on the inter-thread data dependent instruction pair information, a data communication instruction depending on the thread is inserted into the intermediate language, Processing for generating a program including communication instructions;
A process of inputting a program including the communication instruction, dividing the program into the threads based on the thread attribute of each instruction, and converting the program into an execution code ;
A compiler for a parallel processing program , wherein the processing unit is executed . A recording medium storing the parallel processing program compiler according to claim 3 .

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