JP4828561B2 - Triangular / trapezoidal wave generator - Google Patents

Triangular / trapezoidal wave generator Download PDF

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JP4828561B2
JP4828561B2 JP2008089295A JP2008089295A JP4828561B2 JP 4828561 B2 JP4828561 B2 JP 4828561B2 JP 2008089295 A JP2008089295 A JP 2008089295A JP 2008089295 A JP2008089295 A JP 2008089295A JP 4828561 B2 JP4828561 B2 JP 4828561B2
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circuit
signal
triangular wave
phase difference
charge
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JP2009246595A (en
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浩季 森村
俊重 島村
智志 重松
衛 中西
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Nippon Telegraph and Telephone Corp
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Description

本発明は、基準クロック信号に同期した三角波または台形波を発生させ、かつ三角波または台形波と基準クロック信号が位相同期状態にあるか否かを表示する試験回路を含む三角波・台形波生成回路に関する。   The present invention relates to a triangular wave / trapezoidal wave generating circuit including a test circuit that generates a triangular wave or a trapezoidal wave synchronized with a reference clock signal and displays whether the triangular wave or the trapezoidal wave and the reference clock signal are in a phase synchronization state. .

三角波・台形波生成回路は、方形波を積分する方法や、容量負荷の充電・放電を方形波で切り替える方法により三角波または台形波を発生させている。   The triangular wave / trapezoidal wave generating circuit generates a triangular wave or a trapezoidal wave by a method of integrating a square wave or a method of switching charging / discharging of a capacitive load with a square wave.

図8は、従来の三角波生成回路の構成例を示す(特許文献1)。本構成は、容量負荷の充電・放電を方形波で切り替えることにより三角波を発生させるとともに、PLL(位相同期)技術を用いて三角波の周期を基準クロック信号に同期させる波形制御回路を付加したものである。   FIG. 8 shows a configuration example of a conventional triangular wave generation circuit (Patent Document 1). In this configuration, a triangular wave is generated by switching charging / discharging of a capacitive load with a square wave, and a waveform control circuit for synchronizing the period of the triangular wave with a reference clock signal using PLL (phase synchronization) technology is added. is there.

図8において、三角波生成回路は、充放電回路50A、負荷容量60、バッファ70および波形制御回路80Aを備え、充放電回路50Aの出力により負荷容量60を充放電し、バッファ70から三角波の出力信号を出力する構成である。   In FIG. 8, the triangular wave generation circuit includes a charge / discharge circuit 50A, a load capacitor 60, a buffer 70, and a waveform control circuit 80A. The load capacitor 60 is charged / discharged by the output of the charge / discharge circuit 50A. Is output.

波形制御回路80Aは、2つの比較回路81,82、SRラッチ83、位相比較器84、ループフィルタ85により構成される。2つの比較回路81,82は、バッファ70の出力信号(三角波)と高電位Vref-H および低電位Vref-L をそれぞれ比較する。三角波がVref-H またはVref-L になったときに、比較回路81,82の出力をSRラッチ83でラッチすることにより、三角波の位相が図9に示すように検出される。このSRラッチ83の出力信号は、負荷容量60の充電/放電の切替タイミングとなる充放電切替信号として充放電回路50Aに入力する。また、位相比較器84は、SRラッチ83の出力信号(三角波の位相)と基準クロック信号の位相を比較し、位相の進みや遅れに対応したパルス信号をループフィルタ85へ出力する。ループフィルタ85は、位相比較器84が出力するパルス信号を積分し、充放電回路50Aのバイアス電圧を調整する充放電電流調整信号(アナログ電圧)を生成して充放電回路50Aへ出力する。   The waveform control circuit 80A includes two comparison circuits 81 and 82, an SR latch 83, a phase comparator 84, and a loop filter 85. The two comparison circuits 81 and 82 compare the output signal (triangular wave) of the buffer 70 with the high potential Vref-H and the low potential Vref-L, respectively. When the triangular wave becomes Vref-H or Vref-L, the output of the comparison circuits 81 and 82 is latched by the SR latch 83, whereby the phase of the triangular wave is detected as shown in FIG. The output signal of the SR latch 83 is input to the charging / discharging circuit 50A as a charging / discharging switching signal that becomes the charging / discharging switching timing of the load capacitor 60. In addition, the phase comparator 84 compares the output signal (triangular wave phase) of the SR latch 83 with the phase of the reference clock signal, and outputs a pulse signal corresponding to the phase advance or delay to the loop filter 85. The loop filter 85 integrates the pulse signal output from the phase comparator 84, generates a charge / discharge current adjustment signal (analog voltage) for adjusting the bias voltage of the charge / discharge circuit 50A, and outputs it to the charge / discharge circuit 50A.

図10は、充放電回路50Aの構成例を示す。
図10において、波形制御回路80Aから出力される充放電電流調整信号は基準電流発生回路51に入力され、発生する基準電流を変化させる。この基準電流が変化すると、それに応じて定電流回路52,53の電流が変化し、充放電切替信号によって開閉するスイッチ54,55を介して、負荷容量60に対する充放電電流を増減させる。これにより、出力される三角波のスルーレート(波形の傾き)が変化し、最終的に基準クロック信号と三角波の周期が同じになるように制御される。また、電源電圧変動等のノイズにより位相がずれた場合も、基準クロック信号との位相差がゼロに復帰するように調整される。
特開2004−7324号公報
FIG. 10 shows a configuration example of the charge / discharge circuit 50A.
In FIG. 10, the charge / discharge current adjustment signal output from the waveform control circuit 80A is input to the reference current generation circuit 51 to change the generated reference current. When the reference current changes, the currents of the constant current circuits 52 and 53 change accordingly, and the charge / discharge current for the load capacitor 60 is increased or decreased via the switches 54 and 55 that are opened and closed by the charge / discharge switching signal. As a result, the slew rate (slope of the waveform) of the output triangular wave changes, and finally, the control is performed so that the cycle of the reference clock signal and the triangular wave become the same. Even when the phase is shifted due to noise such as power supply voltage fluctuation, the phase difference from the reference clock signal is adjusted to return to zero.
JP 2004-7324 A

ところで、従来の三角波生成回路では、三角波の位相をPLL構成の波形制御回路80Aによってフィードバック制御する構成であり、基準クロック信号と三角波が位相同期状態にあるか否かを確認する手段がなかった。すなわち、製造時や実使用時に三角波生成回路の同期ロック/アンロック状態をモニタし、基準クロック信号に対する位相同期が早い遅いなどの良品検査や動作マージンをチェックすることができなかった。従来の台形波生成回路においても同様であった。   By the way, the conventional triangular wave generation circuit has a configuration in which the phase of the triangular wave is feedback controlled by the waveform control circuit 80A having a PLL configuration, and there is no means for confirming whether or not the reference clock signal and the triangular wave are in a phase synchronization state. In other words, it was impossible to monitor the synchronization lock / unlock state of the triangular wave generation circuit at the time of manufacturing or actual use, and to check non-defective products such as early and late phase synchronization with respect to the reference clock signal and operation margin. The same applies to the conventional trapezoidal wave generation circuit.

本発明は、三角波または台形波と基準クロック信号が位相同期状態にあるか否かを表示することができる試験回路を含む三角波・台形波生成回路を提供することを目的とする。   An object of the present invention is to provide a triangular wave / trapezoidal wave generation circuit including a test circuit capable of displaying whether or not a triangular wave or a trapezoidal wave and a reference clock signal are in phase synchronization.

本発明は、充放電回路に充放電切替信号を入力して容量負荷の充電・放電を切り替えることにより、2つの異なる電位間で傾きを有する三角波または台形波を発生させるとともに、三角波または台形波の周期と基準クロック信号の周期の違いである位相差を検出し、三角波または台形波の周期と基準クロック信号の周期が同期するように制御する波形制御回路を含む三角波・台形波生成回路において、波形制御回路から三角波または台形波と基準クロック信号の位相差に対応する位相差パルス信号を入力し、三角波または台形波を生成する充放電切替信号の周期で所定のパルス幅以上の位相差パルス信号をラッチし、所定の位相差内で位相同期状態にあるか否かを示すステータス信号として出力する試験回路を備える。   The present invention generates a triangular wave or a trapezoidal wave having a slope between two different potentials by inputting a charge / discharge switching signal to the charging / discharging circuit to switch the charging / discharging of the capacitive load. In a triangular / trapezoidal wave generator circuit that includes a waveform control circuit that detects the phase difference, which is the difference between the period and the period of the reference clock signal, and controls the period of the triangular wave or trapezoidal wave to synchronize with the period of the reference clock signal A phase difference pulse signal corresponding to the phase difference between the triangular wave or trapezoidal wave and the reference clock signal is input from the control circuit, and a phase difference pulse signal having a predetermined pulse width or more in the cycle of the charge / discharge switching signal for generating the triangular wave or the trapezoidal wave. A test circuit that latches and outputs as a status signal indicating whether or not the phase is synchronized within a predetermined phase difference is provided.

試験回路は、位相差パルス信号のパルス幅を拡大するパルス幅拡大回路と、充放電切替信号を遅延させる遅延回路と、パルス幅拡大回路でパルス幅を拡大した位相差パルス信号を遅延回路で遅延させた充放電切替信号でラッチし、ステータス信号として出力するラッチ回路とを備える。   The test circuit includes a pulse width expansion circuit that expands the pulse width of the phase difference pulse signal, a delay circuit that delays the charge / discharge switching signal, and a delay circuit that delays the phase difference pulse signal whose pulse width has been expanded by the pulse width expansion circuit. A latch circuit that latches with the charge / discharge switching signal and outputs the status signal.

また、波形制御回路が基準クロック信号の半周期ごとに位相差パルス信号を出力する構成としたときに、試験回路は、位相差パルス信号のパルス幅を拡大するパルス幅拡大回路と、充放電切替信号を遅延させる遅延回路と、パルス幅拡大回路でパルス幅を拡大した位相差パルス信号を、遅延回路で遅延させた充放電切替信号およびその反転信号でそれぞれラッチする2つのラッチ回路と、2つのラッチ回路の出力を、遅延回路で遅延させた充放電切替信号で論理に応じて切り替え、ステータス信号として出力するセレクタとを備える。   In addition, when the waveform control circuit is configured to output a phase difference pulse signal every half cycle of the reference clock signal, the test circuit includes a pulse width expansion circuit that expands the pulse width of the phase difference pulse signal, and charge / discharge switching. A delay circuit for delaying the signal, two latch circuits for latching the phase difference pulse signal whose pulse width has been expanded by the pulse width expansion circuit by the charge / discharge switching signal delayed by the delay circuit and its inverted signal, A selector that switches the output of the latch circuit according to the logic by a charge / discharge switching signal delayed by a delay circuit and outputs the status signal.

試験回路のパルス幅拡大回路は、位相差パルス信号のパルス幅を可変させるパルス幅可変回路に置換し、三角波または台形波と基準クロック信号が位相同期状態であるか否かの基準となる位相差の範囲を調整する構成である。パルス幅可変回路は、遅延量の異なる複数の遅延回路を内蔵し、遅延回路を選択して位相差パルス信号のパルス幅を設定する構成である。   The pulse width expansion circuit of the test circuit is replaced with a pulse width variable circuit that varies the pulse width of the phase difference pulse signal, and a phase difference that is used as a reference to determine whether the triangular wave or trapezoidal wave and the reference clock signal are in phase synchronization. It is the structure which adjusts the range. The pulse width variable circuit has a plurality of delay circuits with different delay amounts, and is configured to select the delay circuit and set the pulse width of the phase difference pulse signal.

本発明の三角波・台形波生成回路は、基準クロック信号に対する三角波または台形波の位相同期状態を確認する試験が可能である。これにより、オンチップ状態で三角波・台形波生成回路の良品テストや動作マージンの評価が可能になり、量産時の良品検査などに絶大な効果を発揮させることができる。   The triangular wave / trapezoidal wave generation circuit of the present invention can perform a test for confirming the phase synchronization state of a triangular wave or a trapezoidal wave with respect to a reference clock signal. As a result, it is possible to perform a non-defective test of the triangular wave / trapezoidal wave generation circuit and an evaluation of an operation margin in an on-chip state, and a great effect can be exhibited in a non-defective product inspection at the time of mass production.

(本発明の三角波生成回路の第1の実施形態)
図1は、本発明の三角波生成回路の第1の実施形態を示す。図2は、本発明の三角波生成回路の第1の実施形態の動作例を示す。ここでは、図8に示す従来の三角波生成回路に試験回路を付加した例を示す。
(First Embodiment of Triangular Wave Generation Circuit of the Present Invention)
FIG. 1 shows a first embodiment of a triangular wave generating circuit of the present invention. FIG. 2 shows an operation example of the first embodiment of the triangular wave generation circuit of the present invention. Here, an example is shown in which a test circuit is added to the conventional triangular wave generating circuit shown in FIG.

図1において、三角波生成回路を構成する充放電回路50A、負荷容量60、バッファ70および波形制御回路80A、さらに波形制御回路80Aを構成する比較回路81,82、SRラッチ83、位相比較器84、ループフィルタ85は図8に示す従来構成と同じである。   In FIG. 1, a charge / discharge circuit 50A, a load capacitor 60, a buffer 70 and a waveform control circuit 80A constituting a triangular wave generating circuit, and comparison circuits 81 and 82, an SR latch 83, a phase comparator 84, constituting a waveform control circuit 80A, The loop filter 85 is the same as the conventional configuration shown in FIG.

本実施形態の試験回路10Aは、OR回路11、パルス幅拡大回路12、遅延回路13およびDラッチ14により構成される。OR回路11は、図2 (1)〜(4) に示すように、位相比較器84が出力する基準クロック信号に対する三角波の位相の進みまたは遅れに対応するパルス信号を入力し、その論理和をとって位相差パルス信号として出力する。パルス幅拡大回路12は、図2(5) に示すように、位相差パルス信号のパルス幅を拡大して出力する。遅延回路13は、図2(3),(6) に示すように、SRラッチ83から充放電回路50Aに出力され、充電/放電の切替タイミングとなる充放電切替信号を分岐して入力し、所定の遅延を与えて出力する。Dラッチ14は、図2 (5)〜(7) に示すように、パルス幅拡大回路12から出力されるパルス幅が拡大された位相差パルス信号を、遅延回路13から出力される遅延させた充放電切替信号でラッチし、基準クロック信号の周期と三角波の周期の違いが所定の範囲にあるか否かの判定に用いるステータス信号を出力する。   The test circuit 10 </ b> A according to this embodiment includes an OR circuit 11, a pulse width expanding circuit 12, a delay circuit 13, and a D latch 14. As shown in FIGS. 2 (1) to (4), the OR circuit 11 inputs a pulse signal corresponding to the advance or delay of the phase of the triangular wave with respect to the reference clock signal output from the phase comparator 84, and calculates its logical sum. It is output as a phase difference pulse signal. As shown in FIG. 2 (5), the pulse width expanding circuit 12 expands the pulse width of the phase difference pulse signal and outputs it. As shown in FIGS. 2 (3) and 2 (6), the delay circuit 13 branches and inputs a charge / discharge switching signal output from the SR latch 83 to the charge / discharge circuit 50A and serving as a charge / discharge switching timing. Output with a predetermined delay. As shown in FIGS. 2 (5) to 2 (7), the D latch 14 delays the phase difference pulse signal output from the pulse width expanding circuit 12 and having the pulse width expanded from the delay circuit 13. The status signal is latched by the charge / discharge switching signal and used to determine whether or not the difference between the period of the reference clock signal and the period of the triangular wave is within a predetermined range.

図2(7) に示すステータス信号の例では、基準クロック信号の位相と三角波の位相にずれがあって位相差パルス信号が発生していれば、ステータス信号がハイレベルになるので位相同期中(調整中)であることがわかる。また、基準クロック信号と三角波の位相差が所定の範囲に入って位相差パルス信号の発生がなくなれば、ステータス信号がローレベルになるので位相同期完了であることがわかる。   In the example of the status signal shown in FIG. 2 (7), if the phase of the reference clock signal and the phase of the triangular wave are out of phase and a phase difference pulse signal is generated, the status signal becomes high level and phase synchronization is in progress ( It can be seen that adjustment is in progress. In addition, when the phase difference between the reference clock signal and the triangular wave falls within a predetermined range and the phase difference pulse signal is not generated, the status signal becomes low level, indicating that phase synchronization is complete.

(本発明の三角波生成回路の第2の実施形態)
図3は、本発明の三角波生成回路の第2の実施形態を示す。第1の実施形態の波形制御回路80Aの位相比較器84は、基準クロック信号の1周期ごとにSRラッチ出力と位相比較する構成であるが、第2の実施形態の波形制御回路80Bの位相比較器84は基準クロック信号の半周期ごとにSRラッチ出力と位相比較する構成とする。三角波生成回路の構成は位相比較器84を除いて第1の実施形態と同じであり、試験回路の構成が第1の実施形態と異なる。図4は、本発明の三角波生成回路の第2の実施形態の動作例を示す。
(Second Embodiment of Triangular Wave Generation Circuit of the Present Invention)
FIG. 3 shows a second embodiment of the triangular wave generating circuit of the present invention. The phase comparator 84 of the waveform control circuit 80A of the first embodiment is configured to perform phase comparison with the SR latch output every cycle of the reference clock signal, but the phase comparison of the waveform control circuit 80B of the second embodiment. The unit 84 is configured to compare the phase with the SR latch output every half cycle of the reference clock signal. The configuration of the triangular wave generation circuit is the same as that of the first embodiment except for the phase comparator 84, and the configuration of the test circuit is different from that of the first embodiment. FIG. 4 shows an operation example of the second embodiment of the triangular wave generation circuit of the present invention.

図3において、本実施形態の試験回路10Bは、OR回路11、パルス幅拡大回路12、遅延回路13、Dラッチ14−1,14−2およびセレクタ15により構成される。OR回路11は、図4 (1)〜(4) に示すように、位相比較器84が出力する基準クロック信号に対する三角波の位相の進みまたは遅れに対応するパルス信号を入力し、その論理和をとって位相差パルス信号として出力する。パルス幅拡大回路12は、図4(5) に示すように、位相差パルス信号のパルス幅を拡大して出力する。遅延回路13は、図4(3),(6) に示すように、SRラッチ83から出力される充放電切替信号を入力し、所定の遅延を与えて出力する。Dラッチ14−1は、図4 (5)〜(7) に示すように、パルス幅が拡大された位相差パルス信号を、遅延させた充放電切替信号の立ち上がりでラッチする。Dラッチ14−2は、遅延させた充放電切替信号を反転クロック入力とし、図4 (5),(6), (8)に示すように、パルス幅が拡大された位相差パルス信号を、遅延させた充放電切替信号の立ち下がりでラッチする。セレクタ15は、遅延回路13から出力される遅延させた充放電切替信号が「1」のときはDラッチ14−1の出力を選択し、充放電切替信号が「0」のときはDラッチ14−2の出力を選択し、基準クロック信号の周期と三角波の周期の違いが所定の範囲にあるか否かの判定に用いるステータス信号として出力する。   In FIG. 3, the test circuit 10 </ b> B of the present embodiment includes an OR circuit 11, a pulse width expanding circuit 12, a delay circuit 13, D latches 14-1 and 14-2, and a selector 15. As shown in FIGS. 4 (1) to (4), the OR circuit 11 inputs a pulse signal corresponding to the advance or delay of the phase of the triangular wave with respect to the reference clock signal output from the phase comparator 84, and calculates its logical sum. It is output as a phase difference pulse signal. As shown in FIG. 4 (5), the pulse width expanding circuit 12 expands the pulse width of the phase difference pulse signal and outputs it. As shown in FIGS. 4 (3) and 4 (6), the delay circuit 13 receives the charge / discharge switching signal output from the SR latch 83, and outputs it with a predetermined delay. As shown in FIGS. 4 (5) to (7), the D latch 14-1 latches the phase difference pulse signal whose pulse width is expanded at the rising edge of the delayed charge / discharge switching signal. The D latch 14-2 uses the delayed charge / discharge switching signal as an inverted clock input, and, as shown in FIGS. 4 (5), (6), and (8), the phase difference pulse signal with an expanded pulse width, Latch at the falling edge of the delayed charge / discharge switching signal. The selector 15 selects the output of the D latch 14-1 when the delayed charge / discharge switching signal output from the delay circuit 13 is “1”, and the D latch 14 when the charge / discharge switching signal is “0”. -2 is selected and output as a status signal used to determine whether the difference between the period of the reference clock signal and the period of the triangular wave is within a predetermined range.

本実施形態の場合は、基準クロック信号の半周期ごとに三角波と位相比較する構成であるので、図4(9) に示すように、基準クロック信号の半周期単位で三角波の位相調整が行われているか否かをステータス信号の状態により判定することができる。   In the case of this embodiment, the phase comparison with the triangular wave is performed every half cycle of the reference clock signal. Therefore, as shown in FIG. 4 (9), the phase adjustment of the triangular wave is performed in half cycle units of the reference clock signal. It can be determined from the status signal status.

(本発明の三角波生成回路の第3の実施形態)
図5は、本発明の三角波生成回路の第3の実施形態を示す。ここでは、第1の実施形態の試験回路10Aの変形例として示すが、第2の実施形態の試験回路10Bにも同様に適用可能である。
(Third Embodiment of Triangular Wave Generation Circuit of the Present Invention)
FIG. 5 shows a third embodiment of the triangular wave generating circuit of the present invention. Here, although shown as a modification of the test circuit 10A of the first embodiment, it can be similarly applied to the test circuit 10B of the second embodiment.

本実施形態の試験回路10Cの特徴は、パルス幅拡大回路12に代えて、位相差パルス信号のパルス幅の拡大範囲を調整可能なパルス幅可変回路16を用いたところにある。パルス幅可変回路16は、遅延時間の異なる複数の遅延回路を用意し、外部から入力する調整信号により遅延回路を選択し、位相差パルス信号のパルス幅を可変とする。これにより、基準クロック信号と三角波の位相差について検出可能な範囲の設定が可能となり、製造時の状況や使用時の条件等に応じて試験基準を任意に調整することができる。   A feature of the test circuit 10C of this embodiment is that a pulse width variable circuit 16 capable of adjusting an expansion range of the pulse width of the phase difference pulse signal is used instead of the pulse width expansion circuit 12. The pulse width variable circuit 16 prepares a plurality of delay circuits having different delay times, selects a delay circuit by an adjustment signal input from the outside, and makes the pulse width of the phase difference pulse signal variable. As a result, it is possible to set a detectable range for the phase difference between the reference clock signal and the triangular wave, and the test reference can be arbitrarily adjusted according to the situation at the time of manufacture and the conditions at the time of use.

(本発明の台形波生成回路の実施形態)
図6は、本発明の台形波生成回路の実施形態を示す。図7は、本発明の台形波生成回路の実施形態の動作例を示す。
(Embodiment of trapezoidal wave generation circuit of the present invention)
FIG. 6 shows an embodiment of the trapezoidal wave generation circuit of the present invention. FIG. 7 shows an operation example of the embodiment of the trapezoidal wave generation circuit of the present invention.

図6において、台形波生成回路を構成する充放電停止機能付き充放電回路50B、負荷容量60、バッファ70および波形制御回路80C、さらに波形制御回路80Cを構成する比較回路81,82、SRラッチ83、位相比較器84、ループフィルタ85は図8に示す従来の三角波生成回路の各部と基本的な機能は同じである。   In FIG. 6, a charge / discharge circuit 50B with a charge / discharge stop function constituting a trapezoidal wave generation circuit, a load capacitor 60, a buffer 70 and a waveform control circuit 80C, and comparison circuits 81 and 82 constituting a waveform control circuit 80C, an SR latch 83 The phase comparator 84 and the loop filter 85 have the same basic functions as those of the conventional triangular wave generating circuit shown in FIG.

波形制御回路80Cの2つの比較回路81,82は、バッファ70の出力信号(台形波)と高電位Vref-H および低電位Vref-L をそれぞれ比較する。台形波がVref-H またはVref-L になったときに、比較回路81,82の出力をSRラッチ83でラッチすることにより、台形波の位相が図7(3) に示すように検出される。このSRラッチ83の出力信号は、負荷容量60の充電/放電の切替タイミングとなる充放電切替信号として充放電停止機能付き充放電回路50Bに入力する。また、充放電切替信号は、EX−NOR回路86に入力して基準クロック信号と排他的否定論理和がとられ、充放電許可信号として充放電停止機能付き充放電回路50Bに入力する。充放電停止機能付き充放電回路50Bは、充放電許可信号がオフ(図7では信号レベルがロー)になると負荷容量60に対する充電および放電を停止し、図7(2) に示すように波形が保持された状態になって台形波が生成される。   The two comparison circuits 81 and 82 of the waveform control circuit 80C compare the output signal (trapezoidal wave) of the buffer 70 with the high potential Vref-H and the low potential Vref-L, respectively. When the trapezoidal wave becomes Vref-H or Vref-L, the phase of the trapezoidal wave is detected as shown in FIG. 7 (3) by latching the outputs of the comparison circuits 81 and 82 with the SR latch 83. . The output signal of the SR latch 83 is input to the charging / discharging circuit 50B with a charging / discharging stop function as a charging / discharging switching signal which is a charging / discharging switching timing of the load capacitor 60. Further, the charge / discharge switching signal is input to the EX-NOR circuit 86, exclusive ORed with the reference clock signal, and input to the charge / discharge circuit 50B with charge / discharge stop function as a charge / discharge permission signal. The charge / discharge circuit 50B with a charge / discharge stop function stops charging and discharging the load capacitor 60 when the charge / discharge permission signal is turned off (the signal level is low in FIG. 7), and the waveform is as shown in FIG. 7 (2). A trapezoidal wave is generated in a held state.

また、SRラッチ83から出力される充放電切替信号は、遅延回路87を介して位相比較器84および試験回路の遅延回路13に入力される。位相比較器84は、遅延回路87で遅延させた充放電切替信号(台形波の位相)と基準クロック信号の位相を比較し、位相の進みや遅れに対応したパルス信号をループフィルタ85へ出力する。ループフィルタ85は、位相比較器84が出力するパルス信号を積分し、充放電停止機能付き充放電回路50Bのバイアス電圧を調整する充放電電流調整信号(アナログ電圧)を生成して充放電停止機能付き充放電回路50Bへ出力する。   The charge / discharge switching signal output from the SR latch 83 is input to the phase comparator 84 and the delay circuit 13 of the test circuit via the delay circuit 87. The phase comparator 84 compares the charge / discharge switching signal (trapezoidal wave phase) delayed by the delay circuit 87 with the phase of the reference clock signal, and outputs a pulse signal corresponding to the phase advance or delay to the loop filter 85. . The loop filter 85 integrates the pulse signal output from the phase comparator 84, generates a charge / discharge current adjustment signal (analog voltage) for adjusting the bias voltage of the charge / discharge circuit 50B with charge / discharge stop function, and performs a charge / discharge stop function. Output to the charge / discharge circuit 50B.

図11は、充放電停止機能付き充放電回路50Bの構成例を示す。
図11において、波形制御回路80Cから出力される充放電電流調整信号は基準電流発生回路51に入力され、発生する基準電流を変化させる。この基準電流が変化すると、それに応じて定電流回路52,53の電流が変化し、充放電切替信号によって開閉するスイッチ54,55を介して、負荷容量60に対する充放電電流を増減させる。また、この充放電電流は、充放電許可信号によって開閉するスイッチ56で出力がオンオフされる。これにより、出力される台形波のスルーレート(波形の傾き)および波形保持期間が変化し、最終的に基準クロック信号と台形波の周期が同じになるように制御される。
FIG. 11 shows a configuration example of a charge / discharge circuit 50B with a charge / discharge stop function.
In FIG. 11, the charge / discharge current adjustment signal output from the waveform control circuit 80C is input to the reference current generation circuit 51, and the generated reference current is changed. When the reference current changes, the currents of the constant current circuits 52 and 53 change accordingly, and the charge / discharge current for the load capacitor 60 is increased or decreased via the switches 54 and 55 that are opened and closed by the charge / discharge switching signal. The output of the charge / discharge current is turned on / off by a switch 56 that is opened / closed by a charge / discharge permission signal. As a result, the slew rate (the slope of the waveform) and the waveform holding period of the trapezoidal wave to be output are changed, and finally the period of the trapezoidal wave and the reference clock signal are controlled to be the same.

本実施形態の試験回路10Dを構成するOR回路11、パルス幅拡大回路12、遅延回路13およびDラッチ14は、図1に示す本発明の三角波生成回路の試験回路10Aと同じ構成である。すなわち、三角波生成回路の試験回路10Aと同様に、OR回路11が位相差パルス信号を出力し、パルス幅拡大回路12が図7(7) に示すように、位相差パルス信号のパルス幅を拡大して出力する。遅延回路13は、図7(5),(8) に示すように、遅延回路87で遅延させた充放電切替信号を入力し、所定の遅延を与えて出力する。Dラッチ14は、図7 (7)〜(9) に示すように、パルス幅拡大回路12から出力されるパルス幅が拡大された位相差パルス信号を、遅延回路13から出力される遅延させた充放電切替信号でラッチし、基準クロック信号の周期と台形波の周期の違いが所定の範囲にあるか否かの判定に用いるステータス信号を出力する。   The OR circuit 11, the pulse width expanding circuit 12, the delay circuit 13, and the D latch 14 that constitute the test circuit 10D of the present embodiment have the same configuration as the test circuit 10A of the triangular wave generation circuit of the present invention shown in FIG. That is, like the test circuit 10A of the triangular wave generation circuit, the OR circuit 11 outputs a phase difference pulse signal, and the pulse width expansion circuit 12 expands the pulse width of the phase difference pulse signal as shown in FIG. And output. As shown in FIGS. 7 (5) and (8), the delay circuit 13 receives the charge / discharge switching signal delayed by the delay circuit 87, gives a predetermined delay, and outputs it. As shown in FIGS. 7 (7) to (9), the D latch 14 delays the phase difference pulse signal output from the pulse width expanding circuit 12 and having the pulse width expanded from the delay circuit 13. The status signal is latched by the charge / discharge switching signal, and a status signal used for determining whether or not the difference between the period of the reference clock signal and the period of the trapezoidal wave is within a predetermined range is output.

図7(9) に示すステータス信号の例では、基準クロック信号の位相と台形波の位相にずれがあって位相差パルス信号が発生していれば、ステータス信号がハイレベルになるので位相同期中(調整中)であることがわかる。また、基準クロック信号と台形波の位相差が所定の範囲に入って位相差パルス信号の発生がなくなれば、ステータス信号がローレベルになるので位相同期完了であることがわかる。   In the example of the status signal shown in FIG. 7 (9), if the phase of the reference clock signal and the phase of the trapezoidal wave are shifted and a phase difference pulse signal is generated, the status signal becomes high level and phase synchronization is in progress. (Under adjustment) In addition, if the phase difference between the reference clock signal and the trapezoidal wave falls within a predetermined range and no phase difference pulse signal is generated, the status signal becomes low level, indicating that phase synchronization is complete.

このように、本実施形態の台形波生成回路の試験回路10Dは、三角波生成回路の試験回路10Aとまったく同様の構成で同様に動作させることができる。また、図3に示す基準クロック信号の半周期比較に対応する試験回路10Bも対応可能であり、さらに図5の位相差パルス信号のパルス幅を調整する試験回路10Cも対応可能であり、基準クロック信号と台形波の位相差について検出可能な範囲を設定可能とすることができる。   As described above, the test circuit 10D of the trapezoidal wave generation circuit according to the present embodiment can be operated in the same manner with the same configuration as the test circuit 10A of the triangular wave generation circuit. Further, the test circuit 10B corresponding to the half cycle comparison of the reference clock signal shown in FIG. 3 can also be supported, and the test circuit 10C for adjusting the pulse width of the phase difference pulse signal shown in FIG. A detectable range can be set for the phase difference between the signal and the trapezoidal wave.

以上説明したように、本発明による試験回路は、基準クロック信号と三角波または台形波の位相差に対応する位相差パルス信号を、三角波または台形波の周期に対応する充放電切替信号でラッチしてステータス信号として出力することにより、位相同期状態にあるか位相同期過程にあるかを判定することができる。また、基準クロック信号に位相同期する三角波または台形波を生成する三角波・台形波生成回路であれば、位相差パルス信号や充放電切替信号が得られるので、図1,図3,図5,図6に示すような三角波・台形波生成回路に限定されることなく、三角波または台形波の位相同期状態を判定する本発明の試験回路を適用することができる。   As described above, the test circuit according to the present invention latches the phase difference pulse signal corresponding to the phase difference between the reference clock signal and the triangular wave or trapezoidal wave with the charge / discharge switching signal corresponding to the period of the triangular wave or trapezoidal wave. By outputting as a status signal, it can be determined whether it is in a phase synchronization state or in a phase synchronization process. A triangular wave / trapezoidal wave generation circuit that generates a triangular wave or a trapezoidal wave that is phase-synchronized with the reference clock signal can obtain a phase difference pulse signal and a charge / discharge switching signal. Without being limited to the triangular wave / trapezoidal wave generating circuit as shown in FIG. 6, the test circuit of the present invention for determining the phase synchronization state of the triangular wave or trapezoidal wave can be applied.

本発明の三角波生成回路の第1の実施形態を示す図。The figure which shows 1st Embodiment of the triangular wave generation circuit of this invention. 本発明の三角波生成回路の第1の実施形態の動作例を示すタイムチャート。The time chart which shows the operation example of 1st Embodiment of the triangular wave generation circuit of this invention. 本発明の三角波生成回路の第2の実施形態を示す図。The figure which shows 2nd Embodiment of the triangular wave generation circuit of this invention. 本発明の三角波生成回路の第2の実施形態の動作例を示すタイムチャート。The time chart which shows the operation example of 2nd Embodiment of the triangular wave generation circuit of this invention. 本発明の三角波生成回路の第3の実施形態を示す図。The figure which shows 3rd Embodiment of the triangular wave generation circuit of this invention. 本発明の台形波生成回路の実施形態を示す図。The figure which shows embodiment of the trapezoidal wave generation circuit of this invention. 本発明の台形波生成回路の実施形態の動作例を示すタイムチャート。The time chart which shows the operation example of embodiment of the trapezoidal wave generation circuit of this invention. 従来の三角波生成回路の構成例を示す図。The figure which shows the structural example of the conventional triangular wave generation circuit. 従来の三角波生成回路の動作例を示すタイムチャート。The time chart which shows the operation example of the conventional triangular wave generation circuit. 充放電回路50Aの構成例を示す図。The figure which shows the structural example of 50 A of charging / discharging circuits. 充放電停止機能付き充放電回路50Bの構成例を示す図。The figure which shows the structural example of the charging / discharging circuit 50B with a charging / discharging stop function.

符号の説明Explanation of symbols

10A,10B,10C,10D 試験回路
11 OR回路
12 パルス幅拡大回路
13 遅延回路
14 Dラッチ
15 セレクタ
16 パルス幅可変回路
50A 充放電回路
50B 充放電停止機能付き充放電回路
51 基準電流発生回路
52,53 定電流回路
54,55,56 スイッチ
60 負荷容量
70 バッファ
80A,80B,80C 波形制御回路
81,82 比較回路
83 SRラッチ
84 位相比較器
85 ループフィルタ
86 EX−NOR回路
87 遅延回路
10A, 10B, 10C, 10D Test circuit 11 OR circuit 12 Pulse width expansion circuit 13 Delay circuit 14 D latch 15 Selector 16 Pulse width variable circuit 50A Charge / discharge circuit 50B Charge / discharge circuit with charge / discharge stop function 51 Reference current generation circuit 52, 53 constant current circuit 54, 55, 56 switch 60 load capacity 70 buffer 80A, 80B, 80C waveform control circuit 81, 82 comparison circuit 83 SR latch 84 phase comparator 85 loop filter 86 EX-NOR circuit 87 delay circuit

Claims (5)

充放電回路に充放電切替信号を入力して容量負荷の充電・放電を切り替えることにより、2つの異なる電位間で傾きを有する三角波または台形波を発生させるとともに、三角波または台形波の周期と基準クロック信号の周期の違いである位相差を検出し、三角波または台形波の周期と基準クロック信号の周期が同期するように制御する波形制御回路を含む三角波・台形波生成回路において、
前記波形制御回路から前記三角波または前記台形波と前記基準クロック信号の位相差に対応する位相差パルス信号を入力し、前記三角波または前記台形波を生成する前記充放電切替信号の周期で所定のパルス幅以上の位相差パルス信号をラッチし、所定の位相差内で位相同期状態にあるか否かを示すステータス信号として出力する試験回路を備えた
ことを特徴とする三角波・台形波生成回路。
A charge / discharge switching signal is input to the charge / discharge circuit to switch charge / discharge of the capacitive load, thereby generating a triangular wave or trapezoidal wave having a slope between two different potentials, and the period of the triangular wave or trapezoidal wave and the reference clock In the triangular wave / trapezoidal wave generation circuit including the waveform control circuit that detects the phase difference that is the difference in the signal cycle and controls the period of the triangular wave or trapezoidal wave and the period of the reference clock signal to be synchronized,
A phase difference pulse signal corresponding to a phase difference between the triangular wave or the trapezoidal wave and the reference clock signal is input from the waveform control circuit, and a predetermined pulse is generated at a cycle of the charge / discharge switching signal for generating the triangular wave or the trapezoidal wave. A triangular wave / trapezoidal wave generation circuit comprising a test circuit that latches a phase difference pulse signal that is equal to or greater than a width and outputs a status signal indicating whether or not a phase synchronization state is within a predetermined phase difference.
請求項1に記載の三角波・台形波生成回路において、
前記試験回路は、
前記位相差パルス信号のパルス幅を拡大するパルス幅拡大回路と、
前記充放電切替信号を遅延させる遅延回路と、
前記パルス幅拡大回路でパルス幅を拡大した前記位相差パルス信号を前記遅延回路で遅延させた前記充放電切替信号でラッチし、前記ステータス信号として出力するラッチ回路と
を備えたことを特徴とする三角波・台形波生成回路。
The triangular wave / trapezoidal wave generating circuit according to claim 1,
The test circuit is
A pulse width expansion circuit for expanding the pulse width of the phase difference pulse signal;
A delay circuit for delaying the charge / discharge switching signal;
A latch circuit that latches the phase difference pulse signal whose pulse width has been expanded by the pulse width expansion circuit with the charge / discharge switching signal delayed by the delay circuit, and outputs the latched signal as the status signal. Triangular / trapezoidal wave generator.
請求項1に記載の三角波・台形波生成回路において、
前記波形制御回路は、前記基準クロック信号の半周期ごとに前記位相差パルス信号を出力する構成であり、
前記試験回路は、
前記位相差パルス信号のパルス幅を拡大するパルス幅拡大回路と、
前記充放電切替信号を遅延させる遅延回路と、
前記パルス幅拡大回路でパルス幅を拡大した前記位相差パルス信号を、前記遅延回路で遅延させた前記充放電切替信号およびその反転信号でそれぞれラッチする2つのラッチ回路と、
前記2つのラッチ回路の出力を、前記遅延回路で遅延させた前記充放電切替信号で論理に応じて切り替え、前記ステータス信号として出力するセレクタと
を備えたことを特徴とする三角波・台形波生成回路。
The triangular wave / trapezoidal wave generating circuit according to claim 1,
The waveform control circuit is configured to output the phase difference pulse signal every half cycle of the reference clock signal,
The test circuit is
A pulse width expansion circuit for expanding the pulse width of the phase difference pulse signal;
A delay circuit for delaying the charge / discharge switching signal;
Two latch circuits for latching the phase difference pulse signal whose pulse width has been expanded by the pulse width expansion circuit with the charge / discharge switching signal delayed by the delay circuit and its inverted signal, respectively;
A triangular wave / trapezoidal wave generation circuit comprising: a selector that switches the outputs of the two latch circuits according to logic with the charge / discharge switching signal delayed by the delay circuit and outputs the status signal .
請求項2または請求項3に記載の三角波・台形波生成回路において、
前記試験回路のパルス幅拡大回路は、前記位相差パルス信号のパルス幅を可変させるパルス幅可変回路に置換し、前記三角波または前記台形波と前記基準クロック信号が位相同期状態であるか否かの基準となる前記位相差の範囲を調整する構成である
ことを特徴とする三角波・台形波生成回路。
In the triangular wave / trapezoidal wave generating circuit according to claim 2 or 3,
The pulse width expanding circuit of the test circuit is replaced with a pulse width variable circuit that varies the pulse width of the phase difference pulse signal, and whether the triangular wave or the trapezoidal wave and the reference clock signal are in a phase-synchronized state. A triangular wave / trapezoidal wave generating circuit characterized by adjusting a range of the phase difference serving as a reference.
請求項4に記載の三角波・台形波生成回路において、
前記パルス幅可変回路は、遅延量の異なる複数の遅延回路を内蔵し、遅延回路を選択して前記位相差パルス信号のパルス幅を設定する構成である
ことを特徴とする三角波・台形波生成回路。
The triangular wave / trapezoidal wave generating circuit according to claim 4,
The pulse width variable circuit includes a plurality of delay circuits having different delay amounts, and is configured to select a delay circuit and set a pulse width of the phase difference pulse signal. .
JP2008089295A 2008-03-31 2008-03-31 Triangular / trapezoidal wave generator Expired - Fee Related JP4828561B2 (en)

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