JP4827074B2 - High density SOI crosspoint memory array and method for manufacturing the same - Google Patents

Description

The present invention relates generally to integrated circuit (IC) memory manufacturing, and more particularly to high density register random access memory array structures (hereinafter abbreviated as high density memory array structures) and manufacturing processes.

Conventionally, high density memory is manufactured on bulk silicon. As is well known to those skilled in the art, there is a relatively high leakage current and capacitance associated with memory cells fabricated on bulk silicon, which reduces read and write times. However, applications for narrowing the high-density memory programming pulse width to about 10 nanoseconds (ns) are beginning to be required. It is known that silicon-on-insulator (SOI) CMOS devices have significantly higher speeds than corresponding bulk silicon devices. Therefore, an SOI substrate high-density memory is desired as a very high-speed memory circuit.

  The SOI substrate is made from a silicon (Si) layer. The silicon layer is on an insulating material, for example sapphire or oxide. The insulating layer of the SOI substrate completely separates the related NMOS and PMOS transistors and prevents the occurrence of latch-up. Furthermore, device channel doping does not need to be over-compensated and the diffusion region does not have a bottom junction. All these factors reduce parasitic resistance.

  Some have described a vertical 1-resistor / 1-diode (1R1D) structure that can be used to form a high-density memory array (Patent Document 1). This structure forms P + on the highly conductive buried N + bit line. However, the resulting P + N junction thickness is at least 500 nanometers (nm) and is not suitable for SOI processes.

FIG. 1 is a partial cross-sectional view of a double trench isolation 1R1D RAM (prior art) on a bulk silicon wafer. The shallow trench extends at least partially into the P + layer and prevents leakage current leaking from the bottom electrode. The conductivity of the N + bit line does not exceed 1 kΩ / m ² when the thickness is less than 500 nm. Therefore, in order to provide a low parasitic resistance, the minimum thickness of the SOI film needs to be on the order of 500 nm. However, the thickness of the peripheral circuit can be much thinner than the thickness of the memory region. This difference in thickness cannot be addressed by state-of-the-art lithographic tools that are too large.

As the process is developed, it is advantageous to increase the density of memory cells formed in an SOI high density memory array.

If SOI high density memory arrays can be formed, it is advantageous to take advantage of the available feature sizes.

  A vertical 1 register / 1 diode (1R1D) structure that can be used to form a high density memory array forms P + on a highly conductive buried N + bit line. However, the resulting P + N junction thickness is at least 500 nanometers (nm) and is not suitable for SOI processes.

  In the conventional double trench isolation 1R1D RAM on the bulk silicon wafer, the minimum thickness of the SOI film needs to be on the order of 500 nm in order to provide a low parasitic resistance. However, the thickness of the peripheral circuit can be much thinner than the thickness of the memory region. This difference in thickness cannot be addressed by state-of-the-art lithographic tools that are too large.

(Summary of the Invention)
The present invention describes an ultra-large scale integrated (ULSI) memory chip and a built-in memory device for a high density crosspoint register memory array. The present invention takes advantage of the features of SOI devices and forms memory cells having a size that is not limited only to the feature scale.

  Accordingly, a method for manufacturing a high density SOI cross-point memory array is provided. The method selectively forms a hard mask on an SOI substrate, defines a memory region, an active device region, and an upper electrode region, and etches to remove the exposed silicon (Si) surface. Selectively forming metal sidewalls adjacent to the hard mask; filling the memory region with a memory resistor material; removing the hard mask and exposing an overlying Si active device region Forming an overlying oxide layer; etching the oxide to form a contact hole in the active device region; forming a diode in the contact hole; and Forming a bottom electrode line overlying.

  The step of selectively forming the metal sidewall adjacent to the hard mask includes the step of isotropically depositing the metal and a sidewall having a width of 25 to 50 nm between the memory region and the active device region. Forming the sidewalls having and anisotropically etching the metal to form bottom electrode lines. The electrode lines are further formed by this process. In another aspect, selectively forming the metal sidewall adjacent to the hard mask includes forming an electrode layer from a material adjacent to the hard mask, such as Ir, Pt, Au, and Ru, and Forming a barrier layer from a material such as Ti, TiN, WN, or TaN adjacent to the electrode layer, and sandwiching the electrode layer between the barrier layer and the hard mask.

The method for producing a high-density silicon on insulator (SOI) cross point memory array of the present invention is a method for producing the silicon (SOI) cross point memory array density insulator, S OI substrate the hard mask on, and selectively formed to cover the linear region extending along a plurality of active device regions in a column of said active device region, the exposed silicon (Si) surface is etched by the active forming a memory region between the device region and the linear region, from the top of the hard mask, the region extending to the bottom of the memory area, and selectively forming a metal sidewall, and the memory area the method comprising the upper electrode lines said metal side wall between the linear region, the memory register member to be connected to the upper electrode lines on the memory area Forming a fee, and removing the hard mask, a step of exposing said active device region, forming a layer of the entire surface oxide, the layer of the oxide, reaching the active device region as the contact hole is formed, and selectively etching the oxide, a diode in the contact hole, the metal side wall between said memory region a first conductivity type region and the active device region connected to the memory area via, and, as a second conductivity type region which is connected to the forming to be stacked on the first conductive type region on, the second conductive type region on the diode Forming the bottom electrode line, thereby achieving the above objective.

In the step of selectively forming the hard mask on the SOI substrate, the hard mask may be formed of nitride or polysilicon .

Wherein said step of selectively forming the metal sidewall adjacent to the hard mask, a step of isotropically depositing a metal, a metal deposited by the step of depositing said metal isotropically, and the memory area the boundary position between the active device region, so that remains as a metallic border, may include a step of anisotropically etching.

An isotropically thickness 50-100 nanometer Le metals deposited in the step of depositing the metal, in the step of etching the anisotropically, forming the metal sidewall ranging from 25 to 50 nanometers Step may be included.

The step of etching the anisotropically may be met plasma etch process.

Said metal side wall adjacent to the hard mask, the electrode layer adjacent to the hard mask, the electrode layer, and the hard mask in contact though not better barrier formed on the opposite faces of the layer, two layers of It may be a structure.

The barrier layer, Ti, TiN, WN, or may be formed of any material of TaN.

The electrode layer may be made of any material of Ir, Pt, Au , and Ru .

In the above method, the step of forming the memory resistor material includes depositing a layer of oxide, and planarizing by chemical mechanical polishing (CMP) a layer of said oxide to said hard mask is exposed, and etching the layer of oxide from the memory area, and depositing the memory resistor material over the height of the metal sidewall, until the hard mask is exposed, planarizing the memory resistor material by CMP And may include the steps of:

In the above method, the step of depositing the memory resistor material is spin coating, sputtering, may be used either metallic organic chemical vapor deposition (MOCVD) process.

In the above method, wherein the memory resistor material is, PCMO, colossal magnetoresistance (CMR), may be met either of the material of the Atsushi Ko superconducting (HTSC).

In the above method, and removing the hard mask, the step of exposing said active device region, so that the active device region and the linear region of the lower side of the hard mask is exposed, removing the hard mask by etching the method comprising the steps of masking the active device areas in the photoresist, and etching to remove the silicon layer of the SOI substrate other than the previous SL active device region may encompass.

Selectively forming the hard mask on the SOI substrate, it includes the steps of forming the active device region of 1F ² geometry, etching said oxide to form a contact hole in the active device region step comprises the steps of forming the contact hole by using the 1F ² geometry etching techniques to overlie the center of said active device region, therefore the step of forming the contact holes, adjacent to said active device region and the Exposing the metal sidewalls.

In the above method, the step of forming a diode in the contact hole may be met forming a diode between said bottom electrode line memory area.

In the above method, the step of forming a diode between said bottom electrode line memory area forms a step of forming a Si layer by epitaxial growth in the contact holes, the deep N + first conductivity type region via injection steps and shallow P ++ by the steps of forming said second conductivity type region by implantation, the epitaxial-grown Si layer P ++ / N + junction diode between the metal side wall and the bottom electrode lines as word lines It may be a step of forming.

Keep the method, the step of forming a diode between said bottom electrode lines the memory region, forming a polysilicon layer in contact with the metal side wall in the contact hole, at least the contact hole is filled forming and depositing the Si in so that solid-phase epitaxial growth process, planarizing the Si to the oxide was deposited at the solid-phase epitaxial growth process to expose at CMP, a deep N + first conductivity type region via injection the method comprising the steps of forming said second conductivity type region by a shallow P ++ injection, by the Oite P ++ / N + junction between the polysilicon layer that is in contact with the metal side walls and the bottom electrode lines as word lines It may be a step of forming a diode .

In the above method, the step of forming a diode between said bottom electrode line memory area forms a step of forming a Si layer by epitaxial growth in the contact holes, a deep P + first conductivity type region via injection steps and shallow N ++ by the steps of forming said second conductivity type region by implantation, the epitaxial-grown Si layer N ++ / P + junction diode between the metal side wall and the bottom electrode lines as bit lines It may be a step of forming.

In the above method, the step of forming a diode between said bottom electrode lines the memory region, forming a polysilicon layer in contact with the metal side wall in the contact hole, at least the contact hole is filled depositing a Si with Yo solid phase epitaxial growth process to form planarizing the Si to the oxide was deposited at the solid-phase epitaxial growth process to expose at CMP, a deep P + first conductivity type region via injection steps and shallow N ++ by the steps of forming said second conductivity type region by injection, the Oite N ++ / P + junction between the polysilicon layer that is in contact with the metal side walls and the bottom electrode lines as bit lines diode It may be a step of forming.

Forming a diode between said bottom electrode lines the active device region may comprise the step of forming a single diode interposed between the bottom electrode lines and a plurality of memory areas.

Step is connected to the metal side wall being formed on opposite sides of the set the memory area adjacent to form a single diode interposed between the bottom electrode lines and a plurality of said memory areas A step of forming a diode may be included.

Array of the present invention, a high-density silicon on insulator (SOI) substrate, a cross-point memory array having arranged a plurality of memory regions to be located at the intersection of the bit line and word line, said array, and the SOI substrate, and the memory register portion formed on a memory area which faces on the SOI substrate, an active device region located between the memory area for the phase opposite on the SOI substrate, the active A device region comprising: upper and lower semiconductor layers having different conductivity types stacked so as to form a diode; and a metal side wall formed on a side surface of the memory register unit, the memory region and the metal side wall comprising an oxide passivation layer formed to cover them up, and a bottom electrode line formed on the oxide passivation layer, the metal Wall portion located at the boundary between the memory register and the lower semiconductor layer of the semiconductor layer of the second layer constitutes a metal border, the diode, the semiconductor layer of the lower side of the metal The memory register unit is connected to the memory register unit via a boundary line, and the upper semiconductor layer of the two semiconductor layers is connected to the bottom electrode line. The portion located on the side surface opposite to the lower semiconductor layer constitutes an upper electrode line connected to the memory register portion , thereby achieving the above object.

The metal side walls, a range may have a width of 25-50 nm.

The metal side wall may have a two-layer structure of an electrode layer located on the memory register portion side and a barrier layer located on the opposite side of the memory register portion .

  The barrier layer may be a metal selected from the group consisting of Ti, TiN, WN, and TaN.

  The electrode layer may be a metal selected from the group consisting of Ir, Pt, Au, and Ru.

The material of the memory register unit may be a material selected from the group consisting of PCMO, giant magnetoresistance (CMR), and high temperature superconducting (HTSC) material.

The active device region has a 1 F ² geometry;
The diode has a 1F ² geometry, may be connected to at least one of the gold Shokusakai boundary lines.

Before Kikatsu of device regions may be surrounded by the metal sidewall.

Before Kida diode via the metal border adjacent, it may be operatively connected to the memory register.

Before Kida diode includes a P ++ / N + junction, the bottom electrode line is a word line, the upper electrode lines may be bit lines.

Before Kida diode includes N ++ / P + junction, the bottom electrode line is a bit line, the upper electrode lines may be word lines.

Before Kida diode may be connected between the bottom electrode lines and a plurality of said memory areas.

The diode may be connected to a pair of the metal boundary line of the memory area adjacent.

The memory area may be formed in a 4F ² geometry square.

  Further details of the above described method and high density SOI cross-point memory array are described below.

It is possible to increase the density of memory cells formed in an SOI high density memory array, and if the SOI high density memory array can be formed, the smallest available shape can be successfully utilized.

FIG. 2 is a partial cross-sectional view of a high-density SOI cross-point memory array of the present invention. The array 200 includes an SOI substrate 202 that includes an insulating layer 204. As shown, most of the Si of the SOI substrate 202 shown has been etched away. The etched region of the memory and the etched region of the upper electrode are formed on the SOI substrate 202 (below the broken line) and extend to the insulating layer 204. The memory register metal 222 overlies the etched area of the memory to form the memory area 206/208/210/212. The memory resistor material 222 can be, for example, a material such as Pr _0.3 Ca _0.7 MnO ₃ (PCMO), giant magnetoresistance (CMR), or high temperature superconducting (HTSC) material.

  The SOI active layer Si active device region 224 is adjacent to the memory regions 206 and 208, and the active device region 226 is adjacent to the memory regions 210 and 212. There is a metal sidewall boundary 228 between the memory region 206 and the active device region 224. There is a metal sidewall boundary 230 between the memory region 208 and the active device region 224. There is a metal sidewall boundary 232 between the memory region 210 and the active device region 226. There is a metal sidewall boundary 234 between the memory region 212 and the active device region 226. In addition, metal sidewall upper electrode lines 214, 216, 218, and 220 are shown.

  The oxide passivation layer 244 overlies the memory region 206/208/210/212 and the upper electrode line 214/216/218/220. The bottom electrode line overlies the oxide passivation layer 244. A bottom electrode line 246 is illustrated. The diode 248 is connected between the bottom electrode line 246 and the metal sidewall boundary lines 228 and 230. The diode 249 is connected between the bottom electrode line 246 and the metal sidewall boundary lines 232 and 234.

  FIG. 3 is a detailed view of a partial cross section of the memory area 206, and the memory area 206 is a representative memory area. In some aspects, as represented by the top electrode 214, the metal sidewall boundary (228/230/232/234, see FIG. 2) and the metal sidewall top electrode line (214/216/218/220) are It has a width 300 in the range of 25-50 nanometers.

  In other aspects, the metal sidewall top electrode as represented by the metal sidewall boundary and the top electrode line 214 includes a barrier layer 302 and an electrode layer 304. The barrier layer 302 overlaps the electrode layer 304 in the horizontal direction. Alternatively, the barrier layer 302 is sandwiched between the electrode layer 304 and the memory region 206. In general, the electrode layer 304 is formed adjacent to the hard mask (described in detail below), and the barrier layer 302 is formed thereafter. The barrier layer 302 can be a material such as Ti, TiN, WN, or TaN, for example. The electrode layer 304 may be a material such as Ir, Pt, Au, or Ru, for example. Note that the metal sidewall boundary 228 can also be formed from a barrier layer 302 sandwiched between the electrode layer 304 and the memory region 206.

The active device region as represented by the active device region 224 has a 1F ² geometry. As shown, the active device region 224 has a width 306 equal to F. Here, F is the minimum shape. The active device region 224 also has a length of F and extends to “in paper” which cannot be shown in this figure. Similarly, a diode as represented by diode 248 has a 1F ² geometry and connects to the metal sidewall boundary. Diode 248 is illustrated as being connected to sidewall boundaries 228 and 230. Diode 248 is operatively connected to memory region 206 via metal sidewall boundary 228 and operably connected to memory region 208 via metal sidewall boundary 230. As used herein, “operably connected” means indirectly connected or connected via an intervening element.

FIG. 4 is a plan view of the active device region 224 of FIG. This figure shows that each active device region, as represented by active device region 224, is surrounded by a metal sidewall boundary. Metal sidewall boundaries 228, 230, 400, and 402 are illustrated. As will be explained in the manufacturing process below, the four boundaries are actually formed as a single element. The active device region 224 is formed in a 1F ² geometry square. Here, the length 404 is equal to the width 306. Memory area or memory cell areas such memory region 206 may be formed on the 4F ² geometry square.

  Returning to FIG. 2, each diode includes a P ++ / N + junction. Diode 248 includes a P ++ region 250 and an N + region 252. Similarly, diode 249 includes a P ++ region 254 and an N + region 256. Therefore, the bottom electrode 246 is a word line, and the top electrode line 214/216/218/220 is a bit line. Alternatively, the bottom electrode line 246 is a bit line and the top electrode line 214/216/218/220 is a word line. Alternatively, although not shown, each diode may be formed with an N ++ / P + junction. FIG. 5 is a schematic diagram of the array structure of the present invention. Although 6 bits (B) × 4 words (W) are clearly illustrated, in other aspects the word lines and bit lines may be interchanged. The designation of either the word line or the bit line depends on the voltage polarity applied to the finished device during operation. Considering both FIG. 2 and FIG. 5, each diode is connected between the bottom electrode line and a plurality of memory regions. More specifically, each diode is connected to a metal sidewall boundary of a set of adjacent memory regions. For example, diode 248 is connected to adjacent memory regions 206 (R5) and 208 (R6).

(Functional description)
A cross-sectional view of the SOI 1R1D high density memory structure of the present invention is shown in FIG. Although a common word line is shown, a common bit line configuration is equally practical. The bit line is formed of a sidewall metal line that overlies the SOI insulator. The bit line also functions as the upper electrode of the memory cell of the high density memory . The top electrode of the memory register is also a sidewall metal line on the insulator. Two adjacent register memory cells are connected to the SOI P + layer and then connected to the word line through a shallow N + junction. Cell size can be equivalently reduced and 4F ^2.

  FIG. 6 is a plan view of an initial etching step of the SOI substrate. A layer of hard mask 600 of either silicon nitride or polysilicon is deposited on SOI wafer 602. The thickness of the SOI film is not critical. The photoresist is used to etch the hard mask and SOI film, as shown.

FIG. 7 is a plan view after formation of the upper electrode and surrounding sidewalls. A high density memory metal electrode material is deposited on the film and anisotropically (plasma) etched. In some aspects, a barrier layer such as Ti, TiN, WN, or TaN is required. The electrode metal can be, for example, Pt or Ir.

  FIG. 8 is a plan view after the oxide deposition process. The layer of oxide 800 is deposited at least 1.5 times thicker than the total thickness of the SOI film and the hard mask 600. After deposition, the oxide is planarized by a CMP process.

  FIG. 9 is a partial cross-sectional view of FIG. This figure shows a Si layer 900 of an SOI substrate protected by an overlying hard mask 600.

  FIG. 10 is a cross-sectional view of FIG. 9 after oxide removal in selected (memory) regions. The photoresist is used as a mask.

  FIG. 11 is a top view of the array of FIG. 10 after the deposition of memory register material 1100. FIG. The memory resistor material can be deposited by spin coating, sputtering, or MOCVD processes.

  FIG. 12 is a partial cross-sectional view of FIG. 11 after the CMP process of the memory resistor material.

  FIG. 13 is a plan view of FIG. 12 after removing the hard mask. The hard mask is removed by any state-of-the-art process such as, for example, wet etching to remove the nitride hard mask or dry etching to remove the polysilicon hard mask. The SOI silicon is removed along the bit lines using a photoresist mask.

  14 is a partial cross-sectional view of FIG.

  FIG. 15 is a partial cross-sectional view after the oxide deposition step. A layer of passivation silicon oxide 1500 is deposited and a CMP process is performed.

FIG. 16 is a partial cross-sectional view after the contact hole etching process. The bit contact is arranged at the center of the square as shown. For minimum geometry layout, this rectangle is 1F ^2. As a result, the bit contact hole overlaps the metal boundary line 700.

  FIG. 17 is a partial cross-sectional view after forming the diode. After the bit contact hole is opened, a layer of silicon is grown epitaxially (selectively) in the bit contact hole, followed by a deep N + implant 1700 and a shallow P ++ implant 1702 to form a P ++ / N + junction. The P ++ / N + depleted region does not contact the metal sidewall boundary. Alternatively, the selective epitaxial growth process may be replaced with a polysilicon deposition and SPE process. The SPE (solid phase epitaxial) growth process includes an annealing process at a temperature of 450 ° C. to 600 ° C. for 30 minutes to 2 hours. The polysilicon is then etched or CMP planarized, followed by a deep N + implant and a shallow P ++ implant.

  An interconnect metal is then deposited, resulting in the structure of FIG. Although the bottom electrode has been described as a word line and the sidewall top electrode as a bit line, the bottom electrode and the top electrode can be a bit line or a word line, respectively, in other aspects of the invention. In any case, for positive voltage operation, it is also preferred to place the polarity of the N ++ / P + junction at the P ++ / N + junction.

  FIG. 18 is a flow chart diagram of the method of the present invention for manufacturing a high density SOI cross-point memory array. This method is described as a sequence of numbered steps for clarity, but the order should not be inferred from the numbering unless explicitly presented. It will be appreciated that some of these steps may be skipped or performed without the need to maintain a strict sequence order. The method starts at step 1800.

  Step 1802 selectively forms a hard mask on the SOI substrate to define a memory region, an active device region, and an upper electrode line. Step 1804 etches to remove the exposed silicon (Si) surface. Step 1806 selectively forms metal sidewalls adjacent to the hard mask. Step 1808 fills the memory area with memory register material. Step 1810 removes the hard mask and exposes the overlying Si active device region. Step 1812 forms an overlying oxide layer. Step 1814 etches the oxide to form contact holes in the active device region. Step 1816 forms a diode in the contact hole. Step 1818 forms a bottom electrode line overlying the diode. Step 1820 forms a bottom electrode / top electrode memory array.

  In some aspects of the method, selectively forming a hard mask on the SOI substrate in step 1802 includes forming the hard mask from materials such as, for example, nitride and polysilicon.

  In other aspects, selectively forming metal sidewalls adjacent to the hard mask in step 1806 includes substeps (not shown). Step 1806a deposits the metal isotropically. Step 1806b etches the metal anisotropically to form sidewalls and top electrode lines between the memory region and the active device region. In some aspects, step 1806b uses a plasma etch process.

  In one aspect, the step of isotropically depositing metal in step 1806a includes isotropically depositing a metal thickness in the range of 50 to 100 nanometers (nm). The step of anisotropically etching the metal in step 1806b includes forming a metal sidewall and a top electrode line having a sidewall width in the range of 25-50 nm.

  In other aspects, selectively forming metal sidewalls adjacent to the hard mask in step 1806 includes alternative sub-steps (not shown). Step 1806c forms an electrode layer adjacent to the hard mask. Step 1806d forms a barrier layer overlapping the electrode layer in the horizontal direction. Alternatively, Step 1806d sandwiches the electrode layer between the barrier layer and the hard mask. In some aspects, step 1806c forms a barrier layer from a metal such as, for example, Ti, TiN, WN, or TaN. Step 1806d may include forming an electrode layer from a metal such as Ir, Pt, Au, or Ru.

  In some aspects, filling the memory area in step 1808 with memory register material includes substeps (not shown). Step 1808a deposits an oxide layer isotropically. Step 1808b CMP planarizes the oxide to the hard mask level. Step 1808c etches oxide from the memory region. Step 1808d deposits memory register material isotropically. Step 1808e CMP planarizes the memory register material to the hard mask level. Step 1808d may include the step of isotropically depositing the memory resistor material, for example by a process such as spin coating, sputtering, or a metal organic chemical vapor deposition (MOCVD) process. In some aspects, step 1808 fills the memory region with a memory resistor material, such as, for example, a PCMO, giant magnetoresistance (CMR), or high temperature superconducting (HTSC) material.

  In some aspects, removing the hard mask in step 1810 includes substeps (not shown). Step 1810a etches to remove all the hard mask, exposing the overlying Si. Step 1810b masks the Si active device region with photoresist. Step 1810c etches to remove exposed Si between adjacent upper electrode lines.

In some aspects, selectively forming a hard mask on the SOI substrate in step 1802 includes forming a 1F ² geometry active device region. Similarly, the step of etching the oxide to form contact holes in the active device region in step 1814 includes substeps (not shown). Step 1814a forms a contact hole overlying the center of the active device region. Step 1814b forms a contact hole using a 1F ² geometry etch technique. Step 1814c exposes the metal sidewall adjacent to the active device region in response to the formation of the contact hole.

  Forming the diode in the contact hole in step 1816 typically includes forming a diode between the bottom electrode line and the memory region in a series of sub-steps (not shown). Step 1816a epitaxially grows Si in the contact hole. Step 1816b performs a deep N + implant. Step 1816c performs a shallow P ++ implant. In response to this implantation, step 1816d forms a P ++ / N + junction in the Si between the bottom electrode word line and the metal electrode sidewall adjacent to the memory region. Alternatively, Step 1816b performs a deep P ++ implant and Step 1816c performs a shallow N ++ implant. Step 1816d then forms an N ++ / P + junction in Si between the bottom electrode bit line and the metal electrode sidewall adjacent to the memory region.

  In other aspects, different substeps (not shown) may be performed. Step 1816e isotropically deposits polysilicon. Step 1816f performs a solid phase epitaxial growth process. Step 1816g CMP planarizes the Si to the oxide level. Step 1816h performs a deep N + implant. Step 1816i performs a shallow P ++ implant. In response to the implantation, step 1816j forms a P ++ / N + junction in Si between the bottom electrode word line and the metal electrode sidewall adjacent to the memory region. Alternatively, step 1816h performs a deep P ++ implant and step 1816i performs a shallow N ++ implant. Step 1816j then forms an N ++ / P + junction in Si between the bottom electrode bit line and the metal electrode sidewall adjacent to the memory region.

  In other aspects, the step of forming a diode between the bottom electrode line and the active electrode device region in step 1816 includes the step of forming a diode between the bottom electrode line and the plurality of memory regions via a single intervening diode. Forming a step. In one example, the diode is connected to the metal sidewall boundary of a set of adjacent memory regions.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  A method is provided for fabricating a high density silicon on insulator (SOI) cross-point memory array. The method selectively forms a hard mask on an SOI substrate, defines a memory region, an active device region, and an upper electrode region, and etches to remove the exposed silicon (Si) surface. Selectively forming metal sidewalls adjacent to the hard mask; filling the memory region with a memory resistor material; removing the hard mask and exposing an overlying Si active device region Forming an overlying oxide layer; etching the oxide to form a contact hole in the active device region; forming a diode in the contact hole; and Forming a bottom electrode line overlying.

FIG. 1 is a partial cross-sectional view of a double trench isolation 1R1D RAM (prior art) on a bulk silicon wafer. FIG. 2 is a partial cross-sectional view of the high density SOI cross-point memory array of the present invention. FIG. 3 is a detailed view of a partial cross section of the memory array, which is a typical memory array. FIG. 4 is a plan view of the active device of FIG. FIG. 5 is a schematic diagram of the array structure of the present invention. FIG. 6 is a plan view of an initial etching step of the SOI substrate. FIG. 7 is a plan view after formation of the upper electrode and surrounding sidewalls. FIG. 8 is a plan view after the oxide deposition process. FIG. 9 is a partial cross-sectional view of FIG. FIG. 10 is a cross-sectional view after removal of oxide in a selected (memory) region. FIG. 11 is a plan view of the array of FIG. 10 after deposition of the memory register material. 12 is a partial cross-sectional view of FIG. 11 after the CMP process of the memory resistor material. FIG. 13 is a plan view of FIG. 12 after removal of the hard mask. 14 is a partial cross-sectional view of FIG. FIG. 15 is a partial cross-sectional view after the oxide deposition step. FIG. 16 is a partial cross-sectional view after the contact hole etching process. FIG. 17 is a partial cross-sectional view after formation of the diode. FIG. 18 is a flow chart illustrating the method of the present invention for manufacturing a high density SOI cross-point memory array.

Explanation of symbols

200 Array 202 SOI substrate 206 Memory region 214 Metal sidewall top electrode line 244 Oxide passivation layer 246 Bottom electrode line 248 Diode 600 Hard mask 700 Metal boundary 800 Oxide 900 SOI substrate Si layer 1100 Memory register material 1500 Passivation silicon oxide

Claims (34)

A method for fabricating a high density insulator-on-silicon (SOI) cross-point memory array comprising:
Selectively forming a hard mask on the SOI substrate so as to cover a plurality of active device regions and linear regions extending along a row of the active device regions;
Etching the exposed silicon (Si) surface to form a memory region between the active device region and the linear region;
Selectively forming a metal sidewall in a region extending from an upper end of the hard mask to a bottom of the memory region, and using the metal sidewall between the memory region and the linear region as an upper electrode line; ,
Forming a memory register material on the memory region to be connected to the upper electrode line;
Removing the hard mask to expose the active device region;
Forming an oxide layer over the entire surface;
Selectively etching the oxide such that contact holes reaching the active device region are formed in the oxide layer;
A diode is connected in the contact hole, a first conductivity type region is connected to the memory region via the metal sidewall between the active device region and the memory region, and a second conductivity type region is the first conductivity type. Forming to be stacked on the conductive type region;
Forming a bottom electrode line on the diode to be connected to its second conductivity type region.   The method of claim 1, wherein in the step of selectively forming the hard mask on the SOI substrate, the hard mask is formed of nitride or polysilicon. Selectively forming the metal sidewalls adjacent to the hard mask;
Depositing the metal isotropically;
And anisotropically etching the metal deposited by the step of isotropically depositing the metal so as to remain as a metal boundary line at a boundary position between the memory region and the active device region. Item 2. The method according to Item 1. The deposited metal in the step of isotropically depositing the metal has a thickness of 50 to 100 nanometers;
The method of claim 3, comprising forming the metal sidewall in the range of 25-50 nanometers in the anisotropic etching step.   The method of claim 3, wherein the anisotropically etching step is a plasma etching process. The metal sidewall adjacent to the hard mask is
An electrode layer adjacent to the hard mask;
A barrier layer formed on a surface of the electrode layer facing a side not in contact with the hard mask;
The method according to claim 1, which has a two-layer structure.   The method according to claim 6, wherein the barrier layer is formed of any one of Ti, TiN, WN, and TaN.   The method according to claim 6, wherein the electrode layer is made of any one of Ir, Pt, Au, and Ru. The method of claim 1, comprising:
Forming the memory register material comprises:
Depositing a layer of oxide;
Planarizing the oxide layer by chemical mechanical polishing (CMP) until the hard mask is exposed;
Etching the oxide layer from the memory region;
Depositing the memory resistor material above the metal sidewall height;
Planarizing the memory resistor material by CMP until the hard mask is exposed;
Including the method. The method of claim 9, comprising:
Depositing the memory register material comprises:
A method using any of spin coating, sputtering, metal organic chemical vapor deposition (MOCVD) processes. The method of claim 1, comprising:
The memory register material is
A method which is any material of PCMO, super giant magnetoresistance (CMR), high temperature superconductivity (HTSC). The method of claim 1, comprising:
Removing the hard mask to expose the active device region comprises:
Removing the hard mask by etching so that the active device region and the linear region under the hard mask are exposed; and
Masking the active device region with photoresist;
Etching to remove the silicon layer of the SOI substrate other than the active device region;
Including the method. Selectively forming the hard mask on an SOI substrate includes forming the active device region of 1F ² geometry;
Etching the oxide to form a contact hole in the active device region comprises:
Forming the contact hole using a 1F ² geometry etching technique overlying the center of the active device region;
The method of claim 1, comprising exposing the metal sidewall adjacent to the active device region by forming the contact hole. The method of claim 1, comprising:
Forming the diode in the contact hole is forming a diode between the bottom electrode line and the memory region. 15. A method according to claim 14, comprising
Forming a diode between the bottom electrode line and the memory region;
Forming a Si layer by epitaxial growth in the contact hole;
Forming the first conductivity type region by deep N + implantation;
Forming the second conductivity type region by shallow P ++ implantation;
Forming a P ++ / N + junction diode in the epitaxially grown Si layer between the bottom electrode line as a word line and the metal sidewall. 15. A method according to claim 14, comprising
Forming a diode between the bottom electrode line and the memory region;
Forming a polysilicon layer in contact with the metal sidewall in the contact hole;
Depositing Si by a solid phase epitaxial growth process so that at least the contact hole is filled;
Planarizing the Si deposited by solid phase epitaxial growth process with CMP until the oxide is exposed;
Forming the first conductivity type region by deep N + implantation;
Forming the second conductivity type region by shallow P ++ implantation;
To form a P ++ / N + junction diode between the bottom electrode line as a word line and a polysilicon layer in contact with the metal sidewall. 15. A method according to claim 14, comprising
Forming a diode between the bottom electrode line and the memory region;
Forming a Si layer by epitaxial growth in the contact hole;
Forming the first conductivity type region by deep P + implantation;
Forming the second conductivity type region by shallow N ++ implantation;
Forming a N ++ / P + junction diode in the epitaxially grown Si layer between the bottom electrode line as a bit line and the metal sidewall. 15. A method according to claim 14, comprising
Forming a diode between the bottom electrode line and the memory region;
Forming a polysilicon layer in contact with the metal sidewall in the contact hole;
Depositing Si by a solid phase epitaxial growth process so that at least the contact hole is filled;
Planarizing the Si deposited by solid phase epitaxial growth process with CMP until the oxide is exposed;
Forming the first conductivity type region by deep P + implantation;
Forming the second conductivity type region by shallow N ++ implantation;
Forming a diode with an N ++ / P + junction between the bottom electrode line as a bit line and a polysilicon layer in contact with the metal side wall.   15. The step of forming a diode between the bottom electrode line and the active device region includes forming a single diode interposed between the bottom electrode line and a plurality of memory regions. The method described in 1.   The step of forming a single diode interposed between the bottom electrode line and the plurality of memory regions is connected to the metal sidewalls formed on opposing side surfaces of a pair of adjacent memory regions. 20. The method of claim 19, comprising forming a diode. A cross-point memory array having a plurality of memory regions arranged to be located at intersections between bit lines and word lines on a high density insulator-on-silicon (SOI) substrate, the array comprising:
An SOI substrate;
A memory register unit formed on opposing memory regions on the SOI substrate;
An active device region located between the opposing memory regions on the SOI substrate;
Two upper and lower semiconductor layers having different conductivity types, stacked on the active device region so as to form a diode;
A metal side wall formed on a side surface of the memory register unit,
An oxide passivation layer formed on and over the memory region and the metal sidewall;
A bottom electrode line formed on the oxide passivation layer,
The portion of the metal sidewall located at the boundary between the lower semiconductor layer of the two semiconductor layers and the memory register portion constitutes a metal boundary line,
The diode is configured such that the lower semiconductor layer is connected to the memory register portion via the metal boundary line, and an upper semiconductor layer of the two semiconductor layers is connected to the bottom electrode line. Has been
An array in which a portion of the metal side wall located on a side surface of the memory register portion opposite to the lower semiconductor layer constitutes an upper electrode line connected to the memory register portion. The array of claim 21 , wherein the metal sidewalls have a width in the range of 25-50 nanometers. The metal sidewall is
An electrode layer located on the memory register section side;
Having a two-layer structure with a barrier layer located on the opposite side of the memory register portion;
The array of claim 21 . 24. The array of claim 23 , wherein the barrier layer is a metal selected from the group consisting of Ti, TiN, WN, and TaN. 24. The array of claim 23 , wherein the electrode layer is a metal selected from the group consisting of Ir, Pt, Au, and Ru. 23. The array of claim 21 , wherein the material of the memory register portion is a material selected from the group consisting of PCMO, giant magnetoresistance (CMR), and high temperature superconducting (HTSC) material. The active device region has a 1F ² geometry;
The array of claim 21 , wherein the diode has a 1F ² geometry and is connected to at least one of the metal boundaries. The array of claim 21 , wherein the active device region is surrounded by the metal sidewall. The array of claim 21 , wherein the diode is operatively connected to the memory register portion via the adjacent metal boundary. The diode includes a P ++ / N + junction;
The bottom electrode line is a word line;
30. The array of claim 29 , wherein the upper electrode line is a bit line. The diode includes an N ++ / P + junction;
The bottom electrode line is a bit line;
30. The array of claim 29 , wherein the upper electrode line is a word line. 30. The array of claim 29 , wherein the diode is connected between the bottom electrode line and a plurality of the memory regions. 33. The array of claim 32 , wherein the diode is connected to the metal boundary of a set of adjacent memory regions. The array of claim 21 , wherein the memory area is formed in a 4F ² geometry square.

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