JP4824785B2 - Core size estimation method, chip size estimation method and design apparatus - Google Patents

Description

The present invention, core size estimation method for efficiently performing a semiconductor integrated circuit design, it relates Chi Ppusaizu estimation method and design apparatus.
In recent years, semiconductor integrated circuits (LSIs) have been increased in scale, increased in power consumption, and increased in number of pins, and accordingly, the design period has been increasing. In order to shorten the design period, it is important how to reduce the number of rework steps in the design flow, and this requires that an optimum design be performed at an initial stage before entering the layout design.

  In designing an LSI, a floor plan is made based on a net list obtained by logic synthesis, cell placement / wiring (layout) is performed based on the floor plan, and then circuit simulation is performed on the layout to verify operation. . Based on this verification, it is determined whether or not the chip layout can guarantee signal and power supply reliability (SI: Signal Integrity / PI: Power Integrity).

  Whether the SI or PI can be guaranteed is determined based on whether or not the IR drop value in the internal circuit of the device (hereinafter referred to as “core part”) exceeds an allowable value, or an input / output buffer (hereinafter referred to as “IO buffer”). ) By determining whether or not the current value flowing in () exceeds the allowable value. If the result of these determinations is NG, it is necessary to redesign the layout.

Japanese Patent Laid-Open No. 11-297840 JP-A-10-294380

  By the way, the rework of the design flow by the redesign as described above becomes a factor of extending the design period and increasing the design cost. Therefore, it is important to optimize the design at the initial stage before layout and reduce the rework process of the design flow.

  The cause of the IR drop value exceeding the allowable value (hereinafter referred to as “allowable IR drop value”) or the reason why the current value flowing through the IO buffer exceeds the allowable value (hereinafter referred to as “allowable current value”) There is a problem that the position is not accurately estimated.

Conventionally, estimation of the number and position of such power supply pads has been performed using the following method, for example.
(1) As a method for estimating the number of power supply pads, the number of power supply pads necessary for reducing the simultaneous switching noise of the output buffer is obtained by making a rule in advance based on past experience, and the number of power supply pads is determined according to the rule. decide.

  (2) As a method for estimating the position of the power supply pad, power supply pads are arranged at both ends of the signal pad connected to the clock buffer in order to reduce power supply noise in the clock buffer.

  Conventionally, the number and position of power supply pads are estimated based on past experience mainly from the viewpoint of noise countermeasures. However, with such an estimation method, the IR drop value that can guarantee the SI and PI and the current value of the IO buffer cannot be satisfied by a single layout, and as a result, redesign is often required.

  In this way, if the layout is performed without properly estimating the number and position of the power supply pads and it is necessary to change them in the subsequent verification, it cannot be solved by simply adding the number of pads or changing the arrangement. In some cases, it was necessary to reselect the package or change the chip size.

  Another factor that causes rework of the design flow is that the chip size (specifically, the core size) is not accurately estimated before layout. Conventionally, as an area prediction method for estimating the core size, there are techniques disclosed in Patent Document 1 and Patent Document 2, for example.

  However, in the method disclosed in Patent Document 1, in the process of estimating the wiring length of the core portion, the net list factor that affects the value of the wiring length is not taken into account, and therefore the core size cannot be accurately estimated. There is.

  In addition, in the method disclosed in Patent Document 2, since the wiring area necessary around the circuit block is derived based on the arrangement of the circuit block, when there are a large number of circuit blocks, each circuit block is optimal. It is necessary to determine the correct arrangement. Therefore, it is difficult to accurately predict the core size.

The present invention has been made in view of the problems as described above, and its purpose is to reduce the rework process in the design flow, shorten the design period, and thus reduce the design cost. core size estimation method is to provide a switch Ppusaizu estimate method and design apparatus.

According to the present invention, there is provided a core size estimation method for a semiconductor integrated circuit by a design apparatus, wherein the processing executed by the design apparatus is performed by a central processing unit provided in the design apparatus by circuit information and layout stored in a storage device. A process for calculating a total wiring length of wirings formed in an internal circuit of the semiconductor integrated circuit based on a condition as a total net length, the central processing unit, the circuit information stored in the storage device and the circuit information A process of calculating a usable channel length based on layout conditions, and the central processing unit, wherein the total net length is equal to or smaller than the usable channel length and the horizontal wiring direction along the wiring layer of the internal circuit the total net length is the available channel length or less and the wiring direction perpendicular direction perpendicular to the horizontal direction to a direction along the wiring layers of said internal circuit Regarding the total net length is the available channel length below, the area of the internal circuit calculates when made, it was to have a process for estimating the area as core size. According to this method, the core size is reduced before layout by comparing the total net length of the internal circuit and the usable channel length while taking into account the components in the horizontal and vertical wiring directions. It can be estimated accurately and with a minimum area.

According to the present invention, the process of calculating the total net length, the central processing unit, a first processing for obtaining an average value of the path length definitive in each net average path length, said central processing unit, wherein Calculating a total net length based on the average path length and the fanout of each net, and calculating a total sum of the calculated total net lengths, and wiring directions in the horizontal direction and the vertical direction The total net length is calculated based on the calculation result of the second process and the coefficient corresponding to the aspect ratio of the circuit block. According to this method, it is possible to estimate the core size accurately and with the minimum area before layout in consideration of the fan-out of each net formed in the core portion.

According to the present invention, the process for calculating the usable channel length, the central processing unit, a first processing for provisionally estimating the area of the internal circuit, the central processing unit, the temporary estimate the internal circuit Second channel length for each wiring layer is calculated based on the wiring-prohibited channel length and the maximum channel usage rate, and a total sum of usable channel lengths for each wiring layer is calculated. The usable channel length in the horizontal and vertical wiring directions is obtained by adding up the usable channel lengths of the wiring layers having the same wiring direction. According to this method, the available channel length for each wiring layer is calculated based on the wiring-prohibited channel length and the maximum channel usage rate with respect to the temporarily estimated core area. The usable channel length can be accurately estimated. As a result, the core size can be estimated accurately and with a minimum area.

According to the present invention, there is provided a chip size estimation method for a semiconductor integrated circuit by a design device, wherein the central processing unit provided in the design device is a core size estimation method according to any one of claims 1 to 3. And calculating the chip size based on the core size . According to this method, the chip size can be accurately estimated before layout.

According to the present invention, a design apparatus for estimating the core size of a semiconductor integrated circuit is formed in an internal circuit of a device provided in the semiconductor integrated circuit based on circuit information and layout conditions stored in a storage device. A total net length calculation processing unit that calculates the total wiring length as a total net length, and an available channel length calculation process that calculates an available channel length based on the circuit information and the layout conditions stored in the storage device And the total net length is equal to or less than the usable channel length, and the total net length is equal to or less than the usable channel length and the internal circuit has a horizontal wiring direction along the wiring layer of the internal circuit. The total net length is equal to or less than the usable channel length with respect to the vertical wiring direction perpendicular to the horizontal direction and along the wiring layer. Calculating the area of Kino said internal circuit comprises a core size estimation processing section for estimating the area as core size, the. According to this design apparatus, the core size can be accurately estimated before layout, and the chip size can be accurately estimated, so that the number of reworks in the design flow can be reduced.

  Therefore, according to the present invention, the core size estimation method, the provisional wiring capacity estimation method, the chip size estimation, which can reduce the rework process in the design flow, shorten the design period, and thereby reduce the design cost. Methods and design devices can be provided.

It is a process flowchart which shows the chip size estimation method of 1st Embodiment. It is a schematic block diagram of a design apparatus. It is a process flowchart which shows the number of the power supply pads of 1st Embodiment, and a position estimation method. 4 is a process flowchart showing details of the estimation method of FIG. 3. It is explanatory drawing which shows the concept of a thinning process, (a) shows an initial state, (b) shows the state after a thinning process. It is a model circuit diagram used for calculation of the amount of current flowing through the power supply pad. It is explanatory drawing which shows the concept of a thinning process. It is explanatory drawing which illustrates the bias | inclination of power supply wiring. It is explanatory drawing which shows the example of arrangement | positioning of a high-speed operation module. It is explanatory drawing which illustrates the bias | inclination of the electric current amount which flows into a power supply pad. It is a process flowchart which shows the core size estimation method of 1st Embodiment. It is a process flowchart which shows the core size estimation method of 2nd Embodiment. It is explanatory drawing of a layout block. It is explanatory drawing which shows the number of wiring required for terminal drawing | extracting. It is explanatory drawing of the wiring which passes a layout block. It is a process flowchart which shows the calculation procedure of the number of wiring which detours a circuit block.

(First embodiment)
Hereinafter, a first embodiment in which the present invention is embodied with respect to processing in an initial stage design before layout design (hereinafter referred to as “initial design”) in a semiconductor integrated circuit (LSI) design flow will be described with reference to FIGS. This will be described with reference to FIG.

  FIG. 1 is a process flowchart showing an outline of a chip size estimation method according to the present embodiment. In this embodiment, the chip size estimation process is designed to function as the power consumption calculation unit 11, the power supply quantity calculation unit 12, the core size calculation unit 13, the power pad number / position calculation unit 14, and the chip size calculation unit 15. This is realized by a central processing unit (hereinafter referred to as “CPU”) of the apparatus.

  In step 1, the power consumption calculation means 11 calculates the power consumption of the core unit based on the net list file F1, the wiring capacity file F2 and the transistor (Tr) activation rate file F3 obtained as a result of logic synthesis, A power file F4 is created.

  In step 2, the power supply quantity calculating means 12 calculates the power supply quantity that satisfies the IR drop value of the core part based on the power consumption file F4 obtained in step 1, and stores the power supply quantity file F5. create. The amount of power supply is a value representing the amount of power supply wiring per unit area.

  In step 3, the core size calculation means 13 determines the core size based on the power quantity file F5 obtained in step 2, the circuit information file F6 created based on the netlist file F1, and the layout condition file F7. The core size capable of securing the signal wiring channel region to be formed in the part is estimated. Details of the core size estimation method will be described later.

  In step 4, the power pad number / position calculating means 14 determines the power pad based on the power consumption file F4 obtained in step 1 and the power wiring resistance network file F8 created based on the net list file F1. Estimate the number and location of At this time, if there are restrictions on the arrangement of the power supply pads, the number and positions of the power supply pads are estimated based on the pad restriction information file F9 storing the number of arrangements and the arrangement positions. The details of the method for estimating the number and position of the power supply pads will be described later.

  In step 5, the chip size calculation means 15 determines whether or not the core size estimated in step 3 is a size capable of arranging the power supply pad estimated in step 4. At this time, if the arrangement is possible, the area necessary for arranging the power supply pad (specifically, the area of the IO region including the IO buffer) and the area required for the subsequent process with respect to the core size. And estimate it as the chip size. On the other hand, if the placement is impossible, the core size obtained in step 3 is expanded to a size that allows the power supply pad obtained in step 4 to be placed.

FIG. 2 is a schematic configuration diagram of the design apparatus according to the present embodiment.
The design device 21 is configured by a general CAD (Computer Aided Design) device. The design device 21 includes a CPU 22, a memory 23, a storage device 24, a display device 25, an input device 26, and a drive device 27, which are connected to each other via a bus 28.

  The CPU 22 executes the program using the memory 23 and realizes the above-described chip size estimation process (see FIG. 1). The memory 23 usually includes a cache memory, a system memory, a display memory, and the like. The display device 25 is used to display a screen showing the results of processing, a parameter input screen, and the like. Usually, a CRT, LCD, PDP or the like is used for this. The input device 26 is used to input requests and instructions from the user and parameters, and a keyboard and a mouse device are used for this.

  The storage device 24 usually includes a magnetic disk device, an optical disk device, a magneto-optical disk device, and the like. The storage device 24 stores various files storing programs for realizing various processes and data necessary for executing the programs. In response to an instruction from the input device 26, the CPU 22 appropriately transfers data stored in a program and various files to the memory 23, and sequentially executes it. The storage device 24 is also used as a database.

  A program executed by the CPU 22 is provided on the recording medium 29. The drive device 27 drives the recording medium 29 and accesses the stored contents. The CPU 22 reads the program from the recording medium 29 via the drive device 27 and installs it in the storage device 24.

  As the recording medium 29, an arbitrary recording medium such as an optical disk (CD-ROM, DVD-ROM,...), A magneto-optical disk (MO, MD,...) Can be used. The recording medium 29 includes a medium and a disk device that record a program uploaded or downloaded via a communication medium.

  Next, a method for estimating the number and position of the power supply pads in the present embodiment (the process of step 4 executed by the power supply pad number / position calculating means 14 in FIG. 1) will be described with reference to FIGS. To do.

FIG. 3 is a flowchart showing an outline of the number of power supply pads and the position estimation process.
First, in step 11, the power supply network analysis of the core unit is performed based on the power consumption file F4 and the power supply wiring resistance network file F8, and the voltage value of each node is obtained. As a result of the power supply network analysis in step 11, if the IR drop value between the nodes exceeds the allowable IR drop value, the processing is stopped at that point.

  Next, in step 12, the current value flowing between the nodes is calculated based on the voltage value of each node obtained in step 11 and the resistance value between the nodes stored in the power supply wiring resistance network file F8. Based on the calculation result, the current value flowing through the power supply pad is obtained.

  Next, in step 13, the number and position of the power supply pads are determined based on the current value flowing in the power supply pad obtained in step 12 and the allowable current value of the input / output buffer (IO buffer) connected to the power supply pad. estimate. Specifically, the current value flowing through the power supply pad is compared with the allowable current value of the IO buffer. If the current value flowing through the power supply pad exceeds the allowable current value, a power supply pad is added in the vicinity of the power supply pad. To do. On the other hand, if the current value flowing through the power supply pad is within the allowable current value, the power supply pad can be deleted (thinned out) as will be described later.

FIG. 4 is a flowchart showing details of the estimation process of FIG.
First, in step 20, power pad initialization processing is performed. This process is performed prior to the above-described power supply network analysis of the core unit. Specifically, all the pads (power pads (including power pads with different potentials) and signal pads) provided in the device (semiconductor integrated circuit) to be designed are all treated as power pads Pv having the same potential. The initial state is assumed (see FIG. 5A). Hereinafter, the power supply pad Pv set to the same potential in the initialization process is referred to as “initial power supply pad Pv”.

  Next, in step 21, the core power supply network analysis is performed based on the power consumption file F4 and the power supply wiring resistance network file F8, and the voltage value of each node is obtained. As described above, when the IR drop value between the nodes exceeds the allowable IR drop value as a result of the power supply network analysis, the processing is stopped at that time.

  In the present embodiment, in order to simplify the processing of the power supply network analysis, a plurality of electrically equivalent equivalent circuits (hereinafter referred to as “power units” or lower PUs) in which the core portion is approximated by a uniform resistance and a current source, respectively. And the node between each of the connection points between the PUs, and the voltage value of each node is obtained.

  Next, in step 22, the voltage value of each node obtained in step 21 and the resistance value between each node stored in the power supply wiring resistance network file F8 (in this embodiment, each PU is connected). The value of the current flowing through the initial power supply pad Pv is calculated based on the resistance value).

  Specifically, as shown in FIG. 6, an IO buffer Buf is connected to a power supply pad Pv provided around the chip. Here, when the power supply pad Pv is a node N1, the connection point on the core side of the IO buffer Buf is a node N2, and the resistance value between the nodes N1 and N2 is approximated as a resistance value R, each node N1, The current value Ip flowing between N2 is obtained by Ip = | V1-V2 | / R. V1 and V2 indicate voltage values of the nodes N1 and N2, respectively. That is, this current value Ip is calculated as a current value flowing through the initial power supply pad Pv.

Next, in step 23, the initial power supply pad Pv is thinned out based on the current value Ip obtained in step 22 and the allowable current value Ic of the IO buffer Buf.
This thinning process will be described in detail. As shown in FIG. 7, in this process, first, a reference pad (hereinafter referred to as “reference pad”) Ps is determined from the initial power supply pads Pv.

  The reference pad Ps is determined in advance among the power supply pads provided around the chip based on the pad constraint information file F9 described above. In the present embodiment, any of the following conditions is determined as the reference pad Ps.

・ Restrictions on placement as a countermeasure against simultaneous switching noise of the output buffer and other noise countermeasures.
・ Placement is restricted by package pin specifications.

・ The value of the current flowing through the power pad is greater than that of the adjacent power pads.
・ Current is concentrated (current value exceeds a predetermined value).
・ Others whose placement is fixed due to the restrictions set for each device to be designed.

  After determining the reference pad Ps, whether or not thinning is possible for each of the other initial power supply pads Pv other than the reference pad Ps, that is, deleting the power supply pad at that position (use as another pad). Determine if you can.

This thinning-out process is sequentially performed from the initial power supply pads Pv on both sides of each reference pad Ps, and is specifically performed as follows.
As shown in FIG. 7, first, a current value A flowing through a pad to be subjected to thinning processing (hereinafter referred to as “thinning target pad”) Pd is determined as a reference pad Ps and a thinning located on the opposite side of the reference pad Ps. Each of the target pads Pd is distributed at a predetermined ratio to the adjacent pads Pso.

  At this time, the distribution ratio of the current value A is determined according to the current value flowing through each pad Ps, Pso and each distance between each pad Ps, Pso and the thinning target pad Pd. Specifically, a larger amount of current is distributed to the pads having a large current value and the pads having a short distance from the thinning target pad Pd among the two pads Ps and Pso. That is, assuming that the current value flowing through the reference pad Ps is B, the current value flowing through the pad Pso is C, the distance between the thinning target pad Pd and the pad Pso is L1, and the distance between the thinning target pad Pd and the reference pad Ps is L2. Distribution amounts X1 and X2 of the current value A for the pads Pso and Ps are as follows:

となる。ただし、距離に対する電流量の比重は等価なものとする。

It becomes. However, the specific gravity of the current amount with respect to the distance is equivalent.

  As a result, the current value flowing through the reference pad Ps after the current distribution is expressed as (B + X2). In the present embodiment, by comparing the current value (B + X2) flowing through the reference pad Ps after the current distribution with the allowable current value Ic of the IO buffer Buf connected to the reference pad Ps, the thinning target pad It is determined whether Pd thinning is possible.

  If the current value (B + X2) does not exceed the allowable current value Ic (Ic ≧ (B + X2)), the thinning target pad Pd is thinned out. That is, the initial power supply pad Pv serving as the thinning target pad Pd is returned to the pad (signal pad or power supply pad having a different potential) before the initialization process in step 20 described above. On the other hand, when the current value (B + X2) exceeds the allowable current value Ic (Ic <(B + X2)), thinning is not performed. In this case, the arrangement of the initial power supply pads Pv serving as the thinning target pads Pd is determined.

  Thereafter, in the same manner, such thinning-out processing is sequentially performed for all initial power supply pads Pv except the reference pad Ps. Then, as shown in FIG. 5B, the reference pad Ps and the pad that has not been thinned out by the thinning process (initial power supply pad Pv) are respectively determined as the power supply pads.

  Next, in step 24, it is determined whether or not the convergence condition is satisfied. Here, the convergence condition indicates whether or not there is a pad thinned out by the thinning process in step 23. If there is no pad thinned out at this time, it is determined that “convergence” has occurred and processing (estimation processing) is performed. ) Ends.

  On the other hand, if there is a thinned pad, it is determined that it is “unconverged”, and the process returns to step 21 and the power supply network analysis is performed again. Then, after performing the current amount calculation in step 22, the thinning-out process in step 23 is performed again. In the second thinning process, among the initial power supply pads Pv that have not become the reference pad Ps in the first thinning process, the pad having the largest current value is determined as a new reference pad Ps. I do. Then, the convergence determination is performed in step 24, and the process is terminated when the above convergence condition is satisfied.

  If the number of power supply pads is restricted due to package pin specifications, etc., the power pad position can be changed (moved) using the following method to optimize the power supply pad layout after estimation. Is possible.

  In this method, after estimating the number and position of the power supply pads by the estimation process described above, the power supply pad whose arrangement is to be changed and the power supply pad adjacent to the power supply pad (here, even if there is a signal pad between each power supply pad are regarded as adjacent to each other). ) Are compared, and among them, the power supply pad with the smaller current value is moved in the direction approaching the power supply pad with the larger current value. Here, if the distance between both power supply pads is L and the current values of both power supply pads are Ia and Ib (Ia> Ib), the movement amount D is

により求められる。

It is calculated by.

  Further, in the present embodiment, by considering the following matters, it is possible to estimate the number and position of the power supply pads before the layout with higher accuracy, and the number and position of the power supply pads during or after the layout. Can be optimized.

[1. Consider the bias of power supply wiring in the core. ]
In the layout of the power supply wiring in the core part C, as shown in FIG. 8, for example, the power supply wiring is disconnected (one-dot chain line in the figure) or wraps around (two-dot chain line in the figure) due to the arrangement of the macros M1 and M2. Thus, the power supply wiring is biased in the layout. By extracting the bias of the power supply wiring from the layout data and storing it in the power supply wiring resistance network file F8 and performing the above-mentioned power supply network analysis in consideration of the bias of the power supply wiring, the number and positions of the power supply pads can be optimized. Can be achieved.

[2. Consider the bias of power consumption in the core. ]
As shown in FIG. 9, the power consumption of the core part C is biased due to, for example, the arrangement of the high-speed operation modules M3 and M4 in the same region. Such power consumption bias is stored in the power consumption file F4 for each design instance or for each module, and the power supply network analysis described above is performed in consideration of the power consumption bias. The estimation accuracy of the number and position can be further improved.

[3. Consider the bias in the amount of current flowing through the power pad. ]
As shown in FIG. 10, the current flowing through the power supply pad is biased in the amount of current depending on the arrangement of the power supply pad. Specifically, the current concentrates in the central part on each side of the chip where the power supply pads are arranged, and the current hardly flows in the peripheral part. Further, when power supply pads that supply power of different potentials are arranged adjacent to each other, current concentration tends to occur in the power supply pads arranged adjacent to each other. By calculating the current amount bias in the power pads in advance and performing the above-described power supply network analysis in consideration of the current amount bias flowing through the power pads, the estimation accuracy of the number and position of the power pads can be further increased. Can be improved.

  Next, a method for estimating the core size according to the present embodiment (the process of step 3 executed by the core size calculating means 13 in FIG. 1 described above) will be described with reference to FIGS.

FIG. 11 is a process flowchart illustrating a core size estimation method.
As described above, the circuit information file F6 and the layout condition file F7 are prepared for this core size estimation process. Here, in the circuit information file F6, various input parameters derived from the net list file F1, in this embodiment, the number of cells N _cell , the total number of nets J, the average fanout m _avg , and the average cell area A _{The cell} and the total macro area used (hereinafter referred to as “total macro area”) A _{macro and the} like are stored as circuit information. In the layout condition file F7, various condition parameters related to the layout design, in this embodiment, the cell usage rate ρ, the number of wiring layers K, and a coefficient corresponding to the aspect ratio of the circuit block (hereinafter referred to as “aspect ratio”). ) Z _{A and the} like are stored as layout conditions. The cell usage rate is obtained by dividing the total cell area mounted on the core part by the area of the area where cells can be arranged in the core part.

  First, based on the circuit information file F6 and the layout condition file F7, the total net length and the usable channel length of the core part are calculated by individual processing flows (step 31a, step 31b).

  The total net length calculation process includes an average path length calculation process (step 311a) and a total net length calculation process (step 312a). On the other hand, the usable channel length calculation process includes a temporary area estimation process (step 311b) and an available channel length calculation process (step 312b).

First, the total net length calculation process in step 31a will be described.
[Step 311a: Average Path Length Calculation Processing]
This process is a process of calculating an average of path lengths (lengths of wirings in which the relationship between output and input has a one-to-one relationship) formed in each net of the core unit. This average path length L _path-idf.avg is calculated using the number of cells N _cell , average cell area A _cell , cell usage rate ρ, and Lenz index p.

により求められる（参考文献: J.A. Davis, V.K. De, J.D. Meindl "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI)- Part II : Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation", IEEE Transaction on Electron Devices, Vol.45, No.3, March 1998）。

(Reference: JA Davis, VK De, JD Meindl "A Stochastic Wire-Length Distribution for Gigascale Integration (GSI)-Part II: Applications to Clock Frequency, Power Dissipation, and Chip Size Estimation", IEEE Transaction on Electron Devices, Vol. 45, No. 3, March 1998).

The average path length L _path-idf.avg is a length _determined by the Manhattan length (the shortest distance when wiring between the input and output is performed only in the horizontal direction or the vertical direction). The Lenz index p is a value determined depending on the circuit architecture, using the number of cells N _cell , the total number of nets J, and the average fanout m _avg ,

で表される。

It is represented by

Here, a and b are empirical values obtained from past layout information. When circuit information parameters (average fan-out m _{avg and the} like) are not obtained, a value determined in advance with the value of the Lenz index p as a default value may be used. Further, the Lenz index p may be obtained using the number of gates instead of the number of cells N _cell . In this case, the average number of gates per cell is calculated in advance, and the Lenz index p is calculated by replacing the average number of gates with the number of cells N _cell .

[Step 312a: Total Net Length Calculation Processing]
This process calculates the total length (total net length) of all nets formed in the core part based on the average path length L _path-idf.avg obtained in step 311a and the _fanout of each net. It is processing to do.

If the total number of nets of fanout m among all nets is J _{FO = m} , the total net length L _{net.FO = m of the} net of _{fanout m} uses the above average path length L _path-idf.avg And

により求められる。ｔ(ｍ)は、ファンアウトｍと、そのファンアウトｍのネットの配線の迂回の影響とについて相関を持つ関数であり、

It is calculated by. t (m) is a function having a correlation between the fanout m and the influence of the bypass of the net wiring of the fanout m.

で表される。

It is represented by

Here, a _{FO = m} is a function for _obtaining the average path length of the net of the fanout m from the average path length L _path-idf.avg . B _{FO = m} is a function for converting the average path length of the net of the fanout m into the average net length. Therefore, in the above _equation 5, “L _path-idf.avg × t (m)” is expressed as an average net length L _{net-avg.FO = m} of the fan-out m net. Note that each of the functions a _{FO = m} and b _{FO = m} described above is expressed using a fan-out m.

Using the number 5 expressed using this function t (m), the total net length corresponding to the fan-out of each net is calculated, and the total net length for each fan-out is added to the core part. It is obtained as the _total net length L _net-total formed. That is, the total net length L _net-total is

となる。

It becomes.

Further, from the total net length L _net-total , the total net length L _{net-total.X in the} horizontal wiring and the total net length L _net-total in the vertical wiring (wiring perpendicular to the horizontal wiring) _When you ask for _.Y

となる。ここで、ｚ_A はアスペクト比（０＜ｚ_A ＜１）である。

It becomes. Here, z _A is an aspect ratio (0 <z _A <1).

Next, the calculation process of the usable channel length in step 31b will be described.
[Step 311b: Temporary Estimation Process for Area]
In this process, the temporary area A _temp-area of the core portion is calculated using the number of cells N _cell , the average cell area A _cell , the cell usage rate ρ, and the total macro area A _macro . The temporary area A _temp-area of the core part is obtained as the sum of the total area of the cells arranged in the core part and the total macro area A _macro ,

となる。

It becomes.

[Step 312b: Usable Channel Length Calculation Processing]
This process is a process of calculating the usable channel length in each wiring layer with respect to the temporary area A _{temp-area of} the core portion obtained in step 311b.

The usable channel length L _usable.n in a certain wiring layer n is the ideal usable channel length L _all.n when the entire surface of the wiring layer n can be wired, and the wiring prohibition in the wiring layer n is prohibited. When the channel length _L prohibit.n, and the maximum channel utilization of the interconnect layer n and r _n,

により求められる。

It is calculated by.

Here, the ideal usable channel length L _all.n in the wiring layer n is obtained from the value of the temporary area A _temp-area and the aspect ratio z _A. In addition, the wiring prohibition channel length L _prohibit.n is determined by the channel length used in the power supply wiring, the channel length that disappears due to the placement of the hard macro, and the stack via generated when connecting from the wiring upper layer to the wiring lower layer. The channel length is calculated as the sum of the channel length when the wiring channel substantially disappears in the intermediate layer, the channel length that cannot be used in advance, and the like.

Similarly, the usable channel lengths in the other wiring layers are calculated using this equation 10, and the sum of them is obtained as the usable channel length L _{usable-total in} all wiring layers. That is, the usable channel length L _usable-total in all wiring layers is

となる。

It becomes.

In addition, the wiring direction of each wiring layer is generally determined for each wiring layer, and usable channel length L _{usable-total.X} in horizontal wiring and usable channel length L _usable-total in vertical wiring. _.Y is obtained by adding up the usable channel lengths of the wiring layers having the same wiring direction. That is, the usable channel length L _{usable-total.X} in the horizontal direction is obtained by adding up the usable channel lengths of the wiring layers whose wiring direction is the horizontal direction, and the usable channel length L _{usable-total.Y} in the vertical direction. Is obtained by adding up the usable channel lengths of the wiring layer whose wiring direction is vertical.

Next, in step 32, the total net lengths L _net-total , L _net-total.Y and L _net-total.Y obtained in step 31a and the usable channel lengths L _usable-total and L obtained in step 31b are used. _{Compare usable-total.X} and L _{usable-total.Y} respectively.

の条件を満たすかどうかを判定する。

It is determined whether or not the condition is satisfied.

Here, if the condition is satisfied, the wiring layout with the core size (temporary area A _temp-area ) provisionally estimated in step 311b becomes possible. Therefore, the value of the temporary area A _temp-area is determined as the core size (step 33). On the other hand, if the condition is not satisfied, the layout condition is changed, and the temporary estimation process of the area in step 311b is performed again. In this case, specifically, the estimated value of the temporary area is increased to the minimum area value satisfying the condition of the above equation 12 by decreasing the cell usage rate ρ or increasing the number K of wiring layers.

Incidentally, the core size decreases as the cell usage rate ρ increases, and when the cell usage rate ρ is set to 100%, the core size (temporary area A _temp-area ) is the smallest (in other words, the cell is the core at this time). It will be in a state where it has been laid without any gaps). However, in general, there is almost no case where layout is possible when the cell usage rate ρ is 100%, and the upper limit value of the cell usage rate ρ depends on the layout tool, the degree of wiring congestion, the layout TAT, and the like. Is also set to a small value. By setting the upper limit value of the cell in advance according to such a design environment, it is possible to efficiently estimate the temporary area A _temp-area of the core part.

In this embodiment, the total net length L _net-total is calculated from the average path length L _path-idf.avg in consideration of the fanout of each net in this way, and based on the _total net length L _net-total. Since the core size is estimated, it is possible to estimate the core size while accurately estimating the total wiring length formed in the core portion as a result. Thus, in the present embodiment, the provisional wiring capacity value of each net can be accurately estimated according to the fan-out of each net and the area (core size) of the core at that time.

For example, the temporary wiring capacity value of the net of fanout m is obtained by the product of the average net length L _{net-avg.FO = m of fanout m} and the wiring capacity value per unit length. Here, the average net length L _{net-avg.FO = m} of the _{fanout m} is obtained by “L _path-idf.avg × t (m)” (see _Expression 5) as described above. The average net length L _{net-avg.FO = m} is a value proportional to the number of cells N _cell included in the core portion. Therefore, it is possible to accurately estimate the temporary wiring capacity value in the fan-out m net according to the fan-out m and the core size of each net.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The current value flowing through the power supply pad is calculated from the voltage value of each node obtained by the power supply network analysis, and the number and position of the power supply pads are estimated based on the comparison between the current value and the allowable current value of the IO buffer. I made it. In this method, the number and position of power supply pads that can guarantee SI and PI can be accurately estimated before layout in consideration of the allowable current value of the IO buffer. Thereby, it is possible to reduce the rework of the design flow, shorten the design period, and thus reduce the design cost.

  (2) If the IR drop value between the nodes exceeds the allowable IR drop value as a result of the power supply network analysis, the processing is stopped. Therefore, it is possible to accurately estimate the number and position of the power supply pads in consideration of the allowable IR drop value in the core portion.

  (3) In the present embodiment, the power supply network analysis is performed using a model circuit in which the core portion is divided by a plurality of electrically equivalent circuits (PU). By simplifying the power supply network analysis in this way, it is possible to easily estimate the number and position of the power supply pads.

  (4) In the present embodiment, the power supply pad whose arrangement is restricted in advance is defined as the reference pad Ps, and the thinning process is performed on the power supply pads (initial power supply pads Pv) excluding the reference pad Ps. In this method, it is possible to accurately estimate the number and position of the power supply pads in consideration of the arrangement constraints.

(5) In the present embodiment, the number and position of the power supply pads can be estimated with higher accuracy by performing the power supply network analysis in consideration of the bias of the power consumption of the core portion.
(6) In the present embodiment, the number and position of the power supply pads can be estimated with higher accuracy by performing the power supply network analysis in consideration of the deviation of the amount of current flowing through the power supply pads.

(7) In the present embodiment, it is possible to optimize the number and positions of power pads after layout by performing power network analysis in consideration of bias of power wiring in the core portion.
(8) In the estimation method of the core size, taking into account the fan-out of each net average path length _{L path-idf.avg} calculates the total net length L _{net Non-total,} total and the total net length L _{net Non-total} The core size is estimated based on the result of comparing the usable channel length L _usable-total in the wiring layer. In this method, since the core size is estimated in consideration of the fan-out of each net, it is possible to estimate the core size accurately and with the minimum area without actually performing layout.

(9) In the present embodiment, when comparing the total net length L _net-total and the usable channel length L _usable-total , the components in the horizontal and vertical wiring directions are also compared. did. In this method, the core size can be estimated more accurately.

  (10) In the present embodiment, the number and position of the power supply pads and the core size can be accurately estimated. As a result, it is possible to accurately estimate the chip size before layout.

(11) In the core size estimation method of the present embodiment, the average net length L _{net-avg.FO = m} corresponding to the fan-out of each net can be obtained with high accuracy. Accurate estimates can be made. Therefore, the circuit performance can be evaluated with higher accuracy before layout.

(Second Embodiment)
A second embodiment embodying the present invention will be described below with reference to FIGS. 12 to 16 with a focus on differences from the first embodiment. The second embodiment is different from the first embodiment in the core size estimation process in step 13 in the chip size estimation process of FIG. 1 described above. That is, the present embodiment describes a core size estimation method that is suitable for application when the core unit is configured by a plurality of circuit blocks.

FIG. 12 is a process flowchart showing the core size estimation method of the present embodiment.
First, in step 41, the area of each circuit block formed in the core part is obtained, and the total of them is obtained. At this time, as a method for calculating the area of the circuit block, if the circuit block has been laid out in the past, the area is used. If the circuit block is not yet laid out, the core in the first embodiment is used. The area may be estimated using a size estimation method.

  Next, in step 42, wiring areas required around each circuit block are obtained, and the total of these wiring areas is obtained. In the present embodiment, as shown in FIG. 13, the circuit block 32 and the wiring region 33 necessary around the circuit block 32 are regarded as one layout plane (a layout block 31 in the figure), and the area of the layout block 31 is shown. The total of Details of the processing in step 42 will be described later.

  Next, in step 43, the total area of the repeater cells used for connection between the circuit blocks 32 is obtained. The processing of this step 43 will be described later. The repeater cell is a so-called buffer circuit that is inserted in the middle of connection in order to reduce path delay when the wiring connecting the circuit blocks is long.

  Next, in step 44, the total value of the area of the circuit block 32 (that is, the layout block 31) including the wiring region 33 and the total value of the area of the repeater cell are summed. Thus, the area of the core size is estimated.

  Hereinafter, the calculation procedure of the wiring region 33 will be described with reference to FIGS. For convenience of explanation, a procedure for calculating a wiring area necessary for the left side and right side of the circuit block 32 (side parallel to the vertical wiring direction (the vertical direction of the paper in FIG. 14)) will be described. The procedure for calculating the necessary wiring area with respect to the lower side (the side parallel to the horizontal wiring direction (the horizontal direction of the paper in FIG. 14)) can be similarly obtained.

[Processing 1] The number of wires necessary for drawing out the terminals of the circuit block 32 is obtained.
As shown in FIG. 14, the number of wires required for withdrawal of the terminal of the circuit block 32 is drawn left side of the circuit block 32, the number of terminals disposed on the right side and T _L, T _R, respectively, left, from the right side If the number of wires is I _L and I _R , respectively,
Number of wires I _L = Number of terminals T _L (Left side)
Number of wires I _R = Number of terminals T _R (Right side)
It becomes.

[Process 2] The number of wirings I _detour that _detour around the circuit block 32 (here, around the left side and the right side) is obtained along with the connection between the circuit blocks.
In connection between circuit blocks, when there is another circuit block (in this case, the case where the circuit block 32 corresponds to this) exists between the blocks, the wiring passes through the layout block 31. At this time, the wiring that passes through the layout block 31 includes wiring that passes over the circuit block 32 and wiring that bypasses the circuit block 32. In the process 2, the number I _detour of wirings that bypass the circuit block 32 among the wirings passing through the layout block 31 is obtained.

FIG. 16 is a process flowchart showing a procedure for calculating the number of wires I _detour .
First, in step 51, the number of wirings I _thru (expected value) passing through the layout block 31 is obtained. The number of wirings I _thru is the number of circuit blocks included in the core part N _block , the total number of nets between circuit blocks J _B , the average fanout m _avg , the Lenz index p, and the connection between adjacent circuit blocks Assuming that the wiring of the ratio c (where 0 ≦ c ≦ 1) among the wirings not used in FIG.

により求められる。

It is calculated by.

Next, in step 52, it is determined whether or not the wiring passing through the layout block 31 can pass over the circuit block 32 (in other words, whether or not the wiring can be placed over the circuit block 32). Specifically, this is determined by _{obtaining the} number of wiring channels I _ch.usable that can be wired on the circuit block 32. If the number of wiring channels obtained at this time is “0”, the number of wiring channels on the circuit block 32 is determined. It is determined that no wiring is possible. The number of channels I _ch.usable does not include the number of channels that cannot be wired due to power supply wiring or the like.

Here, when wiring on the circuit block 32 is impossible (in the case of “NO” in step 52), all the wiring that passes through the layout block 31 is wiring that bypasses the circuit block 32. That is, I _detour = I _thru . FIG. 15 is a schematic diagram when the wiring passing through the layout block 31 passes, for example, I _thru / 2 through the left and right sides of the circuit block 32 when I _detour = I _thru .

If wiring on the circuit block 32 is possible (“YES” in step 52), the process proceeds to step 53. In step 53, it compares the insertion interval d _r repeater cell used in connections between each circuit block, and a length L _block side of the wiring direction circuit parallel to the block 32.

Here, when _dr <L _block (“NO” in step 53), wiring between circuit blocks cannot be performed on the circuit block 32, and the wiring passing through the layout block 31 is the same as described above. , All of the wirings bypass the circuit block 32 (ie, I _detour = I _thru ).

On the other hand, when d _r > L _block (“YES” in step 53), wiring between circuit blocks can be performed on the circuit block 32 via the repeater cell. In this case, the _{process proceeds} to the next step 54, the number of wirings I _thru passing through the layout block 31 is compared with the number of wiring channels I _ch.usable on the circuit block 32, and the number of wiring channels I _ch.usable is It is determined whether the number of wirings is greater than the number I _thru .

Here, if I _thru <I _ch.usable (“YES” in step 54), all the wirings passing through the layout block 31 are wirings passing over the circuit block 32. That is, I _detour = 0.

On the other hand, if I _thru > I _ch.usable (“NO” in step 54), the difference between the number of wirings I _thru passing through the layout block 31 and the number of wiring channels I _ch. This is the number of wires that pass. That is, in this case, I _detour = I _thru −I _ch.usable .

[Process 3] The number of wirings I _L required for drawing out the terminals of the circuit block 32 obtained in Process 1;
The sum I _oh of I _R and the number of wirings I _detour detouring around the circuit block 32 obtained in the process 2 is obtained.

The sum I _oh of the number of wires is a value estimated as the total number of wires passing around the circuit block 32 (here, only on the left and right sides),

となる。

It becomes.

[Process 4] The minimum wiring area that satisfies the sum I _oh of the number of wirings determined in Process 3 is determined.
In this minimum wiring area, the product of the wiring pitch (in this case, the vertical wiring pitch) and the number of wiring channels is equal in each wiring layer, and the total number of wiring channels in all wiring layers is the sum of the above-mentioned number of wirings. It is obtained as an area value when equal to I _oh . Incidentally, the number of wiring channels that can be used in each wiring layer increases as the number of wiring layers increases, and thus the wiring area decreases. Note that the number of wiring channels does not include the number of channels that cannot be wired due to power wiring or the like, similar to the number of wiring channels on the circuit block 32 described above.

  By performing the processing 1 to the processing 4 as described above, wiring areas necessary for the left and right sides of the circuit block 32 can be obtained. Further, the wiring regions necessary for the upper and lower sides of the circuit block 32 can be obtained by the same processing 1 to processing 4.

Here, the lengths of the upper and lower sides and the left and right sides of the circuit block 32 are _set to L _block.X and L _block.Y , respectively, and necessary wiring regions for the respective sides of the layout block 31 obtained by the above processing 1 to processing 4 When the lengths are L _T , L _B , L _L , and L _{R in} the order of the upper side, the lower side, the left side, and the right side, respectively, the area A _block-add of the circuit block 32 (that is, the layout block 31) including the wiring region 33 is

となる。

It becomes.

Therefore, the total value A _{block-add-all} of the layout block area including the necessary wiring region for all circuit blocks formed in the core portion is:

となる。

It becomes.

Next, a procedure for calculating the area (total value) of the repeater cells used for connection between the circuit blocks will be described.
The total value of the area of the repeater cell, a repeater cell number N _buffer which is formed in the core part, determined by the product of the per repeater cell area A _buffer envisaged.

The number of repeater cells N _buffer formed in the core part is

により求められる。

It is calculated by.

Here, l _r is a gate pitch obtained from the average layout block area A _{block-add-avg} calculated from the total value A _{block-add-all of the} layout block areas,

により求められる。

It is calculated by.

Therefore, the total value A _buffer-total of the area of the repeater cell is

となる。

It becomes.

Therefore, the expected area A _core of the core part is the sum of the total value A _{block-add-all of} the layout block areas obtained by Expression 16 and the total area A _buffer-total of the repeater cells obtained by Expression 19. Sought by

となる。

It becomes.

  In the present embodiment, by such a core size estimation method, the area (core size) of a core portion composed of a plurality of circuit blocks can be accurately estimated with a minimum area value before the layout.

As described above, according to the present embodiment, the following effects can be obtained.
(1) When the core section is composed of a plurality of circuit blocks, the area of each circuit block, the wiring area required for connection between the circuit blocks, and the area of the repeater cell used for connection between the circuit blocks The area value obtained by summing and was estimated as the core size. In this method, it is possible to estimate the area of the core portion composed of a plurality of circuit blocks accurately and with a minimum area value without actually performing layout.

In addition, you may implement each said embodiment in the following aspects.
In the method of estimating the number and position of power pads in the first embodiment (FIG. 4), processing is performed with an initial state in which one power pad is provided on each side of the chip (however, all are set to the same potential). The power supply pad may be added based on the comparison result between the current value flowing through each pad and the allowable current value of the IO buffer.

In the first embodiment, the power supply pad defined as the reference pad Ps is not limited to that illustrated in the embodiment.
The core size estimation method according to the second embodiment is naturally applicable not only when the core part is composed of a plurality of circuit blocks, but also when the core part is composed of one circuit block.

The technical ideas that can be grasped from the above embodiments are described below.
(Appendix 1) A method for estimating the number and position of power supply pads of a semiconductor integrated circuit,
A first process of performing a power supply network analysis of the core unit based on the power consumption and the power supply wiring resistance network to obtain a voltage value of each node;
A second process of calculating a current value between the nodes based on a voltage value of each node and a resistance value between the nodes, and obtaining a current value flowing through the power supply pad from the current value between the nodes;
And determining whether a current value flowing through the power supply pad satisfies an allowable current value of the IO buffer, and performing a thinning or addition of the power supply pad based on the determination result. How to estimate the number and location of power pads.
(Additional remark 2) The IR drop value between each node is calculated based on the voltage value of each said node, and subsequent processing is stopped when this IR drop value does not satisfy the allowable IR drop value. The number and position estimation method of the power supply pads according to 1.
(Supplementary note 3) The power supply network analysis is performed using a circuit in which the core part is modeled by a plurality of electrically equivalent circuits each represented by a uniform resistance value and a current source. The number and position estimation method of the power supply pads according to 1 or 2.
(Additional remark 4) The number of power supply pads and the position estimation method of Additional remark 1 or 2 characterized by performing the said power supply network analysis in consideration of the bias | inclination of the power supply wiring of the said core part.
(Additional remark 5) The number and position estimation method of the power supply pads of Additional remark 1, 2 or 4 characterized by performing the said power supply network analysis in consideration of the bias | inclination of the power consumption of the said core part.
(Supplementary note 6) The number and position estimation method of power supply pads according to supplementary note 1, 2, 4 or 5, wherein the power supply network analysis is performed in consideration of a bias of a current value flowing through the power supply pad.
(Appendix 7) Prior to the power supply network analysis, the semiconductor integrated circuit includes an initialization process for setting all the pads provided in the semiconductor integrated circuit as power supply pads having the same potential.
The power supply according to any one of appendices 1 to 6, wherein in the third process, the power supply pad thinning process is performed when a current value flowing through the power supply pad satisfies the allowable current value. How to estimate the number and position of pads.
(Supplementary Note 8) It is determined whether or not a convergence condition is satisfied after the thinning process of the power supply pad. If the convergence condition is satisfied, the estimation process is terminated. If the convergence condition is not satisfied, the power supply network analysis is performed again. The number and position estimation method of the power supply pads according to appendix 7, which is performed.
(Supplementary note 9) Supplementary note 7 or 8 characterized in that among the power supply pads that have undergone the initialization process, a power supply pad whose arrangement is restricted is defined as a reference pad, and the thinning process is performed on power supply pads other than the reference pad. How to estimate the number and location of power pads.
(Supplementary Note 10) In the thinning-out process, the current value flowing through the power supply pad to be processed is distributed to the reference pad at a predetermined ratio, and the current value flowing through the distributed reference pad and the allowable current value are 10. The method for estimating the number and position of power pads according to any one of appendices 7 to 9, wherein the method is performed based on a comparison result.
(Appendix 11) A method for estimating the core size of a semiconductor integrated circuit,
Based on the circuit information and layout conditions, calculate the total net length and usable channel length formed in the core part,
The total net length is less than or equal to the usable channel length;
And, with respect to the horizontal wiring direction, the total net length is not more than the usable channel length,
A core size estimation method for estimating a core size when the total net length is less than or equal to the usable channel length with respect to a vertical wiring direction.
(Supplementary Note 12) The total net length is
A first process for averaging the path lengths formed in each net to obtain an average path length;
A second process for calculating a total net length corresponding to the fan-out of each net from the average path length and obtaining a total sum of the total net lengths for each of the calculated fan-outs;
Calculated by
The total net length in the horizontal and vertical wiring directions is:
12. The core size estimation method according to claim 11, wherein the core size estimation method is calculated based on a calculation result of the second process and a coefficient corresponding to an aspect ratio of the circuit block.
(Supplementary note 13) The usable channel length is
A first process for provisionally estimating the area of the core part;
With respect to the temporarily estimated core area, the usable channel length in each wiring layer is calculated based on the wiring prohibited channel length and the maximum channel usage rate, and the calculated usable channel length for each wiring layer is calculated. A second process for calculating the sum,
Calculated by
Usable channel lengths in the horizontal and vertical wiring directions are:
12. The core size estimation method according to appendix 11, wherein the usable channel lengths of the wiring layers having the same wiring direction are obtained by adding together.
(Supplementary note 14) A method for estimating the core size of a semiconductor integrated circuit comprising a plurality of circuit blocks,
A first process for calculating the total area of each circuit block;
A second process for calculating a wiring area required around each of the circuit blocks and obtaining a sum of the wiring areas;
A third process for calculating the total area of the repeater cells used for connection between the circuit blocks;
Have
A core size estimation method, wherein an area obtained by summing up the calculation results of the first process, the second process, and the third process is estimated as a core size.
(Supplementary Note 15) The wiring region is
The sum of the number of wires corresponding to the number of terminals of the circuit block and the number of wires detouring around the circuit block is equal to the sum of the number of wiring channels that can be used in each wiring layer, and wiring is performed in each wiring layer. 15. The core size estimation method according to appendix 14, characterized in that it is obtained as an area value when the product of the pitch and the number of wiring channels is equal.
(Supplementary Note 16) The total area of the repeater cells is
The number of repeater cells calculated based on the average area of circuit blocks including the wiring region, the insertion interval of repeater cells, the number of circuit blocks, the average fanout, and the Lenz index, and 1 repeater cell 15. The core size estimation method according to supplementary note 14, wherein the core size estimation method is obtained by a product of an area per piece.
(Supplementary Note 17) A method for estimating a temporary wiring capacity of a semiconductor integrated circuit,
The average net length corresponding to the fan-out of each net is calculated based on the average path length described in Appendix 11, and the temporary wiring capacity is estimated based on the average net length and the capacitance value per unit length. To estimate temporary wiring capacity.
(Supplementary Note 18) A method for estimating the chip size of a semiconductor integrated circuit,
The core size obtained using the core size estimation method according to any one of appendices 11 to 16, and the number of power pads and the number of power pads obtained using the position estimation method according to any one of appendices 1 to 10. And a chip size estimation method, wherein the chip size is estimated based on an IO area corresponding to the position.
(Supplementary note 19) A semiconductor integrated circuit design apparatus,
A power pad number / position calculating means for estimating the number and position of the power pads using the power pad number and position estimating method according to any one of appendices 1 to 10;
A design device characterized by that.
(Supplementary note 20) A device for designing a semiconductor integrated circuit,
A core size calculating unit that estimates the core size using the core size estimating method according to any one of appendices 11 to 16;
A design device characterized by that.
(Appendix 21) A semiconductor integrated circuit design apparatus,
Core size calculating means for estimating a core size using the core size estimating method according to any one of appendices 11 to 16,
A design apparatus comprising: a power pad number / position calculating unit that estimates the number and position of power pads using the power pad number and position estimating method according to any one of appendices 1 to 10.
(Additional remark 22) The recording medium with which the program which performs the process according to the number and position estimation method of the power supply pads as described in any one of additional remark 1 thru | or 10 was recorded.
(Additional remark 23) The recording medium with which the program which performs the process according to the core size estimation method as described in any one of Additional remark 11 thru | or 16 was recorded.

C core part F4 power consumption file F6 circuit information file F7 layout condition file F8 power supply wiring resistance network file Ic allowable current value Ps reference pad Pv power supply pad (initial power supply pad)
Pd Power supply pad for thinning processing (pad for thinning)
L _path-idf.avg Average path length L _net-total total net length L _net-total.X Total net length in horizontal wiring direction L _net-total.Y Total net length in vertical wiring direction L _{usable-total Usable} channel length L _{usable-total.X Usable} channel length in horizontal wiring direction L _{usable-total.Y Usable} channel length in vertical wiring direction L _{net-avg.FO = m When} fanout m Average net length L _prohibit.n Wiring prohibited channel length for wiring layer n A _Temp-area Temporarily estimated core area (provisional area)
m Fan-out r _n Maximum channel usage z _A Factor (aspect ratio) according to the aspect ratio of the circuit block
13 Core size calculating means 14 Power pad number / position calculating means 21 Design apparatus 32 Circuit block 33 Wiring area

Claims (5)

A method of estimating a core size of a semiconductor integrated circuit by a design device,
The process executed by the design apparatus is as follows:
Processing said design device central processing unit provided in the can, based on the stored circuit information and layout conditions in the storage device, and calculates the total wiring length of the wiring which is formed on the internal circuit of the semiconductor integrated circuit as total net length When,
A process in which the central processing unit calculates an available channel length based on the circuit information stored in the storage device and the layout condition;
The central processing unit is
The total net length is less than or equal to the usable channel length;
And regarding the horizontal wiring direction along the wiring layer of the internal circuit, the total net length is equal to or less than the usable channel length,
The area of the internal circuit is calculated when the total net length is equal to or less than the usable channel length in the vertical wiring direction that is along the wiring layer of the internal circuit and orthogonal to the horizontal direction. and, a process of estimating the area as core size,
A core size estimation method characterized by comprising: The process of calculating the total net length is as follows:
It said central processing unit, a first processing for obtaining an average value of the path length in each net average path length,
A second process in which the central processing unit calculates a total net length based on the average path length and fan-out of each net, and calculates a total sum of the calculated total net lengths;
Have
The total net length in the horizontal and vertical wiring directions is:
2. The core size estimation method according to claim 1, wherein the core size estimation method is calculated based on a calculation result of the second process and a coefficient corresponding to an aspect ratio of the circuit block. The process of calculating the usable channel length is as follows:
A first process in which the central processing unit temporarily estimates the area of the internal circuit ;
The central processing unit calculates the usable channel length in each wiring layer with respect to the provisionally estimated area of the internal circuit based on the wiring prohibited channel length and the maximum channel usage rate, and calculates each calculated wiring layer. A second process for calculating the sum of available channel lengths of
Have
Usable channel lengths in the horizontal and vertical wiring directions are:
2. The core size estimating method according to claim 1, wherein the usable channel lengths of the wiring layers having the same wiring direction are obtained by adding together. A method of estimating a chip size of a semiconductor integrated circuit by a design device,
A central processing unit included in the design apparatus includes a process of calculating a core size by the core size estimation method according to any one of claims 1 to 3 and estimating a chip size based on the core size. Chip size estimation method. A design apparatus for estimating the core size of a semiconductor integrated circuit,
A total net length calculation processing unit that calculates a total wiring length formed in an internal circuit of a device provided in the semiconductor integrated circuit as a total net length based on circuit information and layout conditions stored in a storage device;
An available channel length calculation processing unit for calculating an available channel length based on the circuit information and the layout condition stored in the storage device;
The total net length is equal to or shorter than the usable channel length, and the horizontal net wiring direction along the wiring layer of the internal circuit, the total net length is equal to or shorter than the usable channel length, and the wiring layer of the internal circuit. The area of the internal circuit is calculated when the total net length is equal to or shorter than the usable channel length with respect to the vertical wiring direction perpendicular to the horizontal direction, and the area is estimated as the core size. A core size estimation processing unit;
A design apparatus comprising:

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