JP4821822B2 - IC card - Google Patents

Description

  The present invention relates to an operating system and an application program that are executed by a CPU of an IC card on which a plurality of applications can be mounted.

  In recent years, with the improvement in performance of IC chips mounted on IC cards, highly convenient multi-application IC cards capable of executing a plurality of applications have been put into practical use. Such an IC card obtains power from a dedicated external device for each application, and executes target processing while exchanging processing information. The IC card performs communication and processing in synchronization with a clock set for establishing a communication path after connection with an external device.

  A plurality of applications mounted on an IC card have different specifications depending on their uses. For example, in some applications, priority is given to reducing power consumption even if the processing speed is slow, but other applications Then, even if power consumption is large, priority may be given to increasing the processing speed.

In particular, the processing for encrypting and decrypting data such as RSA and DES requires a large amount of calculation, so that if the calculation is performed on software, the processing speed of the IC card becomes slow. In this case, if the coprocessor in the IC card is used as dedicated hardware, the processing speed can be increased, but the power consumption increases.
Therefore, an IC card equipped with an application that gives priority to the speed of processing speed can be used in an external device such as a stationary type whose power consumption is not limited, but the recommended load peak value of current consumption is determined. There is a problem that it cannot be used in an external device with limited power consumption, such as a mobile phone using a battery as a power source, and lacks versatility.
In order to solve this problem, there is a conventional IC card that changes the frequency of an internal clock serving as a reference for processing speed in accordance with the type of external device.

Japanese Patent Laid-Open No. 2001-209764 (page 2-3, FIG. 1)

  However, in the conventional IC card, in the plurality of processes included in the application, the processing speed in all the processes is uniformly adjusted according to the process that maximizes the power consumption, which may cause a process delay. In other words, when the IC card is connected to an external device with limited power consumption and the application includes encryption and decryption processing, the frequency of the internal clock must be set low. There is a problem that other processing included in the application must be performed in synchronization with the application.

  An object of the present invention is to provide an operating system and an application program that are executed by a CPU of an IC card, which is highly convenient and versatile and can be processed quickly.

The present invention solves the above problems by the following means. In addition, in order to make an understanding easy, although the code | symbol corresponding to embodiment of this invention is attached | subjected and demonstrated, it is not limited to this. That is, the invention of claim 1 is an IC card (1, 1-2 ) comprising an application program storage means (63) for storing an application program, the CPU (50, 50-2) for executing instructions, A clock generator (42) for selecting a frequency of a clock for operating the CPU by a selection signal; and a clock generator (42) for providing the CPU with the clock selected by the selector; and the application program The clock is generated in response to the CPU executing an instruction that constitutes an application program stored in the storage means and that specifies an argument that is not substantially processed by the CPU. Control the processing speed of the CPU by transmitting a selection signal to the selector of the generation unit IC card, wherein the processing speed control unit (52), that, with a.

The invention according to claim 2, IC card comprising a contact terminal for the antenna (10) or contact communication function to perform contactless communication function (20), the application program storage unit for storing application programs and (63) ( 1, 1-2 ) having a CPU (50, 50-2) for executing an instruction and a selector (424) for selecting a frequency of a clock for operating the CPU by a selection signal, When a processing speed change request is received via the antenna or the contact terminal from the clock generator (42) that provides the CPU with the clock selected by the selector and the external device , the processing speed change request is met. And a processing speed control unit (52) that transmits a selection signal to the selector of the clock generation unit to control the processing speed of the CPU. The processing speed control unit, when receiving a request other than the processing speed change request, is a command constituting a stored application program corresponding to the received request, and the processing performed by the CPU is substantially A control signal is transmitted to the selector of the clock generation unit to control the processing speed of the CPU in response to the CPU executing an instruction in which an argument that is not performed is specified. IC card .

As described above in detail, according to the present invention, the following effects can be obtained.
(1) In order to change the processing speed of the application program execution means (calculation means, CPU) when there is a processing speed change instruction in the application program, the processing speed is changed according to the processing content included in the application program, By adjusting the power consumption and the processing speed, the versatility and convenience of the IC card and the external device are improved, and the processing in the IC card is efficiently accelerated.
(2) In order to change the processing speed of the application program execution means (calculation means, CPU) based on the processing speed change request received from the external device, the power consumption and processing speed are adjusted from the external device side according to the request contents. As a result, the versatility and convenience of the IC card and the external device are improved, and the processing in the IC card is efficiently accelerated.
(3) Since the processing speed is changed in units of processing, the power consumption and the processing speed are adjusted in detail, so that it can be used in an external device with limited power consumption. And speed up processing efficiently.
(4) An instruction in which the application program has another existing meaning (an instruction to execute another existing process), and an argument that erases the other existing meaning (an argument that makes the other existing process meaningless) ) Is specified, and the processing speed is changed based on the processing speed change instruction. Therefore, not only the IC card storing the operating system corresponding to the processing speed change instruction but also the conventional operating This application program can also be used in an IC card that stores the system, thereby improving versatility.
(5) Similarly, since the processing speed is changed based on a processing speed change request that is a request having another meaning and an argument for erasing the other meaning is specified, the external device requests the processing speed change request. This request can be made not only in an IC card having an operating system (application program) corresponding to the above, but also in an IC card storing a conventional operating system (application program), thereby improving versatility.
(6) When an argument that makes this function meaningless is specified as an argument of an instruction that calls a general-purpose function, an application program including this instruction is executed in order to call an original function from the operating system. In addition to being usable with an IC card equipped with an OS, an IC card equipped with an OS having an original function is intended to exhibit unique functions and improve versatility and convenience.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a first embodiment of an IC card according to the present invention.
As shown in FIG. 1, the IC card 1 includes an antenna 10 provided inside the card and a contact terminal 20 provided on the card surface, and is transmitted from the R / W of the external device 2-1. A non-contact communication function for performing transmission and reception of power and clock through the antenna 10 in a non-contact state using electromagnetic waves as a carrier wave and a contact terminal 20 is a reader / writer (hereinafter referred to as “reader / writer”) of an external device 2-2 such as an ATM. It is a contact / non-contact type IC card having a contact type communication function for exchanging data, power, and a clock in contact with a terminal of “R / W”. Further, the IC card 1 is a so-called multi-application IC card that includes a contact / non-contact type IC chip 30 connected to the antenna 10 and the contact terminal 20 and is capable of mounting a plurality of applications.
The external device 2-1 is an information processing device including an R / W that communicates with the IC card 1 in a non-contact manner, such as an entrance / exit management device, and the external device 2-2 is in contact with the IC card 1, such as an ATM. It is an information processor provided with R / W which communicates by a formula.

The antenna 10 is wound by a plurality of turns so that the conductor does not come into electrical contact, and is connected to an interface section 40 (hereinafter, “interface” is referred to as “I / F”) of the IC chip 30. Therefore, mutual conversion of AC electromagnetic wave and AC power is performed.
The contact terminal 20 includes a plurality of terminals that are in electrical contact with the R / W terminal of the external device 2-2, and is connected to the I / F unit 40 of the IC chip 30. Is a contact-type communication means for mediating contact-type communication between the IC chip 30 and the external device 2-2.

The IC chip 30 includes a CPU 50, an I / F unit 40 connected to the CPU 50, a coprocessor 71, a RAM 61, a ROM 62, an NVM (Non Volatile Memory) 63, and the like.
The I / F unit 40 extracts a clock component, that is, a clock for extracting an external clock (basic clock) which is a tempo for synchronizing between peripheral circuits such as the RAM 61 from the AC power input via the antenna 20. A basic clock generation unit 41 including a pulse generation circuit and the like, and a clock generation unit 42 connected to the basic clock generation unit 41 are provided. Further, the I / F unit 40 includes a rectifier circuit for extracting a power component that becomes a power supply voltage from AC power via the antenna 20, a demodulator circuit for extracting a data component to be input to the CPU 50, an AC A modulation circuit that performs load modulation or the like on the electric power according to data output from the CPU 50 and outputs the electric power to the antenna 20 is provided (not shown).

The clock generation unit 42 generates a plurality of clocks from the basic clock (external clock) input from the basic clock generation unit 41 or the contact terminal 20, and inputs any one of the clocks to the CPU 50 as an internal clock.
FIG. 2 is a block diagram showing the clock generation unit 42.
As shown in FIG. 2, the clock generation unit 42 has a frequency eight times the basic clock input from the basic clock generation unit 41 (hereinafter, a clock having a frequency X times the basic clock is referred to as an “X multiplied clock”). Frequency multiplication circuit 421, frequency dividing circuit 422 for reducing the frequency multiplied by 8 clock input from frequency multiplication circuit 421 to 1/2 frequency, and frequency multiplied by 4 frequency input from frequency dividing circuit 422 to 1/2 frequency. A frequency dividing circuit 423 for reduction and a selector 424 are provided.

  The selector 424 is connected to the basic clock generation unit 41, the multiplier circuit 421, the frequency divider circuits 422 and 423, the CPU 50, and the like. The selector 424 switches the connection based on a selection signal input from the CPU 50 and is input by the multiplier circuit 421 or the like. Any one of four types of clocks (basic clock, 8-times clock, 4-times clock, and 2-times clock) is input to the CPU 50 as an internal clock. In the initial state of the IC card 1, the selector 424 inputs a basic clock to the CPU 50.

As shown in FIG. 1, the RAM 61, the ROM 62, and the NVM 63 are storage means for storing information necessary for processing of the CPU 50 such as programs and data. The RAM 61 is a volatile memory, and is used as a work area where the CPU 50 performs processing. The ROM 62 is a nonvolatile read-only memory, and is necessary for executing a program such as an operating system (hereinafter, an operating system stored in the IC card 1 is referred to as “OS-1”) and a program such as a parameter. I remember the data. The operating system is basic software that is executed by the CPU 50 to control hardware such as the CPU 50 and peripheral devices so that application programs can use the data and data necessary for executing the program. is there.
The NVM 63 is a non-volatile rewritable memory such as an EEPROM, a flash memory, or an FRAM, and is normally used as a user work area, a program area, etc., and can store a plurality of applications.

The CPU 50 controls the IC card 1 by executing a program such as OS-1 stored in a memory such as the ROM 62 and the NVM 63, thereby realizing an application execution unit 51, a processing speed control unit 52, and the like.
The application execution unit 51 is an application program execution unit that executes an application program stored in the NVM 63, and includes an operation unit 511 that performs operations such as arithmetic operations and logical operations related to the execution of the application program. The calculation unit 511 performs processing in synchronization with an internal clock provided from the selector 424 to the CPU 50.

  The processing speed control unit 52 controls the selector 424 by transmitting a selection signal including clock identification information to the selector 424 when the application program executed by the application execution unit 51 is instructed to change the processing speed. The processing speed of the CPU 50 is controlled by switching the internal clock input to the CPU 50, for example, by changing the processing speed of the calculation unit 511. The processing speed change instruction is an instruction to change the processing speed. In this embodiment, the processing speed change instruction is an instruction to change the clock input to the CPU 50. Clock identification information indicating an internal clock to be input to the CPU 50 after the change is provided. Contains. The clock identification information is information for identifying one clock from the four types of clocks that the clock generator 42 can input to the CPU 50. The instruction is an instruction for causing the CPU 50 to operate, and includes a function. The coprocessor 71 is a processor that complements the CPU 50 and enhances the performance, and is a calculation unit that exclusively performs processing with a large calculation amount such as data encryption and decryption.

FIG. 3 is a diagram for explaining the first embodiment of the operating system and the application program according to the present invention. FIG. 3A is an application program interface (hereinafter, referred to as OS-1) stored in the ROM 62. It is a figure for demonstrating "API."
As shown in FIG. 3A, the API of OS-1 transmits a selection signal including clock identification information indicating a clock corresponding to the argument “Lv” (level) to the selector 424, that is, processing speed control. It includes an instruction “DNP.util.setClock (BYTE Lv)” (hereinafter, this instruction is referred to as “instruction DUS”) that calls a function of OS-1 that causes the CPU 50 to realize the unit 52. The command DUS is a processing speed change instruction that instructs the CPU 50 to change the processing speed.

The value of the argument of the instruction DUS (value that can be specified by Lv) is four kinds of values of DEFAULT, HIGH, MIDDLE, and LOW. Clock identification information corresponding to a clock, an 8 × clock, a 4 × clock, and a 2 × clock. DEFAULT is a basic clock (external clock), and HIGH, MIDDLE, and LOW are a plurality of clocks generated from the basic clock by the I / F unit 40, respectively, in order from the highest frequency, an 8 × clock, 4 × clock, and Each corresponds to a double clock.
This correspondence relationship may be stored in a memory such as the ROM 62 or the NVM 63 by associating the four types of arguments that can be specified by the instruction DU with the four types of clocks that can be provided by the IF unit 40 without storing them. The association may be performed dynamically by the CPU 50 executing OS-1. Also, which clock is associated with which argument value is arbitrary and is not limited.

FIG. 3B shows a part of the application program according to the present invention. The application program according to the present invention is AP-1 which is stored in the NVM 63 of the IC card 1 and described in the Java language. Note that “heavyFunction ()” is an instruction (hereinafter referred to as “instruction HF”) that causes the CPU 50 to perform processing that places a heavy load on the RSA, such as encryption and decryption.
As shown in FIG. 3B, AP-1 includes an instruction DU in which the argument “HIGH” is designated before the instruction HF, and an instruction DU in which the argument “DEFAULT” is designated after the instruction HF. Yes. Therefore, the CPU 50 performs the processing of the instruction HF in synchronization with the 8-fold clock, and performs the subsequent processing in synchronization with the basic clock.
Therefore, the processing speed control unit 52 can change the processing speed in one or a plurality of processing units according to the command DUS which is a processing speed change instruction. The processing unit is a minimum unit (task) of execution in processing using hardware resources such as an instruction unit of AP-1.

FIG. 4 is a flowchart showing the operation of the IC card, the operating system, and the application program according to the present invention in the first embodiment.
In step 100 (hereinafter, “step” is referred to as “S”), the IC card 1 is connected to the external device 2-1 (or may be the external device 2-2), supplied with power and clock, and AP -1 is selected.
In S110, the IC card 1 receives a command from the external device 2-1. The application execution unit 51 starts executing a program (hereinafter referred to as “command processing program”) corresponding to this command, which is included in the selected AP-1 (S120). When the command processing program includes the instruction DUS, the processing speed control unit 52 transmits a selection signal to the selector 424 and changes the processing speed (S130, S140). The calculation unit 511 performs subsequent processing at the changed processing speed (S150), and repeats the same processing until the execution of the command processing program ends (from S130 to S160). The IC card 1 transmits this processing result as a response to the external device 2-1 (S170), enters a standby state until the next command is received, and performs the same processing until the connection with the external device 2-1 is disconnected. (S110 to S170) is repeated.

According to the first embodiment, according to the instruction DUS included in AP-1, the clock provided to the CPU 50 by the I / F unit 40 in one or a plurality of processing units is changed. By setting the processing speed of the CPU 50 in units of processing, it becomes possible to efficiently speed up the processing.
FIG. 5 is a graph showing the relationship between the elapsed time of processing (horizontal axis) and the current consumption of the IC card (vertical axis) in the execution of the application program. FIG. FIG. 5B shows the current consumption in the IC card 1.
That is, as shown in FIG. 5 (a), in the conventional IC card, an external device 2-2 with limited power consumption, such as a mobile phone using a battery with a recommended load peak value of current consumption as a power source. Cannot be used in On the other hand, as shown in FIG. 5B, the IC card 1 has a process (p4) that consumes a large amount of current (power consumption) (p4). For the external devices 2-1 and 2-2 with limited power consumption, the processing speed of the CPU 50 is changed in units of processing according to the power consumption, such as processing at a high processing speed for p2, p3). It can be used, and the versatility and convenience can be improved, and the processing can be efficiently speeded up.
In addition, in the API, the meanings (e.g., multiplication by 8) indicated by the arguments (DEFAULT, HIGH, MIDDLE, LOW) of the instruction DUs are arbitrary for each card, so multiple clocks can be generated and OS-1 is installed. If so, the type and number of clocks to be generated are not limited, and AP-1 can be used with more IC cards, and versatility can be improved.

(Second Embodiment)
FIG. 6 is a block diagram showing a second embodiment of the IC card according to the present invention.
In addition, the same code | symbol is attached | subjected to the part which fulfill | performs the same function as embodiment mentioned above, and the overlapping description is abbreviate | omitted suitably.
As shown in FIG. 6, the IC card 1-2 includes a CPU 50-2, a ROM 62-2, an NVM 63-2, and the like.
The CPU 50-2 implements the processing speed control unit 52-2 by executing programs stored in the ROM 62-2 and the NVM 63-2.
The ROM 62-2 stores OS-2, which is an operating system, and the NVM 63-2 stores AP-2, which is an application program.

FIG. 7 is a diagram for explaining a second embodiment of the operating system and the application program according to the present invention, and shows a part of the application program. The OS and application program according to the present invention are OS-2 and AP-2.
As illustrated in FIG. 7, the AP-2 has a function of copying the data string at the address indicated by the argument “src” to the address indicated by the argument “dst” by the capacity indicated by the argument “len”. 2 is realized by “standard.arrayCopy (REFERENCE src, REFERENCE dst, short len), which is versatile and can be executed in a conventional general OS (IC card) such as JavaOS (“ JAVA ”is a registered trademark). ”(Hereinafter, this command is referred to as“ command SAC ”).

In OS-2, the argument “len” is designated with an argument “0” that deletes the existing meaning of copying the data string of the instruction SAC (an argument that makes the existing processing meaningless), and a call is made from AP-2. If there is, the CPU 50-2 has a unique function of transmitting a selection signal including clock identification information indicating the multiplied clock to the selector 424, and causes the CPU 50-2 to realize the processing speed control unit 52-2. The meaningless (meaningless) means that substantial processing is performed such as the content of the data to be processed (data at the address indicated by the argument “dst” or “src”) does not change in the processing according to the instruction. It is not to be missed.
Note that when the conventional OS receives a call from AP-2, the capacity of the data string to be copied is zero, so the processing according to this command is not performed or even if it is performed Before and after, the content of the data to be processed (data at the address indicated by dst or src) does not change, and the processing result does not cause an error.

AP-2 is a general-purpose instruction that causes the CPU 50-2 to copy information as in the case of the instruction SAC, and is different from the instruction SAC in that the data string is not backed up in the state before processing. It includes an instruction “standard.arrayCopyNonomic (REFERENCE src, REFERENCEDst, short len)” (hereinafter, this instruction is referred to as “instruction SACN”).
OS-2 is called from AP-2 when the argument “len” is designated with an argument “0” that erases the original meaning of copying the data string of the instruction SACN (an argument that makes the existing processing meaningless). If there is, a unique function of transmitting a selection signal including clock identification information indicating a basic clock to the selector 424 is provided, and the processing speed control unit 52-2 is realized by the CPU 50-2.

AP-2 includes an instruction SAC in which “0” is designated in the argument “len” before the instruction HF, and an instruction SACN in which “0” is designated in the argument “len” after the instruction HF.
An execution procedure of the AP-2 program will be described. First, the processing speed control unit 52-2 changes the clock provided to the CPU 50-2 to an eight-fold clock (# 1), and then the calculation unit 511 performs an operation in synchronization with the eight-fold clock, for example. The execution unit 51 performs processing corresponding to the instruction HF in synchronization with the 8-fold clock (# 2), and the processing speed control unit 52-2 changes the clock to the basic clock (# 3).

  According to the second embodiment, in addition to the effects of the first embodiment, by specifying an argument that erases the original meaning in the instruction SAC and the instruction SACN, which are existing instructions having high versatility, the OS-2's original Since the function is called, AP-2 can be executed on an IC card having a conventional OS that does not have this unique function, and the versatility of AP-2 can be improved. It was.

(Third embodiment)
FIG. 8 is a block diagram showing a third embodiment of the IC card according to the present invention.
As shown in FIG. 8, the IC card 1-3 includes a CPU 50-3, a ROM 62-3, and the like.
The ROM 62-3 stores OS-3 which is an operating system.
When the CPU 50-3 receives from the external devices 2-1 and 2-2 a request for changing the processing speed including the clock identification information, which requests a change in the processing speed of the application execution unit 51, the CPU 50-3 identifies the clock. A processing speed control unit 52-3 for transmitting a selection signal including information to the selector 424 is provided. In the present embodiment, the processing speed change request is a DUS command, and is a command for calling a function similar to the function called from the OS-1 by the instruction DUS from the OS-3 in the first embodiment. The CPU 50-3 implements the processing speed control unit 52-3 by executing a command processing program corresponding to the DUS command of OS-3. The DUS command is designated with an argument (Lv) like the instruction DUS, such as clock identification information.

FIG. 9 is a flowchart showing the operation of the IC card, the operating system, and the application program according to the present invention in the third embodiment.
In S200, the IC card 1-3 is connected to the external device 2-1 (or the external device 2-2) and is in a state of receiving power and a clock.
In S210, the IC card 1-3 receives a command from the external device 2-1 (S210). If the received command is a DUS command, the processing speed control unit 52-3 changes the processing speed (S220, S230), and if it is another command, the command processing program corresponding to the received command. Are executed (S220, S240). The IC card 1-3 sends this processing result as a response to the external device 2-1 (S250), and is in a standby state until the next command is received, and so on until the connection with the external device 2-1 is disconnected. The process (from S220 to S250) is repeated.
When another command such as an authentication command is received after the processing speed is changed (S220) (S210), the calculation unit 511 changes the calculation related to the execution of the command processing program corresponding to the authentication command. (S240).

  According to the third embodiment, in addition to the same effects as those of the first embodiment, for example, the external devices 2-1 and 2-2 that have a restriction on the peak power consumption of a mobile phone or the like can be processed by a DUS command. The power consumption and processing speed can be adjusted for each command, that is, for each job (one or a plurality of processing units) from the external device 2-1 or 2-2, for example, by switching to a low speed. In addition to improving versatility and convenience, it has become possible to speed up processing efficiently.

(Deformation)
The present invention is not limited to the embodiment described above, and various modifications and changes are possible, and these are also within the equivalent scope of the present invention. For example, the IC card 1 includes the contact / non-contact type IC chip 30 that communicates with the external devices 2-1 and 2-2 via the antenna 10 or the contact terminal 20, but is not limited thereto. A non-contact type IC chip or a contact type IC chip may be used. Further, the IC card 1 may include an antenna and an I / F unit that communicate with an external device by an electrostatic coupling method, and a communication method is not limited.

  In each embodiment, the I / F unit 40 generates four types of clocks, ie, a basic clock, a double clock, a quadruple clock, and an eighth clock. A clock having a frequency of another multiple of the basic clock such as a double frequency may be generated, two types of clocks, five or more types of clocks may be generated, and a plurality of types of clocks can be generated. The frequency and the number of types are not limited.

  Also, instead of generating a plurality of types of clocks that the I / F unit 40 provides to the CPUs 50, 50-2, and 50-3 based on the external clocks supplied from the external devices 2-1, 2-2, A plurality of types of clocks may be generated by generating a unique basic clock that is not affected by external clock interference inside an IC card such as the CPU 50, 50-2, or 50-3, and multiplying the basic clock. .

  Furthermore, the clock generator 42 adjusts the frequency by multiplying the frequency of the basic clock by 8 and then by 1/2 and 1/2 to generate a clock having four types of frequencies. For example, when the frequency of the basic clock is high, a plurality of clocks may be generated by multiplying by 1/2 or 1/2. A method for generating a plurality of types of clocks having different frequencies is as follows: It is not limited.

  In each embodiment, the processing speed control unit 52 changes the processing speed of the application execution unit 51 (calculation unit 511) by changing the clock provided to the CPUs 50, 50-2, and 50-3. Similarly, when an application program is executed using the coprocessor 71 (when the coprocessor 71 includes application program execution means), the clock provided to the coprocessor 71 is changed to change the application program execution means. The processing speed may be changed.

  Further, the processing speed control unit 52 may supply clocks having different frequencies from the clock generation unit 42 to the CPU 50 and the coprocessor 71, respectively. It becomes possible to change the processing speed in more detail, and it is possible to improve the processing efficiency, speed up the processing speed, and suppress the maximum power consumption.

  In each embodiment, the command DUS, the command SAC, the command SACN, and the DUS command are commands or requests for switching the processing speed for processing after the command or request, but are synchronized with the clock and the changed clock in the command or request. If the instruction or request includes information indicating the changed clock and information indicating which process is to be performed in synchronization with the changed clock The contents of the instruction or request are not limited.

  In each embodiment, the IC cards 1, 1-2, and 1-3 store application programs such as AP-1 and AP-2 in the NVMs 63 and 63-2, but in the ROMs 62, 62-2, and 62-3. You may memorize | store and you may memorize | store in RAM61. As long as the application program is stored so as to be executable, the storage method is not limited. The same applies to the OS.

  In the second embodiment, the instruction SAC and the instruction SACN in which “0” is specified for the argument “len” are exemplified as the processing speed change instruction. However, the arguments “src” and “dst” of the instruction SAC or the instruction SACN are the same. In this case, it may be a processing speed change instruction, or an instruction for causing the CPU 50-2 to execute another existing process, and an argument that makes the existing process meaningless is specified in the instruction. In this case, the type of instruction and the meaning of the argument are not limited as long as the instruction is a processing speed change instruction.

  In addition, in relation to other instructions in the application program, an instruction in which an argument for which existing processing is meaningless may be designated as a processing speed change instruction. For example, as shown in FIG. 10, in AP-3, an instruction SAC in which “5” is designated as an argument “len” is described twice (# 4, # 5). This second instruction SAC (# 5) may be used as a processing speed change instruction. When the conventional OS receives a call from AP-3, the CPU 50 repeats the process of copying the data string at the address indicated by the argument “gSrc” for 5 bytes to the address indicated by the argument “gDst” twice. -2 is executed. Therefore, the process related to the second instruction SAC (# 5) in which the same argument as the first instruction SAC (# 4) is specified is meaningless.

In the second embodiment, AP-2 includes an instruction SAC and an instruction SACN, but when OS-2 has other unique functions, other unique functions other than changing the clock or general purpose A command for calling a unique function from OS-2, and when an argument that makes a general-purpose function meaningless is specified, a command for calling another unique function may be included. .
The content of the unique function called by the instruction is not limited and can be arbitrarily defined in the API. The unique function is a non-generic function that the conventional OS does not have.
AP-2, which includes instructions for calling various unique functions from the OS, can be stored and executed in a conventional IC card equipped with a conventional OS. In the IC card 1-2 on which 2 is mounted, various functions can be exhibited, and convenience can be improved.

In the third embodiment, the processing speed control unit 52-3 is a command that calls a function similar to the function that the instruction SAC and the instruction SACN call from the OS-2 in the second embodiment, and the existing process is meaningless. The processing speed of the application execution unit 51 may be changed when a general-purpose SAC command or SACN command that is a processing speed change request is received.
When an SAC or SACN command is transmitted from an external device to a conventional IC card, no substantial processing is performed in the IC card and no error occurs, and a SAC command or SACN is sent to the IC card 1-3. When a command is transmitted, it becomes a processing speed change request, and in addition to the same effects as in the third embodiment, it is possible to improve the versatility of the external device.

It is a block diagram which shows 1st Embodiment of the IC card by this invention. 3 is a block diagram showing a clock generation unit 42. FIG. It is a figure for demonstrating 1st Embodiment of the operating system and application program by this invention. It is a flowchart which shows operation | movement of the IC card by this invention, an operating system, and an application program in 1st Embodiment. It is a graph which shows the relationship between the elapsed time of the process in execution of an application program, and the consumption current of an IC card. It is a block diagram which shows 2nd Embodiment of the IC card by this invention. It is a figure for demonstrating 2nd Embodiment of the operating system and application program by this invention. It is a block diagram which shows 3rd Embodiment of the IC card by this invention. It is a flowchart which shows operation | movement of the IC card by this invention, an operating system, and an application program in 3rd Embodiment. It is a figure for demonstrating the deformation | transformation form of the operating system by this invention, and an application program.

Explanation of symbols

1, 1-2, 1-3 IC card 2-1, 2-2 external device 10 antenna 20 contact terminals 30, 30-2, 30-3 IC chip 40 interface unit 41 basic clock generation unit 42 clock generation unit 50 CPU
51 Application Execution Unit 52 Processing Speed Control Unit 61 RAM
62, 62-2, 62-3 ROM
63, 63-2 NVM
71 Coprocessor 424 Selector 511 Operation Unit

Claims (2)

An IC card comprising an application program storing means for storing the application program,
A CPU that executes instructions;
A clock generator for selecting a frequency of a clock for operating the CPU by a selection signal, and providing a clock selected by the selector to the CPU;
In response to the CPU executing an instruction that constitutes an application program stored in the application program storage means and that specifies an argument that is not substantially processed by the CPU. A processing speed control unit that controls a processing speed of the CPU by transmitting a selection signal to the selector of the clock generation unit ,
IC card characterized by A contact terminal for the antenna or contact communication function performs non-contact communication function, an IC card comprising an application program storing means for storing the application program,
A CPU that executes instructions;
A clock generator for selecting a frequency of a clock for operating the CPU by a selection signal, and providing a clock selected by the selector to the CPU;
When a processing speed change request is received from the external device via the antenna or the contact terminal , a selection signal is transmitted to the selector of the clock generation unit in response to the processing speed change request, and the processing speed of the CPU is A processing speed control unit for performing control,
When the processing speed control unit receives a request other than the processing speed change request, the processing speed control unit is a command constituting a stored application program corresponding to the received request, and the processing performed by the CPU is substantially An instruction in which an argument that is not performed is designated is transmitted to the selector of the clock generator in response to execution of the CPU to control the processing speed of the CPU ;
IC card characterized by

Images