JP4812667B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a coating type low dielectric constant film.

  In a multilayer wiring of a semiconductor integrated circuit, the signal propagation speed delay is determined by a time constant RC based on the product of the resistance R of the wiring and the parasitic capacitance C between the wirings. As the degree of integration of semiconductor integrated circuits increases and the device density increases, the wiring width and the wiring interval are narrowed, and the wiring resistance and the parasitic capacitance between the wirings are increasing. In order to increase the signal propagation speed, it is essential to reduce the resistance of the wiring and reduce the parasitic capacitance between the wirings. The wiring material is changed from aluminum to copper, and it is difficult to further reduce the resistance. It is desired to reduce the parasitic capacitance between wirings.

  If the wiring thickness is reduced and the facing area of the adjacent wiring is reduced, the parasitic capacitance of the wiring is reduced. However, reducing the wiring thickness decreases the wiring cross-sectional area, leading to an increase in wiring resistance and an increase in time constant. The remaining possibility is to lower the dielectric constant of the dielectric film that insulates the wiring. Various dielectric films have been lowered in dielectric constant.

  Conventionally, inorganic materials such as silicon oxide, silicon nitride, and phosphosilicate glass (PSG), and organic materials such as polyimide have been used as dielectric materials. The relative dielectric constant of a silicon oxide film by chemical vapor deposition (CVD) which has been most often used is about 4. The relative dielectric constant of the CVD-SiOF film to which F is added for the low dielectric constant is about 3.3 to 3.5. As a material capable of lowering the dielectric constant, there is a coating type porous material. By including a pore having a relative dielectric constant of about 1.0, the relative dielectric constant of the dielectric film can be greatly reduced. Organic polymer materials represented by Dow Chemical's SiLK (registered trademark) and Honeywell's FLARE (registered trademark) are widely known as coating-type porous materials. Organic dielectric materials are significantly different in properties from conventionally used inorganic dielectrics and are not easy to handle.

Japanese Patent Laid-Open No. 2003-197621 discloses that an organic polymer coating film such as SiLK is melted in a solvent even after drying, and when the edge cut with a rinsing agent is performed, the coating film having a width of 2 mm to 3 mm is removed at the wafer edge . It is pointed out that an edge rinse part and an inclined part with an inclined surface of about 1 mm in width are generated, and the organic polymer layer is sandwiched between upper and lower silicon oxide layers due to insufficient mechanical strength near the wafer edge of the organic polymer layer. It is proposed to prevent this by wrapping the edges of the organic polymer layer.

In recent years, a coating type porous (porous) silica having a SiO ₂ skeleton and pores having a relative dielectric constant of about 1.0 has attracted attention. The coating-type porous silica can control the pore size during curing, can form uniform and fine pores, and can suppress a decrease in film strength due to introduction of pores. The coating-type porous silica precursor film adheres to the wafer end face during spin coating, drying, and curing, and collides with the wafer carrier to generate particles when handled as it is. Therefore, after spin coating, edge cutting is performed to remove the coating film in a region of several mm from the wafer end face. The edge-cut side surface is substantially perpendicular to the base surface.

  Japanese Patent Application Laid-Open No. 2003-78005 discloses that a low dielectric constant film has a low film density and is easily affected by outside air, and therefore needs to be covered with a protective film having low outside air permeability. If the interlayer insulating film is formed so as to protrude outward, the side surface of the lower low dielectric constant film is protected, but it points out that the usable area of the wafer is narrowed. It is proposed to edge cut the dielectric film at the same radial position.

  Japanese Patent Application Laid-Open No. 2004-96096 points out that when a film having a vertical sidewall is polished, peeling is likely to occur due to stress concentration, and a coating film is formed by applying a siloxane polymer, and a solvent is discharged from a nozzle to form an edge. After cutting and forming a substantially vertical side wall, it is proposed to prevent peeling in the polishing process by irradiating the end portion with plasma, eroding the end portion, and forming an inclined portion.

JP 2003-197621 A JP 2003-78005 A JP 2004-96096 A

  If the porous silica precursor film forming the porous silica is subjected to edge cutting, a substantially vertical side surface is formed, and microscratching or peeling may occur during polishing.

  An object of the present invention is to provide a method for manufacturing a semiconductor device that uses a porous silica precursor film and can suppress generation of microscratches and peeling even when polishing is performed.

According to one aspect of the present invention,
(A) a step of spin-coating a porous silica precursor film on the ground of a semiconductor wafer;
(B-1) a step of spraying a rinsing liquid onto a peripheral portion of the porous silica precursor film to form an edge cut portion having a constant width from which the polycrystalline silica precursor film is removed;
(B -2) to the end of the remaining porous silica precursor film, while scanning from the outer periphery toward the inside, by injection on the semiconductor wafer to rotate the rinsing liquid from the nozzles, porous silica precursor Forming an inclined portion whose thickness decreases toward the outside at the outer peripheral portion of the film;
(C) curing the porous silica precursor film and converting it to a porous silica film;
A method for manufacturing a semiconductor device is provided.

  After coating the porous silica precursor film on the wafer, the inclined portion can be created by scanning the rinse liquid inward from the radial end. The inclined portion is effective for suppressing the occurrence of micro scratches and peeling.

  Examples of the coating film forming material include organic SOG, porous silica precursor, and porous polyarylene. Among these, a porous silica precursor is preferable from the viewpoint that the dielectric constant of the material alone is low. As such a porous silica precursor, a template type in which pores are formed by adding a thermally decomposable resin or the like to organic SOG and thermally decomposing by heating, silica particles are formed in an alkali, A non-template type that forms voids by using the gaps between them is mentioned. The alkali is added as a synthesis catalyst when the siloxane polymer is synthesized. The coating solution becomes an alkaline solution. The non-template type is preferable in that fine pores can be formed uniformly.

  Examples of the non-template type porous silica precursor include NSC series manufactured by Catalyst Kasei Kogyo Co., Ltd. and LKD series manufactured by JSR Corporation. Moreover, the non-template type porous silica precursor can also be prepared. In this case, as a raw material silicon compound, for example, tetraalkoxysilane such as tetramethoxysilane, tetraethoxysilane, tetrapropoxysilane, tetrabutoxysilane, tetraisopropoxysilane, methyltrimethoxysilane, methyltriethoxysilane, Methyltripropoxysilane, methyltributoxysilane, methyltriisopropoxysilane, phenyltrimethoxysilane, phenyltriethoxysilane, phenyltripropoxysilane, phenyltributoxysilane, phenyltriisopropoxysilane, vinyltrimethoxysilane, vinyltriethoxy Trialkoxysilanes such as silane, vinyltripropoxysilane, vinyltributoxysilane, vinyltriisopropoxysilane, and dimethyl Methoxysilane, dimethyldiethoxysilane, dimethyldipropoxysilane, dimethyldibutoxysilane, dimethyldiisopropoxysilane, phenylmethyldimethoxysilane, phenylmethyldiethoxysilane, phenylmethyldipropoxysilane, phenylmethyldibutoxysilane, phenylmethyldi Isopropoxysilane, phenylmethyldimethoxysilane, phenylmethyldiethoxysilane, phenylmethyldipropoxysilane, phenylmethyldibutoxysilane, phenylmethyldiisopropoxysilane, diphenyldimethoxysilane, diphenyldiethoxysilane, diphenyldipropoxysilane, diphenyldi Tetramethylammonium using dialkoxysilane such as butoxysilane and diphenyldiisopropoxysilane Idro oxide, tetraethylammonium oxide, tetrapropylammonium oxide, liquid composition containing an organic silicon compound obtained by hydrolyzing in the presence of a tetraalkyl ammonium hydroxide such as tetrabutylammonium oxide (TAAOH) are preferred. This allows an elastic modulus of 10 GPa or more and a hardness of 1 GPa or more.

  The solvent of the non-template type porous silica precursor is not particularly limited as long as the siloxane resin of the porous silica precursor can be dissolved, but methyl alcohol, ethyl alcohol, propyl alcohol, isopropyl alcohol, butyl alcohol, isobutyl alcohol, tertiary butyl. Alcohols such as alcohol, phenols such as phenol, cresol, diethylphenol, triethylphenol, propylphenol, nonylphenol, vinylphenol, allylphenol, nonylphenol, etc., ketones such as cyclohexane, methylisobutylketone, methylethylketone, methylcellosolve, ethylcellosolve Cellosolve such as hexane, octane, decane, etc., propylene glycol, propylene glycol Bruno methyl ether, or other solvents glycol such as propylene glycol monomethyl ether acetate can be used as a single or mixed solvent.

  When the porous silica precursor solution is spin-coated on the wafer, a film that adheres also to the wafer end surface is generated. If this adhering film on the end face is left as it is, particles are generated due to friction and collision with the wafer carrier, so that the rinse liquid is sprayed from the nozzle of the edge cut arm and the edge is cut about several millimeters from the end.

  Rinse solutions used for edge cutting include alcohols such as methyl alcohol, ethyl alcohol, propyl alcohol, isopropyl alcohol, butyl alcohol, isobutyl alcohol, and tertiary butyl alcohol, phenol, cresol, diethylphenol, triethylphenol, propylphenol, and nonylphenol. Phenols such as vinylphenol, allylphenol and nonylphenol, ketones such as cyclohexane, methylisobutylketone and methylethylketone, cellosolves such as methylcellosolve and ethylcellosolve, hydrocarbons such as hexane, octane and decane, propylene glycol and propylene Glycols such as glycol monomethyl ether and propylene glycol monomethyl ether acetate , It can be used anisole, methyl lactate, ethyl lactate, gamma-butyrolactone, hexane, as solvent alone or a mixed solvent such as tetrahydrofuran.

  When normal edge cutting is performed, the side surface of the film is almost perpendicular to the underlying surface, and this causes micro scratching and peeling in the subsequent chemical mechanical polishing (CMP) process.

  In the edge cutting process, the present inventors sprayed a rinsing liquid while scanning the edge cutting arm in the radial direction of the wafer, and created an inclined portion having a surface inclined at the edge portion of the porous silica precursor film. investigated.

  The porous silica precursor film after coating is converted into a porous silica film by, for example, a process of heating and drying the substrate at a temperature of 80 ° C. to 350 ° C. and a process of curing the substrate at a temperature of 350 ° C. to 450 ° C. Note that the step of heating and drying the substrate at a temperature of 80 ° C. to 350 ° C. and the step of curing the substrate at a temperature of 350 ° C. to 450 ° C. are preferably performed in an inert atmosphere with an oxygen concentration of 100 ppm or less. This is to prevent a decrease in moisture resistance due to oxidation of the coating.

  After forming the interlayer insulating film, a damascene process is performed in which a recess for wiring is formed and copper wiring is embedded. It is difficult to form the interlayer insulating film only with the porous silica film, and the interlayer insulating film is combined with the CVD oxide film. Further, a SiN film or a SiC film that functions as copper diffusion prevention, an etch stopper, or a CMP stopper is also laminated. Hereinafter referred to as a stopper film. When forming a multilayer wiring, the interlayer insulating film forming step and the wiring forming step are repeated.

  In order to investigate the effect when the inclined portion is created in the edge cutting process, the inventors created a sample of a multilayer interlayer insulating film under different conditions and examined the result. However, only the insulating laminate was formed, and the device structure and wiring structure were omitted.

  The main materials, stopper films, devices, etc. used in the experiment are as follows.

Wafer: 8-inch silicon wafer on which a thermal oxide film having a thickness of 100 nm is formed;
Porous silica film forming apparatus: ACT12SOD manufactured by Tokyo Electron Ltd .;
Porous silica precursor solution: Ceramate NCS (non-template type porous silica precursor solution) manufactured by Catalyst Kasei Kogyo Co., Ltd .;
Edge rinse solution: gamma butyrolactone;
Chemical mechanical polishing equipment;
Plasma CVD equipment.

  1A to 1E are cross-sectional views schematically showing a sample creation process.

  As shown in FIG. 1A, a SiC: N: H film (hereinafter referred to as a SiC film) 12 having a thickness of 50 nm is formed on the surface of the silicon wafer 11 by plasma CVD. The CVD film becomes thin at the edge of the silicon wafer, does not deposit on the edge, and does not cause particles.

  As shown in FIG. 1B, a silicon wafer 11 on which an SiC film 12 is formed is loaded on a porous silica film forming apparatus ACT12SOD, and a ceramate NCS solution (non-template type porous silica precursor solution) is placed on the SiC film 12. A porous silica precursor film 13 is formed by spin coating.

  As shown in FIG. 1C, a rinse liquid (gamma butyrolactone) 16 is sprayed from the nozzle 15 of the edge cut arm onto the rotating wafer, and the edge of the wafer edge is cut. The nozzle diameter is 0.5 mm to 1.0 mm, and the rinsing liquid injection amount is about 15 ml / min to 20 ml / min. The porous silica precursor film 13 struck with the rinsing liquid 16 is removed to form an edge cut portion 17, and a substantially vertical side wall is formed in the porous silica precursor film 13. The porous silica precursor film on the periphery of the silicon wafer 11 is completely removed, and particle generation is prevented.

  In addition, after the porous silica precursor film 13 is formed, heating H is performed at 150 ° C. for 1 minute, 250 ° C. for 1 minute, and 350 ° C. for 1 minute, and the porous silica precursor film 13 is dried. When the porous silica precursor film 13 is completely dried, it does not dissolve in the rinse liquid.

  As shown in FIG. 1D, while the nozzle 15 of the edge cut arm is scanned radially inward from the wafer edge, the rinse liquid 16 is sprayed onto the rotating wafer to remove the inclination of the edge of the porous silica precursor film 13. To do. An inclined portion 18 having a scanned width is formed. The slope width is set to 0.0, 0.5, 0.7, 1.0, 1.5, 2.0 (mm), and the scan speed is set to 0.1, 0.2, 0.5, 1.0 and 1.2 (mm / sec) were set.

  As shown in FIG. 1E, the porous silica precursor film 13 in which the edge cut portion and the inclined portion are formed is cured (C) at 450 ° C. for 30 minutes to be converted into a porous silica film 19.

  As shown in FIG. 1F, a silicon oxide film 21 having a thickness of 100 nm is deposited on the porous silica film 19 by plasma CVD using tetraethoxysilane (TEOS) as a silicon source.

  As shown in FIG. 1G, the silicon oxide film 21 is polished to a thickness of 50 nm by chemical mechanical polishing. That is, an interlayer insulating film for one layer can be formed.

  As shown in FIG. 1H, the steps shown in FIGS. 1A to 1F are repeated six times to laminate six layers of porous silica interlayer insulating films ILD1 to ILD6 for lower layer wiring. Note that FIG. 1H shows a different scale for easy viewing.

Three intermediate interlayer insulating films ILD7 to ILD9 using SiOC layers are formed on the lower interlayer insulating films ILD1 to ILD6 by CVD. Further, an upper interlayer insulating layer ILD10 using an SiO ₂ layer as the uppermost layer is formed by CVD.

  Thus, in each sample in which the 10-layer interlayer insulating film was formed, the edge cut portion was observed with an optical microscope to observe whether defects such as peeling occurred. As a defect, a residue other than peeling was also detected, and whether or not an inclined portion was formed was also detected.

  FIG. 2 is a graph summarizing the results. The horizontal axis indicates the slope width in units (mm), and the vertical axis indicates the scan speed in units (mm / second). Samples are shown as plots in the graph. Those having peeling are indicated by ×, those having residue are indicated by Δ, those having no sloped portion are indicated by −, and those having no such defect are indicated by ○. Regarding the scanning speed, a residue remains at 0.1 mm / second, but there is no residue at 0.2 mm / second to 1.0 mm / second. At 1.2 mm / second, no residue remains and no inclined part is formed. If the scanning speed is too slow, it is considered that drying proceeds too much, and if the scanning speed is too fast, it is considered that the inclined portion is not formed.

  Regarding the inclined portion width, peeling occurs at 0.0 mm (no inclined portion width). The absence of the inclined portion corresponds to the conventional technology, and it can be confirmed that peeling which is a problem occurs. Peeling does not occur when the slope width is 0.5 mm or more. It was confirmed that the formation of the inclined portion is effective for preventing peeling. In addition, if the width of the inclined portion is 0.5 mm or more, the peeling preventing effect can be surely obtained. Since the width of the edge cut portion and the inclined portion is a region that cannot be used as a semiconductor device, the sum of the width of the edge cut portion and the inclined portion is preferably 4 mm or less.

  As shown in FIG. 1I, the nozzle 15 of the edge cut arm may be continuously scanned from the edge of the silicon wafer 11 toward the center in the radial direction without separating the rinse of the edge cut portion and the rinse of the inclined portion. Care is taken not to leave a porous silica precursor film at the edge of the silicon wafer. After scanning from the outside to the inside, it may be folded and scanned from the inside to the outside.

  The porous silica precursor film does not dissolve in the rinse liquid when completely dried, but exhibits a phenomenon that it is physically scraped immediately before complete drying.

  As shown in FIG. 1J, it is also effective to incline the nozzle 15 of the edge cut arm toward the outside by about 2 to 10 degrees, for example, about 5 degrees so that the rinse liquid 16 is directed from the outside in the wafer radial direction to the inside. is there. The ridges (corners) on the side wall of the porous silica precursor film standing vertically can be effectively eliminated.

  The rules for semiconductor integrated circuit devices continue to shrink, increasing to 0.14 μm or less. In the logic LSI, the 90 nm rule is mainly used. When the wiring and the wiring interval are each half pitch, the wiring width and the wiring interval are 45 nm each. In multilayer wiring with a wiring interval of 45 nm or less, suppression of parasitic capacitance is strongly desired, and adoption of porous silica is effective. Hereinafter, a method for manufacturing a semiconductor device according to an embodiment will be described.

  As shown in FIG. 3A, an element isolation region 102 is selectively formed on the surface portion of the silicon wafer 101 to define an active region surrounded by the element isolation region 102. Although the element isolation region is formed by LOCOS, the element isolation region may be formed by shallow trench isolation (STI). A gate insulating film is formed on the surface of the active region, a gate electrode layer such as polycrystalline silicon is deposited thereon, and patterned by photolithography and etching to form the gate electrode 104. An insulating film such as silicon oxide is deposited and anisotropic etching such as reactive ion etching is performed to form sidewall spacers 103 on the gate electrode sidewalls. Ion implantation using the gate electrode and sidewall spacer as a mask is performed to form a source region 105a and a drain region 105b.

  As shown in FIG. 3B, an interlayer insulating film 106 of PSG (phosphorus glass) and a stopper film 107 such as SiN are deposited on the silicon wafer 101 so as to cover the gate electrode 104, thereby forming an interlayer insulating film. Contact holes for extracting electrodes are formed by photolithography and etching.

As shown in FIG. 3C, a TiN barrier film 108 having a thickness of about 50 nm is deposited by sputtering so as to cover the inner surface of the contact hole, and a bracket W film 109 is deposited thereon by a reduction reaction of WF ₆ and hydrogen. The metal layer on the stopper film 107 is removed by CMP, and the conductive plugs of the barrier film 108 and the W film 109 are left in the contact holes. In this CMP, the SiN stopper film 107 functions as a CMP stopper. In addition, the above process is a well-known thing, A well-known various change, substitution, etc. are possible.

  As shown in FIG. 3D, a stopper film 110 such as SiN or SiC is deposited on the interlayer insulating film so as to cover the conductive plug. On the stopper film 110, a non-template type porous silica precursor film 111 is applied under the condition that the thickness on the flat portion is 150 nm, and the rinse is performed as described with reference to FIGS. 1C and 1D. The liquid is sprayed to the peripheral portion to form an edge cut portion and an inclined portion. For example, an inclined portion having a width of 0.5 mm is formed at a scanning speed of 0.5 mm / second. Thereafter, curing is performed to convert the porous silica precursor film into the porous silica film 111.

  As shown in FIG. 3E, a silicon oxide film 112 having a thickness of about 100 nm is deposited on the porous silica film 111 by CVD using TEOS as a Si source to form a protective film.

As shown in FIG. 3F, the silicon oxide film 112 and the porous silica film 111 are etched by F plasma using CF ₄ / CHF ₃ gas by using a resist mask having an opening having a wiring pattern shape. The etching is once stopped at the stopper film 110, and then the stopper film 110 is also etched.

  As shown in FIG. 3G, a TaN diffusion barrier layer 113 is deposited by sputtering with a thickness of approximately 10 nm, and a Cu seed layer is deposited thereon by sputtering with a thickness of approximately 50 nm. A Cu layer 114 is grown to a thickness of about 600 nm by electrolytic plating, and the metal layer above the protective layer 112 is removed by CMP. In this way, a Cu wiring having a single damascene structure is formed.

  As shown in FIG. 3H, a stopper film 115 such as SiN or SiC is deposited by plasma CVD with a thickness of about 50 nm. Similar to the process shown in FIG. 3D, the porous silica precursor film 116 is applied on the stopper film 115 under the condition that the thickness on the flat portion is 250 nm, and the description will be given with reference to FIGS. 1C and 1D. As described above, the rinsing liquid is sprayed to the peripheral portion to form an edge cut portion and an inclined portion. For example, an inclined portion having a width of 0.5 mm is formed at a scanning speed of 0.5 mm / second. Thereafter, curing is performed to convert the porous silica precursor film into the porous silica film 116.

  Further, a stopper film 117 is formed on the porous silica film 116 by plasma CVD with a thickness of about 50 nm, and a porous silica film 118 is formed thereon in the same process as the porous silica film 116 with a thickness of about 150 nm. A silicon oxide protective film 119 is deposited on the porous silica film 118 by plasma CVD.

The silicon oxide film 119, the porous silica film 118, the stopper film 117, the porous silica film 116, and the stopper film 115 are made of F plasma using CF ₄ / CHF ₃ gas using a resist mask having a via pattern-shaped opening. Etching is performed by changing the gas composition along the way. A via hole is formed. If necessary, the via hole is filled, and then the silicon oxide film 119, the porous silica film 118, and the stopper film 117 are formed using CF ₄ / CHF ₃ gas using a resist mask having an opening in the shape of a wiring pattern. Etching is performed by changing the gas composition in the middle of the plasma. A wiring groove is formed.

  As shown in FIG. 3I, a TaN diffusion barrier layer 120 is deposited by sputtering with a thickness of about 50 nm, and a Cu seed layer is deposited thereon by sputtering with a thickness of about 50 nm. A Cu layer 121 is grown to a thickness of about 1400 nm by electrolytic plating, and the metal layer above the protective layer 119 is removed by CMP. In this way, a Cu wiring having a dual damascene structure is formed.

Thereafter, for example, six lower wiring layers are formed by the same process. Three intermediate wiring layers using a plasma SiOC film using tetramethylsilane as an interlayer insulating film are formed on the lower wiring layer, and further an upper wiring layer using SiO ₂ using silane as a source for the interlayer insulating film. One layer is formed.

  FIG. 4 is a cross-sectional view schematically showing the configuration of the semiconductor device to be produced. A device layer DL including a CMOS transistor is formed on the surface portion of the silicon substrate 101, a lower wiring layer LW using a porous silica film as an interlayer insulating film is formed thereon, and a SiOC film is formed as an interlayer insulating film thereon. The used middle wiring layer MW is formed, an upper wiring layer UW using a silicon oxide film as an interlayer insulating film is formed thereon, and a pad PD is formed as the uppermost layer. Note that the numbers of the lower wiring layer LW and the middle wiring layer MW are shown in a simplified manner. Even when a multilayer wiring having a large number of layers is formed, the occurrence of microscratching and peeling can be efficiently prevented by providing an inclined portion around the porous silica film.

  5A and 5B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a modification.

  As shown in FIG. 5A, following the step of FIG. 3G, after depositing a stopper layer 115 such as SiN or SiC, a porous silica precursor film 116 is formed. The porous silica precursor film 116 is applied under the condition that the thickness on the flat portion is 400 nm. At that time, as described with reference to FIGS. Forming an inclined portion. Thereafter, curing is performed to convert the porous silica precursor film into the porous silica film 116. A silicon oxide protective film 119 is deposited on the porous silica film 116 by plasma CVD.

As shown in FIG. 5B, the silicon oxide film 119, the porous silica film 116, and the stopper film 115 are formed with F plasma using CF ₄ / CHF ₃ gas using a resist mask having an opening with a via pattern shape. Etching is performed by changing the composition. After forming the via hole, pad the via hole as necessary, and then use a resist mask having a wiring pattern shaped opening to the entire thickness of the silicon oxide film 119 and the middle of the porous silica film 118. Etching is performed by control etching in which the thickness is F plasma using CF ₄ / CHF ₃ gas and the etching amount is controlled by the etching time.

  A TaN diffusion barrier layer 120 is deposited by sputtering with a thickness of about 50 nm, and a Cu seed layer is deposited thereon by sputtering with a thickness of about 50 nm. A Cu layer 121 is grown to a thickness of about 1400 nm by electrolytic plating, and the metal layer above the protective layer 119 is removed by CMP. In this way, a Cu wiring having a dual damascene structure is formed. A plurality of wiring layers are formed in the same process.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, substitutions, combinations, and the like can be made.

  The features of the present invention will be described below.

(Appendix 1)
(A) a step of spin-coating a porous silica precursor film on the ground of a semiconductor wafer;
(B) including a step of spraying a rinsing liquid from the nozzle while scanning from the outer periphery to the inner side of the porous silica precursor film, and the thickness decreases toward the outer side at the outer peripheral part of the porous silica precursor film. Forming an inclined portion;
(C) curing the porous silica precursor film and converting it to a porous silica film;
A method of manufacturing a semiconductor device including:

(Appendix 2)
The method for manufacturing a semiconductor device according to appendix 1, wherein the porous silica precursor film is formed of a non-template type siloxane resin solution, and the rinse liquid is gamma butyrolactone.

(Appendix 3)
The manufacturing method of the semiconductor device according to claim 1, wherein the step (b) includes a step of inclining a nozzle for injecting a rinsing liquid from 2 degrees to 10 degrees outward and injecting a rinsing liquid from the outside to the inside of the semiconductor wafer. Method.

(Appendix 4)
The manufacturing method of the semiconductor device according to appendix 1, wherein the step (b) forms an edge cut portion from which the porous silica precursor film is removed outside the inclined portion.

(Appendix 5)
The manufacturing method of a semiconductor device according to supplementary note 4, wherein a width of the inclined portion is 0.5 mm or more, and a total width of the inclined portion and the edge cut portion is 4 mm or less.

(Appendix 6)
The step (b)
(B-1) spraying a rinsing liquid on the peripheral edge of the porous silica precursor film to form an edge cut portion having a constant width;
(B-2) a step of spraying a rinsing liquid while scanning from the outer periphery to the inner side of the remaining porous silica precursor film to form the inclined portion;
The manufacturing method of the semiconductor device of Claim 4 including this.

(Appendix 7)
(D) forming an oxide film by CVD on the porous silica film, and forming an interlayer insulating film together with the porous silica film;
(E) a step of embedding copper wiring in the interlayer insulating film by a damascene process;
The method for manufacturing a semiconductor device according to appendix 1, further comprising:

(Appendix 8)
The method of manufacturing a semiconductor device according to appendix 7, wherein the step (d) deposits a silicon oxide film using tetraethoxysilane as a silicon raw material.

(Appendix 9)
(F) The method for manufacturing a semiconductor device according to appendix 7, including a step of repeating the steps (a) to (e) to form a multilayer wiring.

(Appendix 10)
(G) The method for manufacturing a semiconductor device according to appendix 9, including a step of forming an upper interlayer insulating film and an upper wiring after the step (f).

(Appendix 11)
11. The method of manufacturing a semiconductor device according to appendix 10, wherein the upper interlayer insulating film is an oxide film formed by CVD.

(Appendix 12)
12. The method of manufacturing a semiconductor device according to claim 11, wherein the upper interlayer insulating film includes an intermediate interlayer insulating film including a SiOC film and an upper interlayer insulating film including a SiO film.

/ 1A to 1H are cross-sectional views of a semiconductor wafer showing a manufacturing process of a sample for which an experiment was performed, and FIGS. 1I and 1J are cross-sectional views of the semiconductor wafer showing a manufacturing process according to a modification. FIG. 2 is a graph collectively showing the experimental results. / / 3A to 3I are cross-sectional views of a semiconductor wafer showing main steps of a method of manufacturing a semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view of a semiconductor substrate schematically showing a configuration of a semiconductor device fabricated according to an embodiment. 5A and 5B are cross-sectional views of a semiconductor wafer showing a method of manufacturing a semiconductor device according to a modification.

Explanation of symbols

11 Silicon wafer,
12 SiC film,
13 porous silica precursor film,
15 nozzles,
16 Rinse solution,
17 Edge cut part,
18 Inclined part,
19 porous silica membrane,
21 (TEOS) silicon oxide film,
ILD interlayer insulation film,
101 silicon wafer,
102 element isolation region,
103 sidewall spacer,
104 gate electrode,
105 source / drain regions,
106 PSG film,
107 stopper film,
108 barrier film,
109 W film,
110 stopper film,
111 porous silica precursor film,
112 protective film,
113 barrier film,
114 Cu film,
115 stopper film,
116 porous silica precursor film,
117 stopper film,
118 porous silica precursor film,
119 Stopper film

Claims (8)

(A) a step of spin-coating a porous silica precursor film on the ground of a semiconductor wafer;
(B-1) a step of spraying a rinsing liquid onto a peripheral portion of the porous silica precursor film to form an edge cut portion having a constant width from which the polycrystalline silica precursor film is removed;
(B -2) to the end of the remaining porous silica precursor film, while scanning from the outer periphery toward the inside, by injection on the semiconductor wafer to rotate the rinsing liquid from the nozzles, porous silica precursor Forming an inclined portion whose thickness decreases toward the outside at the outer peripheral portion of the film;
(C) curing the porous silica precursor film and converting it to a porous silica film;
A method of manufacturing a semiconductor device including:   The method of manufacturing a semiconductor device according to claim 1, wherein the porous silica precursor film is formed of a non-template type siloxane resin solution, and the rinse liquid is gamma butyrolactone. (A) a step of spin-coating a porous silica precursor film on the ground of a semiconductor wafer;
(B) including a step of spraying a rinsing liquid from the nozzle while scanning from the outer periphery to the inner side of the porous silica precursor film, and the thickness decreases toward the outer side at the outer peripheral part of the porous silica precursor film. Forming an inclined portion;
(C) curing the porous silica precursor film and converting it to a porous silica film;
Including
The step (b), tilted 10 degrees twice a nozzle for jetting the rinsing liquid outwardly, the manufacturing method of the step of injecting a rinsing solution so as to be directed from the outside of the semiconductor wafer on the inside including semiconductors devices. The width of the inclined part is at 0.5mm or more, the total width of the inclined portion and the edge cut portion A method according to claim 1, wherein at 4mm or less. (D) forming an oxide film by CVD on the porous silica film, and forming an interlayer insulating film together with the porous silica film;
(E) a step of embedding copper wiring in the interlayer insulating film by a damascene process;
The method of manufacturing a semiconductor device according to claim 1, further comprising: (F) The method of manufacturing a semiconductor device according to claim 5 , including a step of repeating the steps (a) to (e) to form a plurality of layers of wiring. 7. The method of manufacturing a semiconductor device according to claim 6 , further comprising a step of forming an upper interlayer insulating film and an upper wiring after the step (f). 8. The method of manufacturing a semiconductor device according to claim 7, wherein the upper interlayer insulating film includes an intermediate interlayer insulating film including an SiOC film and an upper interlayer insulating film including an SiO film.

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