JP4811851B2 - Method for cross-linking growth of silicon nanowires - Google Patents

Description

  The present invention relates to a controlled growth method in which single crystal silicon nanowires that can be used as a material for information communication devices such as semiconductors are crosslinked between arbitrary metal particle dots.

  With the progress of nanotechnology, the synthesis of silicon nanowires and their application are attracting attention.

  Under such circumstances, the present inventors have established a method for synthesizing silicon nanowires at a temperature of 300 ° C. or lower by low-temperature CVD of polysilane, and have already proposed this as a new technology (Patent Document 1). .

On the other hand, materials for micromachines and nano-sized semiconductors are considered as applications of silicon nanowires. However, in semiconductor applications, it is desirable that semiconductor wires be directly incorporated into circuits as in lithography techniques. For that purpose, it is necessary to be able to synthesize the wire at as low a temperature as possible. Furthermore, if the nanowire can be grown spontaneously in a direction controlled to an arbitrary position, the circuit configuration becomes easier. As a method for bridging silicon nanowires for such a circuit configuration, a method of producing a wire using thermal decomposition of monosilicon between opposing silicon wafers has been reported (Non-patent Document 1). However, this method has a problem that a high temperature condition of 600 ° C. or more is required for the growth reaction of silicon nanowires, and the formed crosslinked structure is complicated.
Japanese Patent Application No. 2004-307618 M. Saif Islam et al, Nanotechnology, 15, (2004) L5-L8

  The present invention is based on the background as described above, taking advantage of the characteristics of the synthesis method of silicon nanowires already proposed by the present inventors by polysilane CVD, and has a high temperature of 600 ° C. or higher for crosslinking of conventional silicon nanowires. This solves the problem of thermal damage on the circuit, which is unavoidable, and is a complicated cross-linked structure, and at a lower temperature without causing thermal damage on the circuit. It is an object to provide a new technical means capable of forming a crosslinked structure of silicon nanowires in situ.

  The present invention is characterized by the following as means for solving the above problems.

First: A silicon prism column pattern coated with a catalytic metal is disposed at a predetermined position on the substrate surface, and between the silicon prisms coated with the predetermined catalytic metal by CVD at a temperature of 300 ° C. or less of polysilane gas. A method for cross-linking and growing silicon nanowires, characterized in that silicon nanowires are cross-linked and grown.

  Second: A crosslinked structure of silicon nanowires having a crosslinked structure formed by the above method.

  According to the present invention as described above, a crystalline silicon nanowire bridge can be produced at an arbitrary place at a temperature of 300 ° C. or lower without solving the conventional problems and without causing thermal damage to the circuit. For this reason, semiconductor circuit fabrication by nanowire wiring at an arbitrary position can be realized. In addition, the wire size can be controlled by controlling the pressure and flow rate of the reaction gas.

  The present invention is characterized in that silicon nanowires are crosslinked and grown by a CVD method using a polysilane gas.

  The polysilane gas is selected from those which are thermally unstable and decompose to produce Si. For CVD at a temperature of 300 ° C. or less, for example, a gas such as disilane or trisilane is preferably used. It is considered that the CVD temperature is 300 ° C. or less, and more preferably in the range of 250 ° C. to 300 ° C.

  In the cross-linking growth of the silicon nanowire of the present invention, for example, preferably, dots of catalyst metal particles of about 2 μm square or less are prepared in advance by lithography, and the total pressure is 1 to 5 Torr and the polysilane gas flow rate is 0.1 to 1 SCCM. The silicon nanowires are cross-linked between the dots by contacting them on the pattern at a temperature of about 250-300 ° C. Gold, silver, iron, nickel etc. are illustrated as a metal used for a dot. The thickness is desirably about 1 to 5 nm.

  The silicon nanowires that are cross-linked and grown are crystalline and are preferably single crystals. Examples of the substrate on which the silicon nanowires are crosslinked and grown preferably include silicon or silica.

  Therefore, an example will be shown below and will be described in more detail. Of course, the invention is not limited by the following examples.

<Example 1>
In order to grow and control the position of silicon nanowires, it is necessary to pattern catalytic metal particles on a silicon substrate. First, using a SOI (Silicon On Insurator) substrate, Si single crystal dots having a thickness of 2 μm and a 2 μm square are formed on SiO ₂ by etching at intervals of about 15 μm as shown in the plan view of FIG. Subsequently, about 2 nm of gold is coated by sputtering. Furthermore, when the SiO ₂ layer is removed with diluted hydrofluoric acid, a silicon prism pattern covered with gold particles is obtained (FIG. 1b). Here, the symbols in FIGS. 1A and 1B indicate the following.

1: dot spacing of 3-20 μm, 2: metal / silicon pillar, 3: SiO ₂ layer, 4: silicon substrate.

  The actually obtained image is shown in FIG.

The gold dot pattern sample obtained as shown in FIG. 2 is evacuated to 1 × 10 ⁻⁶ Torr in a reaction vessel. The sample is then heated to 296 ° C. When the temperature becomes constant, Si ₂ H ₆ gas (1 SCCM) and argon gas (20 SCCM) diluted to 10% with H ₂ gas are introduced into the container up to 5 Torr, and kept in that state for 20 min. After the experiment, when the substrate surface is observed with an electron microscope, silicon nanowires are generated as shown in FIG. It can be seen that the gold dots are cross-linked.
< Reference Example 1 >
On a silicon substrate, gold is sputter-coated with a thickness of about 2 nm, and a thin scratch having a width of about 15 μm is made. Thereafter, silicon nanowires are formed under the same conditions as in Reference Example 1 . As shown in FIG. 4, it can be seen that crosslinking with silicon nanowires is performed. In FIG. 4, the reaction gas flows from the upper right to the lower left, and a wire is formed substantially along the flow direction.

It is the figure which showed the catalyst metal dot pattern produced by lithography, Comprising: (a) The pattern seen from the top, (b) It is sectional drawing. It is the photograph which showed the example of the catalyst metal dot (2x2x4 (height)) pattern. It is a photograph figure of silicon nanowire which bridged between gold dots. It is a photograph figure of the example of a silicon nanowire bridge.

Explanation of symbols

1 dot spacing 3-20μm
2 Metal / silicon pillar 3 SiO ₂ layer 4 Silicon substrate

Claims (2)

Silicon nanowires are disposed between the silicon prisms coated with a predetermined catalytic metal by CVD at a temperature of 300 ° C. or less of polysilane gas, with a silicon prism column pattern coated with a catalytic metal at a predetermined position on the substrate surface. A method for cross-linking growth of silicon nanowires, characterized by comprising: A crosslinked structure of silicon nanowires having a crosslinked structure formed by the method of claim 1.