JP4811036B2 - PWM control circuit for power converter - Google Patents

Description

  The present invention relates to a pulse width modulation (PWM) control circuit for a switching element in a power converter, and more particularly to a control circuit for reducing EMI (electromagnetic interference) noise.

FIG. 5 shows an example of a boost chopper type power factor correction circuit and its control circuit. In this circuit, the current harmonics flowing through the AC power supply 1 are reduced by controlling the current flowing through the AC power supply 1 in a sine wave form while controlling the voltage across the output terminals 10 and 11 to be constant.
The control operation of the circuit of FIG.
An operational amplifier (voltage error amplifier) 18 amplifies an error between a signal obtained by dividing the voltage across the output terminals 10 and 11 with resistors 14 and 15 and a reference voltage Vr serving as an output voltage command value. The gain and phase of the voltage error amplification are set by resistors 16, 19 and a capacitor 20.

  The output signal of the operational amplifier 18 and the signal obtained by dividing the output terminal voltage of the diode bridge 3 by the resistors 12 and 13 are multiplied by the multiplier 21, and the output of the multiplier 21 is used as a current command value. An error between the current command value and the current flowing through the current detection resistor 9 is amplified by the current error amplifier 23. The gain and phase of the current error amplification are set by resistors 22, 24 and capacitors 25, 26, etc. The output of the current error amplifier 23 becomes a command value of the pulse width, and this is compared with the sawtooth wave signal generated by the carrier signal generation circuit 30 by the comparator 52, and the gate of the switching element 6 is connected via the gate driver 53. To drive.

FIG. 6 shows a specific example of the carrier signal generation circuit.
In FIG. 6, the capacitor 31 is charged and discharged by the constant current circuits 32 and 34 to generate a sawtooth wave carrier signal. The output current of the constant current circuit 32 is set sufficiently smaller than the output current of the constant current circuit 34. When the capacitor 31 is charged, the switch element 33 is off, and the voltage of the capacitor 31 rises gently. When the voltage of the capacitor 31 exceeds the reference voltage Vu that sets the upper limit, the output of the comparator 37 becomes high (H) level and the flip-flop circuit 39 is set, and the output (Q) becomes H level and the switch element 33. Turn on. As a result, the capacitor 31 is rapidly discharged by the difference current between the output current of the constant current circuit 34 and the output current of the constant current circuit 32.

When the voltage of the capacitor 31 falls below the reference voltage Vb that sets the lower limit, the output of the comparator 38 becomes H level and the flip-flop circuit 39 is reset, and its output (Q) becomes low (L) level and the switch element 33. Turn off.
Thereafter, the voltage of the capacitor 31 is repeatedly charged and discharged between the voltages set by the reference voltages Vu and Vb. The frequency of the carrier signal is determined by the output current value of the constant current circuits 32 and 34 and the capacitance value of the capacitor 31.

In the case of FIG. 5, when the pulse width command value exceeds the carrier signal, the switching element 6 is turned on. The frequency of the carrier signal is equal to the switching frequency of the switching element 6, but the on timing is fixed and the off timing is pulse width controlled.
If the EMI noise level generated at the on timing is greater than that generated at the off timing, the EMI noise level near the switching frequency is generated to be large, and the noise filter indicated by symbol 2 in FIG. It will be enlarged.

In order to solve the above problems, a technique for dispersing the EMI noise level near the switching frequency and changing the peak value of the noise component by changing the carrier frequency randomly or continuously is disclosed in Patent Document 1, for example. 2 is disclosed.
Japanese Patent Application Laid-Open No. 07-264849 JP 2002-064979 A

However, in the case of the control methods such as Patent Documents 1 and 2, magnetic components such as a transformer and an inductor may be saturated at the timing when the switching frequency is lowered. However, there is a problem that the magnetic parts become large and expensive.
Therefore, an object of the present invention is to easily and inexpensively reduce the EMI noise level while maintaining the design at the conventional fixed frequency.

In order to solve such a problem, according to the first aspect of the present invention, in the power conversion device that converts the power supply voltage into a DC voltage by the on / off operation of the switching element, the on / off timing of the switching element is set to a carrier signal and a pulse width command value In the PWM control circuit of the power conversion device that is determined by comparing the size and
First control means for controlling the switching element ON timing as a fixed period and controlling the OFF timing thereof for pulse width, and second control means for controlling the switching element OFF timing as a fixed period and controlling the ON timing for pulse width And a signal input terminal for inputting a signal indicating which of the first and second control means is to be valid .
In the invention of claim 1, the first and second control means and the signal input terminal can be integrated (invention of claim 2).

  According to the present invention, since the EMI noise level can be reduced without changing the carrier frequency, magnetic parts such as transformers and inductors can be made smaller than the conventional method in which the carrier frequency is changed randomly or continuously, and as a result, noise is reduced. The advantage that the filter can also be reduced in size is obtained.

  FIG. 1 is a circuit diagram showing an embodiment of the present invention. This is configured by adding constant current circuits 44 and 47, switch elements 45 and 46, a knot circuit 49, AND circuits 50 and 51, and the like to the circuit shown in FIG. Here, the output current of the constant current circuit 40 is set to be sufficiently smaller than the output current of the constant current circuit 43. Further, the output current of the constant current circuit 44 is set to be approximately equal to the output current of the constant current circuit 43, and the output current of the constant current circuit 47 is set to be approximately equal to the output current of the constant current circuit 40. When the signal input IN is set to H level, the switch element 41 is turned on. Further, the output of the knot circuit 49 becomes L level and the switch element 46 is turned off. Further, the output of the AND circuit 50 becomes L level, and the switch element 45 is turned off. As a result, the same operation as in FIG. 6 is performed.

In FIG. 1, when the signal input IN is set to L level, the switch element 41 is turned off, and the output of the AND circuit 51 becomes L level, and the switch element 42 is turned off. Further, the output of the knot circuit 49 becomes H level, and the switch element 46 is turned on.
Here, when the switch element 45 is turned on, the capacitor 31 is rapidly charged. When the reference voltage Vu that sets the upper limit is exceeded, the output of the comparator 37 becomes a high (H) level, and the flip-flop circuit 39 is set. The output QB becomes L level, and the switch element 45 is turned off.

As a result, the capacitor 31 is slowly discharged by the output current of the constant current circuit 47. When the voltage of the capacitor 31 falls below the reference voltage Vb that sets the lower limit, the output of the comparator 38 becomes H level when the voltage of the capacitor 31 falls below the reference voltage Vd that sets the lower limit. The output circuit (QB) becomes H level and the switch element 45 is turned on.
Thereafter, the voltage of the capacitor 31 is repeatedly charged and discharged between the voltages set by the reference voltages Vu and Vd. The frequency of the carrier signal is determined by the output current values of the constant current circuits 44 and 47 and the capacitance value of the capacitor 31.

From the above, if the signal input IN is set to H level, the carrier signal has a gradual rise and a steep fall. Conversely, if the signal input IN is set to the L level, the carrier signal has a sharp rise and a slow fall.
As a result, by setting the signal input IN to the H level in the circuit of FIG. 1, the on timing becomes a fixed period as shown in FIG. 2A, and the off timing is pulse width controlled. Conversely, when the signal input IN is set to the L level, the off timing becomes a fixed period as shown in FIG. 2B, and the on timing is subjected to pulse width control.

Therefore, as shown in FIG. 3A, when the noise level at the off timing is large, the signal input IN is set to the H level so that the off period changes, as shown by the solid line in FIG. The peak level of noise is reduced as shown by the dotted line.
Further, as shown in FIG. 3B, when the noise level at the on timing is large, the signal input IN is set to the L level and the on period is changed, so that the noise peak is similar to the above. The level is reduced.
In FIG. 3, G indicates a gate signal waveform, and N indicates a noise waveform.

  In the step-up chopper type power factor correction circuit as shown in FIG. 5, since the instantaneous value of the input AC voltage continuously changes, the pulse width also changes continuously, and the same effect as the conventional carrier frequency changing method is obtained. However, under the condition of a constant input voltage and constant load with a DC / DC converter, etc., the ON and OFF timings are the same, so no noise reduction effect can be obtained, but the output of the power factor correction circuit is used as the input power supply. In a DC / DC converter that uses a voltage, as the input power supply voltage fluctuates at twice the frequency of the AC power supply frequency, the pulse width command value also fluctuates at the same frequency, so that a noise reduction effect can be obtained. .

  In addition, it is necessary to examine in advance which noise level is greater at the on and off timings. As a method for this, the input signal of the spectrum analyzer that measures the noise and the gate drive signal or switching waveform of the switching element are used with an oscilloscope. It can be determined by measuring at the same time. In this regard, noise is measured with the power supply circuit finally installed in the product, and the noise generated by the product is effectively suppressed by selecting whether the load is fixed to on or off. be able to. Alternatively, noise may be measured in two cases of fixed on-timing and fixed off-timing, and one of the smaller noises may be selected. Note that the cost of the circuit in FIG. 1 can be further reduced by making it an integrated circuit.

Circuit diagram showing an embodiment of the present invention Waveform diagram explaining the PWM method Operation explanatory diagram of FIGS. 1 and 5 Explanatory drawing explaining the effect of this invention Circuit diagram showing a conventional example Circuit diagram showing the carrier signal generation circuit used in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... AC power source, 2 ... Noise filter, 3 ... Diode bridge, 4 ... Filter capacitor, 5 ... Inductor, 6 ... Switching element, 7 ... Diode, 8 ... Smoothing capacitor, 9 ... Current detection resistor, 10, 11 ... Output terminal 12, 12, 13, 14, 15, 16, 19, 22, 24, 28, 29 ... resistors, 18 ... voltage error amplifiers (op amps), 20, 25, 26 ... capacitors, 21 ... multipliers, 23 ... current error amplifiers (Op-amp), 30, 30a, 30b ... carrier signal generation circuit, 37, 38, 52 ... comparator, 39 ... flip-flop circuit, 40, 43, 44, 47 ... constant current circuit, 41, 42, 45, 46 ... switch Element 49... NOT circuit 50, 51 AND circuit 53 Gate driver Vc Control reference voltage Vr u, Vb ... reference voltage.

Claims (2)

In a PWM control circuit of a power conversion device that determines the on / off timing of the switching element by comparing the magnitude of a carrier signal and a pulse width command value in a power conversion device that converts a power supply voltage into a DC voltage by an on / off operation of the switching element. ,
First control means for controlling the switching element ON timing as a fixed period and controlling the OFF timing thereof for pulse width, and second control means for controlling the switching element OFF timing as a fixed period and controlling the ON timing for pulse width And a signal input terminal for inputting a signal indicating which of the first and second control means is to be valid, and a PWM control circuit for a power converter. The PWM control circuit for a power converter according to claim 1, wherein the first and second control means and the signal input terminal are integrated.

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