JP4810328B2 - Video playback device - Google Patents

Description

  The present invention relates to a video reproduction apparatus capable of performing progressive-interlace conversion.

  2. Description of the Related Art Conventionally, there has been known a video reproducing apparatus that can read digital data recorded on a recording medium and reproduce video and audio. As this type of video playback apparatus, there is a disk playback apparatus that uses an optical disk as a recording medium. In particular, in recent years, DVD players that use optical discs according to the DVD (digital versatile disk) standard have become widespread.

  Among DVD players, a DVD player according to the conventional DVD standard outputs a video signal to a display device that displays video, and the output video signal is an interlace method (interlace scanning method, frame rate: 29.97 Hz, 25.25 Hz). 0 Hz). In a DVD player, in addition to an interlace display device (CRT) as a display device for displaying video, a progressive display device (sequential scanning method, frame rate: 59.94 Hz, 50.0 Hz) (a liquid crystal display device or a plasma display device). Equipped with a device that converts video signals from interlaced to progressive format when a progressive display device is connected, because a thin television receiver such as a display device may be connected. Has been.

Here, with regard to an apparatus for converting from the interlace system to the progressive system, for example, there has conventionally been a signal converter as described below. In this signal conversion device, an interlace synchronization signal of N scanning lines is converted into a progressive synchronization signal of N / 2 scanning lines in accordance with the control information.
Japanese Patent Laid-Open No. 10-285559

  By the way, the conventional DVD player is, for example, a progressive method (frame rate of 59.94 Hz) in addition to the interlace method, such as a DVD player (hereinafter referred to as “HD DVD player”) based on the HD DVD (High Definition DVD) standard. And 50 Hz) may be permitted.

  However, since such a DVD player also displays the decoded frame according to the display control information included in the input video stream, if the output request in the progressive format is described in the display control information, the decoder Video signals are output in a progressive manner. However, even in such a case, when an interlace display device is connected, the video signal must be output in the interlace format. For this purpose, the progressive video is changed from the progressive format to the interlace format. Conversion must be done. In order to perform such progressive-interlace conversion, a change due to the addition of new hardware such as a frame memory is unavoidable.

  Therefore, the present invention has been made to solve the above-described problems. In a video playback apparatus such as an HD DVD player in which video signals are output in an interlace format and a progressive format, a hardware such as a new frame memory is added. An object of the present invention is to realize progressive-interlaced conversion for a decoded video signal without any change.

In order to solve the above-described problem, the present invention generates a frame by decompressing compressed video data included in an input video stream, and displays the defined frame scanning method included in the compressed video data. A video decoder that outputs the generated frame according to control information and a frame rate; and the frame rate of the compressed video data that is arranged before the video decoder and the scanning method of the display control information is a progressive method And rewriting means for rewriting the scanning method of the display control information to the interlace method, and the rewriting means has a frame rate of 59. 5 for the compressed video data. In the case of 94 Hz or 50 Hz, the frame rate is 29.97 Hz. It is characterized in that rewriting in 25 Hz.

  As described above in detail, according to the present invention, in a video playback apparatus such as an HD DVD player in which a video signal is output in an interlace format and a progressive format, it does not depend on a hardware change such as newly adding a frame memory. Progressive-interlaced conversion for the decoded video signal can be realized.

  Embodiments of the present invention will be described below. In addition, the same code | symbol is used for the same element and the overlapping description is abbreviate | omitted.

  FIG. 1 is a block diagram showing a configuration of a video playback apparatus 1 according to an embodiment of the present invention. As shown in FIG. 1, the video reproduction apparatus 1 includes a demultiplexer (Demux) 10, a video decoder (Video Decoder) 20, a frame buffer (Frame Buffer) 30, a video encoder (Video Encoder) 40, and main processing. Part (Main Process) 50. In the present embodiment, it is assumed that the video reproduction apparatus 1 is an HD-DVD player using a DVD as a recording medium. However, the present invention provides an HD-video in which video signals are output in an interlace format and a progressive format. This also applies to DVD players other than DVD players.

  The demultiplexer 10 is arranged before the video decoder 20 and converts the input MPEG-2 program stream (Program Stream) ps into video packet (Video Packet) vp, sub-picture packet including audio and subtitle information ( Audio & Sub-pic Packet) ap is performed, and each is output to a corresponding decoder.

  Further, the demultiplexer 10 constitutes the rewriting means in the present invention, and when an instruction command ic, which will be described later indicating the output in the progressive method, is not input, the demultiplexer 10 outputs in the interlaced method, so that the payload of the video packet ( The display control information (pic_struct) included in the portion excluding the packet header) and the frame rate are rewritten. The video packet vp is input from the demultiplexer 10 to the video decoder 20.

  The video decoder 20 and other decoders (not shown) output the decoded data according to the display time information (PTS) included in each input packet.

  Here, as shown in FIG. 1, the video decoder 20 includes a decoding processing unit (Decode Process) 21, a post processing unit (Post Process) 22, and a host processing unit (Host Process) 23.

  The decode processing unit 21 decompresses the compressed video data included in the video packet vp to generate frames 31, 32, 33, 34..., And the generated frames 31, 32, 33, 34. -Is written into the frame buffer 30. Further, the decode processing unit 21 generates timing control information (Timing Information) 35 to be described later, and outputs the generated timing control information 35 to the post processing unit 22.

  4 and 5, the timing control information 35 includes a frame buffer number 35a of the frames 31, 32, 33, 34,... Written in the frame buffer 30, display control information (pic_struct) 35b, PTS (PTS of I picture described in video packet vp, display control information 35b and PTS of other picture obtained by interpolation calculation from frame rate and PTS of other picture) 35c ing.

  The timing control information 35 shown in FIG. 4 shows an example when a digital video signal (Digital Video Output) vd, which will be described later, is output in a progressive manner. In this timing control information 35, the display control information 35b is "8", "7" for the four frames whose frame buffer numbers 35a are "2", "3", "0", "1", respectively. “,” “8” and “7”, and the PTS 35c is set to PTS0, PTS1, PTS2 and PTS3.

  Further, the timing control information 35 shown in FIG. 5 shows an example when the digital video signal vd is output by the interlace method. In this timing control information 35, the display control information 35b is "5", "4" for the four frames whose frame buffer numbers 35a are "2", "3", "0", "1", respectively. “6”, “3”, and PTS 35c is set to PTS0, PTS1, PTS2, and PTS3. The display control information 35b will be described in detail later.

  The post processing unit 22 receives the timing control information 35 output from the decoding processing unit 21 and the synchronization signal STC generated by a clock generator (CG). Further, the post processing unit 22 transmits frames 31, 32, 33, 34... From the frame buffer 30 according to the display control information 35b included in the input timing control information 35 and the frame rate included in each frame. The read frame is read, and a digital video signal (digital video output) vd is output.

  The host processing unit 23 receives an instruction command (Instruction) ic to be described later from the main processing unit 50, and decodes control means for controlling the operation of each processing block (the decoding processing unit 21 and the post processing unit 22) in the video decoder 20. Is configured.

  A video encoder 40 is provided outside the video decoder 20 (after the video decoder 20). The video encoder 40 receives the digital video signal vd output from the video decoder 20, converts the digital video signal vd into an analog video signal ad, and the analog video signal ad is connected to the outside. Output to a display device (not shown).

  Further, the video encoder 40 has a function as a field signal input means for inputting a field signal (Field ID) fd and a video synchronization signal (Video Sync) vs, which will be described later, to the post processing unit 22.

  The main processing unit 50 inputs a user command (User Instruction) uc generated by a user's remote control operation or output from an external device. Then, the main processing unit 50 generates an instruction command ic (instruction information in the present invention) according to the input user command uc, and inputs the generated instruction command ic to the demultiplexer 10, the video decoder 20, and the video encoder 40. It has a function as instruction information input means. The user command uc may indicate a request for progressive output (progressive output) or a request for output (interlaced output) by an interlace method.

  Then, when the demultiplexer 10, the video decoder 20, and the video encoder 40 operate according to the instruction command ic, progressive-interlace conversion in the video reproduction apparatus 1 is performed.

  Next, an operation procedure when progressive-interlace conversion, which is a feature of the present invention, is performed in the video reproduction apparatus 1 having the above-described configuration will be described.

  6 to 8 are flowcharts showing respective operation procedures of the main processing unit 50, the video encoder 40, and the demultiplexer 10 when the progressive-interlace conversion is performed in the video reproducing apparatus 1. FIG.

  As shown in FIG. 6, the main processing unit 50 determines in step 1 whether or not a user command uc indicating a request for progressive output has been input (whether or not a progressive output request has been input), and requests a progressive output. When the user command uc indicating is input, the process proceeds to step 2; otherwise, the process proceeds to step 3. When the process proceeds to step 2, the main processing unit 50 outputs an instruction command (progressive output command) ic indicating progressive output to the video encoder 40 and the demultiplexer 10. Further, when the process proceeds to step 3, the main processing unit 50 outputs an instruction command (interlace output command) ic indicating interlace output to the video encoder 40 and the demultiplexer 10.

  Next, as shown in FIG. 7, the video encoder 40 determines whether or not the progressive output command ic is input in step 11, and when the progressive output command ic is input, the process proceeds to step 12. If not, the process proceeds to Step 13. When the video encoder 40 proceeds with the process to step 12, it fixes the field signal fd (a signal indicating first field output or second field output) to “Low” and outputs it to the post processing unit 23. Further, when the video encoder 40 proceeds to step 13, the post encoder 23 generates the field signal fd that alternately switches between “Low” and “High” so that the digital video signal vd is output in an interlaced manner. Output to.

  On the other hand, as shown in FIG. 8, the demultiplexer 10 determines whether or not the progressive output command ic has been received in step 21. If the progressive output command ic is received, the process proceeds to step 22. If so, the process proceeds to step 23. When the process proceeds to step 22, the demultiplexer 10 performs the packet separation process, but does not rewrite the display control information 35b and the frame rate. In this case, the process ends thereafter.

  In addition, when the demultiplexer 10 advances the process to step 23, in this case, an instruction command (interlace output command) ic indicating interlace output is input and becomes an interlace output. Therefore, the demultiplexer 10 performs packet separation processing and rewrite means. The display control information 35b included in the payload of the video packet vp (the part excluding the packet header) in the program stream ps and the frame rate rewriting (in this rewriting, the frame rates are 59.94 Hz and 50 Hz). 29.97 Hz and 25.0 Hz are switched and the progressive method is switched to the interlace method), and then the process ends.

  Here, the display control information 35b is information for controlling video display using the decoded frame, and takes values from “0” to “8” and other values as shown in FIG. It is supposed to be.

  For example, pic_struct = “3” reads each line of the decoded frame in accordance with the frame rate (every 1 / 29.97 seconds if the frame rate = 29.97 Hz), and the top line by interlaced scanning ( This means that the lines are displayed alternately in the two fields in the order of the line displayed first (Top) and the bottom line (line displayed next to the top line, Bottom). Also, pic_struct = “4” means that each line is alternately displayed in two fields in the order of bottom line and top line by interlaced scanning.

  Furthermore, pic_struct = “5” means that each line is alternately displayed in two fields in the order of the top line and the bottom line by interlaced scanning, and then the top line is displayed in the next field. pic_struct = “6” means that each line is alternately displayed in two fields in the order of bottom line and top line by interlaced scanning, and then the bottom line is displayed in the next field.

  Then, pic_struct = “7” displays the decoded frame twice (by sequential scanning) according to the frame rate (every 1 / 59.94 seconds if the frame rate = 59.94 Hz), and pic_struct = “8” means that the decoded frame is displayed three times.

  By processing as described above, when the user command uc indicates a request for interlace output (when a request for progressive output is not indicated), the main processing unit 50 outputs the interlace output command ic. The multiplexer 10 rewrites the display control information 35b and the frame rate. Then, for example, the timing information 35 is as shown in FIG. 4 before rewriting, but the display control information 35b is rewritten as shown in FIG.

  The rewritten display control information 35 b is output from the decode processing unit 21 to the post processing unit 23 as timing information 35. The post processing unit 23 reads a frame from the frame buffer 30 according to the rewritten frame rate, and displays a picture while controlling the display of each line according to the display control information 35b included in the timing information 35. The field signal fd is also input to the post processing unit 23 so as to be output in an interlaced manner. Therefore, progressive-interlace conversion is performed as shown in FIG.

  Here, the timing information 35 in FIG. 4 is that the pic_struct is “8”, “7”, “8” in order for the frame buffers of the frame buffer numbers: “2”, “3”, “0”, “1”. , “7” (these pic_structs correspond to progressive data indicating that the frame is output in a progressive manner), so that the frame output (digital video signal vd) from the video decoder 20 is shown in FIG. It was output as in 3 (a).

  However, in FIG. 5, the display control information 35b is “5”, “4”, “6”, “3” in order for the frame buffers of the frame buffer numbers: “2”, “3”, “0”, “1”. (These pic_structs correspond to interlaced data indicating that the frame is output in an interlaced manner), so that the frame output from the video decoder 20 is as shown in FIG. 3B. .

  In FIG. 3A, the field signal fd remains “LOW”, and each frame is sequentially scanned in the order of the top line and the bottom line, and is output, and the frame rate is 59.94 Hz.

  Further, in FIG. 3B, the field signal fd is output as “LOW” and “HIGH” alternately, and each line is alternately scanned in two fields in the order of top line and bottom line. , The frame rate is 29.97 Hz (the white circles in FIGS. 3, 4 and 5 indicate the top line, and the black circles indicate the bottom line).

  As described above, in the video reproduction apparatus 1, the video decoder 20 reads the frame according to the frame rate according to the frame rate and outputs the digital video signal vd so that the picture display is performed according to the display control information 35b. As shown in 3 (a) and 3 (b), the display control information 35b and the frame rate are rewritten to be output in the interlace method, and the field signal fd is output to be output in the interlace method. The digital video signal vd can be output in an interlaced manner.

  Therefore, in the video reproduction apparatus 1, hardware such that progressive-interlace conversion is performed in response to addition or change of functions to existing configurations such as the demultiplexer 10, the video decoder 20, and the video encoder 40, and a frame memory is newly added. Progressive-interlace conversion can be realized without any change.

  The “PTS interpolation calculation” will be described as follows. In the DVD standard (conventional DVD and HD DVD standards), normally only the I picture PTS (Presentation Time Stamp) is described in the stream. Therefore, the PTS of other pictures (P picture, B picture) is obtained by interpolation calculation in the decoding processing unit 21 of the video decoder 20.

  For example, when the PTS of the I picture is “PTS0”, the PTSs of the pictures other than the I picture are calculated in the display order as follows (PTS is indicated in units of 90 kHz).

PTS [n] = PTS [n−1]
+ (Num_of_repeat [n-1] x picture_period)
Where n ≧ 1
picture_period = 90000 / 59.94≈1501.5
num_of_repeat [n−1] indicates the number of picture repetitions for the (n−1) th picture.

For example, the display control information (pic_struct) shown in FIG.
If pic_struct = "3", num_of_repeat = 2
If pic_struct = "4", num_of_repeat = 2
If pic_struct = "5", num_of_repeat = 3
If pic_struct = "6", num_of_repeat = 3
If pic_struct = "7", num_of_repeat = 2
If pic_struct = “8”, num_of_repeat = 3

  In the above embodiment, the case where the rewriting unit is configured by the demultiplexer 10 is described as an example, but the function of the rewriting unit may be realized by another unit. The present invention can also be applied to a video playback device (video / audio playback device) capable of playing back audio in addition to video.

  The above description is the description of the embodiment of the present invention, and does not limit the apparatus and method of the present invention, and various modifications can be easily implemented. In addition, an apparatus or method configured by appropriately combining components, functions, features, or method steps in each embodiment is also included in the present invention.

It is a block diagram which shows the structure of the video reproduction apparatus concerning embodiment of this invention. It is a figure which shows an example of display control information. FIG. 4 is a diagram showing time, field ID, video synchronization signal, frame output, and display control information in progressive output and interlaced output, where (a) shows the case of progressive output and (b) shows the case of interlaced output. It is a figure which shows an example of the display control information and frame before rewriting. It is a figure which shows an example of the display control information and frame after rewriting. It is a flowchart which shows the operation | movement procedure of a main process part. It is a flowchart which shows the operation | movement procedure of a video encoder. It is a flowchart which shows the operation | movement procedure of a demultiplexer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Video reproduction apparatus, 10 ... Demultiplexer, 20 ... Video decoder 21 ... Decoding processing part, 22 ... Post processing part, 23 ... Host processing part 30 ... Frame buffer, 35 ... Timing control information 35b ... Display control information, 40 ... Video encoder, 50 ... main processing section

Claims (6)

The compressed video data included in the input video stream is decompressed to generate a frame, and the generation is performed according to display control information and a frame rate defined in the generated frame scanning method included in the compressed video data. A video decoder for outputting the frame,
The frame rate of the compressed video data, which is arranged before the video decoder and the scanning method of the display control information is a progressive method, is rewritten to a value corresponding to the output of the interlace method, and the scanning of the display control information Rewriting means for rewriting the method to the interlaced method,
Have
The video rewriting device , wherein the rewriting means rewrites the frame rate to 29.97 Hz or 25 Hz when the frame rate of the compressed video data is 59.94 Hz or 50 Hz.   Field signal input means for generating a field signal for controlling the frame output from the video decoder to be output by either the progressive method or the interlace method, and inputting the frame signal to the video decoder is further provided. The video reproduction apparatus according to claim 1. Further comprising instruction information input means for inputting instruction information indicating either progressive output or interlace output to the rewriting means;
The rewriting means rewrites the frame rate and the display control information when the instruction information indicates the interlace output, and rewrites the frame rate and the display control information when the instruction information indicates the progressive output. The video playback apparatus according to claim 1, wherein the video playback apparatus is configured not to perform video. Further comprising instruction information input means for inputting instruction information indicating either progressive output or interlace output to the field signal input means;
The field signal input means inputs the field signal so that the frame is output by the interlace method when the instruction information indicates the interlaced output, and when the instruction information indicates the progressive output, 3. The video reproducing apparatus according to claim 2, wherein the field signal is input so that a frame is output by the progressive method. A frame buffer in which the frame generated by the video decoder is written;
5. The video reproducing apparatus according to claim 1, wherein the video decoder reads out and outputs the frame written in the frame buffer according to the display control information.   6. The video reproduction apparatus according to claim 1, wherein the rewriting unit is configured by a demultiplexer that separates the video stream from an input program stream.

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