JP4808240B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to an embedded DRAM (dynamic random access memory) having a very large internal bus width.

  In recent years, with the progress of miniaturization of semiconductor memory devices, research and development of system LSIs in which a DRAM (dynamic random access memory) and a logic circuit are mixedly mounted on one chip have been actively conducted. One of the features of such a DRAM / logic mixed chip is that the internal bus width between the DRAM and the logic circuit is reduced by a wiring layer on the chip as compared with the case where the DRAM chip and the logic chip are mounted on the board. By using it, the data transfer rate between the DRAM and the logic circuit can be remarkably increased because it can be remarkably widened. Here, “the internal bus width is wide” means that a large amount of data can be simultaneously read from and written to the memory cell array in the DRAM. This means that the global input / output lines are turned on and activated simultaneously to transfer a large amount of data through the global input / output lines at once.

  In a normal DRAM, the internal bus width is about 32 to 64 bits, and there are about 32 to 64 pairs of global input / output lines corresponding thereto. On the other hand, the DRAM / logic mixed DRAM core has an internal bus width of about 128 to 256 bits and is said to expand to about 1024 to 2048 bits in the future. The number will be needed.

  The global input / output line is a read / write data transfer path, and usually includes a write driver, a global input / output line precharge circuit, an amplifier circuit, and the like for each global input / output line.

  When the internal bus width is small as in a normal DRAM, the power consumption by these circuits is small. Therefore, as shown in FIG. 27, the internal power supply voltage Vcc1 is supplied to the write driver 23 and the global input / output line precharge circuit 24 by the internal power supply circuit 101 common to other circuits such as the sense amplifier 25 and the peripheral circuit 90. Have been supplied. In recent DRAMs, an internal power supply circuit (VDC: Voltage Down Converter) is generally provided in a chip from the viewpoint of reducing power consumption and ensuring reliability.

  In a memory (DRAM) / logic mixed LSI, the gate oxide film of the transistor tends to be thinned in order to ensure a sufficient operation speed of the transistor in the logic region. In order to use transistors of the same size in a DRAM memory cell under the gate array configuration, it is necessary to lower the voltage level of the power source of the memory cell array, that is, the power source for sense amplifier operation, from the viewpoint of ensuring reliability.

  By reducing the voltage level of the memory cell array power supply, the current consumption in the memory cell array can be suppressed, and the effect of reducing the power consumption is great in a memory that handles a large capacity.

  On the other hand, with the increase in memory capacity, in order to efficiently exchange data with the outside, technologies for hierarchical I / O line (input / output line) DRAM and multi-bit DRAM have been developed. ing.

  FIG. 28 shows the overall configuration of a DRAM 500 having a hierarchical I / O line configuration. Referring to FIG. 28, DRAM 500 includes four memory mats 501 and a peripheral circuit 505 divided into 16M bits.

  FIG. 29 shows the configuration of the memory mat 501 in detail. Referring to FIG. 29, memory mat 501 is further divided into sub-blocks 505 by sense amplifier band 504 in which sense amplifiers are arranged and word line shunt region 502. Each sub-block 505 includes 32K memory cells formed by 256 word lines WL and 128 sense amplifiers. That is, the 16 Mbit memory mat 501 is divided into 16 parts by the sense amplifier band 504 and the word line shunt region 502.

  The column selection line CSL in the memory mat 501 is selected by the column decoder 510 provided at the end of the memory mat 501. Column selection line CSL is provided as a signal line common to memory cells having the same column address included in memory mat 501 and extending in the column direction in common to a plurality of sub-blocks.

  FIG. 30 is a diagram for showing the structure of the I / O line of DRAM 500. Referring to FIG. 30, DRAM 500 includes a pair of local input / output lines LI / O, / LI / O provided for every two sub-blocks 505. In response to activation of the column selection line CSL, the data of the selected memory cell is amplified by the sense amplifier and then transmitted to LI / O and / LI / O. LI / O and / LI / O are connected to a global input / output line pair GI / O and / GI / O by a transfer gate 520. GI / O and / GI / O read / write data from / to the outside via the main amplifier and write driver 530.

  FIG. 31 is a diagram showing the configuration of the transfer gate 520 in detail. Referring to FIG. 31, transfer gate 520 connects LI / O, / LI / O and GI / O, / GI / O, and receives subblock selection signal BS at the gate. Receiving transistors 521 and 522 are provided. Transistors 521 and 522 are turned on in response to activation of bank selection signal BS, and data is transferred between LI / O, / LI / O and GI / O, / GI / O. Transmission takes place.

  As described above, the I / O lines are hierarchized by the local input / output lines and the main input / output lines, and the memory mat 501 is operated independently for each group of the sub-blocks 505, thereby transferring data to / from the outside. Can be performed more efficiently.

  Next, the configuration of the multi-bit DRAM will be described. FIG. 32 is a schematic diagram showing a configuration of multi-bit DRAM 600.

  Referring to FIG. 32, DRAM 600 includes a memory mat 501 divided into a plurality of sub blocks 505. DRAM 600 further includes column decoder 510, word line driver 550, and main amplifier block 560 adjacent to memory mat 501. The main amplifier 560 includes a plurality of main amplifiers.

  In DRAM 600, column decoder 510 is provided beside row decoder 550 disposed at the end of memory mat 501. Column selection line CSL is selected by column decoder 510 and is provided to extend in a direction parallel to word line WL on sense amplifier band 504 provided between the sub-blocks. Main input / output line pair MI / O, / MI / O is provided as a signal line common to sub-blocks 505 adjacent in the column direction, and is included in main amplifier band 560 at the end of memory mat 501. Connected to each amplifier. Through the main amplifier, MI / O and / MI / O read / write data from / to the outside.

  FIG. 33 is a schematic diagram for illustrating the configuration of DRAM 600 in detail. Referring to FIG. 33, in sub-block 505, as an example, main input / output line pair MI / O, / MI / O has 128 input / output line pairs MI / O1, / M- I / O1 to MI / O128 and / MI / O128. Under this configuration, each of M-I / O1, / M-I / O1 to M-I / O128, / M-I / O128 has four bit line pairs BL, / BL included in sub-block 505. Is provided. Each of bit line pair BL, / BL is connected to sense amplifiers SA1-SA512 included in sense amplifier band 504, respectively. The sense amplifiers SA1 to SA512 amplify the data stored in the memory cells transmitted from the bit line pairs BL and / BL, and pass through the transmission gate pairs N1 to N512 to the main input / output line pairs MI / O1, / It is connected to MI / O1 to MI / O128, / MI / O128. Transmission gates N1-N512 include N-type transistors that receive column select line CSL at their gates and connect a sense amplifier and a main-I / O line pair.

  In response to the activation of the column selection line CSL, 128 pairs of transmission gates are turned on at the same time, and one column is formed by MI / O1, / MI / O1 to MI / O128, / MI / O128. In accordance with the selection operation, 128-bit data can be exchanged with the outside.

  Thus, in multi-bit DRAM 600, the number of processing data per column selection operation can be designed more than before.

  When the number of global input / output lines is large as in the case of a DRAM / logic mixed DRAM core, the power consumed by the write driver 23 and the global input / output line precharge circuit 24 is particularly large. This is because the write driver 23 consumes power associated with charging / discharging of global input / output lines, and the global input / output line precharge circuit 24 consumes power associated with precharging operations of global input / output lines. Therefore, as shown in FIG. 27, when the write driver 23 and the global input / output line precharge circuit 24 use an internal power supply circuit common to other circuits such as the sense amplifier 25 and the peripheral circuit 90, the write driver 23 When the global input / output line precharge circuit 24 is operated, the large current consumption causes the internal power supply voltage to drop or bounce, which causes other circuits to malfunction.

  The present invention has been made to solve the above problems, and its purpose is that other circuits such as sense amplifiers and peripheral circuits are affected by the operation of the write driver and global I / O line precharge circuit. There is no semiconductor integrated circuit device.

  On the other hand, as described above, particularly in an embedded DRAM, it is necessary to lower the voltage level of the power supply of the memory cell array. Under this condition, the voltage level of the write driver power supply for writing data transmitted from the outside is set to the same level as the power supply voltage for driving peripheral circuits such as a logic circuit as in the conventional case. Will arise.

  That is, since the power supply voltage level of the write driver corresponds to the amplitude level of the I / O line, the amplitude level of the I / O line is large, so that the I / O line performed prior to the data writing and reading operations. The time required for the equalizing operation becomes longer.

  In particular, the data read operation after the data write operation is particularly problematic because the operation speed is limited by the time required for the equalize operation, and as a result, it is difficult to increase the operation speed of the DRAM.

  In the embedded DRAM, since the data bus width is wide as described above, the number of data handled at one time, that is, the number of activated I / O lines is remarkably increased. For this reason, the amplitude level of the I / O line greatly affects the power consumption of the entire DRAM.

  Further, as the voltage level of the memory cell array power supply is reduced, it is difficult to configure the transfer gate used when the hierarchical-I / O line method is adopted for the DRAM only with the N-type transistor as shown in FIG. become. This is because the voltage level corresponding to the “H” level of the data is lowered as the voltage level of the sense amplifier power supply is lowered, so that the “H” level data is composed of only N-type transistors. This is because the transfer gate cannot obtain a sufficient voltage level due to the influence of the threshold voltage drop of the N-type transistor.

  Another object of the present invention is to provide a semiconductor integrated circuit device having a write driver and a transfer gate that can cope with various problems caused by lowering the voltage level of the memory cell array power supply, that is, the sense amplifier power supply as described above. It is.

According to one aspect of the present invention, a semiconductor integrated circuit device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a local input / output line pair, a plurality of column selection gates, and a global input / output line. A pair, a transfer gate, a first internal power supply means, a second internal power supply means, a sense amplifier, a write driver, and a voltage balancing means are provided. The memory cell array has a plurality of memory cells arranged in a plurality of rows and a plurality of columns. The plurality of word lines are provided corresponding to a plurality of rows, respectively. The plurality of bit line pairs are provided corresponding to a plurality of columns, respectively. The plurality of column selection gates are provided corresponding to the plurality of bit line pairs, respectively, and each is connected between the corresponding bit line pair and the local input / output line pair. The transfer gate is connected between the local input / output line pair and the global input / output line pair. Each of the first and second internal power supply circuit generates a low have Internal power supply voltage than the external power supply voltage by receiving an external power supply voltage. The sense amplifier is connected to corresponding bit line pairs provided corresponding to each bit line pair, first it operates by receiving the internal power supply unit or et Internal power supply voltage, read out from the memory cell in the memory cell array The amplified data signal is amplified. Write driver is connected to the global output line pair, receiving the second internal power supply means or et Internal power supply voltage operation, write data signals to the memory cells in the memory cell array. The voltage balancing means sets the generated voltage of the first internal power supply means and the generated voltage of the second internal power supply means to the same level. The transfer gate includes a P-type MOS transistor. One of the source and drain of the P-type MOS transistor is connected to one of the local input / output line pairs, the other of the source and drain is connected to one of the global input / output line pairs, and the gate thereof is connected to the local input / output line. Upon receiving a selection signal for associating the line pair with the global input / output line pair, an internal power supply voltage is applied to the well immediately below the gate.

  In the semiconductor integrated circuit device, the sense amplifier and the write driver operate in response to the voltages from the first internal power supply means and the second internal power supply means that have generated voltages at the same level by the voltage balancing means.

  Preferably, the voltage balancing means includes a power supply wiring. The power supply wiring connects the output node of the first internal power supply means and the output node of the second internal power supply means.

  In the semiconductor integrated circuit device, the sense amplifier and the write driver receive the voltages from the first internal power supply means and the second internal power supply means whose output nodes are at the same level by the voltage balancing means connected by the power supply wiring. And work.

Preferably, the voltage balancing means includes a reference voltage generating means and a signal wiring. The reference voltage generation means receives the external power supply voltage and generates a reference voltage signal corresponding to the internal power supply voltage. Signal lines transmits the reference voltage signal to the first and second internal power supply means.

  In the semiconductor integrated circuit device, the first internal power supply means and the second internal power supply means generate a voltage based on the same reference voltage signal. The sense amplifier operates in response to the voltage from the first internal power supply means, and the write driver operates in response to the voltage from the second internal power supply means.

According to another aspect of the present invention, a semiconductor integrated circuit device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a local input / output line pair, a plurality of column selection gates, and a global input / output. A line pair, a transfer gate, an internal power supply means, a sense amplifier, and a write driver are provided. The memory cell array has a plurality of memory cells arranged in rows and columns. The plurality of word lines are provided corresponding to a plurality of rows, respectively. The plurality of bit line pairs are provided corresponding to a plurality of columns, respectively. The plurality of column selection gates are provided corresponding to the plurality of bit line pairs, respectively, and each is connected between the corresponding bit line pair and the local input / output line pair. The transfer gate is connected between the local input / output line pair and the global input / output line pair. The internal power supply means receives the external power supply voltage and generates an internal power supply voltage lower than the external power supply voltage. The sense amplifier is provided corresponding to each bit line pair and connected to the corresponding bit line pair, operates by receiving an internal power supply voltage, and amplifies a data signal read from the memory cell in the memory cell array. The write driver is connected to the global input / output line pair, operates by receiving an internal power supply voltage, and writes a data signal to a memory cell in the memory cell array. The transfer gate includes a P-type MOS transistor. One of the source and drain of the P-type MOS transistor is connected to one of the local input / output line pairs, the other of the source and drain is connected to one of the global input / output line pairs, and the gate thereof is connected to the local input / output line. Upon receiving a selection signal for associating the line pair with the global input / output line pair, an internal power supply voltage is applied to the well immediately below the gate.

  In the semiconductor integrated circuit device, the sense amplifier and the write driver operate in response to the voltage from the internal power supply means.

  In the semiconductor integrated circuit device according to one aspect of the present invention, the voltage is supplied to the write driver and the send amplifier by the first and second internal power supply means for generating the first power supply voltage, so that fluctuations in the power supply voltage are reduced. can do.

  In addition, since the power supply voltage is supplied to the write driver by the second internal power supply means independent of the first internal power supply means, fluctuations in the power supply voltage can be further reduced.

  Further, since the transfer gate includes the P-type transistor, the voltage corresponding to the “H” level data can be sufficient.

  In addition, since the first power supply voltage, which is the drive power level of the sense amplifier, is applied to the body region of the P-type transistor used for the transfer gate, the hierarchical I / O line even when the drive power supply level of the sense amplifier is lowered A structure can be adopted.

  In the semiconductor integrated circuit device according to another aspect of the present invention, the write driver operates upon receiving the internal power supply voltage from the internal power supply means, so that the amplitude of the global input / output line can be reduced and the power consumption can be reduced. In addition, high-speed operation can be achieved by shortening the time required for equalization.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a block diagram showing an overall configuration of a system LSI according to the first embodiment of the present invention. Referring to FIG. 1, this system LSI includes a DRAM 1 and a logic circuit 2. The DRAM 1 and the logic circuit 2 are provided on the same chip CH, and input / output data DQ is transferred between them.

  The DRAM 1 includes internal power supply circuits 11 and 12, a memory cell array 13, a row address strobe (/ RAS) buffer 14, a column address strobe (/ CAS) buffer 15, a write enable (/ WE) buffer 16, and an address buffer. 17, row decoder 18, word line driver 19, column decoder 20, amplifier 21, input / output buffer 22, write driver 23, global input / output line (GI / O) precharge circuit 24 , And sense amplifier 25. Internal power supply circuit 11 has external power supply voltage Ext. Vcc (for example, 3.3 V) is received and external power supply voltage Ext. Internal power supply voltage Vcc1 (for example, 2.5 V) lower than Vcc is generated. Internal power supply circuit 12 receives external power supply voltage Ext. Vcc and external power supply voltage Ext. Internal power supply voltage Vcc2 (for example, 2.5 V) lower than Vcc is generated. Memory cell array 13 includes a plurality of memory cells arranged in rows and columns, a plurality of word lines (not shown) arranged in rows, and a plurality of bit line pairs (not shown) arranged in columns. including. / RAS buffer 14 is connected to external power supply voltage Ext. Vcc operates and external row address strobe signal Ext. In response to / RAS, internal row address strobe signal / RAS is generated. / CAS buffer 15 is connected to external power supply voltage Ext. Vcc operates and external column address strobe signal Ext. In response to / CAS, internal column address strobe signal / CAS is generated. / WE buffer 16 is connected to external power supply voltage Ext. Vcc operates and the external write enable signal Ext. In response to / WE, an internal write enable signal / WE for activating the write driver 23 is generated. Address buffer 17 is connected to external power supply voltage Ext. Operates in response to Vcc and supplies external address signal EAD as row address signal RAD to row decoder 18 in response to internal row address strobe signal / RAS and external address signal in response to internal column address strobe signal / CAS. EAD is supplied to the column decoder 20 as the column address signal CAD. The row decoder 18 selects a row (word line) of the memory cell array 13 in response to a row address signal RAD from the address buffer 17. Word line driver 19 boosts the selected word line to potential Vpp. The column decoder 20 selects a column (bit line pair) of the memory cell array 13 in response to the column address signal CAD from the address buffer 17. The amplifier 21 amplifies a data signal read from a memory cell (not shown) in the memory cell array 13 and supplies it to the input / output buffer 22. The input / output buffer 22 outputs the data signal from the amplifier 21 to the logic circuit 2 and outputs the data signal from the logic circuit 2 to the write driver 23. Write driver 23 operates in response to internal power supply voltage Vcc2, and writes a data signal from input / output buffer 22 into a memory cell in memory cell array 13. The GI / O line precharge circuit 24 operates in response to the internal power supply voltage Vcc2, and precharges a global input / output line pair (not shown). Sense amplifier 25 operates in response to internal power supply voltage Vcc1, and amplifies a data signal read from a memory cell (not shown) in memory cell array 13.

  FIG. 2 is a block diagram showing in more detail the configurations of the memory cell array 13, the amplifier 21, the write driver 23, the GI / O line precharge circuit 24, and the sense amplifier 25 shown in FIG. Referring to FIG. 2, these are composed of n memory blocks 301 to 30n, 2n GI / O line precharge circuits 24a1 to 24bn, and 2n input / output blocks 40a1 to 40bn. Memory block 301 includes two global input / output line pairs GI / O and m sub-blocks 311-31m. One global input / output line pair GI / O-a is connected to the input / output block 40a1 and GI / O line precharge circuit 24a1, and is connected to m sub-blocks 311 to 31m in the memory block 301. Connected. The other global input / output line pair GI / O-b is connected to the input / output block 40b1 and the GI / O line precharge circuit 24b1, and in the memory block 301, m sub-blocks 311 to 31m are connected. Connected to. Each of the sub blocks 311 to 31m includes a plurality of memory cells 32 arranged in rows and columns, a plurality of word lines WL arranged in the rows, and a plurality of bit line pairs BL and / BL arranged in the columns. , A plurality of sense amplifiers 25a1 to 25b1, a plurality of NMOS transistors 33a11, 33a12 to 33bn1, and 33bn2, two local input / output line pairs LI / Oa and LI / O-b, and two transfers Gates 34a and 34b. Sense amplifiers 25a1 to 25bn operate with internal power supply voltage Vcc1, are provided corresponding to bit line pair BL, / BL, and amplify a data signal read from memory cell 32. The NMOS transistors 33a11, 33a12 to 33bn1, and 33bn2 constitute column selection gates and are provided corresponding to the sense amplifiers 25a1 to 25bn, respectively.

  As an example, the NMOS transistors 33a11 and 33a12 will be described. The NMOS transistors 33a11 and 33a12 are connected between the sense amplifier 25a1 and the local input / output line LI / O-a, and are connected to the column decoder 20 shown in FIG. ON / OFF by the column selection signal. The local input / output line pair LI / O-a is connected to the transfer gate 34a and the NMOS transistors 33a11, 33a12 to 33an1, 33an2, and the local input / output line pair LI / O-b is connected to the transfer gate 34b and the NMOS. The transistors 33b11 and 33b12 to 33bn1 and 33bn2 are connected. The transfer gates 34a and 34b are connected between the local input / output line pair LI / Oa and LI / Ob and the global input / output line pair GI / Oa and GI / Ob. Are connected to each other and turned on / off in response to the sub-block selection signal BS.

  Note that subblocks 312 to 31n similar to the subblock 311 configured as described above are provided in the memory block 301.

  The GI / O line precharge circuit 24a1 includes PMOS transistors 35a1 and 35a2. The PMOS transistor 35a1 has a source connected to the internal power supply voltage Vcc2, a drain connected to one of the global input / output line pair GI / O-a, and is turned on / off by a global input / output line precharge signal / PR. The PMOS transistor 35a2 has a source connected to the external power supply voltage Vcc2, a drain connected to the other of the global input / output line pair GI / O-a, and is turned on / off by a global input / output line precharge signal / PR.

  A global input / output line precharge circuit 24b1 similar to the global input / output line precharge circuit 24a1 configured as described above is provided corresponding to the global input / output line pair GI / O-b.

  The input / output block 40a1 includes an amplifier 21a and a write driver 23a. The amplifier 21a is connected to the external power supply voltage Ext. It operates by Vcc, is connected between the global input / output line pair GI / O-a and the input / output buffer 22, and amplifies the data signal from the global input / output line pair GI / O-a. The write driver 23a operates with the internal power supply voltage Vcc2, is connected between the input / output buffer 22 and the global input / output line pair GI / O-a, and amplifies the data signal from the input / output buffer 22 to globally Transfer to I / O line pair GI / O-a.

  An input / output block 40b1 similar to the input / output block 40a1 configured as described above is provided corresponding to the global input / output line pair GI / O-b. The GI / O line precharge circuits 24a2, 24b2 to 24an, 24bn and the input / output blocks 40a2, 40b2 to 40an, 40bn are the same as the global input / output line precharge circuits 24a1, 24b1 and the input / output blocks 40a1, 40b1. Are also provided for the memory blocks 302 to 30n.

  FIG. 3 is a circuit diagram showing a specific configuration of sense amplifiers 25a1 to 25bn shown in FIG. Referring to FIG. 3, sense amplifiers 25a1 to 25bn are cross-coupled, and PMOS transistors PT2 and PT3 for driving a high potential bit line of corresponding bit line pair BL, / BL to power supply potential level (Vcc1). NMOS transistors NT2 and NT3 that are cross-coupled to drive the low-potential bit line of corresponding bit line pair BL to the ground potential level (GND) and conductive in response to sense amplifier activation signal / SE In order to activate the cross-coupled NMOS transistors NT2 and NT3, the PMOS transistor PT1 for activating the cross-coupled PMOS transistors PT2 and PT3 is turned on in response to the sense amplifier activation signal SE. An NMOS transistor NT1 is included.

  Similarly, PMOS transistors PT2a and PT3a and NMOS transistors NT2a and NT3a are provided corresponding to the bit line pair BLa and / BLa to form a sense amplifier.

  FIG. 4 is a circuit diagram showing a specific configuration of the write drivers 23a and 23b shown in FIG. Referring to FIG. 4, write drivers 23a, 23b include inverters 50, 51, 111, 112, AND gates 52, 53, NMOS transistors 54, 55, and PMOS transistors 58, 59. Inverter 50 inverts write enable signal / WE for output. The inverter 51 inverts the value of the data signal DATA and outputs it. The AND gate 52 receives the output signal from the inverter 50 and the data signal DATA and outputs a logical product of them. The AND gate 53 receives the output signal from the inverter 50 and the output signal from the inverter 51 as inputs, and outputs a logical product of them. The NMOS transistor 54 has a source grounded, a drain connected to one of the global input / output line pair GI / O and the PMOS transistor 58, and is turned on / off by an output signal from the AND gate 52. The NMOS transistor 55 has a source grounded, a drain connected to the other of the global input / output line pair GI / O and the PMOS transistor 59, and is turned on / off by an output signal from the AND gate 53. The inverter 111 inverts the output signal from the AND gate 53 and outputs it. The inverter 112 inverts the output signal from the AND gate 52 and outputs it. The PMOS transistor 58 has a source connected to the internal power supply voltage Vcc2 and a drain connected to the global input / output line pair GI / O to which the NMOS transistor 54 is connected and to the NMOS transistor 54. Turns on / off by output signal. The PMOS transistor 59 has a source connected to the internal power supply voltage Vcc 2, and a drain connected to the global input / output line pair GI / O to which the NMOS transistor 55 is connected and to the NMOS transistor 55. Turns on / off by output signal.

  Here, the operation of the write drivers 23a and 23b configured as described above will be described. When the write enable signal / WE is at the H level, an L level signal is input to one of the input terminals of the AND gates 52 and 53, so that the output signals from the AND gates 52 and 53 are at the L level. Therefore, the NMOS transistors 54 and 55 and the PMOS transistors 58 and 59 are turned off.

  When the write enable signal / WE is at L level and the data signal DATA from the input / output buffer 22 is at H level, the output from the AND circuit 52 is at H level, so that the NMOS transistor 54 and the PMOS transistor 59 are turned on. Become. On the other hand, since the output from the AND circuit 53 is at the L level, the NMOS transistor 55 and the PMOS transistor 58 are turned off.

  As a result, the global input / output line connected to the NMOS transistor 54 and the PMOS transistor 58 becomes the ground potential, and the global input / output line connected to the NMOS transistor 55 and the PMOS transistor 59 becomes the Vcc2 potential.

  When the write enable signal / WE is at the L level and the data signal from the input / output buffer 22 is at the L level, the output from the AND circuit 53 is at the H level, so that the NMOS transistor 55 and the PMOS transistor 58 are turned on. . On the other hand, since the output from the AND circuit 52 becomes L level, the NMOS transistor 54 and the PMOS transistor 59 are turned off.

  As a result, the global input / output line connected to the NMOS transistor 55 and the PMOS transistor 59 becomes the ground potential, and the global input / output line connected to the NMOS transistor 54 and the PMOS transistor 58 becomes the Vcc2 potential.

  Next, the operation of the system LSI configured as described above will be described with reference to FIG.

  In a standby state where data is not written / read to / from memory cell 32 in DRAM 1, global input / output line precharge signal / PR is at L level. Therefore, the PMOS transistors 35a1 and 35a2 of the global input / output line precharge circuit 24a1 are turned on and the global input / output line pair GI / O-a is precharged to the Vcc2 level. Hereinafter, a data read operation from the memory cell will be described.

  When the word line WL arranged in the row including the memory cell to be accessed (herein, the memory cell 32) is boosted to the potential Vpp, the bit corresponding to the memory cell 32 is generated by the charge stored in the memory cell 32. A potential difference is generated between the line pair BL, / BL.

  Subsequently, sense amplifier activation signal SE and sub-block selection signal BS rise to H level. Thereby, the potential difference between the bit line pair BL, / BL is amplified to the potential difference Vcc by the sense amplifier 25a1. Further, the transfer gate 34a becomes conductive, and the global input / output line pair GI / Oa and the local input / output line pair LI / Oa are connected.

  Subsequently, global input / output line precharge signal / PR rises to H level. As a result, the PMOS transistors 35a1 and 25a2 are turned off, so that the global input / output line precharge circuit 24a1 and the global input / output line pair GI / O-a are disconnected.

  At the same time as the global input / output line precharge signal / PR rises to the H level, the column selection signal CSL input from the column decoder 18 to the gates of the NMOS transistors 33a11 and 33a12 rises to the H level, and the NMOS transistors 33a11, 33a12 is turned on. As a result, the potential difference Vcc1 between the bit line pair BL and / BL amplified by the sense amplifier 25a1 is transferred to the local input / output line pair LI / O-a, and further the global input / output line pair LI / O-. forwarded to a. The potential difference Vcc1 is amplified by the amplifier 21a and sent to the input / output buffer 22.

  Next, a case where data is written to a memory cell (here, memory cell 32) will be described.

  A data signal DATA is sent from the input / output buffer 22 to the write driver 23a. Write enable signal / WE falls, data signal DATA is taken into write driver 23a, one of the two outputs of write driver 23a is at Vcc2 level and the other is at ground level in accordance with the level of data signal DATA. Become. Global input / output line precharge signal / PR, sub-block selection signal BS, and column selection signal CSL attain H level, global input / output line pair GI / O-a, local input / output line pair LI / O-a Are connected, and the NMOS transistors 33a11 and 33a12 are turned on. As a result, the data signal from the write driver 23a is transferred to the sense amplifier 25a1. Sense amplifier activation signal SE becomes H level, and data is written to memory cell 32.

  The read / write operation as described above is performed by the global input / output line pair GI / Ob, the local input / output line pair LI / Ob, the input / output block 40b1 connected thereto, the global input / output. The same applies to the line precharge circuit 24b1, the transfer gate 34b, the NMOS transistors 33b11 to 33bn2, and the sense amplifiers 25b1 to 25bn.

  Further, the same operation as described above is performed for the memory blocks 302 to 30n.

  Therefore, each of the memory blocks 301 to 30n can be simultaneously accessed from the input / output buffer 22 through the global input / output line pair GI / O provided in each of the memory blocks 301 to 30n. As the number of memory blocks 301 to 30n increases, the number of write drivers 23a and 23b and global input / output line precharge circuits 24a1, 24b1 to 24an and 24bn also increases accordingly. Therefore, the amount of current supplied when the write drivers 23a1 and 23b1 and the global input / output line precharge circuits 24a1 to 24bn operate also increases.

  FIG. 6 is a block diagram showing a power supply system of DRAM 1 in the first embodiment of the present invention. Referring to FIG. 6, in DRAM 1, internal power supply circuit 21 for driving sense amplifier 25, global input / output line precharge circuit 24 and internal power supply circuit 12 for write driver 23 are provided and supplied to sense amplifier 25. Internal power supply Vcc1 is separated from internal power supply Vcc2 supplied to global input / output line precharge circuit 24 and write driver 23. Peripheral circuit 90 including address buffer 17, / RAS buffer 14, / CAS buffer 15, and / WE buffer 16 is connected to external power supply voltage Ext. It is driven by Vcc.

  As a result, the power supply line is supplied by the power supply current supplied to the global input / output line precharge circuit 24 during charging / discharging of the global input / output line GI / O and the power supply current supplied to the write driver 23 during operation of the write driver 23. Even when noise is generated, noise does not propagate to the power supply line to the sense amplifier 25 and the peripheral circuit 90.

  In addition, although the PMOS transistor 35 is used in the global input / output line precharge circuit 24, NMOS transistors 61 and 62 may be used as shown in FIG.

[Embodiment 2]
FIG. 8 is a block diagram showing a power supply system in the DRAM in the system LSI according to the second embodiment of the present invention. Referring to FIG. 8, in the second embodiment, sense amplifier 25, global input / output line precharge circuit 24, internal power supply circuit 11 for supplying power supply Vcc1 for driving peripheral circuit 90, and write driver 23 are referred to. And an internal power supply circuit 12 for supplying a power supply Vcc2 for supplying power.

  Thereby, even when noise occurs in the power supply line to the write driver due to the power supply current supplied to the write driver during the operation of the write driver, the noise does not propagate to the power supply line to the sense amplifier 25. .

[Embodiment 3]
FIG. 9 is a block diagram showing a power supply system in the DRAM in the system LSI according to the third embodiment of the present invention. Referring to FIG. 9, in the third embodiment, sense amplifier 25, internal power supply circuit 11 for supplying power supply Vcc1 for driving peripheral circuit 90, write driver 23, and global input / output line precharge circuit 24 are provided. An internal power supply circuit 12 that supplies power Vcc2 for driving is received.

  Accordingly, the write driver is driven by the power supply current supplied to the write driver 23 during the operation of the write driver 23 and the current consumed when the global input / output line GI / O is charged / discharged by the global input / output line precharge circuit 24. 23 and the power supply line to the global input / output line precharge circuit 24, no noise is propagated to the power supply line to the sense amplifier 25 and the peripheral circuit 90.

[Embodiment 4]
FIG. 10 is a block diagram showing a power supply system in the DRAM in the system LSI according to the fourth embodiment of the present invention.

  Referring to FIG. 10, in the fourth embodiment, internal power supply circuit 11 that supplies power supply Vcc1 for driving sense amplifier 25 and global I / O line precharge circuit 24, and write driver 23 are driven. An internal power supply circuit 12 for supplying the power supply Vcc2 and an internal power supply circuit 60 for supplying the power supply Vcc3 for driving the peripheral circuit 90 are provided.

  Thus, even when noise occurs in the power supply line to the write driver 23 due to the power supply current supplied to the write driver 23 during the operation of the write driver 23, the power supply line to the sense amplifier 25 and the peripheral circuit 90 Noise does not propagate to

  Further, since the internal power supply circuit 60 is provided separately for the peripheral circuit 90, the internal power supply voltage Vcc3 can be set to a value different from Vcc1 and Vcc2 in order to improve the operation speed of the peripheral circuit.

[Embodiment 5]
FIG. 11 is a block diagram showing a power supply system in the DRAM in the system LSI according to the fifth embodiment of the present invention. Referring to FIG. 11, in the fifth embodiment, internal power supply circuit 11 supplying power Vcc1 for driving sense amplifier 25, write driver 23 and global input / output line precharge circuit 24 are driven. An internal power supply circuit 12 that supplies power Vcc2 and an internal power supply circuit 60 that supplies power Vcc3 for driving the peripheral circuit 90 are provided.

  As a result, the power supply current supplied to the write driver 23 during the operation of the write driver 23 charges the power supply line to the write driver 23 and the global input / output line pair GI / O by the global input / output line precharge circuit 24. Even when noise is generated in the power supply line to the write driver 23 and the global input / output line precharge circuit 24 due to the current consumed at the time of discharge, the power supply line to the sense amplifier 25 and the peripheral circuit 90 is supplied. Noise does not propagate.

[Embodiment 6]
In the first to sixth embodiments, an internal power supply circuit is provided in the DRAM, and sense amplifier 25, write driver 23, global input / output line precharge circuit 24, and peripheral circuit 90 are driven by the internal power supply voltage generated thereby. However, in the sixth embodiment and later-described seventh to ninth embodiments, pads are provided to drive the sense amplifier 25, the write driver 23, the global input / output line precharge circuit 24, and the peripheral circuit 90. For this purpose, a power source for applying power to the pad is externally applied.

  FIG. 12 is a block diagram showing a power supply system in the DRAM according to the sixth embodiment of the present invention. Referring to FIG. 12, this DRAM includes pads 71 and 74 connected to sense amplifier 25 and global input / output line precharge circuit 24, pads 72 and 75 connected to write driver 23, and peripheral circuit 90. Pads 73 and 76 to be connected are provided. A power supply voltage Vcc is applied to the pads 70, 71, 72 from the outside, and the sense amplifier 25, the global input / output line precharge circuit 24, the write driver 23, and the peripheral circuit 90 are driven by this voltage. Pads 73, 74, 75 are connected to ground level.

  As a result, the power supply line for driving the sense amplifier 25 and the global input / output line precharge circuit 24 and the power supply line for driving the peripheral circuit are different systems in the DRAM. Therefore, even when noise occurs in the power supply line to the write driver 23 due to the power supply voltage supplied to the write driver 23 during the operation of the write driver 23, the power supply line to the sense amplifier 25 and the peripheral circuit 90. Noise does not propagate to

[Embodiment 7]
FIG. 13 is a block diagram showing a power supply system in the DRAM according to the seventh embodiment of the present invention. Referring to FIG. 13, this DRAM is one in which pads 74, 75 and 76 shown in FIG.

  Since the pads 74, 75, and 76 are connected to the ground level, the same effect as in the sixth embodiment can be obtained even when these pads are connected to the ground level as one pad. In addition, the number of pads can be reduced.

[Embodiment 8]
FIG. 14 is a block diagram showing a power supply system in the DRAM according to the eighth embodiment of the present invention. Referring to FIG. 14, this DRAM includes pads 78 and 80 connected to sense amplifier 25, pads 79 and 81 connected to write driver 23 and global input / output line precharge circuit 24, and peripheral circuit 90. Pads 73 and 76 to be connected are provided.

  A power supply voltage Vcc is applied to the pads 78, 79, 73 from the outside, and the sense amplifier 25, the global input / output line precharge circuit 24, the write driver 23, and the peripheral circuit 90 are driven by this voltage. Pads 80, 81, 76 are connected to ground level.

  Thus, a power supply line for driving the sense amplifier 25, a power supply line for driving the write driver 23 and the global input / output line precharge circuit 24, and a power supply line for driving the peripheral circuit 90 are provided. Are different systems in the DRAM. Therefore, the power supply voltage supplied to the write driver 23 during the operation of the write driver 23 and the current consumed when the global input / output line pair is charged / discharged by the global input / output line precharge circuit 24 are used. Even when noise occurs in the power supply line to the output line precharge circuit 24, the noise does not propagate to the power supply line to the sense amplifier 25 and the peripheral circuit 90.

[Embodiment 9]
FIG. 15 is a block diagram showing a power supply system in the DRAM according to the ninth embodiment of the present invention. Referring to FIG. 15, this DRAM is one in which pads 80, 81, and 76 shown in FIG.

  Since the pads 80, 81, and 76 are connected to the ground level, even when these pads are connected to the ground level as one pad 82, the same effect as in the sixth embodiment can be obtained. In addition, the number of pads can be reduced.

[Embodiment 10]
FIG. 16 is a block diagram showing configurations of memory cell array 13, amplifier 21, write driver 23, I / O line precharge circuit 124, and sense amplifier 25 in the system LSI according to the tenth embodiment of the present invention. Referring to FIG. 16, in the tenth embodiment, instead of the global input / output line pair GI / O and the local input / output line pair LI / O shown in the first to ninth embodiments, an input is provided. An output line pair I / O is provided.

  Memory block 301 includes input / output line pairs I / O-a and I / O-b and a sub-block 311. The input / output line pair I / O-a is connected to the input / output block 40a1 and the I / O line precharge circuit 124a1, and is connected to the NMOS transistors 33a11, 33a12 to 33an1, and 33an2 in the memory block 301. The input / output line pair I / O-b is connected to the input / output block 40b1 and the I / O line precharge circuit 124b1, and is connected to the NMOS transistors 33b11, 33b12 to 33bn1, 33bn2 in the memory block 301.

  I / O line precharge circuit 124a1 includes PMOS transistors 35a1 and 35a2. PMOS transistors 35a1 and 35a2 are turned on / off by input / output line precharge signal / PR.

  I / O line precharge circuit 124b1 includes PMOS transistors 35b1 and 35b2. PMOS transistors 35b1 and 35b2 are turned on / off by input / output line precharge signal / PR.

  I / O line precharge circuits 124a2, 124b2 to 124an, 124bn similar to the input / output line precharge circuits 124a1 and 124b1 are also provided for the memory blocks 302 to 30n. Next, the operation of the system LSI configured as described above will be described.

  In a standby state where data is not written / read to / from memory cell 32 in DRAM 1, input / output line precharge signal / PR is at L level, and PMOS transistors 35a1 and 35a2 of input / output line precharge circuit 124a1 are turned on. It becomes. As a result, the input / output line pair I / O-a is precharged to the Vcc2 level. Hereinafter, a data read operation from the memory cell will be described.

  When the input / output line precharge signal / PR rises to the H level, the PMOS transistors 35a1 and 25a2 are turned off, so that the input / output line precharge circuit 124a1 and the input / output line pair I / O-a are disconnected. Be released.

  The potential difference Vcc1 between the bit line pair BL, / BL amplified by the sense amplifier 25a1 is transferred to the input / output line pair I / O-a, amplified by the amplifier 21a, and sent to the input / output buffer 22.

  Next, a case where data is written to the memory cell will be described. The input / output line precharge signal / PR becomes H level, the data signal from the write driver 23a is transferred to the sense amplifier 25a1 through the input / output line pair I / O-a, and data is written into the memory cell 32.

  The read / write operation as described above includes the input / output line pair I / O-b and the input / output block 40b1, the input / output line precharge circuit 124b1, the NMOS transistors 33b11 to 33bn2, and the sense amplifiers 25b1 to 25bn connected thereto. The same is done for.

  Further, the same operation as described above is performed for the memory blocks 302 to 30n.

  Therefore, each of the memory blocks 301 to 30n can be simultaneously accessed from the input / output buffer 22 through the input / output line pair I / O provided in each of the memory blocks 301 to 30n. As the number of memory blocks 301 to 30n increases, the number of write drivers 23a and 23b and input / output line precharge circuits 124a1, 124b1 to 124an, and 124bn also increase accordingly. Therefore, the amount of current supplied when the write drivers 23a1 and 23b1 and the input / output line precharge circuits 124a1 to 124bn operate also increases.

  FIG. 17 is a block diagram showing a power supply system of DRAM 1 in the tenth embodiment of the invention. Referring to FIG. 17, in DRAM 1, internal power supply circuit 21 for driving sense amplifier 25, input / output line precharge circuit 124, and internal power supply circuit 12 for write driver 23 are provided, and the internal power supplied to sense amplifier 25 is provided. The power supply Vcc1 is separated from the internal power supply Vcc2 supplied to the input / output line precharge circuit 124 and the write driver 23. Peripheral circuit 90 including address buffer 17, / RAS buffer 14, / CAS buffer 15, and / WE buffer 16 is connected to external power supply voltage Ext. It is driven by Vcc.

  As a result, noise is generated in the power supply line by the power supply current supplied to the input / output line precharge circuit 124 during charging / discharging of the input / output line I / O and the power supply current supplied to the write driver 23 during operation of the write driver 23. Even in this case, noise does not propagate to the power supply line to the sense amplifier 25 and the peripheral circuit 90.

  8 to 11, the GI / O line precharge circuit 24 is replaced with the I / O line precharge circuit 124, so that the power supply system of the DRAM 1 in the second to fifth embodiments is changed. Thus, the same effect as in the second to fifth embodiments can be obtained.

[Embodiment 11]
FIG. 18 is a block diagram showing a power supply system in the DRAM according to the eleventh embodiment of the present invention. FIG. 18 is obtained by replacing the GI / O line precharge circuit 24 shown in FIG. 14 with an I / O line precharge circuit 124.

  Thus, a power supply line for driving the sense amplifier 25, a power supply line for driving the write driver 23 and the input / output line precharge circuit 124, and a power supply line for driving the peripheral circuit 90 are provided. Different systems are provided inside the DRAM. Therefore, the power supply voltage supplied to the write driver 23 during the operation of the write driver 23 and the current consumed when the input / output line pair is charged / discharged by the input / output line precharge circuit 124 are used. Even when noise occurs in the power supply line to the charge circuit 124, the noise does not propagate to the power supply line to the sense amplifier 25 and the peripheral circuit 90.

  12, 13, and 15, by replacing the GI / O line precharge circuit 24 with the I / O line precharge circuit 124, the power supply system of the DRAM 1 is changed to the above-described sixth, seventh, and ninth embodiments. Thus, the same effect as in the sixth, seventh and ninth embodiments can be obtained.

[Embodiment 12]
FIG. 19 is a block diagram showing an overall configuration of a system LSI according to the twelfth embodiment of the present invention. Referring to FIG. 19, this system LSI includes a synchronous DRAM 1 and a logic circuit 2. Synchronous DRAM 1 and logic circuit 2 are provided on the same chip CH, and input / output data DQ is transferred between them.

  The synchronous DRAM 1 includes a control signal buffer 132 instead of the / RAS buffer 14, / CAS buffer 15, and / WE buffer 16 shown in FIG. Clock buffer 131 is connected to external power supply voltage Ext. Vcc operates and receives internal clock signal int. In response to clock signal CLK from logic circuit 2. Generate CLK. Control signal buffer 132 receives external power supply voltage Ext. Vcc operates and receives internal clock signal int. Based on control signal CTL from logic circuit 2. The internal control signal int. Generate CTL. Address buffer 17 is connected to external power supply voltage Ext. It operates in response to Vcc, and the internal control signal int. In response to CTL, the external address signal EAD is supplied to the row decoder 18 as the row address signal RAD, or the external address signal EAD is supplied to the column decoder 20 as the column address signal CAD. Write driver 23 operates in response to internal power supply voltage Vcc2, and receives internal control signal int. In response to CTL, the data signal from input / output buffer 22 is written into the memory cell.

  Next, the operation of the system LSI configured as described above will be described. The internal clock signal int. Internal control signal int. Strobe for row address synchronization in synchronization with the clock of CLK. A CTL is generated in the control signal buffer 132. This internal control signal int. A row address is taken in by CTL and a corresponding word line is selected. The next internal clock signal int. The internal control signal int. Strobe for strobing the column address in synchronization with the clock of CLK. A CTL is generated in the control signal buffer 132. This internal control signal int. The column address is taken in by CTL, and the data in the memory cell is read out to the input / output line by the column decoder 20. This data is stored in the internal clock signal int. Output in synchronization with CLK.

  In this DRAM 1, an internal power supply circuit 21 for driving the sense amplifier 25, a global input / output line precharge circuit 24, and an internal power supply circuit 12 for the write driver 23 are provided, and an internal power supply Vcc1 supplied to the sense amplifier 25 and a global input The output line precharge circuit 24 and the internal power supply Vcc2 supplied to the write driver 23 are disconnected. Peripheral circuits including the address buffer 17, clock buffer 131, control signal buffer 132, and the like are connected to the external power supply voltage Ext. It is driven by Vcc.

  As a result, the power supply line is supplied by the power supply current supplied to the global input / output line precharge circuit 24 during charging / discharging of the global input / output line GI / O and the power supply current supplied to the write driver 23 during operation of the write driver 23. Even when noise is generated, noise does not propagate to the sense amplifier 25 and the power supply line to the peripheral circuit.

[Embodiment 13]
In the first to twelfth embodiments, the adverse effect of noise that increases due to an increase in current consumption in the write driver and the global input / output line precharge circuit as the internal bus width is expanded affects other circuits such as sense amplifiers and peripheral circuits. The main purpose was to prevent the spread.

  In the thirteenth embodiment, a solution to the problem necessary for lowering the voltage level of the memory cell array power supply, that is, the sense amplifier power supply is considered.

  FIG. 20 is a diagram illustrating the configuration of the write driver 23. In the thirteenth embodiment, the voltage level of the power supplied to the write driver 23 is the same as the voltage level of the sense amplifier power.

  That is, the voltage level of drive power supply Vcc-WD of the write driver in FIG. 20 is set to the same level as supply voltage Vcc1 of the internal power supply circuit in the first to twelfth embodiments. As a result, the amplitude level of the global input / output line pair GI / O, / GI / O can be reduced, and the operation speed can be increased and the current consumption can be reduced by shortening the time required for the equalization operation. Can do.

  These effects are particularly prominent in the embedded DRAM that widens the internal bus width and transfers a large amount of data at a time.

  Furthermore, by making the voltage level of the drive power supply of the write driver 23 the same as the drive power supply voltage level of the sense amplifier power supply, even when the voltage level of the sense amplifier power supply is lowered from the voltage level of the drive power supply of the peripheral circuit, The / O line structure can be employed. The reason will be described in detail below.

  FIG. 21 shows a transfer gate for connecting the local input / output line LI / O and the global input / output line GI / O in the hierarchical I / O line structure when the voltage level of the sense amplifier power supply is lowered. FIG.

  Referring to FIG. 21, transfer gate 34 includes a P-type transistor 113 and an N-type transistor 114. N-type transistor 114 and P-type transistor 113 receive a sub-block selection signal SB signal and its inverted signal at their gates.

  In FIG. 20, the transfer gate shown in FIG. 31 is composed of only an N-type transistor, but is composed of a pair of a P-type transistor and an N-type transistor. As the voltage level of the sense amplifier power supply is lowered, the voltage level corresponding to the corresponding “H” level data is also lowered. Therefore, when the “H” level data is written, it is composed of only N-type transistors. This is because the transfer gate cannot obtain a sufficient voltage level corresponding to the “H” level data due to the influence of the threshold voltage drop of the transistor.

  Therefore, although the P-type transistor 113 is used for the transfer gate 34, there is a problem when the voltage level of the drive power source of the write driver is set to the voltage level of the drive power source of the peripheral circuit higher than the voltage of the sense amplifier power source as in the prior art. Occurs.

  FIG. 22 is a conceptual diagram for explaining problems in the P-type transistor 113 included in the transfer gate 34. FIG. 22 shows a configuration of the P-type transistor 113 connected between the global input / output line GI / O and the local input / output line LI / O.

  Referring to FIG. 22, P-type transistor 113 includes one of source / drain 134 connected to local input / output line LI / O and source / drain connected to global input / output line GI / O. The other 135. When the P-type transistor 113 transmits "H" level data, different voltage levels are applied to the local input / output line LI / O and the global input / output line GI / O connected to the drain and source. Will be applied. Since this transfer gate is provided for each sub-block, it is desirable in terms of layout to be provided in a region adjacent to the sub-block such as a sense amplifier band or a sub-word driver band in the memory mat. Therefore, the voltage applied to the N well forming body region 132 via body contact 136 becomes voltage level Vcc1 of the sense amplifier power supply.

  However, by the write operation by the write driver 23 via the global input / output line GI / O, the voltage level of the N-type well forming the body region in the P + type source / drain region of the P-type transistor 113 is increased. When a high power supply voltage for peripheral circuits is applied, a PN forward junction is formed between the source / drain 135 and the body 132, and current flows. This current not only causes unnecessary current consumption, but when the amount of current increases, it may cause a bipolar operation by a parasitic transistor, leading to a memory failure.

  This problem is solved by setting the power supply voltage level of the write driver 23 to the same level as the voltage level of the sense amplifier power supply.

  FIG. 23 shows a structure of P-type transistors 58 and 59 included in write driver 23 of the DRAM of the thirteenth embodiment.

  Referring to FIG. 23, in the thirteenth embodiment, the power supply voltage level supplied to sources 144 of P-type transistors 58 and 59 included in write driver 23 is set to a power supply voltage level Vcc3 common to the peripheral circuits. Instead, it is set to the same voltage level Vcc1 of the sense amplifier power supply lower than that.

  In general, the write driver 23 is designed as a peripheral circuit outside the memory cell array. Therefore, in order to drive the P-type transistors 58 and 59 by the sense amplifier power supply, it is common with other P-type transistors 150 provided in this region. P-type transistors 58 and 59 cannot be provided in the N-type well. That is, it is necessary to electrically insulate body region 142 of P-type transistors 58 and 59 from body regions 151 of other transistors.

  Since write driver 23 writes data at “H” level by P-type transistors 58 and 59 having such a configuration, global input / output line pair GI / O, / G connected to drain 145 is written. The “H” level of −I / O is pulled up to the voltage level of the power supply for the sense amplifier, and the voltage between the “H” level data of the local input / output line pair LI / O, / LI / O The above-mentioned problem does not occur because the difference is eliminated.

  In configuring the write driver, the voltage levels of the power sources that drive the inverters 111 and 112, the NAND gates 52 and 53, and the inverters 50 and 51, which are other elements, are not particularly limited.

  However, as described above, since it is necessary to provide an N-type well independently in order to perform insulation, there is a disadvantage that the area is increased.

  Therefore, if there is a margin in the layout, only the P-type transistors 58 and 59 that directly correspond to data writing may be driven by the sense amplifier power supply, but the entire circuit elements of the write driver shown in FIG. Is driven by a memory cell array power supply, which is advantageous in terms of layout.

  FIG. 24 is a block diagram showing a power supply system in the DRAM for making the voltage level of the drive power supply of the write driver 23 the same as the voltage level of the sense amplifier power supply.

  Referring to FIG. 24, internal power supply circuit 11 supplies a power supply voltage to memory cell array 13, sense amplifier 25, and write driver 23. Thereby, the power supply voltage level for driving the write driver 23 can be made the same as the voltage level of the memory cell array power supply.

  On the other hand, the peripheral circuit 90 is supplied with a power supply voltage by another independent internal power supply circuit 61. As described above, in the peripheral circuit, the power supply voltage supplied to the peripheral circuit 90 is higher than the voltage level of the sense amplifier power supply from the viewpoint of improving the operation speed of the logic circuit section.

[Embodiment 14]
In the fourteenth embodiment, in addition to the configuration of the thirteenth embodiment, a power supply system for suppressing an adverse effect caused by an increase in current consumption of the write driver due to an expansion of the internal bus width is considered.

  FIG. 25 is a block diagram showing a power supply system in the DRAM according to the fourteenth embodiment of the present invention. Referring to FIG. 25, internal power supply circuit 12 is further provided in addition to the configuration of FIG. Further, by providing wiring 65 for connecting the power supply node of internal power supply circuit 11 and the power supply node of internal power supply circuit 12, the voltage levels of both power supply nodes are maintained at the same level. As a result, the write driver 23 is driven at the same voltage level as the voltage level of the sense amplifier power supply. The supply of power supply voltage to peripheral circuit 60 is as described with reference to FIG. 24, and therefore description thereof will not be repeated.

  FIG. 26 is a diagram showing a power supply system in the DRAM of another configuration example according to the fourteenth embodiment of the present invention.

  Referring to FIG. 26, internal power supply circuit 12 is provided as an independent power supply for write driver 23. On the other hand, a reference voltage generation circuit 67 is newly provided to make the voltage level generated by internal power supply circuits 11 and 12 the same level. Reference voltage generating circuit 67 is connected to external power supply voltage Ext. Reference voltage Vref. Vcc applied in common to internal power supply circuits 11 and 12 in response to Vcc. Is generated. Internal power supply circuits 11 and 12 have a reference voltage Vref. The voltage of the same level is supplied to the memory cell array 13, the sense amplifier 25, and the write driver 23. The supply of power supply voltage to peripheral circuit 60 is as described with reference to FIG.

  By using the power supply system of the fourteenth embodiment described with reference to FIGS. 25 and 26, the increase in noise caused by the increase in the current consumption of the write driver due to the expansion of the internal bus width, etc. The adverse effect on the circuit can be reduced, and the operation of the entire semiconductor integrated circuit device can be made stable.

  In the thirteenth and fourteenth embodiments, the power supply voltage is supplied from the independent internal power supply circuit 61 to the peripheral circuit 90, but the present invention is not limited to such a configuration. That is, peripheral circuit 90 directly connects external power supply voltage Ext. A configuration driven by Vcc is also possible.

  Recently, a method of switching the voltage level of the sense amplifier power supply according to timing in order to direct higher-speed operation has been proposed. However, the present invention is also realized under such a method. In the above method, the voltage level of the sense amplifier power supply is set such that the first S / A voltage level corresponding to the “H” level of data and the second S / A voltage higher than the first S / A voltage level. Adopting a configuration that can be switched to a level, the precharge operation after the data write / read operation is started by supplying the second S / A voltage level, and the operation speed is increased by shortening the precharge time. It is intended.

  Under this configuration, the power supply system is configured as shown in FIG. 24, for example, and the reference voltage Vref. By using the first S / A voltage level corresponding to the “H” level of data, the effects of the present invention can be enjoyed together.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing an overall configuration of a system LSI according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating in detail a configuration of a memory cell array, an amplifier, a write driver, a GI / O line precharge circuit, and a sense amplifier illustrated in FIG. 1. FIG. 3 is a circuit diagram showing a specific configuration of the sense amplifier shown in FIG. 2. FIG. 3 is a circuit diagram showing a specific configuration of the write driver shown in FIG. 2. 4 is a timing chart for explaining the operation of the system LSI according to the first embodiment of the present invention. 1 is a block diagram showing a power supply system of a DRAM according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing another configuration example of the global input / output line precharge circuit shown in FIG. 2. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 2 of this invention. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 3 of this invention. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 4 of this invention. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 5 of this invention. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 6 of this invention. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 7 of this invention. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 8 of this invention. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 9 of this invention. It is a block diagram showing a configuration of a memory cell array, an amplifier, a write driver, an I / O line precharge circuit, and a sense amplifier in a system LSI according to a tenth embodiment of the present invention. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 10 of this invention. It is a block diagram which shows the power supply system inside DRAM in the system LSI by Embodiment 11 of this invention. It is a block diagram which shows the whole structure of the system LSI by Embodiment 12 of this invention. FIG. 23 is a diagram showing a circuit configuration of a write driver 23 in a DRAM according to a thirteenth embodiment. FIG. 38 shows a structure of a transfer gate 34 in the DRAM of the thirteenth embodiment. 4 is a conceptual diagram for explaining a problem in a P-type transistor 113 included in a transfer gate 34. FIG. FIG. 44 is a conceptual diagram showing a configuration of P-type transistors 58 and 59 included in a write driver 23 in a DRAM of Embodiment 13. FIG. 38 is a block diagram showing a power supply system of a DRAM according to the thirteenth embodiment. FIG. 44 is a block diagram showing a power supply system of a DRAM according to the fourteenth embodiment. FIG. 34 is a block diagram showing a DRAM power supply system of another example of the fourteenth embodiment. It is a block diagram which shows an example of the power supply system in the conventional DRAM. 1 is a diagram showing an overall configuration of a DRAM 500 having a hierarchical I / O line structure. 2 is a diagram showing in detail a configuration of a memory mat 501 of a DRAM 500. FIG. 4 is a schematic diagram for explaining column selection and data transmission in DRAM 500. FIG. 5 is a diagram showing a configuration of a transfer gate 520. FIG. 2 is a schematic diagram showing a configuration of a multi-bit DRAM 600. FIG. 4 is a schematic diagram for explaining connection between a −I / O line and a sense amplifier in DRAM 600. FIG.

Explanation of symbols

  11, 12, 60 Internal power supply circuit, 13 memory cell array, 14 row address strobe buffer, 15 column address strobe buffer, 17 address buffer, 18 row decoder, 20 column decoder, 23, 23a, 23b write driver, 24, 24a1-24an 24b1-24bn Global I / O line precharge circuit, 25, 25a1-25an, 25b1-25bn sense amplifier, 32 memory cells, 34a, 34b transfer gate, 58, 59, 113, 150 P-type transistor, 71-82 pad, 124, 124a1-124an, 124b1-124bn I / O line precharge circuit, 131, 141 P-type substrate, 132, 142, 154 body, 134, 135, 144, 145 source / drain, 133, 43 gate, 136,145 body contact, Ext. Vcc external power supply voltage, Vcc1, Vcc2, Vcc3 internal power supply voltage, Ext. / RAS external row address strobe signal, / RAS internal row address strobe signal, Ext. / CAS external column address strobe signal, / CAS internal column address strobe signal, Ext. / WE external write enable signal, / WE internal write enable signal, WL word line, BL, / BL bit line pair, LI / O-a, LI / O-b local I / O line pair, GI / O, GI / Oa, GI / Ob Global I / O line pair, I / O, I / Oa, I / Ob I / Ob pair.

Claims (4)

A memory cell array having a plurality of memory cells arranged in a plurality of rows and columns;
A plurality of word lines each corresponding to the plurality of rows;
A plurality of bit line pairs provided corresponding to the plurality of columns,
A local I / O line pair;
A plurality of column selection gates each provided corresponding to the plurality of bit line pairs, each connected between the corresponding bit line pair and the local input / output line pair;
A global I / O line pair,
A transfer gate connected between the local input / output line pair and the global input / output line pair;
A first internal power supply unit and the second internal power supply means each of which generates a low have Internal power supply voltage than the external power supply voltage by receiving an external power supply voltage,
Provided corresponding to each bit line pair is connected to a corresponding bit line pair, and operates by receiving a pre-Symbol Internal power supply voltage from said first internal power supply means, it is read from the memory cells in said memory cell array A sense amplifier for amplifying the received data signal;
And connected to said global input and output line pairs, the second operates by receiving a pre-Symbol Internal power supply voltage from the internal power supply unit, the write data signal to the memory cell in the memory cell array write driver,
Voltage balancing means (65 or 67) for making the generated voltage of the first internal power supply means and the generated voltage of the second internal power supply means the same level ;
The transfer gate includes a P-type MOS transistor,
One of the source and drain of the P-type MOS transistor is connected to one of the local input / output line pairs, the other of the source and drain is connected to one of the global input / output line pairs, and the gate thereof is It said receiving a selection signal associating the local input and output line to said global input and output line pairs, the the well beneath the gate Ru is applied the internal power supply voltage, the semiconductor integrated circuit device. The voltage balancing means (65 or 67)
2. The semiconductor integrated circuit device according to claim 1, further comprising a power supply wiring (65) for connecting an output node of the first internal power supply means and an output node of the second internal power supply means. The voltage balancing means (65 or 67)
A reference voltage generating means (67) for receiving the external power supply voltage and generating a reference voltage signal corresponding to the internal power supply voltage;
And a signal line for transmitting the reference voltage signal to said first and second internal power supply means, a semiconductor integrated circuit device according to claim 1. A memory cell array having a plurality of memory cells arranged in a plurality of rows and columns;
A plurality of word lines each corresponding to the plurality of rows;
A plurality of bit line pairs provided corresponding to the plurality of columns,
A local I / O line pair;
A plurality of column selection gates each provided corresponding to the plurality of bit line pairs, each connected between the corresponding bit line pair and the local input / output line pair;
A global I / O line pair,
A transfer gate connected between the local input / output line pair and the global input / output line pair;
Internal power supply means for receiving an external power supply voltage and generating an internal power supply voltage lower than the external power supply voltage;
A sense amplifier provided corresponding to each bit line pair, connected to the corresponding bit line pair, operating in response to the internal power supply voltage, and amplifying a data signal read from a memory cell in the memory cell array;
A write driver connected to the global input / output line pair, operating in response to the internal power supply voltage, and writing a data signal to a memory cell in the memory cell array ;
The transfer gate includes a P-type MOS transistor,
One of the source and drain of the P-type MOS transistor is connected to one of the local input / output line pairs, the other of the source and drain is connected to one of the global input / output line pairs, and the gate thereof is It said receiving a selection signal associating the local input and output line to said global input and output line pairs, the the well beneath the gate Ru is applied the internal power supply voltage, the semiconductor integrated circuit device.

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