JP4807075B2 - Imaging device and defective pixel correction method thereof - Google Patents

Description

  The present invention relates to an imaging apparatus that includes a solid-state imaging device such as a charge coupled device (CCD) and a complementary metal oxide semiconductor (CMOS) sensor, and improves sensitivity by pixel addition, and particularly has an ability to compensate for defective pixels. The present invention relates to an apparatus and a defective pixel correction method thereof.

In general, it is known that a solid-state imaging device such as a CCD or a CMOS has a defective pixel that outputs an abnormal imaging signal due to a local crystal defect of a semiconductor and causes image quality degradation due to this.
These include, for example, black defect pixels and white defect pixels, both of which are isolated points.

Conventionally, various methods and circuit configurations for correcting these defective pixels by signal processing have been proposed. Basically, however, the defective pixels have storage means (memory or buffer) for storing the position data of the defective pixels. Defect correction means for correcting such data by replacing it with the previous data or the average value data of neighboring pixels is generally used. Conventionally, for example, there is Japanese Patent No. 3544304.
Japanese Patent No. 3544304

Now, a solid-state imaging device may be provided with a mode for reducing the image size and increasing the frame rate.
In this mode, for example, a total of four pixels of two pixels, top, bottom, left, and right, are added and treated as one pixel, and the image size is 1/4, but the time for outputting one screen is also 1/4.
When using this mode, if even one of the four pixels to be added contains a defective pixel, the pixel after the addition is also treated as a defective pixel.
In addition, as the number of additions increases, the possibility that the number of defective pixels included in the addition pixels increases also increases. Furthermore, there is a high possibility that what was an isolated point defect before addition becomes a continuous defect by addition.

Here, in the conventional defect correction, only the address information at the maximum image size before addition is stored as the position information of the defective pixel.
For this reason, in the pixel addition mode, a storage device for storing address information therefor must be prepared separately or calculated from the address information of the maximum image size.
If a separate storage device is prepared, the circuit scale increases. In the case of obtaining from the address in the maximum size, the processing when the added pixel includes a plurality of defects is complicated (address information is stored in order of position and sequentially processed).
When a plurality of defects are included in the addition pixel, the same addition pixel has a plurality of pieces of address information, but the processing must have a structure that ignores other than the first address. For this reason, in the pixel addition mode, defect correction is mostly not performed.

In recent years, in order to increase the number of pixels and reduce the size without reducing the sensitivity of the solid-state imaging device, a configuration in which a signal detection transistor is shared by a plurality of pixels has been adopted.
In this configuration, when the signal detection transistor shared by the plurality of pixels becomes defective, all the shared pixels become defective pixels, and in the case of defective pixels due to this cause, the defect at the isolated point Instead, a defect occurs in the shared pixel arrangement pattern.
Here, even if a conventional defect correction method is used, it can be corrected without any problem.

However, since it is a defect in the shared pixel arrangement pattern, if the position of one pixel among the shared pixels is known, the position information of all the shared pixels is stored even though the positions of the other pixels are obvious. Therefore, the memory capacity for storing the defect information is wasted.
When correction is performed, depending on the shared pixel arrangement pattern, a pixel used for interpolation may be defective, and thus a function for determining a defect of the pixel used is required.

  It is an object of the present invention to provide an imaging apparatus capable of simplifying position information calculation and suppressing an increase in circuit scale of a defect correction system and a defective pixel correction method thereof.

According to a first aspect of the present invention, there is provided an imaging apparatus capable of reading information of a plurality of pixel units of an imaging device, storing defective pixel information, and in addition to the defective pixel information, A defect information storage unit that stores information indicating a defect status with respect to information of a plurality of pixel units, and position information of the plurality of pixel units is generated based on the defect pixel information and flag information stored in the defect information storage unit, and generated position information based on anda defect correction unit that performs defect correction on the read image signal of the image pickup device, readable pixel addition readout mode while a plurality adds the image information of each pixel of the image sensor And a normal pixel read mode in which pixel information is read without pixel addition, and the output from the image sensor is added to the flag information in the defect information storage unit. When the pixel after addition in the state includes two or more defective pixels in the state before the addition, the second and subsequent defective pixels include flag information that invalidates the position information, and the defect correction unit In the normal pixel readout mode, defect correction is performed based on the position information stored in the defect information storage unit .

Preferably, the upper Symbol defect correction unit includes a determination unit for determining a defective pixel after pixel addition based on the flag information in the defect information storage unit, a position information generating unit for generating position information of the added pixel, And a defect correction circuit that performs defect correction based on the generated position information.

In addition, the present invention is an imaging apparatus capable of reading out information of a plurality of pixel units of an image sensor, stores defective pixel information, and in addition to the defective pixel information, a plurality of pixel units of the image sensor A defect information storage unit that stores information indicating a defect status with respect to the information of the image, and the positional information generated by generating the position information of the plurality of pixels based on the defective pixel information and flag information stored in the defect information storage unit A defect correction unit that performs defect correction on the read image signal of the image sensor based on the information, and the information of the plurality of pixel units includes a plurality of pixel information sharing the signal detection element, and the defect information The flag information of the storage unit includes flag information indicating that the signal detection element of the image sensor is a defect in a state shared by a plurality of pixels, and the defect correction unit detects the defect based on the generated position information. Picture Correcting all shared pixels determined to.
Preferably, the upper Symbol defect correction unit includes a shared determination unit determines all pixels with defects that are shared on the basis of flag information indicating a defect in the pixel shared state, according to a determination result of the shared determination unit A position information generation unit that generates position information of the shared pixels, and a defect correction circuit that corrects all of the shared pixels that are determined to be defective pixels based on the generated position information.

  Preferably, there is provided a buffer for referring to the position information generated by the position information generation unit with the defect correction circuit.

  Preferably, the defect correction unit performs an interpolation process that does not use a neighboring pixel that is a defect if the defect is due to pixel sharing and the neighboring pixel used for correction is also a defect.

According to a second aspect of the present invention, there is provided a defective pixel correction method for an image pickup apparatus capable of reading out information of a plurality of pixel units of the image pickup device, in addition to the defective pixel information, information of the plurality of pixel units of the image pickup device. information indicating the defective status is stored in the defect information storage section for, based on the defect information the defect pixel information stored in the storage unit and the flag information to generate position information of the plurality of pixels, based on the generated position information the have line defect correction on the read image signal from the image sensor, the reading of pixel information without readable pixel addition reading mode, and pixel addition with a plurality adds the image information of each pixel of the image pickup device In the flag information, the pixel after addition in the state where the output from the image sensor is added is displayed in the flag information in the state before the addition. In the normal pixel read mode, the second and subsequent defective pixels include flag information that invalidates the position information, and are stored in the defect information storage unit in the normal pixel readout mode. Defect correction is performed based on the positional information .
In addition, the present invention is a defective pixel correction method for an image pickup apparatus capable of reading out information of a plurality of pixel units of the image pickup device, and includes a defect situation for information of the plurality of pixel units of the image pickup device in addition to the defective pixel information. Information is generated, position information for each of the plurality of pixels is generated based on the stored defective pixel information and flag information, and defect correction is performed on the read image signal of the image sensor based on the generated position information. The information of the plurality of pixels includes a plurality of pieces of pixel information sharing the signal detection element, and the flag information is a defect in a state where the signal detection element of the imaging element is shared by the plurality of pixels. When performing the defect correction, the flag information indicating the fact is corrected, and all the shared pixels determined to be defective pixels based on the generated position information are corrected .

According to the present invention, it is possible to cope with defect correction at the time of pixel addition while suppressing an increase in memory.
In addition, the capacity of the defect information storage memory can be greatly reduced.
Furthermore, even if neighboring pixels used for correction become defective due to pixel sharing, it is possible to cope with them.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus according to the first embodiment of the present invention.

As shown in FIG. 1, the imaging apparatus 10 includes a lens system 11, for example, an imaging element 12 formed by a CMOS sensor, a pre-processing unit 13, a pixel defect detection unit 14, a defect information storage memory 15, a defect correction unit 16, And a camera signal processing unit 17.

The image sensor 12 has a plurality of unit pixels arranged in a matrix. In the present embodiment, the image sensor 12 is configured to be readable while adding a plurality of pieces of pixel information of the unit pixels by the drive unit of the image sensor 12.
The imaging apparatus 10 of the present embodiment thus has a pixel addition reading mode MOD1 that performs reading while adding a plurality of pieces of pixel information of unit pixels, and a normal pixel reading mode MOD2 that reads pixel information without performing pixel addition. And is configured to be selectively settable.

FIG. 2 is a circuit diagram illustrating a first configuration example of a unit pixel of the image sensor 12 according to the present embodiment.
As shown in FIG. 2, each pixel 120 is basically stored in a photoelectric conversion element 121 that receives light and accumulates signal charges, an amplification transistor 122 that amplifies the accumulated signal charges, and photoelectric conversion elements 121. A transfer transistor 123 that transfers signal charges to the gate electrode of the amplification transistor 122 and a reset transistor 124 that resets the gate potential of the amplification transistor 122 are included.
The drains of the amplification transistor 122 and the reset transistor are connected to the selection signal wiring 125, the source of the amplification transistor 122 is connected to the signal line 126, and the gate electrode of the transfer transistor 123 is connected to the transfer signal wiring 127.
A plurality of selection signal lines 125 and transfer signal lines 127 and signal lines 126 are arranged in a matrix so as to be orthogonal to each other, and the selection signal lines 125 and the transfer signal lines 127 are selectively driven by a vertical selection circuit (not shown) to generate signals. The line 126 is connected to a CDS circuit (correlated double sampling circuit) or the like.

  The pre-processing unit 13 performs sampling processing, quantization processing, and the like on the analog pixel information read from the image sensor 12, converts the analog signal into a digital signal (A / D conversion), and performs the defect correction circuit 16. , And the pixel defect detection unit 14.

  The pixel defect detection unit 14 detects a defective pixel based on the digital pixel information supplied from the pre-processing unit 13.

The defect information storage memory 15 stores pixel defect position information (address information) detected by the pixel defect detection unit 14, and the pixel after addition in a state where the output from the image sensor 12 is pixel-added is stored. When two or more defective pixels are included in the state before being added, the second and subsequent defective pixels also store flag information indicating that the position information is invalid (not corrected (care)).

  FIGS. 3A to 3C are diagrams illustrating an example in which the defect address in the pixel addition state in the defect information storage memory 15 according to the first embodiment is stored, and is stored in the defective pixel and the memory. It is a figure which shows the relationship between an address and a flag.

The example of FIG. 3A is a case of all pixel readout, and shows a 4 × 4 pixel matrix extracted.
The first row is an R, G, R, G pixel array, the second row is a GB, R, GB, B pixel array, and the third row is an R, G, R, G pixel. The fourth row is a pixel array of GB, B, GB, and B.

FIG. 3B shows the relationship between the address ADR15 stored in the defect information storage memory 15 and the flag FLG15.
In this example, in the 3 × 3 pixel addition indicated by a bold line in FIG. 3A, the address of the R pixel in the first row and the first column is N, and the R pixel in the first row and the first column and the address (N + 3 line + 2) ), That is, when there is a defect in the R pixel in the third row and the third column, the pixel after the addition in the state where the output from the image sensor 12 is added is the pixel before the addition. When the state includes two or more defective pixels, flag information indicating that the second and subsequent defective pixels invalidate the position information (do not perform correction (care)) is stored as “1”.
In this case, the address addition for pixel addition stores the address N of the R pixel in the first row and the first column of the 3 × 3 pixel array.
Thus, in the present embodiment, it can be seen that it can be dealt with by adding a flag without adding a defect information storage memory for pixel addition.

  FIG. 3C shows a case where the defect correcting unit 16 uses the information of the flag FLG15 by performing address conversion in the pixel addition reading mode MOD1.

  The defect correction unit 16 applies flag information stored in the defect information storage memory 15 to the digital image signal by the pre-processing unit 13 and address information (position information) according to the pixel addition reading mode MOD1 or the normal pixel reading mode MOD2. ) To correct defects.

  The camera signal processing unit 17 performs processing such as color interpolation, white balance, and compression on the output image signal of the defect correction unit 16.

  FIG. 4 is a block diagram illustrating a configuration example of the defect correction unit 16 according to the first embodiment.

  The defect correction unit 16 in FIG. 4 determines the defective pixel after pixel addition based on the flag FLG15 of the defect information storage memory 15 and the determination unit 161 determines the information of the address ADR15 of the defect information storage memory 15. A selector 162 that selects and outputs based on the result, an address converter 163 that generates an address that is position information of the added pixel by address conversion based on the address information selected by the selector 162, and a pixel addition read mode MOD1 or normal A selector 164 that selects and outputs the address information ADR15 by the defect information storage memory 15 or the address information ADR163 of the added pixel by the address converter 163 according to the signal indicating the pixel readout mode MOD2, and the address information selected by the selector 164 Defect correction based on It has a correction circuit 165, a.

In the pixel addition readout mode MOD1, the selector 164 selects the address information ADR 163 of the added pixel by the address conversion unit 163 and outputs it to the defect correction circuit 165.
On the other hand, the selector selects the address information ADR15 from the defect information storage memory 15 and outputs it to the defect correction circuit 165 in the normal pixel readout mode MOD2.

  The address conversion of the address conversion unit 163 can be easily obtained as follows. Therefore, it can be realized with small-scale hardware.

(Equation 1)
Vertical address after conversion = vertical address before conversion / number of vertical pixels to add Horizontal address after conversion = horizontal address before conversion / number of horizontal pixels to add

  FIG. 5 is a diagram for explaining the operation of the defect correction unit 16 according to the first embodiment.

The captured image of the image sensor 12 is subjected to predetermined processing by the pre-processing unit 13 and input to the defect correction unit 16 as a digital image signal.
In the defect correction unit 16, the determination unit 161 reads the flag FLG15 in the defect information storage memory 15 (ST1).
In the pixel addition reading mode (ST2), the information of the address ADR15 in the defect information storage memory 15 is read out to the address conversion unit 163 through the selector 162 (ST3).
In the address conversion unit 163, an address that is position information of the addition pixel is generated by address conversion based on the address information selected by the selector 162 (ST4).
The address information ADR 163 of the added pixel obtained by this address conversion is supplied to the defective pixel circuit 165 through the selector 164.
Then, the defective pixel circuit 165 performs defect correction on the input image based on the address information ADR 163 of the addition pixel.

  On the other hand, in the normal pixel readout mode MOD2, the address information ADR15 from the defect information storage memory 15 is supplied to the defect correction circuit 165 through the selector 164, and defect correction is performed on the input image.

As described above, according to the first embodiment, pixel defect information detected by the pixel defect detection unit 14 is stored, and addition in a state where the output from the image sensor 12 is pixel-added. When the subsequent pixel includes two or more defective pixels in a state before addition, flag information indicating that the second and subsequent defective pixels invalidate the position information (do not correct (care)) Defect correction for performing defect correction based on address information (position information) corresponding to the pixel addition reading mode MOD1 or the normal pixel reading mode MOD2 for the digital image signal by the defect information storage memory 15 to be stored and the pre-processing unit 13. The defect correction unit 16 includes a determination unit 161 that determines a defective pixel after pixel addition based on the flag FLG15 of the defect information storage memory 15, and a defect information storage. A selector 162 that selects and outputs the information of the address ADR15 of the memory 15 based on the determination result of the determination unit 161, and an address that is position information of the addition pixel is generated by address conversion based on the address information selected by the selector 162. The address conversion unit 163 and the address information ADR15 by the defect information storage memory 15 or the address information ADR163 of the addition pixel by the address conversion unit 163 are selected and output according to a signal indicating the pixel addition reading mode MOD1 or the normal pixel reading mode MOD2. Since the selector 164 and the defect correction circuit 165 that performs defect correction based on the address information selected by the selector 164 are provided, the following effects can be obtained.

In the correction of defective pixels when the solid-state image sensor is added and output, if there are a plurality of defects in the added pixels, the position information calculation after the addition only needs to know one position, Since the flag for invalidating other position information (address information) is provided, it is possible to simplify the calculation of the position information after addition and to realize a defect correction unit that suppresses an increase in circuit scale.
In other words, it is possible to cope with defect correction at the time of pixel addition while suppressing an increase in memory, and the capacity of the defect information storage memory can be greatly reduced.

Second Embodiment
FIG. 6 is a block diagram illustrating a configuration example of an imaging apparatus according to the second embodiment of the present invention.

The second embodiment is different from the first embodiment in that the imaging device 12A has a circuit corresponding to a case where a plurality of pixels share a signal detection transistor (amplification transistor).
The other configuration is the same as that of the first embodiment. In FIG. 6, the same components as those in FIG.

  Hereinafter, a configuration example of the shared pixel of the image sensor 12A, storage information of the defect information storage memory 15A, and a configuration and function of the defect correction unit 16A will be described.

  FIG. 7 is a circuit diagram illustrating a specific configuration example in which a plurality of pixels share a signal detection transistor (amplification transistor).

As shown in FIG. 7, the shared pixel cell (unit cell) 200 includes two pixels 201 and 202, two upper and lower photoelectric conversion elements 203 and 204 in the figure, and transfer transistors 2055 and 206, respectively. Two pixels 201 and 2022 are formed by one reset transistor 207 and one amplification transistor 208.
The full-surface selection signal wiring 209 is connected to the drains of the reset transistors 207 and the amplification transistors 208. The full-surface selection signal wiring 209 is controlled together with the transfer signal wirings 210 and 211 and the reset signal wiring 212, so that the signal By performing the reading operation, simplification of the pixel wiring, reduction of the pixel, and the like are realized.

  The shared pixel 200 is illustrated as an example in which two pixels are shared, but can be configured similarly in the case of a plurality of pixels, for example, four pixels.

  In the defect information storage memory 15A of the second embodiment, in addition to the defect position information of the pixel, the signal detection transistor (amplification transistor and reset transistor in the example of FIG. 7) is shared by a plurality of pixels. A flag indicating that the defect is a defect is also stored.

  FIGS. 8A to 8C are diagrams illustrating a first example when a defective address in a pixel sharing state is stored.

FIG. 8A shows a first example of shared pixels. This example shows a case of sharing 4 pixels in a 2 × 2 matrix array.
FIG. 8B shows storage information in the defect information storage memory 15A when the shared pixel in FIG. 8A has a defect.
In this case, if there is a defect in the shared pixel, the address of the pixel in the first row and the first column is stored as N in the 2 × 2 shared pixel. In addition to this, flag information indicating that the shared pixel is defective is stored as “1”.

FIG. 8C shows the address information developed in the defect address storage buffer when the defect correction unit 16 recognizes that there is a defect in the shared pixel from the flag information.
In this example, in addition to the address N, an address (N + 1), an address (N + 1 line), and an address (N + 1 line + 1) are expanded.
At this time, the flag “0” indicating the original address of the shared pixel is set in the address N, and the address (N + 1), address (N + 1 line), and address (N + 1 line + 1) are expanded to the address after that. A flag “1” indicating the expanded address is set.
This is because the defect between pixel shares is not used for interpolation in the defect correction process.

  FIGS. 9A to 9C are diagrams illustrating a second example in which a defective address in a pixel sharing state is stored.

FIG. 9A illustrates a second example of the shared pixel. This example shows a case of sharing four pixels arranged alternately in two columns instead of a 2 × 2 matrix arrangement.
FIG. 9B shows storage information in the defect information storage memory 15A when the shared pixel in FIG. 9A has a defect.
In this case, if there is a defect in the shared pixel, the address of the pixel in the first row and first column is stored as N in the shared pixel. In addition to this, flag information indicating that the shared pixel is defective is stored as “1”.

FIG. 9C shows address information developed in the defect address storage buffer when the defect correction unit 16 recognizes that there is a defect in the shared pixel from the flag information.
In this example, in addition to the address N, an address (N + 1), an address (N + 1 line), and an address (N + 1 line + 1) are expanded.
At this time, a flag “0” indicating that the original address of the shared pixel is set in the address N, and thereafter, the developed address (N + 1 line + 1), address (N + 2 line), and address (N + 3 line + 1) are set. The flag “1” indicating that the address has been expanded is set.
This is because the defect between pixel shares is not used for interpolation in the defect correction process.

  When the defect correction unit 16A according to the second embodiment determines that the pixel is shared based on the storage information of the defect information storage memory 15A, the defect correction unit 16A determines the address of the shared pixel based on the address information ADT15A of the defect information storage memory 15A. The defect is corrected by the generated address.

  FIG. 10 is a block diagram illustrating a configuration example of the defect correction unit 16A according to the second embodiment.

  The defect correction unit 16A in FIG. 10 determines whether the correction target is a shared pixel based on the flag FLG15A in the defect information storage memory 15A, and the share determination unit 166 determines that the defect is shared. An address generation unit 167 that generates an address of the shared pixel based on the address information ADT15A of the information storage memory 15A, and a defective address storage buffer 168 for referring to the current pixel address and the generated address (position) information by the correction circuit. And a defect correction circuit 169 that corrects all of the shared pixels determined to be defective pixels based on the address information buffered in the buffer 168.

  In the second embodiment, in the case of a defect due to pixel sharing, there is a possibility that neighboring pixels used for correction may also be defective. Therefore, as a corresponding correction method, In addition to the method of interpolating with an average value, in the case of a defect due to pixel sharing, and when a neighboring pixel used for correction is also a defect, an interpolation method that does not use a neighboring pixel that is a defect is taken.

FIG. 11 is a diagram illustrating a first example of the defect correction method according to the second embodiment.
In the pixel sharing state as shown in FIG. 11, the pixel used for interpolation (in this case, R8) is also defective and cannot be used as an interpolation pixel. For this reason, R8 is not used, and interpolation pixels are generated using only other normal pixels.

FIG. 12 is a diagram illustrating a second example of the defect correction method according to the second embodiment.
The example of FIG. 12 is processing when the target pixel is a pixel generated by address expansion in the method of FIG.
In this example, the pixel above the pixel of the developed address (in this case, R5) is also a defective pixel due to pixel sharing and cannot be used for interpolation. For this reason, R5 is not used, and interpolation pixels are generated using only other normal pixels.
This process can be determined by providing the buffer 168.

  FIG. 13 is a diagram for explaining the operation of the defect correcting unit 16A according to the second embodiment.

The captured image of the image sensor 12A is subjected to predetermined processing by the pre-processing unit 13 and is input to the defect correction unit 16A as a digital image signal.
In the defect correction unit 16A, the address ADR 15A is read from the defect information storage memory 15A (ST11), and the address of the current pixel is stored in the buffer 168 (ST12).
Then, the sharing determination unit 166 reads the flag FLG15A of the defect information storage memory 15A, and determines whether or not the pixels can be shared (ST13).
In the case of pixel sharing, the address generation unit 167 generates an address of the shared pixel (ST14), and the generated address is stored in the buffer 168 (ST15).
Then, address sorting is performed. Then, in the defect correction circuit 169, all of the shared pixels that are determined as defective pixels based on the address information buffered in the buffer 168 are corrected.

As described above, according to the second embodiment, in the correction of defective pixels in the case where the signal detection transistor of the image sensor 12A is shared by a plurality of pixels, there are a plurality of defects in the shared pixels. In this case, since the defect is stored in the shared state, it is possible to realize a correction circuit that suppresses an increase in circuit scale.
In other words, the defect information storage memory can be greatly reduced, and there is an advantage that the neighboring pixels used for correction can be dealt with even if they become defective due to pixel sharing.

1 is a block diagram illustrating a configuration example of an imaging apparatus according to a first embodiment of the present invention. It is a circuit diagram showing the 1st example of composition of a unit pixel of an image sensor concerning this embodiment. It is a figure which shows the example at the time of storing the defective address of the pixel addition state in the defect information storage memory of 1st Embodiment, Comprising: It is a figure which shows the relationship between the address stored in a defective pixel, memory, and a flag. It is a block diagram which shows the structural example of the defect correction part which concerns on 1st Embodiment. It is a figure for demonstrating operation | movement of the defect correction part which concerns on 1st Embodiment. It is a block diagram which shows the structural example of the imaging device which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the specific structural example which shares a signal detection transistor (amplification transistor) with a some pixel. It is a figure which shows the 1st example at the time of storing the defect address of a pixel shared state. It is a figure which shows the 2nd example at the time of storing the defect address of a pixel shared state. It is a block diagram which shows the structural example of the defect correction part which concerns on 2nd Embodiment. It is a figure which shows the 1st example of the defect correction method of 2nd Embodiment. It is a figure which shows the 2nd example of the defect correction method of 2nd Embodiment. It is a figure for demonstrating operation | movement of the defect correction part which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,10A ... Imaging device, 11 ... Lens system, 12, 12A ... Imaging element, 13 ... Pre-processing part, 14 ... Pixel defect detection part, 15, 15A ... Defect information Storage memory 16, 16A ... defect correction circuit, 17 ... camera signal processing unit.

Claims (8)

An imaging device capable of reading out information in units of a plurality of pixels of an imaging element,
A defect information storage unit that stores defect pixel information, and stores information indicating a defect status with respect to information of a plurality of pixel units of the imaging element in addition to the defect pixel information;
Based on the defective pixel information and flag information stored in the defect information storage unit, position information of the plurality of pixels is generated, and defect correction is performed on the read image signal of the image sensor based on the generated position information. It has a defect correction section, and
Including a pixel addition readout mode in which a plurality of image information of each pixel of the image sensor is added, and a normal pixel readout mode in which pixel information is read out without performing pixel addition,
In the flag information of the defect information storage unit, when the pixel after addition in a state where the output from the image sensor is added includes two or more defective pixels in the state before addition, The second and subsequent defective pixels include flag information that invalidates the position information,
The defect correction unit is
In the normal pixel readout mode, an imaging apparatus that performs defect correction based on position information stored in the defect information storage unit . Above Symbol defect correction unit,
A determination unit that determines a defective pixel after pixel addition based on the flag information in the defect information storage unit;
A position information generation unit that generates position information of the addition pixels;
The imaging device according to claim 1, further comprising: a defect correction circuit that performs defect correction based on the generated position information. An imaging device capable of reading out information in units of a plurality of pixels of an imaging element,
A defect information storage unit that stores defect pixel information, and stores information indicating a defect status with respect to information of a plurality of pixel units of the imaging element in addition to the defect pixel information;
Based on the defective pixel information and flag information stored in the defect information storage unit, position information of the plurality of pixels is generated, and defect correction is performed on the read image signal of the image sensor based on the generated position information. A defect correction unit,
The information of the plurality of pixel units includes a plurality of pixel information sharing the signal detection element,
The flag information of the defect information storage unit includes flag information indicating that the signal detection element of the image sensor is a defect in a state where the signal detection element is shared by a plurality of pixels,
The defect correction unit is
An imaging device that corrects all shared pixels determined to be defective pixels based on generated position information . Above Symbol defect correction unit,
A sharing determination unit that determines all pixels that are shared based on flag information indicating defects in the pixel sharing state as defects,
A position information generation unit that generates position information of a shared pixel according to a determination result of the sharing determination unit;
The imaging apparatus according to claim 3, further comprising: a defect correction circuit that corrects all of the shared pixels determined to be defective pixels based on the generated position information. The imaging apparatus according to claim 4, further comprising a buffer for referring to the position information generated by the position information generation unit in the defect correction circuit. The defect correction section, in the case of a defect in the pixel sharing, and if the neighboring pixels to be used for correction is also defective, any one of claims 3 to 5 for performing an interpolation process that does not use neighboring pixels is a defective the image pickup apparatus according to. A defective pixel correction method for an image pickup apparatus capable of reading out information of a plurality of pixel units of an image pickup element,
In addition to the defective pixel information, the defect information storage unit stores information indicating a defect status with respect to information on a plurality of pixel units of the image sensor,
Based on the defective pixel information and flag information stored in the defect information storage unit, to generate position information of the plurality of pixels,
Based on the generated position information it has line defect correction to the read image signal of the image pickup device,
Including a pixel addition readout mode in which a plurality of image information of each pixel of the image sensor is added, and a normal pixel readout mode in which pixel information is read out without performing pixel addition,
In the flag information, when the pixel after addition in the state where the output from the image sensor is pixel-added includes two or more defective pixels in the state before addition, the second and subsequent pixels The defective pixel includes flag information that invalidates the position information,
When performing the above defect correction,
In the normal pixel readout mode, a defective pixel correction method for an imaging apparatus that performs defect correction based on position information stored in the defect information storage unit . A defective pixel correction method for an image pickup apparatus capable of reading out information of a plurality of pixel units of an image pickup element,
In addition to the defective pixel information, information indicating the defect status for the information of the plurality of pixels of the image sensor is stored,
Based on the stored defective pixel information and flag information, the position information of the plurality of pixels is generated,
Perform defect correction on the read image signal of the image sensor based on the generated position information,
The information of the plurality of pixel units includes a plurality of pixel information sharing the signal detection element ,
To the flag information, see contains flag information indicating that a defect in a state where the signal detection element of the image pickup device is shared by a plurality of pixels,
When performing the above defect correction,
A defective pixel correction method for an imaging apparatus, which corrects all shared pixels determined to be defective pixels based on generated position information .

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