JP4801682B2 - Display device - Google Patents

Description

  The present invention relates to a contact structure for electrically connecting wirings formed on opposing substrates via conductive spacers. In particular, the present invention relates to a contact structure applied to a common contact of an electro-optical device such as a liquid crystal display device.

  In recent years, a liquid crystal display device has been widely used for a display unit of a portable information terminal device (mobile device) such as a mobile computer or a mobile phone (including PHS). As a liquid crystal display device, an active matrix liquid crystal display device using a thin film transistor as a switching element is widely known.

  In a liquid crystal display device, liquid crystal is sealed in two substrates, an electric field is formed by electrodes respectively formed on the two substrates, and display is performed by controlling the electric field strength. In an active matrix liquid crystal display device, one of two substrates is called a TFT substrate because a thin film transistor (TFT) for controlling voltage supply is formed on a pixel electrode, and the other substrate is called Since a counter electrode facing the pixel electrode is formed, it is called a counter substrate.

  In an active matrix display device, display is realized by generating an electric field between a pixel electrode on a TFT substrate and a counter electrode on a counter substrate. Although the potential of the pixel electrode on the TFT substrate is controlled and varied by the thin film transistor, the counter electrode on the counter substrate is fixed at a constant common potential. In order to fix the counter electrode at a common potential, the counter electrode is connected to an extraction terminal via a common contact formed on the TFT substrate, and the extraction terminal is connected to a power supply outside the substrate. With such a connection configuration, the potential of the counter electrode is fixed to the common potential by the power supply.

  The structure of the common contact of the conventional active matrix display device will be briefly described below with reference to FIGS.

  FIG. 12 is a top view of the TFT substrate 10. On the substrate 11, the pixel region 12 in which pixel electrodes and thin film transistors connected to the pixel electrodes are arranged in a matrix and the ON / OFF timing of the thin film transistors are controlled. There are provided a scanning line driving circuit 13 and a signal line driving circuit 14 for supplying image data to the pixel electrodes. Furthermore, an extraction terminal 15 for supplying electric power and a control signal from the outside is provided, and common contact portions 16a to 16d serving as connection portions with the counter electrode are provided.

  FIG. 13 is a cross-sectional configuration diagram of the pixel region 12 and the common contact portion 16. As shown in FIG. 13, in the pixel region 12 of the TFT substrate 11, a thin film transistor 17 is formed on the substrate 11, an interlayer insulating film 18 is formed on the thin film transistor 17, and a thin film transistor 17 is formed on the interlayer insulating film 18. A pixel electrode 19 connected to the drain electrode is formed.

  In the common contact portion 16, the internal wiring 21 is formed by patterning the starting film of the source / drain electrode of the thin film transistor 17. A rectangular opening is formed in the interlayer insulating film 18, and a conductive pad 22 connected to the internal wiring 21 is formed in the opening. The pixel electrode 19 and the conductive pad 22 are patterned from the same starting film.

  FIG. 14 is a top view of the conventional common contact portion 16, and the dotted line region inside the conductive pad 22 corresponds to the opening formed in the interlayer insulating film 18.

  As shown in FIG. 13, a counter electrode 24 made of a transparent conductive film is formed on the surface of the counter substrate 23, the counter electrode 24 faces the pixel electrode 19 in the pixel region 12, and the conductive pad 22 in the common contact portion 16. opposite.

  In order to maintain the distance between the substrates 11 and 23, a spherical insulating spacer 25 is disposed in the pixel region 12, and a spherical conductive spacer 26 is disposed in the common contact portion 16. The counter electrode 24 is electrically connected to the conductive pad 22 of the TFT substrate by the conductive spacer 26. The conductive pad 22 is electrically connected to the internal wiring 21, and the internal wiring 21 is electrically connected to the extraction terminal 15. With such a connection configuration, the counter electrode 24 on the counter substrate 23 side is connected to the extraction terminal 15 on the TFT substrate 11 side.

  In the conventional liquid crystal display device, as shown in FIG. 13, since an opening is formed in the interlayer insulating film 18 in the common contact portion 16, (cell gap Gc in the common contact portion) ≈ (cell gap in the pixel region) Gp) + (film thickness t of the interlayer insulating film 18).

  The cell gap Gp of the pixel region 12 is defined by the spacer 25. Since a standard product is used for the spacer 25, if the diameter of the spacer 25 is the same, the cell gap Gp of the pixel region 12 is substantially the same for each substrate. However, it is difficult to avoid the cell gap Gc of the common contact portion varying from substrate to substrate.

  The cell gap Gc of the common contact portion depends only on the film thickness t of the interlayer insulating film 18 because the cell gap Gp is constant from the above relationship. Therefore, in order to make the cell gap Gc constant for each substrate, it is necessary to prevent the film thickness t of the interlayer insulating film 18 from varying. The film thickness t of the interlayer insulating film 18 is the same film for each substrate. Even if the film is formed to have a thickness t, it is inevitable that the film thickness t varies from substrate to substrate.

  In addition, two to four common contact portions of the liquid crystal display device are usually formed. Even in the same substrate, the film thickness t of the interlayer insulating film 18 may vary from place to place. Even if it exists, there exists a possibility that the film thickness t may differ for every common contact part.

  Due to such variations in the film thickness t of the interlayer insulating film 18, the cell gap Gc of the common contact portion varies from substrate to substrate or from common contact portion. Further, the variation of the cell gap Gc causes the variation of the cell gap Gp in the pixel region.

  The influence of the variation in the cell gap Gc in the common contact portion on the cell gap Gp in the pixel region becomes more apparent as the area of the pixel region 12 becomes relatively smaller than the area of the common contact portion. In particular, a projection display used for a projector or the like is a very high-definition small display of about 1 to 2 inches, and thus the above-described problem of variation in the cell gap Gp of the pixel region becomes obvious.

  A standard product is also used for the conductive spacer 26, and the diameter is determined by the diameter of the spacer 25 in the pixel region 12 and the thickness of the interlayer insulating film 18 at the time of design. However, when the film thickness of the interlayer insulating film 18 is much larger than the design value, the cell gap Gc of the common contact portion becomes very large. Therefore, the conductive spacer 26 makes the counter electrode a conductive pad. It becomes impossible to connect. In such a case, the potential of the counter electrode cannot be fixed to the common potential, and display cannot be performed.

  The object of the present invention is to eliminate the above-mentioned problems, eliminate variations in the distance between substrates from one substrate to another even if the film thickness of the interlayer insulating film varies, and reduce the occurrence of contact failures caused by conductive spacers. An object of the present invention is to provide a contact structure that makes it possible.

  In order to solve the above-described problems, the configuration of the present invention includes a first conductive film, an insulating film provided on the first conductive film, an opening provided in the insulating film, A common contact portion provided with a second conductive film electrically connected to the first conductive film in the opening, and a conductive spacer; and a second contact layer provided opposite to the common contact portion. The second conductive film and the third conductive film are electrically connected by the conductive spacer, and the fourth conductive film is formed on the third conductive film. The conductive film is provided.

  Further, it is preferable that the conductive spacer is in contact with both the second conductive film and the third conductive film on the insulating film. In this case, it is preferable that the third conductive film has a light-transmitting property and an opening is provided at a position overlapping the opening of the fourth conductive film. Further, in this case, it is preferable that the area of the opening provided in the fourth conductive film is larger than the area of the opening.

  The conductive spacer may be in contact with both the second conductive film and the third conductive film in the opening.

  Further, the substrate provided with the common contact portion is provided with a pixel region, and the fourth conductive film and the black matrix provided opposite to the pixel region are formed from the same starting film. Preferably it is formed.

  Note that ITO can be typically used for the second conductive film and the third conductive film.

  According to the common contact structure of the present invention, even if the film thickness of the interlayer insulating film varies, it is possible to eliminate variations in the distance between the substrates and to reduce the occurrence of contact failure caused by the conductive spacer.

  That is, in the present invention, since the substrate interval depends only on the size of the conductive spacer, if the size of the conductive spacer is the same, the first conductive film and the second conductive film are connected. Even when the thickness of the insulating film that is insulated differs from one substrate to another, the distance between the opposing substrates can be the same for each substrate.

An embodiment of the present invention will be described with reference to FIGS.

First Embodiment FIG. 1 is a cross-sectional configuration diagram of a common contact portion according to the present embodiment, and FIG. 2 is a top view on the TFT substrate side. A cross-sectional enlarged view of the region 120 illustrated in FIG. 2A corresponds to FIG.

  As shown in FIG. 13, in the conventional example, the spacer in the pixel region 12 is disposed on the interlayer insulating film 18 via the pixel electrode 19, but the interlayer insulating film is formed below the conductive pad 22 of the common contact portion 16. 18 does not exist. The absence of the interlayer insulating film 18 causes the cell gap Gc of the common contact portion to depend on the film thickness of the interlayer insulating film 18.

  Therefore, in the present embodiment, an insulator is also present below the conductive pad in the common contact portion, and a conductive spacer is disposed on the insulator, so that the cell gap Gc in the common contact portion is reduced to the interlayer insulating film 18. This embodiment is characterized in that the opening is formed so as to selectively leave the interlayer insulating film 18.

  In this embodiment, the first substrate 101 has a first conductive film 103, an insulating film 104 covering the first conductive film 103, and the insulating film 104 is selectively left open so that the first conductive film is opened. An opening 111 exposing 103, and a second conductive film 105 covering the remaining insulating film 104a and opening 111 are formed.

  A third conductive film 106 is formed over the second substrate 102, and a conductive spacer 107 is sandwiched between the first substrate 101 and the second substrate 102.

  In the case of the conventional common contact portion 16 shown in FIG. 13, the interlayer insulating film 18 has been completely removed from the opening 110, but in this embodiment, the insulating film 104a is selectively left to leave the opening 111. Form. The first conductive film 103 is exposed through the opening 111, and the first conductive film 103 and the second conductive film 105 are connected to each other.

  Further, since the remaining insulating film 104a is closest to the second substrate 102 on the first substrate 101 side, a conductive spacer is formed on the remaining insulating film 104a as shown in FIG. By 107, the second conductive film 105 on the first substrate and the third conductive film 106 on the second substrate 102 are electrically connected.

  Further, since the remaining insulating film 104 a is closest to the second substrate in the opening 110, the conductive spacer 107 that electrically connects the second conductive film 105 and the third conductive film 106. Thus, the substrate gap G is maintained. Therefore, this substrate interval G depends only on the size of the conductive spacer 107. Therefore, if the size of the conductive spacer 107 is the same, even if the thickness t of the insulating film 104 is different for each substrate, the substrate gap G can be the same for each substrate.

  In the present embodiment, the area of the opening 111 is preferably sufficiently larger than the area occupied by one conductive spacer, and it is preferable to have a margin that allows the conductive spacer to move freely. The reason for this is to prevent the conductive spacer 107 present in the opening 111 from contributing to maintaining the gap. If there is no room for the conductive spacers to move freely in this region, a plurality of conductive spacers 107 are stacked here, and the substrate interval G cannot be made uniform over the entire substrate.

  Furthermore, in the present embodiment, the area of the remaining insulating film 104a surface is preferably sufficiently larger than one conductive spacer 107 to occupy and is a space where the conductive spacer 107 is surely disposed. This is because if the conductive spacer 107 is not reliably disposed on the insulating film 104a, it is impossible to establish an electrical connection between the first substrate and the second substrate, and further it is impossible to maintain a gap. Because.

  In this embodiment, the opening 111 is formed as shown in FIG. 2A. However, as shown in FIG. 2B, the relationship between the remaining insulating film 104a and the opening 111 is reversed. You can also. Note that an enlarged cross-sectional view of a region 120 indicated by a dotted line in FIG. 2A corresponds to FIG.

  Embodiment Mode 2 An embodiment mode of the present invention is described with reference to FIGS. 1 and 2A. FIG. 1 is a cross-sectional configuration diagram of the common contact portion of the present embodiment, and FIG. 2A is a top view on the TFT substrate side. An enlarged cross-sectional view of a region 120 indicated by a dotted line in FIG. 2A corresponds to FIG.

  In the present embodiment, similarly to the first embodiment, an insulator is also present in the common contact portion below the conductive pad, and a conductive spacer is disposed on the insulator, so that the cell gap Gc of the common contact portion is increased between layers. It is intended not to depend on the thickness of the insulating film 18. Therefore, the present embodiment is characterized in that the opening is formed so as to selectively leave the interlayer insulating film 18.

  That is, in the present embodiment, an insulator is formed below the conductive pad 22 and a conductive spacer is disposed on the insulator, so that the cell gap Gc of the common contact portion becomes the film thickness of the interlayer insulating film 18. It was made not to depend on.

  As shown in FIG. 1, the first substrate 101 includes a first conductive film 103, an insulating film 104 covering the first conductive film 103, and a first conductive film 103 formed on the insulating film 104. An exposed opening 111, an insulating film 104 a selectively formed on the surface of the first conductive film 103 exposed from the opening 111, and a second conductive film 105 covering the opening 111 are formed.

  A third conductive film 106 is formed over the second substrate 102, and a conductive spacer 107 is disposed between the first substrate 101 and the second substrate 102.

  FIG. 2A is a top view on the TFT substrate side and shows a state where the second conductive film 105 is not formed. In FIG. 2A, an opening 110 indicated by a dotted line corresponds to an opening for a common contact formed in the interlayer insulating film 18 of the conventional example. In this embodiment, the insulating film 104a is selectively formed so as to leave a portion where the first conductive film 103 is exposed in the opening 110.

  In the opening 110, in the region where the insulating film 104a is not formed, the first conductive film 103 is exposed and connected to the second conductive film 105 formed thereon.

  Further, on the first substrate 101 side, since the insulating film 104a is closest to the second substrate in the opening 110, the conductive spacer 107 on the insulating film 104a as shown in FIG. The second conductive film 105 over the first substrate 101 and the third conductive film 106 over the second substrate 102 are electrically connected.

  Further, since the insulating film 104a is closest to the second substrate 102 in the opening portion 110, the conductive spacer 107 that electrically connects the second conductive film 105 and the third conductive film 106 is used. The substrate gap G is maintained. Therefore, this substrate interval G depends only on the size of the conductive spacer 107. Therefore, if the conductive spacers 107 have the same size, the substrate gap G can be made the same for each substrate even if the thickness t of the insulating film 104 is different for each substrate.

  In the present embodiment, the area of the region where the insulating film 104a is not formed is sufficiently larger than that occupied by one conductive spacer 107, and it is preferable to have a margin that allows the conductive spacer 107 to move freely. This is because the conductive spacer 107 existing in the region where the insulating film 104a is not formed does not contribute to maintaining the gap. If there is no room for the conductive spacers to move freely in this region, a plurality of conductive spacers 107 are stacked here, and the substrate interval G cannot be made uniform over the entire substrate.

  Furthermore, in the present embodiment, the surface area of the insulating film 104a is sufficiently larger than one conductive spacer 107 to occupy, and is preferably a space where the conductive spacer 107 is surely arranged. This is because if the conductive spacer 107 is not securely arranged on the insulating film 104a, it is impossible to establish an electrical connection between the first and second substrates, and it is impossible to maintain a gap. is there.

  In this embodiment mode, the insulating film 104a is formed as shown in FIG. 2A. However, as shown in FIG. 2B, the region where the insulating film 104a is formed and the first conductive film 103 are formed. It is also possible to reverse the relationship of the exposed areas.

  In this embodiment, an example in which the present invention is applied to a common contact portion of a reflective liquid crystal display device is shown. FIG. 3 is a top view of the TFT substrate of this embodiment, and FIG. 4 is a top view of the counter substrate.

  As shown in FIG. 3, in the TFT substrate 200, on the substrate 201, a pixel region 202 in which thin film transistors connected to the pixel electrode and the pixel electrode are arranged in a matrix, and ON / OFF timing of the thin film transistor are controlled. A scanning line driving circuit 203 for supplying image data to the pixel electrode and a signal line driving circuit 204 for supplying image data are provided. Further, an extraction terminal 205 for supplying electric power and a control signal from the outside is provided, and common contact portions 206a to 206d serving as connection portions with the counter electrode are provided.

  As shown in FIG. 4, the counter substrate 250 has a structure in which a counter electrode 252 made of a light-transmitting conductive film is formed on the substrate. A rectangular region 253 at the center is a region facing the pixel region 202 of the TFT substrate 200, and regions 254 a to 254 d at the four corners are regions electrically connected to the contact portions 206 a to 206 d of the TFT substrate 200.

  As shown in FIG. 3, conductive pads are formed on the common contact portions 206a to 206d of the TFT substrate 200, respectively. These conductive pads are electrically connected by internal wirings 207a to 207c. The internal wirings 207a and 207b extend to the extraction terminal 205 and are electrically connected to the common terminals 205a and 205b.

  Hereinafter, a process of manufacturing the pixel region 202 and the common contact portion 206 of the TFT substrate will be described with reference to FIGS.

  First, a substrate 201 having an insulating surface is prepared. In this embodiment, a silicon oxide film is formed as a base film on a glass substrate. An active layer 302 made of a crystalline silicon film is formed on the substrate 201. Note that although only one thin film transistor is illustrated in this embodiment, in reality, one million or more thin film transistors are formed in the pixel region 202.

  In this embodiment, an amorphous silicon film is thermally crystallized to obtain a crystalline silicon film. Then, the crystalline silicon film is patterned by a normal photolithography process to obtain an active layer 302. In this embodiment, a catalyst element (nickel) that promotes crystallization is added during crystallization. This technique is described in detail in Japanese Patent Application Laid-Open No. 7-130652.

  Next, a silicon oxide film 303 with a thickness of 150 nm is formed, an aluminum film (not shown) containing scandium of 0.2 wt% is formed thereon, and the aluminum film is formed using the resist mask 304. Patterning was performed to form an island pattern 305 as a prototype of the gate electrode (FIG. 5A).

  In this embodiment, the anodizing technique described in JP-A-7-135318 is used here. For details, refer to the publication.

  First, anodic oxidation is performed in a 3% oxalic acid aqueous solution while leaving the resist mask 304 used for patterning on the island pattern 305. At this time, a formation current of 2 to 3 mV is passed using the platinum electrode as a cathode, and the ultimate voltage is 8V. As a result, since the resist mask 304 exists on the upper surface, a porous anodic oxide film 306 is formed on the side surface of the island pattern 305 (FIG. 5B).

  Thereafter, after removing the resist mask 304, anodization is performed in a solution obtained by neutralizing an ethylene glycol solution of 3% tartaric acid with aqueous ammonia. At this time, the formation current may be 5 to 6 mV, and the ultimate voltage may be 100V. Thus, a dense anodic oxide film 307 is formed.

  Then, the portion of the island pattern 305 that is not anodized is defined as the gate electrode 308 by the anodizing step. Note that the internal wiring 207c that connects the common contact portions 206c and 206d is also formed simultaneously with the formation of the gate electrode 308 using the aluminum film as a starting film.

  Next, the silicon oxide film 303 is etched using the gate electrode 308 and the surrounding anodic oxide films 306 and 307 as a mask to form a gate insulating film 309. Etching employed a dry etching method using CF 4 gas (FIG. 5C).

  After forming the gate insulating film 309, the porous anodic oxide film 306 was removed by wet etching using aluminum mixed acid.

  Next, impurity ions imparting one conductivity are added by an ion implantation method or a plasma doping method. If an N-type thin film transistor is arranged in the pixel region, P (phosphorus) ions may be added, and if a P-type thin film transistor is arranged, B (boron) ions may be added.

  In this example, the impurity ion addition step was performed twice using an ion implantation method. The first time was performed at a high acceleration voltage of 80 keV, and adjustment was made so that the peak of impurity ions was located under the end (protrusion) of the gate insulating film 309. The second time was performed at a low acceleration voltage of 5 keV, and the acceleration voltage was adjusted so that impurity ions were not added under the end portion (projecting portion) of the gate insulating film 309.

  Thus, the source region 310, the drain region 311, the low concentration impurity regions 312, 313, and the channel formation region 314 of the thin film transistor are formed. Note that the low-concentration impurity region 313 on the drain region 311 side is also referred to as an LDD region (FIG. 5D).

  At this time, it is preferable to add impurity ions to the source and drain regions 310 and 311 to such an extent that a sheet resistance of 300 to 500 Ω / □ can be obtained. The low concentration impurity regions 312 and 313 need to be optimized in accordance with the performance of the thin film transistor. After the impurity ion addition step was completed, heat treatment was performed to activate the impurity ions.

  Next, a silicon oxide film having a thickness of 1 μm was formed as the first interlayer insulating film 315. The reason why the thickness of the first interlayer insulating film 315 is set to 1 μm is to make the surface of the first interlayer insulating film 315 as flat as possible. Can be relaxed.

  As the first interlayer insulating film 315, a silicon nitride film or a silicon oxynitride film may be formed in addition to the silicon oxide film. Alternatively, a multilayer film of these insulating films may be used.

  Then, after forming contact holes for the source and drain regions 310 and 311 in the first interlayer insulating film 315 and contact holes for the internal wiring 207c in the common contact portions 206c and 206d, the source and drain electrodes 316 and 317, A conductive film to be a starting film for the internal wiring 318 is formed.

  Here, a multilayer film of a titanium (Ti) film, an aluminum (Al) film, and a titanium (Ti) film was formed by a sputtering method as the conductive film. The thickness of the titanium (Ti) film was 100 nm, and the thickness of the aluminum film was 300 nm. The multilayer film was patterned to form a source electrode 316, a drain electrode 317, and an internal wiring 318 (FIG. 5E).

  The internal wiring 318 in FIG. 5 corresponds to the internal wirings 207a and 207b in FIG. The internal wirings 207a and 207b are connected to the internal wiring 207c formed through the same process as the gate electrode 308 in the common contact portions 206b and 206c.

  Next, an organic resin film is formed to a thickness of 1 to 2 μm as the second interlayer insulating film 319. As the organic resin film, polyimide, polyamide, polyimide amide, acrylic, or the like can be used. The organic resin film is used in order to flatten the surface of the second interlayer insulating film 319. Flattening the surface of the second interlayer insulating film 319 is important for making the cell gap uniform. In this embodiment, polyimide is formed to a thickness of 1 μm as the second interlayer insulating film 319.

  Next, contact holes 320 and 321 for the drain electrode 317 and the internal wiring 318 were opened in the second interlayer insulating film 319. The contact hole 321 of the internal wiring 318 has a rectangular opening of 100 μm × 100 μm in a rectangular region 110 of 1.1 mm × 1.1 mm, like the opening 111 shown in FIG. The matrix was formed in a 5 × 5 matrix at intervals of In addition to the contact hole 321, a contact hole for connecting the internal wiring 318 (207a, 207b) and the common terminal 205a, 205b in the extraction terminal 205 is also formed (FIG. 5F).

  As will be described later, in this embodiment, since the diameter of the conductive spacer is set to 3.5 μm, the opening is set to 100 μm × 100 μm, and a sufficient clearance is provided so that the conductive spacer disposed therein can move. The conductive spacers were not stacked on the part.

  In addition, since the area of the region where the second interlayer insulating film 319 remains in the common contact portion is also a sufficiently wide area so that the conductive spacer can move, the conductive spacer is surely disposed in this area. be able to. Therefore, the cell gap can be held and the electrical connection can be reliably performed by the conductive spacer disposed in this region.

  Then, a metal thin film that will later become the pixel electrode 322 and the conductive pad 323 is formed to a thickness of 100 nm to 400 nm. In this embodiment, an aluminum film to which 1 wt% titanium is added as a metal thin film is formed to a thickness of 300 nm by sputtering. Thereafter, the metal thin film was patterned to form a pixel electrode 322 and a conductive pad 323, respectively. The conductive pad 323 was formed in a 1.1 mm × 1.1 mm rectangular shape so as to cover the contact hole 321. Further, the extraction terminal 205 is also patterned. Thus, the TFT substrate is completed (FIG. 5G).

  On the other hand, as shown in FIG. 6, in the counter substrate 250, the counter electrode 252 made of an ITO film was formed on the translucent substrate 251. As the substrate 251, a glass or a quartz substrate can be used.

  Next, the TFT substrate 200 and the counter substrate 250 are bonded together. This bonding step may be performed according to a known cell assembling method.

  First, a sealing material is applied to one of the TFT substrate 200 and the counter substrate 250. In this embodiment, a sealing material is applied to the counter substrate 250 side. An ultraviolet / thermosetting resin material was used as the sealing material, and the sealing material was applied linearly around the substrate with the seal dispenser device leaving the liquid crystal injection port. Further, a sealing material in which 3.0 wt% of the spherical conductive spacer 401 is applied is applied to the regions 254a to 254d shown in FIG. The sealing material mixed with the conductive spacer functions as an anisotropic conductive film.

  As the conductive spacer 401, a sphere made of a resin material coated with a conductive film is generally used. In this embodiment, the conductive spacer 401 coated with gold (Au) is used. The diameter of the conductive spacer 401 may be about 0.2 μm to 1 μm larger than the cell gap. In this example, a conductive spacer 401 having a diameter of 3.5 μm was used in order to set the cell gap to 3 μm. After applying the sealing material, it is temporarily fired.

  Next, spacers 402 for maintaining the cell gap are dispersed on one of the TFT substrate 200 and the counter substrate 250. In this embodiment, the spacers 402 are dispersed on the counter substrate 250 side. In order to set the cell gap to 3 μm, the spacer 402 is a spherical spacer made of a polymer material having a diameter of 3 μm.

  Next, the TFT substrate 200 and the counter substrate 250 were opposed to each other and pressed until the cell gap in the pixel region became the diameter of the spacer 402. In the pressed state, the sealing material is irradiated with ultraviolet rays for 10 seconds or more to cure the sealing material, fix the cell gap, and then heat while applying pressure to improve the adhesive strength of the sealing material.

  And a cell assembly process is completed by enclosing a liquid crystal and sealing an enclosure port. As shown in FIG. 6, the counter electrode 252 of the counter substrate 250 is electrically connected to the conductive pad 323 of the TFT substrate 200 by the conductive spacer 401, and the conductive pad 323 is connected via the internal wiring 318 on the TFT substrate side. Connected to the common terminal. With such a connection structure, the counter electrode 252 on the counter substrate 250 side can be connected to an external power source by wiring on the TFT substrate side. An enlarged view of the common contact portion in FIG. 6 corresponds to FIG.

  In this embodiment, in order to set the cell gap to 3 μm, the diameter of the spacer 402 dispersed in the pixel region is 3 μm, and the diameter of the conductive spacer 401 is 3.5 μm. The reason why the diameter of the conductive spacer is larger than the diameter (cell gap) of the spacer 402 is to ensure the connection between the counter electrode 252 and the conductive pad 323. In the pressing step of the substrate bonding step, the conductive spacer 401 is crushed because it has a diameter larger than the cell gap. By being crushed, the contact area between the counter electrode 252 and the conductive pad 323 is increased, electrical connection is ensured, and the cell gap can be kept the same as the pixel region.

  In this embodiment, the internal wiring 318 is formed by the starting films of the source and drain electrodes 316 and 317, but the internal wiring 318 may be a wiring below the pixel electrode 322. For example, when a black matrix made of a conductive film such as titanium is formed in the second interlayer insulating film 319, the internal wiring 318 can be formed using this conductive film.

  In this embodiment, in order to make the cell gap uniform, it is important that the surface of the second interlayer insulating film 319 on which the pixel electrode 322 is formed is flat, and the internal wiring 318 is formed. The flatness of the surface of the first interlayer insulating film 315 is also important.

  Examples of a method for obtaining an interlayer insulating film having a flat surface include a method by increasing the thickness of the interlayer insulating film, a method by leveling using an organic resin film, a method by mechanical polishing, and a method by an etch back technique. In this embodiment, a method using a thick film is adopted for flattening the first interlayer insulating film 315, and a method using leveling using an organic resin film is adopted for flattening the second interlayer insulating film 319. Other methods may be used for planarization.

  In the liquid crystal display device of this embodiment, it is possible to disperse a dichroic dye in the liquid crystal layer, provide an alignment film on the TFT substrate and the counter substrate, or provide a color filter on the counter substrate. The type of the liquid crystal layer, the alignment film, the presence / absence of the color filter, and the like may be appropriately determined by the practitioner depending on the driving method, the type of liquid crystal, and the like.

  For example, when a color filter is provided on the counter substrate 250 side, the color filter is not formed in the common contact portion, so that a step is generated between the pixel region and the common contact portion in the counter substrate. In order to correct this step, it is necessary to increase the diameter of the conductive spacer by about the thickness of the color filter.

  Further, although the present embodiment shows an example of a reflective liquid crystal display device, a transmissive liquid crystal display device can also be used. In this case, the starting film of the pixel electrode and the conductive pad is made transparent. What is necessary is just to form with the ITO film | membrane etc. which have.

  In this embodiment, a coplanar thin film transistor which is a typical top gate thin film transistor is described as an example, but a bottom gate thin film transistor may be used. In addition to the thin film transistor, a thin film diode, an MIM element, a varistor element, or the like can be used.

  The present embodiment is a modification of the common contact portion of the first embodiment. FIG. 7 is a cross-sectional configuration diagram of the active matrix display device of this embodiment. In FIG. 7, the configuration of the TFT substrate is the same as that in FIG. 6, and some of the reference numerals are omitted. In FIG. 7, the same reference numerals as those in FIG. 6 denote the same members. FIG. 9 shows an enlarged view of the common contact portion shown in FIG.

  In Example 1 shown in FIG. 6, since the counter electrode 252 is made of an ITO film that is a transparent conductive film, the electrical resistance between the counter electrode 252 and the conductive spacer 401 is larger than that of the metal film. The present embodiment aims to reduce this electrical resistance.

  For this reason, a metal film is formed on the counter substrate 250 side and patterned to form connection pads 501 made of conductive films on the common contact portions 254a to 254d, respectively. By forming the connection pad 501, the resistance value between the counter electrode 252 and the conductive spacer 401 can be reduced. However, it is important that the conductive film constituting the connection pad 501 has a lower electrical resistance than the conductive film used for the counter electrode 252.

  In addition, when the black matrix on the counter substrate side is formed of a conductive film such as chromium, the connection pad 501 can be formed of this conductive film. When the black matrix is formed by patterning the conductive film, A pad 501 may be formed.

  The present embodiment is a modification of the second embodiment, and FIG. 8 is a cross-sectional configuration diagram of the active matrix display device of the present embodiment. In FIG. 8, the configuration of the TFT substrate is the same as that in FIG. 6, and some of the reference numerals are omitted. In FIG. 8, the same reference numerals as those in FIG. 6 denote the same members. Moreover, the enlarged view of the common contact part of FIG. 8 corresponds to FIG.

  In Example 1, since both the counter substrate 251 and the counter electrode 252 are translucent, the state of the distribution of the conductive spacer 401 is visually recognized from the counter substrate 250 side to the common contact portion in a state where the substrates are bonded together. I was able to. However, since the connection pad 501 made of a metal film is formed in the second embodiment, the state of distribution of the conductive spacer 401 cannot be visually recognized.

  The object of the present embodiment is to make it possible to visually recognize the distribution of the conductive spacer 401 in a state where a connection pad for lowering the resistance value is provided. Therefore, an opening is selectively provided in the connection pad 601 so that the conductive spacer 401 can be seen through the opening.

  FIG. 11 is a top view of the contact portion of the present embodiment and shows a state viewed from the counter substrate side. 10 corresponds to a cross-sectional configuration diagram of a common contact portion in a region 600 surrounded by a dotted line in FIG. As shown in FIG. 11, an opening 602 is formed in the conductive pad 601. Since only the counter substrate 251 and the counter electrode 252 exist in the opening portion 602, and both have translucency, it is possible to check the distribution of the conductive spacer 401 from the opening portion 602.

  In order to maintain the cell gap, the opening 602 is preferably formed at a position facing the contact hole 321 opened in the second interlayer insulating film of the TFT substrate, where the conductive spacer 401 is not in contact with the counter electrode. Further, the area is preferably slightly larger than the opening of the second interlayer insulating film by several% to 30%. Note that the number, arrangement, shape, and the like of the openings 602 are not limited to those in FIG. 11, and can be set as appropriate by the practitioner.

  The reason why the opening 602 of the connection pad 601 is formed to be slightly larger than the opening of the second interlayer insulating film is that the conductive pad 323 on the second interlayer insulating film 319 that contributes to electrical connection is formed. This is to make it visible.

  In the second and third embodiments, the configuration for simultaneously realizing the uniform cell gap of the common contact portion and lowering the connection resistance between the conductive spacer 401 and the counter electrode 252 has been described. If the main purpose is to lower the resistance values of 401 and the counter electrode 252, the structure of the common contact portion on the TFT substrate side may be a conventional common contact portion as shown in FIG. In this case, the connection pads 501 and 601 shown in the second and third embodiments may be formed between the substrate 23 and the counter electrode 24 in the common contact portion 16 of FIG.

  In the first to third embodiments described above, an example in which the present invention is applied to an active matrix type liquid crystal display device has been shown. However, the contact structure of the present invention connects wirings formed on opposing substrates via conductive spacers. For example, it is possible to connect ICs or the like formed on different silicon wafers.

The cross-sectional block diagram of the common contact part of this embodiment. The top view of the common contact part of this embodiment. 3 is a top view of a TFT substrate of the liquid crystal display device of Example 1. FIG. 3 is a top view of a counter substrate of the liquid crystal display device according to Embodiment 1. FIG. FIG. 5 shows a manufacturing process of the TFT substrate of Example 1; FIG. 3 is a cross-sectional configuration diagram of a pixel region and a common contact portion according to the first embodiment. FIG. 6 is a cross-sectional configuration diagram of a pixel region and a common contact portion in Example 2. FIG. 6 is a cross-sectional configuration diagram of a pixel region and a common contact portion in Example 3. FIG. 6 is an enlarged configuration diagram of a common contact portion according to the second embodiment. FIG. 6 is a cross-sectional configuration diagram of a common contact portion according to a third embodiment. FIG. 6 is a top view of a contact portion according to Embodiment 3. The top view of the TFT substrate of a prior art example. The cross-sectional block diagram of the pixel region of a prior art example, and a common contact part. The top view of the common contact part of a prior art example.

Explanation of symbols

101 First substrate 102 Second substrate 103 First conductive film 104 Insulating film 105 Second conductive film 106 Third conductive film 107 Conductive spacer 200 TFT substrate 205 Extraction terminal 206 Common contact portion 207 Internal wiring 250 Opposing Substrate 252 Counter electrode 315 First interlayer insulating film 318 Internal wiring 319 Second interlayer insulating film 322 Pixel electrode 323 Conductive pad 401 Conductive spacer 402 Spacer 501, 601 Connection pad

Claims (6)

A first substrate, a first conductive film provided on the first substrate, an insulating film provided on the first conductive film, an opening provided in the insulating film, A second conductive film electrically connected to the first conductive film in the opening ;
A second substrate, a third conductive film provided on the second substrate, a fourth conductive film provided on the third conductive film,
A conductive spacer provided at a position overlapping the insulating film,
The conductive spacer is in contact with both the second conductive film and the fourth conductive film,
The fourth conductive film has translucency,
The display device is characterized in that an opening is provided at a position overlapping the opening of the third conductive film . In claim 1 ,
The display device, wherein an area of the opening provided in the third conductive film is larger than an area of the opening. Oite to claim 1 or claim 2,
A display device, wherein a switching element is provided under the insulating film. In claim 3 ,
The display device, wherein the switching element is a top gate type thin film transistor, a bottom gate type thin film transistor, a thin film diode, an MIM element, or a varistor element. In any one of Claims 1 thru | or 4 ,
The first substrate is provided with a pixel region,
The display device, wherein the third conductive film and the black matrix provided to face the pixel region are formed from the same starting film. In any one of Claims 1 thru | or 5 ,
The display device, wherein the second conductive film and the fourth conductive film are ITO.

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