JP4800898B2 - Wiring board, electronic circuit device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a high-frequency signal in an electronic circuit device such as a semiconductor device in which a wiring board on which a substrate of an electronic circuit device is mounted or a plurality of semiconductor chips are stacked and through electrodes are provided by microfabrication technology to be electrically connected. The present invention relates to a shape of a through electrode for propagating a metal between chips and a manufacturing method thereof.

  In order to stack LSI chips made of semiconductors such as memories and CPUs in a small and thin manner, a semiconductor device is being developed to connect by providing through electrodes that penetrate the front and back surfaces of the chip instead of conventional wire bonding. (For example, refer nonpatent literature 1). In such a semiconductor device, the wiring length can be shortened as compared with the conventional wire bonding, and therefore, it is suitable for propagating a high-speed, high-frequency signal of several GHz class such as a clock.

  For example, as shown in FIG. 11, semiconductor chips 1002 each having a plurality of through electrodes 1001 are stacked in five layers and connected. In FIG. 11, the upper part of each semiconductor chip 1002 is the front surface, and the lower part is the back surface. The side surface of the through electrode 1001 and the side surface of the semiconductor chip 1002 are insulated by an insulating film, and can be connected to the wiring on the front surface or back surface of the semiconductor chip 1002 only at the top or bottom of the through electrode 1001. Further, the through electrode 1001 is connected to an input / output terminal 1003 formed under the lowermost semiconductor chip 1002 (the first layer from the bottom), and a signal with an external board substrate 1004 is passed through the input / output terminal 1003. I / O is performed.

  In FIG. 11, the description of the connection portion between the through electrodes 1001 of the semiconductor chip 1002 adjacent in the vertical direction is omitted, but connection between the through electrodes 1001 adjacent in the vertical direction is performed using a known technique. Just do it. By such vertical connection, through-electrode wirings 1005a and 1005b including a plurality of through-electrodes 1001 are formed, for example. The signal from the second lowest semiconductor chip 1002 reaches the back surface of the lowermost semiconductor chip 1002 via the through electrode wiring 1005a, and the signal from the uppermost (fifth lowermost) semiconductor chip 1002 Can reach the back surface of the lowermost semiconductor chip 1002 via the through-electrode wiring 1005b.

K. Takahashi et al., “Current status of research and development for three-dimensional chip stack technology”, Jpn.J.Appl.Phys., Vol.40, p.3032-3037, 2001

  As described above, in a semiconductor device formed by stacking semiconductor chips, a signal output from any layer regardless of the position of the stacked semiconductor chips 1002 is the arrival time to the back surface of the lowermost semiconductor chip 1002. Are preferably the same. However, since the through electrode 1001 has the same cylindrical or prismatic shape between the stacked semiconductor chips, the propagation characteristics of high-frequency signals are all the same for each semiconductor chip 1002. In other words, the signal delay (RC delay) determined by the resistance R of the through electrode itself and the capacitance C formed between the peripheral portions is the same for each semiconductor chip 1002. Here, the resistance R is determined by the resistivity and shape of the conductor constituting the through electrode 1001. The capacitor C is formed by using a thin film of an insulator between the through electrode 1001 and the semiconductor substrate of the semiconductor chip 1002 as a dielectric. The capacitance C is determined by the side shape of the through electrode 1001 and the dielectric constant and thickness of the insulating thin film.

As described above, in the conventional semiconductor device shown in FIG. 11, since the signal delay is added for the same time every time it passes through each semiconductor chip 1002, the delay time increases as the signal is output from the upper semiconductor chip 1002. There was a problem of becoming longer. For example, in FIG. 11, the time required for a signal output from the fifth-layer semiconductor chip 1002 to reach the back surface of the lowermost semiconductor chip 1002 via the through-electrode wiring 1005b is the second-layer semiconductor chip 1002. Is about 25 times as long as the time required for the signal output from the terminal to reach the back surface of the lowermost semiconductor chip 1002 via the through electrode wiring 1005a.
The above-described problems occur not only in a semiconductor device in which a plurality of semiconductor chips are stacked, but also in a wiring board such as an interposer on which semiconductor chips are mounted.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a wiring board, an electronic circuit device, and a method for manufacturing the same that can equalize the signal delay time of each through electrode wiring.

The present invention is an electronic circuit device having a plurality of stacked substrates, wherein each of the substrates includes a plurality of through electrodes penetrating from the front surface to the back surface, and the through electrodes of each substrate are along the stacking direction. The through electrode wirings are electrically connected to the input / output terminals, and at least a part of the plurality of through electrodes includes a through electrode including the through electrode so that the signal delay time of each through electrode wiring is equal. signal delay adjustment through electrodes der the molded shape according to the length of the electrode wires is, the signal delay adjustment through electrode, the cross-sectional area in a direction perpendicular to a plane passing through the substrate, each of the through electrodes It is characterized in that it changes within the same substrate in accordance with the length of the through electrode wiring including the through electrode so that the signal delay time of the wiring becomes equal .

Further, the present invention is an electronic circuit device having a plurality of stacked substrates, each of the substrates including a plurality of through electrodes penetrating from the front surface to the back surface, and the through electrodes of each substrate are in the stacking direction Are electrically connected to the input / output terminals by through-electrode wirings connected along the at least one of the plurality of through-electrodes, so that at least some of the through-electrode wirings have the same signal delay time of each through-electrode wiring. A signal delay adjusting through electrode having a shape formed according to the length of the through electrode wiring including the cross section of the signal delay adjusting through electrode in a plane perpendicular to the direction penetrating the substrate. The number of the stacked substrates is n (n is 2 or more), so that the signal delay time of the electrode wiring is made equal in accordance with the length of the through electrode wiring including the through electrode. Integer) The number of through-electrodes for signal delay adjustment is two or more, and the through-electrode for signal delay adjustment is long with a cross-sectional area of A and a length of X and a cross-sectional area of B (B> A). The p-th substrate (p is an integer satisfying 1 ≦ p <n) and the input / output terminal are connected from the side closer to the input / output terminal. The signal delay adjusting through electrode included in the through electrode wiring P is connected to the qth substrate (q is an integer satisfying p <q ≦ n) and the input / output terminal from the side closer to the input / output terminal. When the cross-sectional area A is the same value and the cross-sectional area B is the same value with respect to the signal delay adjusting through-electrode included in the through-electrode wiring Q, the above-mentioned included in the through-electrode wiring P The length X of the detail of the signal delay adjustment through electrode is determined by the signal delay adjustment included in the through electrode wiring Q. It is characterized in longer than the length X of a detail of the through electrode.
Further, in one configuration example of the electronic circuit device of the present invention, the signal delay time of each through electrode wiring is made equal by setting the product of resistance and capacitance to the same value in each through electrode wiring. .

In addition, the present invention is a manufacturing method for manufacturing an electronic circuit device in which a plurality of substrates are stacked, the first step of forming a recess on the substrate surface, and a space in the recess on the substrate surface. a second step of attaching a thin film which closes the mouth of the recess, by patterning a portion of the thin film on the true of the recess to form an opening smaller than the mouth of the recess, the bottom of the recess one a third step of exposing the part, the thin film as a mask, and a fourth step of processing the bottom of the recess by etching, wherein repeated as necessary the fourth step from the first step A fifth step of forming an insulating film on the side wall and the bottom of each concave portion after forming the concave portion having a multistage structure in which a cross-sectional area in a plane perpendicular to the thickness direction of the substrate is changed inside the substrate ; Form a conductor pattern inside each recess A sixth step, a seventh step of grinding the back surface of the substrate to expose the conductor pattern on the back surface, and dividing the substrate after the seventh step to form a plurality of the conductor patterns This includes an eighth step of producing a plurality of substrates each having a through electrode, and a ninth step of laminating the plurality of substrates after the eighth step.

  According to the present invention, the substrate of the electronic circuit device is mounted on the surface of the base material, and the plurality of through electrodes penetrating from the front surface to the back surface of the base material together with the wiring in the connection destination substrate constitute the through electrode wiring In the substrate, at least a part of the plurality of through electrodes is formed as a signal delay adjusting through electrode having a shape formed so that the signal delay time of each through electrode wiring is equalized, whereby the electronic circuit device of the electronic circuit device is formed on the wiring substrate. In a state where the substrate is mounted, the signal delay time of each through electrode wiring can be set to be equal, and the operation timing of each electronic circuit in the substrate can be matched.

  Further, according to the present invention, at least a part of the plurality of through electrodes is formed according to the length of the through electrode wiring including the through electrode so that the signal delay time of each through electrode wiring is equal. By forming the signal delay adjusting through electrode in the shape, in an electronic circuit device such as a semiconductor device in which a plurality of substrates (for example, semiconductor chips) are stacked, the electronic circuit provided on any of the stacked substrates Regardless of the position in the stacking direction, the signal delay time of each through electrode wiring can be set to be equal, and the operation timing of each electronic circuit can be matched.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view showing a configuration example of a semiconductor device (electronic circuit device) according to a first embodiment of the present invention. 1 represents a cross section of the semiconductor device.

  The semiconductor device 101 includes a plurality of stacked semiconductor chips 102 (102a or 102b). Each semiconductor chip 102 includes a plurality of through electrodes 106 (106a or 106b) that penetrate the semiconductor substrate portion 105 from the front surface to the back surface. The side surface of the through electrode 106 and the side surface of the semiconductor chip 102 are insulated by an insulating film (not shown), and connected to the wiring (not shown) on the front surface or the back surface of the semiconductor chip 102 only at the top or bottom of the through electrode 106. It is possible. The through electrode 106 connects a semiconductor circuit (not shown) formed in an arbitrary semiconductor chip 102 to the upper and lower chips stacked.

  Connection between the through electrodes 106 adjacent to each other in the stacking direction is performed using a known technique. By this connection, a through electrode wiring in which a plurality of through electrodes 106 are connected in the stacking direction is formed. The through electrode 106 formed in the lowermost semiconductor chip 102a is connected to an input / output terminal 103 formed under the semiconductor chip 102a, and a substrate 104 such as an interposer is connected via the input / output terminal 103. It is connected to the. The substrate 104 is connected to an external board or package substrate (not shown).

  As shown in FIGS. 2A and 2B, the through electrode 106 is made of, for example, a cylindrical conductor. That is, the cross-sectional shape of the through electrode 106 when it is cut along a plane perpendicular to the axis 107 of the through electrode 106 parallel to the stacking direction is a circle. In the example of FIG. 1, the lower semiconductor chip 102 a includes a through electrode 106 a having a wide cross-sectional area and a through electrode 106 b having a narrower cross-sectional area. On the other hand, the upper semiconductor chip 102b includes only the through electrode 106a having a wide cross-sectional area.

  Here, a through electrode wiring connecting the lower semiconductor chip 102a and the input / output terminal 103 is denoted by 110, and a through electrode wiring connecting the upper semiconductor chip 102b and the input / output terminal 103 is denoted by 111. The signal delay (RC delay) in the through electrode 106 is a function of the product RC of the resistance R of the through electrode itself and the capacitance C formed between the peripheral portions. Here, the resistance R is determined by the resistivity and the shape of the conductor constituting the through electrode 106. The capacitor C is formed by using a thin film of an insulator between the through electrode 106 and the semiconductor substrate of the semiconductor chip 102 as a dielectric. The capacitance C is determined by the side surface shape of the through electrode 106 and the dielectric constant and thickness of the insulating thin film.

For example, when considering a cylindrical through electrode 106 having a bottom surface with a radius r and a length L, the resistance R and the capacitance C are as follows.
R = ρ × L / (πr ² ) (1)
C = ε × (L × 2πr) / T (2)
ρ is the resistivity of the conductor constituting the through electrode 106, ε is the dielectric constant of the insulator between the through electrode 106 and the semiconductor substrate of the semiconductor chip 102, and T is the thickness of the insulator. From Equations (1) and (2), RC = α × L ² / r (α is a constant), and it can be seen that the product of the resistance R and the capacitance C is proportional to the square of the length L of the through electrode 106. . The signal delay is a function of RC, but its form varies depending on the boundary condition, and the specific form is not clearly shown.

  In order to equalize the signal delay determined by the product RC of the resistor R and the capacitance C between the through electrode wirings 110 and 111, at least some of the through electrodes 106 among the through electrodes 106 constituting the through electrode wirings 110 and 111. The cross-sectional area may be changed according to the length of the electrical signal propagation portion of the through-electrode wirings 110 and 111. For example, when the length of the through electrodes 106 a and 106 b for each semiconductor chip 102 is 100 μm, the bottom surface radius of the through electrode 106 a constituting the through electrode wiring 111 is 40 μm and the through electrode 106 b constituting the through electrode wiring 110 is formed. The bottom radius may be 10 μm.

  That is, when the number of semiconductor chips 102 to be stacked is n, the through-electrode wiring 110 connecting the pth semiconductor chip 102 from the bottom (p is an integer satisfying 1 ≦ p <n) and the input / output terminal 103 is provided. The cross-sectional area of the through electrode 106b included is that of the through electrode 106a included in the through electrode wiring 111 that connects the qth semiconductor chip 102 from the bottom (q is an integer satisfying p <q ≦ n) and the input / output terminal 103. It is smaller than the cross-sectional area. As a result, the product RC of the resistance R and the capacitance C becomes the same value for the through electrode wiring 110 (bottom radius 10 μm, length 100 μm) and the through electrode wiring 111 (bottom radius 40 μm, length 200 μm).

Therefore, signals simultaneously output from the surface of the lower semiconductor chip 102 a and the surface of the upper semiconductor chip 102 b reach the output destination input / output terminal 103 simultaneously.
A through electrode 106a is formed inside the semiconductor chip 102b above the through electrode wiring 110. The through electrode 106a is a dummy pattern in the manufacturing process. By forming the dummy pattern, it is possible to make common the design of the arrangement of the through electrode 106 and the manufacturing process conditions of dry etching and plating described later, regardless of the position of the stacked chip. Of course, the complexity of changing the manufacturing process depending on the stacking position of the chips increases, but the dummy pattern need not be formed.

  In the example of FIG. 1, the case where the semiconductor chip 102 has two layers is shown, but the same can be applied to the case where there are three or more layers. For example, as shown in FIG. 3, consider a case where five semiconductor chips 102 are stacked. Here, a through electrode wiring for propagating a signal output from the surface of the semiconductor chip 102 in the nth layer (n = 1, 2, 3, 4, 5) from the bottom is 201-n. The through electrode constituting the lowermost portion of the through electrode wiring 201-n, that is, the through electrode in the first semiconductor chip 102 is 106d-n, and the through electrode in the second or higher semiconductor chip 102 is 106c. To do.

  As in the example of FIG. 1, in order to make the signal delay equal in each of the through electrode wirings 201-1 to 201-5, the cross-sectional area of at least some of the through electrodes 106 is changed to the through electrode wirings 201-1 to 201-. What is necessary is just to change according to the length of 5 electric signal propagation | transmission parts. For example, when the length of the through electrodes 106c, 106d-1 to 106d-5 for each semiconductor chip 102 is 100 μm, the through electrodes 106d-1, 106d-2, 106d-3, 106d-4, 106d-5 are used. The radius of each of the through electrodes 106c may be 4 μm, 23 μm, 34 μm, 49 μm, and 100 μm, and the radius of the through electrode 106c may be 100 μm.

  As a result, the product RC of the resistor R and the capacitor C has a signal propagation portion (bottom radius 4 μm, length 100 μm) of the through electrode wiring 201-1 and a signal propagation portion (bottom radius 23 μm, long) of the through electrode wiring 201-2. And a signal propagation portion of the through-electrode wiring 201-3 (bottom radius of 34 μm, length of 100 μm, bottom radius of 100 μm, thickness of 200 μm) And a signal propagation portion of the through electrode wiring 201-4 (consisting of details of a bottom surface radius of 49 μm and a length of 100 μm and a bottom surface radius of 100 μm and a thick portion of a length of 300 μm) and a signal of the through electrode wiring 201-5 It becomes the same value in the propagation part (bottom radius 100 μm, length 500 μm).

As described above, in this embodiment, the signal delay time of each through electrode wiring can be set to be equal.
In the above description, the chip in the lowermost layer is assumed to have the function of the same semiconductor element as the upper layer. However, this chip is also used when it has a function as a wiring board such as an interposer having only through electrodes and wiring. The invention can be applied.

  That is, the wiring board includes, for example, a base material made of ceramic or the like and a plurality of through electrodes penetrating from the surface of the base material to the back surface, and a substrate (semiconductor chip) of an electronic circuit device is mounted on the surface of the base material. The back surface is provided with a plurality of input / output terminals for connection to the outside, and serves to electrically connect the substrate of the electronic circuit device and the mother board. Each through electrode electrically connects the electrode of the substrate of the electronic circuit device and the input / output terminal of the wiring substrate. Thereby, each through electrode constitutes a through electrode wiring together with the wiring in the connection destination substrate. In such a wiring board, as described in the present embodiment, at least a part of the plurality of through-electrodes has a signal delay adjustment through shape formed so that the signal delay time of each through-electrode wiring is equal. By using electrodes, the signal delay time of each through electrode wiring can be set to be equal, and the operation timing of each circuit in the substrate can be matched.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIG. First, the back surface of the semiconductor substrate 301 is ground so that the thickness of the semiconductor substrate 301 is, for example, 120 μm, and a resist pattern 302 is formed on the surface of the semiconductor substrate 301 by a known photolithography technique (FIG. 4A). Although not shown, the semiconductor substrate 301 is formed with semiconductor elements and multilayer wiring.

Subsequently, using the resist pattern 302 as a mask, the insulating film on the surface of the semiconductor substrate 301 or the semiconductor substrate 301 is dry-etched by ICP-RIE (Inductively Coupled Plasma-Reactive Ion Etching) or the like to form a recess 303 having a depth of, for example, 100 μm. Then, the resist pattern 302 is removed after the recess 303 is formed (FIG. 4B).
Then, an insulating film 304 such as an oxide film is formed on the sidewall and bottom of the recess 303 by a CVD (Chemical Vapor Deposition) method (FIG. 4C).

  Next, after the copper plating is deposited inside the recess 303 by the electroless plating method, a resist pattern 305 or the like is formed on a part of the surface of the semiconductor substrate 301 to cover the surface, and only on the exposed part. A copper pattern 306 is grown using electrolytic plating (FIG. 4D). Here, the portions not covered with the resist pattern 305 are the recesses 303 and the connection portions between the multilayer wiring (not shown) on the surface of the semiconductor substrate 301 and the copper pattern 306. Therefore, by growing the copper pattern 306, the copper pattern 306 is electrically connected to the multilayer wiring on the surface of the semiconductor substrate 301.

After the copper pattern 306 is formed, the resist pattern 305 is removed, and unnecessary copper deposited by electroless plating is removed by etching. Finally, the back surface of the semiconductor substrate 301 is ground to expose the copper pattern 306 on the back surface. Thus, the copper pattern 306 becomes the through electrode 106 penetrating from the front surface to the back surface of the semiconductor substrate 301 (FIG. 4E).
Thereafter, an insulating film and a conductor for connection are appropriately formed on the back surface of the semiconductor substrate 301, the semiconductor substrate 301 is diced and divided into chips, and these chips are stacked and connected. The semiconductor device shown in FIG. In the steps shown in FIGS. 4A to 4E, the resist pattern 302 may be appropriately formed so as to form the through electrode 106 having a desired radius. As a technique for connecting between the through electrodes 106 adjacent in the stacking direction, for example, the technique described in Non-Patent Document 1 can be used.

[Second Embodiment]
FIG. 5 is a cross-sectional view showing a configuration example of a semiconductor device according to the second embodiment of the present invention. The semiconductor device 401 includes a plurality of stacked semiconductor chips 402 (402a or 402b). Each semiconductor chip 402 includes a plurality of through electrodes 406 (406a or 406b). By connecting through electrodes 406 adjacent in the stacking direction, through electrode wiring is formed. The through electrode 406 formed in the lowermost semiconductor chip 402a is connected to the input / output terminal 103 formed under the semiconductor chip 402a, and the substrate 104 such as an interposer is connected via the input / output terminal 103. It is connected to the.

  As shown in FIGS. 6A and 6B, the through electrode 406 is made of, for example, a cylindrical conductor. That is, the cross-sectional shape of the through electrode 406 when it is cut along a plane perpendicular to the axis 407 of the through electrode 406 parallel to the stacking direction is a circle. The difference from the first embodiment is that the cross-sectional area of the through electrode 106 in each semiconductor chip 102 is unchanged in the first embodiment, whereas in this embodiment, the through electrode 106 penetrates in the semiconductor chip 402. That is, the cross-sectional area of the electrode 406 may change. The through electrode 406a has a constant cross-sectional area as shown in FIG. On the other hand, the through electrode 406b has a two-stage structure including a thick portion 408 having a wide cross-sectional area and a detail 409 having a narrower cross-sectional area, and the cross-sectional area changes in the semiconductor chip 402. To do.

  The lower semiconductor chip 402a in FIG. 5 includes through electrodes 406a and 406b. On the other hand, the upper semiconductor chip 402b includes only the through electrode 406a. Here, 410 is a through electrode wiring that connects the lower semiconductor chip 402 a and the input / output terminal 103, and 411 is a through electrode wiring that connects the upper semiconductor chip 402 b and the input / output terminal 103.

  As in the first embodiment, in order to equalize the signal delay between the through-electrode wirings 410 and 411, the shape of the through-electrodes 406a and 406b is set to the length of the electric signal propagation portion of the through-electrode wirings 410 and 411. It may be set accordingly. In the through electrode wiring 411, the resistance increases due to the details 409 of the through electrode 406b, and the signal is delayed. Therefore, if the through electrodes 406a and 406b are set to an appropriate shape size, the signal delay amount determined by the product RC of the resistor R and the capacitor C becomes equal between the through electrode wires 410 and 411. Therefore, signals simultaneously output from the surface of the lower semiconductor chip 402a and the surface of the upper semiconductor chip 402b reach the output destination input / output terminal 103 simultaneously.

  In the example of FIG. 5, the case where the semiconductor chip 402 has two layers is shown, but the same can be applied to the case of three or more layers. For example, as shown in FIG. 7, consider a case where five layers of semiconductor chips 402 are stacked. Here, it is assumed that the through-electrode wiring for propagating a signal output from the surface of the semiconductor chip 402 in the nth layer (n = 1, 2, 3, 4, 5) from the bottom is 501-n. The through electrode constituting the lowermost part of the through electrode wiring 501-n, that is, the through electrode in the first semiconductor chip 402 is 406d-n, and the through electrode in the second or higher semiconductor chip 402 is 406c. To do. The cross-sectional area of the through electrode 406c is constant.

  As in the example of FIG. 5, in order to make the signal delay equal for each through-electrode wiring 501-1 to 501-5, the shape of the through-electrodes 406c, 406d-1 to 406d-5 is changed to the through-electrode wiring 501-1. What is necessary is just to set according to the length of the electric signal propagation | transmission part of -501-5. For example, when the lengths of the through electrodes 406c, 406d-1 to 406d-5 for each semiconductor chip 402 are all 100 μm, the radius of the bottom of the through electrode 406c is 100 μm, and the through electrodes 406d-1 to 406d-5 The radius of the thick portion is 100 μm, the radius of the details is 10 μm, and the lengths of the details of the through electrodes 406d-1, 406d-2, 406d-3, 406d-4, 406d-5 are 37 μm, 12 μm, 6 μm, 3 μm, It may be 0 μm. Note that the through electrode 406d-5 has a constant cross-sectional area of 0 μm in detail.

  With this setting, the product RC of the resistor R and the capacitor C is a signal propagation portion of the through-electrode wiring 501-1 (consisting of details of a bottom surface radius of 10 μm, a length of 37 μm, a bottom surface radius of 100 μm, and a length of 63 μm). And a signal propagation portion of the through-electrode wiring 501-2 (consisting of details of a bottom surface radius of 10 μm and a length of 12 μm and a thick portion of a bottom surface radius of 100 μm and a length of 188 μm), and a signal propagation portion of the through-electrode wiring 501-3 (bottom surface) Details of radius 10 μm, length 6 μm and bottom radius 100 μm, thick part 294 μm long, and signal propagation part of through electrode wiring 501-4 (bottom radius 10 μm, length 3 μm detail and bottom radius 100 μm, length) And a signal propagation portion (bottom radius of 100 μm, length of 500 μm) of the through-electrode wiring 501-5.

  That is, when the number of stacked semiconductor chips 402 is n, the through electrodes 406d-1 to 406d-5 are long with a cross-sectional area of A and a length of X and a cross-sectional area of B (B> A). A through electrode wiring P having a two-stage structure consisting of a thick portion of Y and connecting the input / output terminal 103 and the p-th (p is an integer satisfying 1 ≦ p <n) semiconductor chip 402 from the bottom. The through-electrode 406d included and the through-electrode 406d included in the through-electrode wiring Q connecting the qth semiconductor chip 402 from the bottom (q is an integer satisfying p <q ≦ n) and the input / output terminal 103, When A is the same value and the cross-sectional area B is the same value, the length X of the details of the through electrode 406d included in the through electrode wiring P is the length of the details of the through electrode 406d included in the through electrode wiring Q. Longer than X.

  According to the example of FIG. 5, in the lowermost semiconductor chip 402, the top shape size (circular with a radius of 100 μm) of the through electrodes 406 d-1 to 406 d-5 is made the same in the chip surface, and the bottom shape size. (Circle with a radius of 10 μm) is made the same in the chip surface, and in the semiconductor chip 402 of the second or higher layer, the top and bottom shape sizes (circular with a radius of 100 μm) of the through electrode 406 c are made the same in the chip surface. There is an advantage that the design and manufacturing process are simplified.

  Note that the length of the through electrode is substantially the same value as the thickness of the semiconductor chip, but is precisely a value slightly larger than the thickness of the semiconductor chip. This is because there is a portion protruding from the surface of the semiconductor chip for connection with the multilayer wiring on the surface of the semiconductor chip.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. First, the back surface of the semiconductor substrate 601 is ground so that the thickness of the semiconductor substrate 601 is 120 μm, for example, and a resist pattern 602 is formed on the surface of the semiconductor substrate 601 by photolithography. Subsequently, using the resist pattern 602 as a mask, the insulating film on the surface of the semiconductor substrate 601 or the semiconductor substrate 601 is dry-etched by ICP-RIE or the like to form a recess 603 having a depth of, for example, 100 μm (FIG. 8A).

  Next, after removing the resist pattern 602, a resist film is formed on the surface of the semiconductor substrate 601 so as to close the mouth of the recess 603. In this step, for example, a resist film may be attached using an STP method (Spin-coating film transfer and hot-pressing method) or the like. Then, the resist film is processed using a photolithography technique to form a resist pattern 604. The resist pattern 604 includes an opening 604a having a radius of 100 μm. Using this resist pattern 604 as a mask, the insulating film on the surface of the semiconductor substrate 601 and the semiconductor substrate 601 are dry-etched by ICP-RIE or the like to form a recess 605 having a depth of 97 μm, for example (FIG. 8B).

  Next, after removing the resist pattern 604, a resist film is formed on the surface of the semiconductor substrate 601 to close the mouths of the recesses 603 and 605 using the STP method or the like again. This resist film is processed using a photolithography technique to form a resist pattern 606. The resist pattern 606 includes an opening 606a having a radius of 10 μm immediately above the recess 605. Using this resist pattern 606 as a mask, the bottom of the recess 605 is dry-etched by ICP-RIE or the like to form a recess 605a having a depth of 3 μm, for example (FIG. 9A).

  The steps similar to those shown in FIGS. 8B and 9A are repeated twice to form the recesses 607 and 608 having a two-stage structure with a desired radius and depth. Further, after removing the resist pattern used as a mask when forming the recess 608, a resist film is formed on the surface of the semiconductor substrate 601 to close the mouths of the recesses 603, 605, 607, and 608, and this resist film is processed. Thus, a resist pattern 609 is formed. The resist pattern 609 includes an opening 609a having a radius of 100 μm. Using the resist pattern 609 as a mask, the insulating film on the surface of the semiconductor substrate 601 and the semiconductor substrate 601 are dry-etched to form a recess 610 having a depth of, for example, 63 μm (FIG. 9B).

  Subsequently, after removing the resist pattern 609, a resist film is formed on the surface of the semiconductor substrate 601 to block the openings of the recesses 603, 605, 607, 608, 610, and the resist film is processed to form a resist pattern 611. To do. The resist pattern 611 includes an opening 611 a having a radius of 10 μm immediately above the recess 610. Using the resist pattern 611 as a mask, the bottom of the recess 610 is dry-etched to form a recess 610a having a depth of 37 μm, for example (FIG. 9C). Then, when the resist pattern 611 is removed, the semiconductor substrate 601a in which various concave portions are formed is completed (FIG. 9D).

  Next, an insulating film 612 such as an oxide film is formed on the sidewall and bottom of the recess of the semiconductor substrate 601a, and after copper plating is deposited inside the recess, a resist pattern 613 or the like is formed on a part of the surface of the semiconductor substrate 601a. A copper pattern 614 is grown only on the exposed portion by forming and covering the surface (FIG. 9E). The grown copper pattern 614 is electrically connected to the multilayer wiring on the surface of the semiconductor substrate 601a.

After the copper pattern 614 is formed, the resist pattern 613 is removed. Finally, the back surface of the semiconductor substrate 601a is ground to expose the copper pattern 614 on the back surface. As a result, the copper pattern 614 becomes a through electrode 406 penetrating from the front surface to the back surface of the semiconductor substrate 601a (FIG. 9F).
Thereafter, as in the first embodiment, an insulating film and a conductor for connection are appropriately formed on the back surface of the semiconductor substrate 601a, the semiconductor substrate 601a is diced and divided into chips, and these chips are stacked. Thus, the semiconductor device shown in FIG. 7 can be manufactured.

In the present embodiment, some of the through electrodes have a two-stage structure, but it goes without saying that it may have a multi-stage structure. For example, a three-stage structure such as a through electrode 901 illustrated in FIG.
In addition, when a multi-stage through electrode is used, when a signal propagates from a thick part to a detail, the signal may be reflected depending on the frequency of the high frequency signal or the wiring length because the cross-sectional shape is a right angle. is there. In that case, a taper 902a may be provided in a step portion from the thick portion to the detail of the through electrode 902 by using isotropic etching or the like as shown in FIG. For the etching for forming the taper 902a, for example, plasma composed of SF ₆ and O ₂ may be used.
Further, the structure of the through electrode according to the present embodiment may be applied to a wiring substrate such as the interposer described in the first embodiment.

  In the first and second embodiments, a semiconductor device in which a plurality of semiconductor chips are stacked is described as an example of an electronic circuit device in which a plurality of substrates are stacked. However, other electronic circuit devices are described. The present invention may be applied to. In the first and second embodiments, through electrodes having different shapes and sizes coexist in the lowermost semiconductor chip, such coexistence is not limited to the lowermost semiconductor chip. In the first and second embodiments, the shape of the through electrode in the chip of each layer may be changed according to the signal propagation path between the plurality of chips and the through electrode wiring. Further, although a semiconductor is used as the substrate, it goes without saying that other materials capable of being thinned to about 100 μm may be used.

  The present invention can be applied to an electronic circuit device in which a plurality of substrates are stacked.

It is a perspective view which shows the structural example (in the case of 2 layers) of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 2 is a perspective view illustrating a shape of a through electrode in the semiconductor device of FIG. 1. It is sectional drawing which shows the structural example (in the case of 5 layers) of the semiconductor device which concerns on the 1st Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the structural example (in the case of 2 layers) of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 6 is a perspective view illustrating a shape of a through electrode in the semiconductor device of FIG. 5. It is sectional drawing which shows the structural example (in the case of 5 layers) of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101,401 ... Semiconductor device, 102, 402 ... Semiconductor chip, 103 ... Input / output terminal, 104 ... Substrate, 105 ... Semiconductor substrate part, 106, 406 ... Through electrode, 110, 111, 201, 410, 411, 501 ... Through Electrode wiring.

Claims (4)

In an electronic circuit device having a plurality of stacked substrates,
Each of the substrates includes a plurality of through electrodes penetrating from the front surface to the back surface, and the through electrodes of each substrate are electrically connected to the input / output terminals by through electrode wirings connected along the stacking direction,
At least a part of the plurality of through-electrodes has a signal delay adjusting through-hole shaped according to the length of the through-electrode wiring including the through-electrode so that the signal delay time of each through-electrode wiring is equal. electrode der is,
The signal delay adjusting through-electrode has a cross-sectional area in a plane perpendicular to the direction penetrating the substrate so that the signal delay time of each through-electrode wiring is equal to the length of the through-electrode wiring including the through-electrode. The electronic circuit device is characterized in that it changes within the same substrate . In an electronic circuit device having a plurality of stacked substrates,
Each of the substrates includes a plurality of through electrodes penetrating from the front surface to the back surface, and the through electrodes of each substrate are electrically connected to the input / output terminals by through electrode wirings connected along the stacking direction,
At least a part of the plurality of through-electrodes has a signal delay adjusting through-hole shaped according to the length of the through-electrode wiring including the through-electrode so that the signal delay time of each through-electrode wiring is equal. Electrodes,
The signal delay adjusting through-electrode has a cross-sectional area in a plane perpendicular to the direction penetrating the substrate so that the signal delay time of each through-electrode wiring is equal to the length of the through-electrode wiring including the through-electrode. In response to changes inside the board,
The number of the laminated substrates is n (n is an integer of 2 or more),
The number of through-electrodes for signal delay adjustment is two or more,
The signal delay adjusting through electrode has a two-stage structure including a detail having a cross-sectional area of A and a length of X and a thick section having a cross-sectional area of B (B> A) and a length of Y.
The signal delay adjusting through-electrode included in the through-electrode wiring P connecting the p-th substrate (p is an integer satisfying 1 ≦ p <n) and the input / output terminal from the side closer to the input / output terminal; The signal delay adjusting through-electrode included in the through-electrode wiring Q connecting the q-th substrate (q is an integer satisfying p <q ≦ n) and the input / output terminal from the side closer to the input / output terminal. When the cross-sectional area A is the same value and the cross-sectional area B is the same value,
A detail length X of the signal delay adjustment through electrode included in the through electrode wiring P is longer than a detail length X of the signal delay adjustment through electrode included in the through electrode wiring Q. Electronic circuit device to do. The electronic circuit device according to claim 1 or 2 ,
An electronic circuit device characterized in that the signal delay time of each through electrode wiring is made equal by setting the product of resistance and capacitance to the same value in each through electrode wiring. In the manufacturing method which manufactures the electronic circuit device in any one of Claims 1 thru | or 3 ,
A first step of forming a recess in the substrate surface;
A second step of attaching a thin film that closes the mouth of the recess while keeping the space in the recess on the substrate surface;
And patterning a portion of the thin film on the true of the recess to form an opening smaller than the mouth of the recess, a third step of exposing a part of the bottom of the recess,
A fourth step of processing the bottom of the recess by etching using the thin film as a mask;
After the first step to the fourth step are repeated as necessary to form a recess having a multistage structure in which a cross-sectional area in a plane perpendicular to the thickness direction of the substrate is changed inside the substrate A fifth step of forming an insulating film on the side wall and bottom of each recess;
A sixth step of forming a conductor pattern inside each recess;
A seventh step of grinding the back surface of the substrate to expose the conductor pattern on the back surface;
An eighth step of dividing the substrate after the seventh step to produce a plurality of substrates each having a plurality of the conductor patterns as through electrodes;
And a ninth step of laminating the plurality of substrates after the eighth step.

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