JP4799590B2 - Mixer circuit - Google Patents

Description

  The present invention relates to a mixer circuit used in a radio communication LSI (Large Scale Integration).

  Conventionally, in wireless communication, a mixer circuit that performs frequency conversion of an RF (Radio Frequency) signal is used.

  Here, due to technology scaling accompanying the development of CMOS process technology, a decrease in power supply voltage has become a major problem in future RF analog circuit design. Also, mounting of RF analog circuits to mobile devices is actively performed, and it is one of the major issues to operate a wireless communication LSI mounted with RF analog circuits with low power.

  However, the mixer circuit used in the conventional wireless communication LSI has a configuration in which two or more MOS transistors are stacked, and is not suitable for low voltage operation.

  In order to solve this problem, a mixer circuit (mixer core circuit, analog signal adding circuit) for low-voltage operation has been proposed (for example, see Patent Document 1).

  However, in order to realize a mixer circuit with this circuit configuration, an analog signal adding circuit is required.

  When analog signals are added by this adding circuit, power consumption is caused by the DC bias current of the MOS transistor.

Therefore, although the above conventional mixer circuit can realize a low voltage operation, there is a problem that it is difficult to reduce the power of the adder circuit.
Patent No. 3520175

  An object of the present invention is to provide a mixer circuit capable of operating at a low voltage and reducing power consumption.

A mixer circuit according to one embodiment of the present invention includes:
A first input terminal to which a first voltage signal is input;
A second input terminal to which a second voltage signal is input;
A third input terminal to which a third voltage signal equivalent to a signal obtained by inverting the first voltage signal is input;
A fourth input terminal to which a fourth voltage signal equivalent to a signal obtained by inverting the second voltage signal is input;
A fifth input terminal to which the first voltage signal is input;
A sixth input terminal to which the fourth voltage signal is input;
A seventh input terminal to which the second voltage signal is input;
A first resistance circuit having one end connected to the first potential;
A first output terminal connected to the other end of the first resistance circuit;
A first transistor connected between the other end of the first resistance circuit and a second potential;
A first impedance element connected between the first input terminal and a control electrode of the first transistor;
A second impedance element connected between the second input terminal and a control electrode of the first transistor;
A second transistor connected in parallel with the first transistor and having the same conductivity type as the first transistor between the other end of the first resistor circuit and the second potential;
A third impedance element connected between the third input terminal and a control electrode of the second transistor;
A fourth impedance element connected between the fourth input terminal and a control electrode of the second transistor;
A second resistance circuit having one end connected to the first potential;
A second output terminal connected to the other end of the second resistance circuit;
A third transistor connected between the other end of the second resistor circuit and a second potential and having the same conductivity type as the first transistor;
A fifth impedance element connected between the fifth input terminal and a control electrode of the third transistor;
A sixth impedance element connected between the sixth input terminal and a control electrode of the third transistor;
A fourth transistor connected in parallel with the third transistor and having the same conductivity type as the first transistor between the other end of the second resistor circuit and the second potential;
A seventh impedance element connected between the third input terminal and a control electrode of the fourth transistor;
And an eighth impedance element connected between the seventh input terminal and the control electrode of the fourth transistor.

A mixer circuit according to another aspect of the present invention includes:
A first input terminal to which a first voltage signal is input;
A second input terminal to which a second voltage signal is input;
A third input terminal to which a third voltage signal equivalent to a signal obtained by inverting the first voltage signal is input;
A fourth input terminal to which a fourth voltage signal equivalent to a signal obtained by inverting the second voltage signal is input;
A fifth input terminal to which the first voltage signal is input;
A sixth input terminal to which the fourth voltage signal is input;
A seventh input terminal to which the second voltage signal is input;
An eighth input terminal to which the third voltage signal is input;
A ninth input terminal to which the second voltage signal is input;
A tenth input terminal to which the first voltage signal is input;
An eleventh input terminal to which the fourth voltage signal is input;
A twelfth input terminal to which the third voltage signal is input;
A thirteenth input terminal to which the fourth voltage signal is input;
A fourteenth input terminal to which the second voltage signal is input;
A first transistor of a first conductivity type, one end of which is connected to a first potential;
A first output terminal connected to the other end of the first transistor;
A first impedance element connected between the first input terminal and a control electrode of the first transistor;
A second impedance element connected between the second input terminal and a control electrode of the first transistor;
A second transistor connected in parallel with the first transistor between the first output terminal and the first potential and having the same conductivity type as the first transistor;
A third impedance element connected between the third input terminal and a control electrode of the second transistor;
A fourth impedance element connected between the fourth input terminal and a control electrode of the second transistor;
A third transistor having one end connected to the first potential;
A second output terminal connected to the other end of the third transistor;
A fifth impedance element connected between the fifth input terminal and a control electrode of the third transistor;
A sixth impedance element connected between the sixth input terminal and a control electrode of the third transistor;
A fourth transistor connected in parallel with the third transistor between the second output terminal and the first potential and having the same conductivity type as the first transistor;
A seventh impedance element connected between the third input terminal and a control electrode of the fourth transistor;
An eighth impedance element connected between the seventh input terminal and a control electrode of the fourth transistor;
A fifth transistor of a second conductivity type different from the first conductivity type connected between the first output terminal and a second potential;
A ninth impedance element connected between the eighth input terminal and the control electrode of the fifth transistor;
A tenth impedance element connected between the ninth input terminal and a control electrode of the fifth transistor;
A sixth transistor connected in parallel with the fifth transistor and having the same conductivity type as the fifth transistor between the first output terminal and the second potential;
An eleventh impedance element connected between the tenth input terminal and a control electrode of the sixth transistor;
A twelfth impedance element connected between the eleventh input terminal and a control electrode of the sixth transistor;
A seventh transistor connected between the second output terminal and a second potential and having the same conductivity type as the fifth transistor;
A thirteenth impedance element connected between the twelfth input terminal and a control electrode of the seventh transistor;
A fourteenth impedance element connected between the thirteenth input terminal and a control electrode of the seventh transistor;
An eighth transistor connected in parallel with the seventh transistor between the second output terminal and the second potential and having the same conductivity type as the fifth transistor;
A fifteenth impedance element connected between the tenth input terminal and the control electrode of the eighth transistor;
And a sixteenth impedance element connected between the fourteenth input terminal and the control electrode of the eighth transistor.

  With the mixer circuit according to one embodiment of the present invention, low voltage operation and low power consumption can be achieved.

Here, it is assumed that each NMOS transistor constituting the conventional mixer circuit operates in a saturation region. In this case, the drain current I _dsn of each NMOS transistor is expressed by equations (1) and (2). For simplification, the channel length modulation effect is ignored.

式（１）、（２）に示すように、各ＮＭＯＳトランジスタのドレイン電流I_dsnは、二乗特性をもつ。 In Equation (1), Vgs represents the gate-source voltage, and V _thn represents the threshold voltage of the NMOS transistor. In equation (2), μ _n represents electron mobility, C _ox represents the gate oxide thickness of the transistor, and W _n and L _n represent the gate width and gate length of the NMOS transistor, respectively.

As shown in equations (1) and (2), the drain current I _dsn of each NMOS transistor has a square characteristic.

In this case, the difference I _p -I _n of the two output currents of the circuit of the mixer core is expressed by equation (3).

式（３）に示すように、２つの出力電流の差を求めることにより、ミキサ回路の入力信号であるv₁とv₂の乗算を行うことができる。 In Expression (3), v ₁ and v ₂ are input voltages (AC voltages) of the mixer circuit. Moreover, in Formula (3), since it cancels regarding DC voltage, it is not considered. The voltage input to the mixer core is represented by v ₁ + v ₂ (−v ₁ −v ₂ ) and v ₁ −v ₂ (−v ₁ + v ₂ ). The input voltage of the mixer core is generated by adding an analog signal adding circuit to the input voltages v ₁ (−v ₁ ) and v ₂ (−v ₂ ) of the mixer circuit.

As shown in Expression (3), by obtaining the difference between the two output currents, it is possible to multiply v ₁ and v ₂ which are input signals of the mixer circuit.

Further, when the voltage output through the difference I _p -I _n of the two output current resistance R, the difference V _outp -V _outn of the two output voltages is expressed by the equation (4).

  In this mixer core circuit, the transistor stacked between the power source and the ground is one stage, and is suitable for low voltage operation.

  In the present invention, the addition of analog signals is realized with a configuration that does not involve power consumption due to the DC bias current of the transistor, and the mixer circuit is reduced in voltage and power.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. In each of the following embodiments, a case where a MOS transistor is used as a transistor constituting the mixer circuit will be described.

  In this embodiment, an example of a mixer circuit that realizes addition of analog signals input to each input terminal by capacitive coupling will be described. In this embodiment, the addition of analog signals by capacitive coupling and the square characteristic of the drain current of the MOS transistor operating in the saturation region are utilized. As a result, the mixer circuit is reduced in voltage and power.

  In this embodiment, the first potential is described as a power supply potential, and the second potential is described as a ground potential. An n-type MOS transistor is used as the MOS transistor. The control electrode of the transistor corresponds to the gate electrode of the MOS transistor.

  In addition, although a DC voltage is biased at the gate of each MOS transistor, it is canceled when considering the output characteristics, and therefore a DC current is not considered here.

  Unnecessary spurious, which is a particular problem in radio transmitters, is caused by distortion generated in the orthogonal modulator (mixer circuit).

  FIG. 1 is a circuit diagram showing a main configuration of a mixer circuit according to a first embodiment which is an aspect of the present invention.

  As shown in FIG. 1, the mixer circuit 100 includes a first input terminal 1, a second input terminal 2, a third input terminal 3, a fourth input terminal 4, and a fifth input terminal 5. And a sixth input terminal 6 and a seventh input terminal 7.

The first input terminal 1 receives a first voltage signal v ₁ that is an analog signal.

The second input terminal 2 receives a second voltage signal v ₂ that is an analog signal.

A third voltage signal (−v ₁ ) equivalent to a signal obtained by inverting the first voltage signal v ₁ is input to the third input terminal 3.

A fourth voltage signal (−v ₂ ) equivalent to a signal obtained by inverting the second voltage signal v ₂ is input to the fourth input terminal 4.

The fifth voltage input v ₁ is input to the fifth input terminal 5.

The sixth input terminal 6 is adapted to receive a fourth voltage signal (−v ₂ ).

The seventh input terminal 7 is configured to receive the _second voltage signal v2.

  The mixer circuit 100 includes a first resistor circuit 8, a second resistor circuit 9, a first output terminal 10, and a second output terminal 11.

  One end of the first resistance circuit 8 is connected to the power supply potential Vdd that is the first potential. The first resistance circuit 8 has a resistance value R. For example, a load resistor is used for the first resistance circuit 8. The first resistance circuit 8 includes parasitic resistances such as transistors, inductors, and wiring.

  The second resistor circuit 9 has one end connected to the power supply potential Vdd that is the first potential. The second resistance circuit 9 has a resistance value R, similar to the first resistance circuit 8. For example, a load resistor is used for the second resistance circuit 9. The second resistance circuit 9 includes parasitic resistances such as transistors, inductors, and wiring.

  The first output terminal 10 is connected to the other end of the first resistance circuit 8. When the output current Ip flows through the first resistance circuit 8, the output voltage Voutp is output from the first output terminal 10.

  The second output terminal 11 is connected to the other end of the second resistance circuit 9. When the output current In flows through the second resistor circuit 9, the output voltage Voutn is output from the second output terminal 11.

  In addition, the mixer circuit 100 includes the first transistor 12, the first capacitor 13, the second capacitor 14, the second transistor 15, the third capacitor 16, and the fourth capacitor 17. Prepare.

  The first transistor 12 that is an n-type MOS transistor is connected between the other end of the first resistor circuit 8 and a ground potential that is a second potential.

  The first capacitor 13 is connected between the first input terminal 1 and the gate that is the control electrode of the first transistor 12. The first capacitor 13 has a capacitance value C1.

  The second capacitor 14 is connected between the second input terminal 2 and the gate of the first transistor 12. The second capacitor 14 has a capacitance value C2.

  The second transistor 15 is connected in parallel with the first transistor 12 between the other end of the first resistor circuit 8 and the ground potential. The second transistor 15 is an n-type MOS transistor having the same conductivity type as the first transistor 12.

  The third capacitor 16 is connected between the third input terminal 3 and the gate of the second transistor 15. The third capacitor 16 has the same capacitance value C1 as the first capacitor 13.

  The fourth capacitor 17 is connected between the fourth input terminal 4 and the gate of the second transistor 15. The fourth capacitor 17 has the same capacitance value C2 as the second capacitor 14.

  The mixer circuit 100 includes a third transistor 18, a fifth capacitor 19, a sixth capacitor 20, a fourth transistor 21, a seventh capacitor 22, and an eighth capacitor 23. Prepare.

  The third transistor 18 is connected between the other end of the second resistor circuit 9 and the ground potential. The third transistor 18 is an n-type MOS transistor having the same conductivity type as the first transistor 12.

  The fifth capacitor 19 is connected between the fifth input terminal 5 and the gate of the third transistor 18. The fifth capacitor 19 has the same capacitance value C1 as the first capacitor 13.

  The sixth capacitor 20 is connected between the sixth input terminal 6 and the gate of the third transistor 18. The sixth capacitor 20 has the same capacitance value C2 as the second capacitor 14.

  The fourth transistor 21 is connected in parallel with the third transistor 18 between the other end of the second resistor circuit 9 and the ground potential. The fourth transistor 21 is an n-type MOS transistor having the same conductivity type as the first transistor 12.

  The seventh capacitor 22 is connected between the third input terminal 3 and the gate of the fourth transistor 21. The seventh capacitor 22 has the same capacitance value C1 as the first capacitor 13.

  The eighth capacitor 23 is connected between the seventh input terminal 7 and the gate of the fourth transistor 21. The eighth capacitor 23 has the same capacitance value C2 as the second capacitor 14.

The mixer circuit 100 further includes a current source 24 connected between the sources of the first to fourth transistors 12, 15, 18, and 21 and the ground potential. The current source 24 outputs a current I _BIAS .

  Here, the operation of the mixer circuit 100 having the above configuration will be described.

The mixer circuit 100 includes the voltage Vpp obtained by capacitively coupling the first input signal v ₁ and the second input signal v ₂ , the third input signal (−v ₁ ), and the fourth input signal (− Based on the voltage Vnn obtained by capacitively coupling v ₂ ), the first and second MOS transistors 12 and 15 are operated differentially. The magnitude of the output current Ip changes according to the operation of the first and second MOS transistors 12 and 15. As described above, the output voltage Voutp corresponding to the voltage drop in the first resistance circuit 8 is output to the first output terminal 10.

Similarly, the mixer circuit 100 includes the voltage Vpn and the third input signal (−v ₁ ) obtained by capacitively coupling the first input signal v ₁ and the fourth input signal (−v ₂ ) with the first input signal v ₁ and the fourth input signal (−v ₂ ). The third and fourth MOS transistors 18 and 21 are differentially operated based on the voltage Vnp obtained by capacitively coupling the _two input signals v ₂ . Depending on the operation of the third and fourth MOS transistors 18 and 21, the magnitude of the output current In changes. As described above, the output voltage Voutn corresponding to the voltage drop in the second resistance circuit 9 is output to the second output terminal 11.

  As described above, the mixer circuit 100 outputs an output voltage according to the first to fourth input signals.

  Here, as described above, the mixer circuit 100 realizes addition of analog signals input to the input terminals by capacitive coupling. The principle of adding analog signals by capacitive coupling will be described below.

これらの式（５）ないし式（８）から分かるように、容量結合によってアナログ信号の加算が実現可能である。 First, the voltage at each node connected to the gate of each MOS transistor of the mixer circuit 100 shown in FIG. 1 is obtained using Kirchhoff's law. The voltages v _pp , v _nn , v _pn , and v _{np at} each node are expressed by the following equations (5) to (8).

As can be seen from these equations (5) to (8), addition of analog signals can be realized by capacitive coupling.

式（９）ないし式（１１）に示すように、ミキサ回路１００の回路構成を用いれば、出力電流の差を求めることにより、入力信号であるｖ₁とｖ₂の乗算を行うことができる。 Here, for example, it is assumed that each MOS transistor of the mixer circuit 100 in FIG. 1 operates in the saturation region. In this case, the difference I _p -I _n of the output current of the mixer circuit is expressed by the equation (9) to (11). Note that β _n is the same as the value shown in Expression (2).

As shown in the equations (9) to (11), if the circuit configuration of the mixer circuit 100 is used, the difference between the output currents can be obtained to multiply the input signals v ₁ and v ₂ .

式（１２）に示すように、ミキサ回路１００の回路構成を用いれば、出力電圧の差を求めることによっても、入力信号であるv₁とｖ₂の乗算を行うことができる。 Further, by making a voltage output through a resistance circuit, the difference V _outp -V _outn of the output voltage is expressed as in Expression (12).

As shown in Expression (12), if the circuit configuration of the mixer circuit 100 is used, the input signal v ₁ and v ₂ can be multiplied by obtaining the difference between the output voltages.

  As described above, the mixer circuit according to the first embodiment does not require an analog signal adding circuit as in the related art in which power consumption is caused by the DC bias current of the transistor. Therefore, the mixer circuit according to the first embodiment can operate with lower power compared to the above-described conventional technology.

  As described above, the mixer circuit according to the present embodiment can operate at a low voltage and can reduce power.

  In the first embodiment, an example of the configuration of the mixer circuit has been described.

  The mixer circuit shown in the first embodiment can achieve the same effect even if the polarity of the circuit is reversed.

  Therefore, in this embodiment, a configuration example of a mixer circuit in which the polarity of the circuit of the first embodiment is reversed will be described.

  In this embodiment, since the polarity of the circuit is inverted as described above, the first potential is set as the ground potential, and the second potential is set as the power supply potential. The MOS transistor is a p-type MOS transistor. The control electrode of the transistor corresponds to the gate electrode of the MOS transistor.

  As in the first embodiment, a DC voltage is biased at the gate of each MOS transistor. However, the DC current is not considered here because it is canceled when considering the output characteristics.

  FIG. 2 is a circuit diagram showing a main configuration of a mixer circuit according to a second embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 1 was attached | subjected is a structure similar to Example 1. FIG.

  As shown in FIG. 2, the mixer circuit 200 includes a first input terminal 201, a second input terminal 202, a third input terminal 203, a fourth input terminal 204, and a fifth input terminal 205. And a sixth input terminal 206 and a seventh input terminal 207.

The first input terminal 201 is adapted to receive a _first voltage signal v ₁ that is an analog signal.

The second input terminal 202 is configured to receive a _second voltage signal v ₂ that is an analog signal.

The third input terminal 203 is configured to receive a third voltage signal (−v ₁ ) equivalent to a signal obtained by inverting the first voltage signal v ₁ .

A fourth voltage signal (−v ₂ ) equivalent to a signal obtained by inverting the second voltage signal v ₂ is input to the fourth input terminal 204.

The fifth input terminal 205 is configured to receive the _first voltage signal v1.

The sixth input terminal 206 is configured to receive a fourth voltage signal (−v ₂ ).

The seventh input terminal 207 is configured to receive the _second voltage signal v2.

  The mixer circuit 200 includes a first resistor circuit 208, a second resistor circuit 209, a first output terminal 210, and a second output terminal 211.

  One end of the first resistance circuit 208 is connected to the ground potential which is the first potential. The first resistance circuit 208 has a resistance value R. For example, a load resistor is used for the first resistance circuit 208.

  One end of the second resistance circuit 209 is connected to the ground potential which is the first potential. The second resistance circuit 209 has a resistance value R, similar to the first resistance circuit 208. For example, a load resistor is used for the second resistance circuit 209.

  The first output terminal 210 is connected to the other end of the first resistance circuit 208. When the output current Ip flows through the first resistance circuit 208, the output voltage Voutp is output from the first output terminal 210.

  The second output terminal 211 is connected to the other end of the second resistance circuit 209. When the output current In flows through the second resistance circuit 209, the output voltage Voutn is output from the second output terminal 211.

  The mixer circuit 200 includes a first transistor 212, a first capacitor 213, a second capacitor 214, a second transistor 215, a third capacitor 216, and a fourth capacitor 217. Prepare.

  The first transistor 212 which is a p-type MOS transistor is connected between the other end of the first resistor circuit 208 and the power supply potential Vdd which is the second potential.

  The first capacitor 213 is connected between the first input terminal 201 and the gate that is the control electrode of the first transistor 212. The first capacitor 213 has a capacitance value C1.

  The second capacitor 214 is connected between the second input terminal 202 and the gate of the first transistor 212. The second capacitor 214 has a capacitance value C2.

  The second transistor 215 is connected in parallel with the first transistor 212 between the other end of the first resistor circuit 208 and the power supply potential Vdd. The second transistor 215 is a p-type MOS transistor having the same conductivity type as the first transistor 212.

  The third capacitor 216 is connected between the third input terminal 203 and the gate of the second transistor 215. The third capacitor 216 has the same capacitance value C1 as the first capacitor 213.

  The fourth capacitor 217 is connected between the fourth input terminal 204 and the gate of the second transistor 215. The fourth capacitor 217 has the same capacitance value C2 as the second capacitor 214.

  The mixer circuit 200 includes the third transistor 218, the fifth capacitor 219, the sixth capacitor 220, the fourth transistor 221, the seventh capacitor 222, and the eighth capacitor 223. Prepare.

  The third transistor 218 is connected between the other end of the second resistor circuit 209 and the power supply potential Vdd. The third transistor 218 is a p-type MOS transistor having the same conductivity type as the first transistor 212.

  The fifth capacitor 219 is connected between the fifth input terminal 205 and the gate of the third transistor 218. The fifth capacitor 219 has the same capacitance value C1 as the first capacitor 213.

  The sixth capacitor 220 is connected between the sixth input terminal 206 and the gate of the third transistor 218. The sixth capacitor 220 has the same capacitance value C 2 as the second capacitor 214.

  The fourth transistor 221 is connected in parallel with the third transistor 218 between the other end of the second resistor circuit 209 and the power supply potential Vdd. The fourth transistor 221 is a p-type MOS transistor having the same conductivity type as the first transistor 212.

  The seventh capacitor 222 is connected between the third input terminal 203 and the gate of the fourth transistor 221. The seventh capacitor 222 has the same capacitance value C1 as the first capacitor 213.

  The eighth capacitor 223 is connected between the seventh input terminal 207 and the gate of the fourth transistor 221. The eighth capacitor 223 has the same capacitance value C2 as the second capacitor 214.

The mixer circuit 200 further includes a current source 224 connected between the sources of the first to fourth transistors 212, 215, 218, and 221 and the power supply potential Vdd. The current source 224 outputs a current I _BIAS .

  Here, the operation of the mixer circuit 200 having the above configuration is the same as that of the mixer circuit 100 shown in the first embodiment.

  That is, the mixer circuit 200 outputs an output voltage according to the first to fourth input signals.

  In addition, the mixer circuit 200 realizes addition of analog signals input to the input terminals by capacitive coupling, as in the first embodiment.

  Therefore, like the first embodiment, the mixer circuit according to the second embodiment does not need an analog signal adding circuit as in the related art in which power consumption is caused by the DC bias current of the transistor. Therefore, the mixer circuit according to the second embodiment can operate with lower power than the conventional technology described above.

  As described above, the mixer circuit according to the present embodiment can operate at a low voltage and can reduce power.

  In the first and second embodiments, an example of the configuration of the mixer circuit has been described.

  For example, a resistive load is used for the first and second resistance circuits of the mixer circuits shown in the first and second embodiments. However, transistors may be used for the first and second resistance circuits.

  Therefore, in this embodiment, a configuration example of a mixer circuit using transistors for the first and second resistor circuits will be described. Here, as an example, an example in which transistors are used for the first and second resistance circuits of the mixer circuit of the first embodiment will be described.

  As in the first embodiment, a DC voltage is biased at the gate of each MOS transistor. However, the DC current is not considered here because it is canceled when considering the output characteristics.

  FIG. 3 is a circuit diagram showing a main configuration of a mixer circuit according to a third embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 1 was attached | subjected is a structure similar to Example 1. FIG.

  As shown in FIG. 3, the first resistance circuit and the second resistance circuit of the mixer circuit 300 are configured by p-type MOS transistors 308 and 309 having control electrodes (gates) connected to a fixed potential Vbias. . These p-type MOS transistors 308 and 309 also function as current sources.

In the configuration of the mixer circuit 300, assuming that the output impedance of the p-type MOS transistors 308 and 309 is infinite, the first and second output terminals 10 and 11 are current outputs. Under this assumption, the difference I _p −I _n between the output currents Ip and Ip has a form similar to that in the equation (9).

  Further, it is possible to obtain a voltage output by arranging a current / voltage conversion circuit after the mixer circuit 300.

  The mixer circuit 300 having the above configuration outputs an output voltage in accordance with the first to fourth input signals, as in the first embodiment.

  In addition, the mixer circuit 300 realizes addition of analog signals input to the respective input terminals by capacitive coupling as in the first embodiment.

  Therefore, as in the first embodiment, the mixer circuit according to the third embodiment does not need an analog signal adding circuit as in the prior art in which power consumption is caused by the DC bias current of the transistor. Therefore, the mixer circuit according to the third embodiment can operate with lower power than the conventional technology described above.

  As described above, the mixer circuit according to the present embodiment can operate at a low voltage and can reduce power.

  In the first and second embodiments, an example of the configuration of the mixer circuit has been described.

  In this embodiment, an example of the configuration of a mixer circuit for further improving the characteristics will be described. Here, as an example, an example in which transistors are used for the first and second resistance circuits of the mixer circuit of the first embodiment will be described.

  As in the first embodiment, a DC voltage is biased at the gate of each MOS transistor. However, the DC current is not considered here because it is canceled when considering the output characteristics.

  FIG. 4 is a circuit diagram showing a main configuration of a mixer circuit according to a fourth embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 1, 2 was attached | subjected is a structure similar to Example 1,2.

  As shown in FIG. 4, the mixer circuit 400 includes a first input terminal 1, a second input terminal 2, a third input terminal 3, a fourth input terminal 4, and a fifth input terminal 5. And a sixth input terminal 6 and a seventh input terminal 7.

The first input terminal 1 receives a first voltage signal v ₁ that is an analog signal.

The second input terminal 2 receives a second voltage signal v ₂ that is an analog signal.

A third voltage signal (−v ₁ ) equivalent to a signal obtained by inverting the first voltage signal v ₁ is input to the third input terminal 3.

A fourth voltage signal (−v ₂ ) equivalent to a signal obtained by inverting the second voltage signal v ₂ is input to the fourth input terminal 4.

The fifth voltage input v ₁ is input to the fifth input terminal 5.

The sixth input terminal 6 is adapted to receive a fourth voltage signal (−v ₂ ).

The seventh input terminal 7 is configured to receive the _second voltage signal v2.

  The mixer circuit 400 includes a first output terminal 10 and a second output terminal 11.

  The first output terminal 10 is configured to output an output current Ioutp. The second output terminal 11 is configured to output an output current Ioutn.

  The mixer circuit 400 includes the first transistor 12, the first capacitor 13, the second capacitor 14, the second transistor 15, the third capacitor 16, and the fourth capacitor 17. Prepare.

  The first transistor 12 which is an n-type MOS transistor is connected between the first output terminal 10 and a ground potential which is a second potential.

  The first capacitor 13 is connected between the first input terminal 1 and the gate that is the control electrode of the first transistor 12. The first capacitor 13 has a capacitance value C1.

  The second capacitor 14 is connected between the second input terminal 2 and the gate of the first transistor 12. The second capacitor 14 has a capacitance value C2.

  The second transistor 15 is connected in parallel with the first transistor 12 between the first output terminal 10 and the ground potential. The second transistor 15 is an n-type MOS transistor having the same conductivity type as the first transistor 12.

  The third capacitor 16 is connected between the third input terminal 3 and the gate of the second transistor 15. The third capacitor 16 has the same capacitance value C1 as the first capacitor 13.

  The fourth capacitor 17 is connected between the fourth input terminal 4 and the gate of the second transistor 15. The fourth capacitor 17 has the same capacitance value C2 as the second capacitor 14.

  In addition, the mixer circuit 400 includes the third transistor 18, the fifth capacitor 19, the sixth capacitor 20, the fourth transistor 21, the seventh capacitor 22, and the eighth capacitor 23. Prepare.

  The third transistor 18 is connected between the second output terminal 11 and the ground potential. The third transistor 18 is an n-type MOS transistor having the same conductivity type as the first transistor 12.

  The fifth capacitor 19 is connected between the fifth input terminal 5 and the gate of the third transistor 18. The fifth capacitor 19 has the same capacitance value C1 as the first capacitor 13.

  The sixth capacitor 20 is connected between the sixth input terminal 6 and the gate of the third transistor 18. The sixth capacitor 20 has the same capacitance value C2 as the second capacitor 14.

  The fourth transistor 21 is connected in parallel with the third transistor 18 between the second output terminal 11 and the ground potential. The fourth transistor 21 is an n-type MOS transistor having the same conductivity type as the first transistor 12.

  The seventh capacitor 22 is connected between the third input terminal 3 and the gate of the fourth transistor 21. The seventh capacitor 22 has the same capacitance value C1 as the first capacitor 13.

  The eighth capacitor 23 is connected between the seventh input terminal 7 and the gate of the fourth transistor 21. The eighth capacitor 23 has the same capacitance value C2 as the second capacitor 14.

The mixer circuit 400 includes a current source 24 connected between the sources of the first to fourth transistors 12, 15, 18, and 21 and the ground potential. The current source 24 outputs a current I _BIAS .

  The mixer circuit 400 includes an eighth input terminal 401, a ninth input terminal 402, a tenth input terminal 403, an eleventh input terminal 404, a twelfth input terminal 405, and a thirteenth input terminal. An input terminal 406 and a fourteenth input terminal 407 are provided.

The eighth input terminal 401 is configured to receive a third voltage signal (−v ₁ ).

The ninth input terminal 402 is configured to receive the _second voltage signal v2.

The tenth input terminal 403 is configured to receive the _first voltage signal v1.

The eleventh input terminal 404 is adapted to receive a fourth voltage signal (−v ₂ ).

The twelfth input terminal 405 is configured to receive a third voltage signal (−v ₁ ).

The thirteenth input terminal 406 is configured to receive a fourth voltage signal (−v ₂ ).

The fourteenth input terminal 407 is configured to receive the _second voltage signal v2.

  The mixer circuit 400 includes a fifth transistor 412, a ninth capacitor 413, a tenth capacitor 414, a sixth transistor 415, an eleventh capacitor 416, and a twelfth capacitor 417. Prepare.

  The fifth transistor 412 that is a p-type MOS transistor is connected between the first output terminal 10 and the power supply potential Vdd that is the first potential.

  The ninth capacitor 413 is connected between the first input terminal 401 and the gate which is the control electrode of the fifth transistor 412. The ninth capacitor 413 has a capacitance value C1.

  The tenth capacitor 414 is connected between the second input terminal 402 and the gate of the fifth transistor 412. The tenth capacitor 414 has a capacitance value C2.

  The sixth transistor 415 is connected in parallel with the fifth transistor 412 between the first output terminal 10 and the power supply potential Vdd. The sixth transistor 415 is a p-type MOS transistor having the same conductivity type as the fifth transistor 412.

  The eleventh capacitor 416 is connected between the tenth input terminal 403 and the gate of the sixth transistor 415. The eleventh capacitor 416 has the same capacitance value C1 as the ninth capacitor 413.

  The twelfth capacitor 417 is connected between the eleventh input terminal 404 and the gate of the sixth transistor 415. The twelfth capacitor 417 has the same capacitance value C2 as the tenth capacitor 414.

  The mixer circuit 400 includes a seventh transistor 418, a thirteenth capacitor 419, a fourteenth capacitor 420, an eighth transistor 421, a fifteenth capacitor 422, and a sixteenth capacitor 423. Prepare.

  The seventh transistor 418 is connected between the second output terminal 11 and the power supply potential Vdd. The seventh transistor 418 is a p-type MOS transistor having the same conductivity type as the fifth transistor 412.

  The thirteenth capacitor 419 is connected between the twelfth input terminal 405 and the gate of the seventh transistor 418. The thirteenth capacitor 419 has the same capacitance value C1 as the ninth capacitor 413.

  The fourteenth capacitor 420 is connected between the thirteenth input terminal 406 and the gate of the seventh transistor 418. The fourteenth capacitor 420 has the same capacitance value C2 as the tenth capacitor 414.

  The eighth transistor 421 is connected in parallel with the seventh transistor 418 between the second output terminal 11 and the power supply potential Vdd. The eighth transistor 421 is a p-type MOS transistor having the same conductivity type as the fifth transistor 412.

  The fifteenth capacitor 422 is connected between the tenth input terminal 403 and the gate of the eighth transistor 421. The fifteenth capacitor 422 has the same capacitance value C1 as the ninth capacitor 413.

  The sixteenth capacitor 423 is connected between the fourteenth input terminal 407 and the gate of the eighth transistor 421. The sixteenth capacitor 423 has the same capacitance value C2 as the tenth capacitor 414.

  The operation of the mixer circuit 400 having the above configuration is the same as that of the mixer circuit shown in the first and second embodiments.

  That is, the mixer circuit 400 outputs an output voltage according to the first to fourth input signals.

  In addition, the mixer circuit 400 realizes addition of analog signals input to the input terminals by capacitive coupling as in the first and second embodiments.

  Here, the principle by which the characteristics of the mixer circuit 400 having the above configuration is improved as compared with the mixer circuits described in the first to third embodiments will be described.

なお、式（１３）、（１４）において、μ_pはホールの移動度、C_oxはトランジスタのゲート酸化膜厚、W_pとL_pはそれぞれｐ型ＭＯＳトランジスタのゲート幅、ゲート長である。また、V_gsはゲート・ソース間電圧、V_thpはｐ型ＭＯＳトランジスタのしきい値電圧を表している。 As a premise, it is assumed that each transistor of the mixer circuit 400 operates in a saturation region. For simplicity, the channel length modulation effect is also ignored here. That is, the drain current of the n-type MOS transistor is expressed as the above-described formula (1). Further, the drain current of the p-type MOS transistor is expressed as in the equations (13) and (14).

In equations (13) and (14), μ _p is the mobility of holes, C _ox is the gate oxide thickness of the transistor, and W _p and L _p are the gate width and gate length of the p-type MOS transistor, respectively. V _gs represents the gate-source voltage, and V _thp represents the threshold voltage of the p-type MOS transistor.

Under the above premise, the currents I _{p_NMOS} , I _{n_NMOS} , I _{p_pMOS} , and I _{n_pMOS} flowing in the mixer circuit 400 shown in FIG. 4 are expressed as in equations (15) to (18).

この式（１９）から分かるように、β_n=β_pとなるように設計すると、本実施例に係るミキサ回路は、実施例１ないし３のミキサ回路と比較して２倍の出力電流を得ることができる。また、このミキサ回路の後段に電流・電圧変換回路を配置することで電圧出力とすることが可能である。 Therefore, the output current _{I outp} = I p_pmos -I p_nmos, when the output current _{I outn} = I n_nmos -I n_pmos, the difference I _outp -I _outn of the output current is expressed by the equation (19).

As can be seen from this equation (19), when designed so that β _n = β _p , the mixer circuit according to the present embodiment obtains twice the output current as compared with the mixer circuits of the first to third embodiments. be able to. Further, it is possible to obtain a voltage output by arranging a current / voltage conversion circuit in the subsequent stage of the mixer circuit.

  Further, the mixer circuit according to the fourth embodiment does not need an analog signal adding circuit as in the prior art in which power consumption is caused by the DC bias current of the transistor, as in the first and second embodiments. Therefore, the mixer circuit according to the fourth embodiment can operate with lower power compared to the above-described conventional technology.

  As described above, the mixer circuit according to the present embodiment can operate at a low voltage and can reduce power.

  In the first to fourth embodiments, an example of the configuration of a mixer circuit that can achieve low voltage and low power has been described.

  In the mixer circuit, capacitive coupling is used for the signal input portion to the mixer circuit. Therefore, the two input signals to the mixer circuit assumed in the embodiment are high frequency signals.

  In other words, the first to fourth embodiments are assumed to be used in an RFIC (Radio Frequency Integrated Circuit) receiving system for down-converting a high-frequency signal into a baseband signal.

  For this reason, it is difficult to use the mixer circuits shown in the first to fourth embodiments as they are in the transmission system.

  Therefore, in this embodiment, a configuration example of a mixer circuit capable of low voltage / low power operation for use in an RFIC transmission system will be described.

  In this embodiment, the basic configuration of the transistor of the mixer circuit shown in the first embodiment is not changed, and one of the capacitive couplings in the signal input portion is replaced with DC (Direct Current) coupling. Thus, a mixer circuit that can be used in the RFIC transmission system is configured.

  As in the first embodiment, a DC voltage is biased at the gate of each MOS transistor.

  FIG. 5 is a circuit diagram showing a main configuration of a mixer circuit according to a fifth embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 1 was attached | subjected is a structure similar to Example 1. FIG.

  As shown in FIG. 5, in the mixer circuit 500, the first capacitor 13 of the mixer circuit 100 shown in the first embodiment is replaced with a first resistance element 513. Similarly, the third capacitor 16 of the mixer circuit 100 is replaced with a second resistance element 516. Similarly, the fifth capacitor 19 of the mixer circuit 100 is replaced with a third resistance element 519. Similarly, the seventh capacitor 22 of the mixer circuit 100 is replaced with a fourth resistance element 522.

Here, in the present embodiment (the same applies to following embodiments), the first voltage signal _{v 1,} for example, has a frequency of about 20MHz～30MHz, a baseband signal. The second voltage signal v ₂ is, for example, a high-frequency signal having a frequency of about 400MHz~ number GHz.

  The other configuration of the mixer circuit 500 is the same as that of the mixer circuit 100 shown in the first embodiment.

  The operation of the mixer circuit 500 having the above configuration is the same as that of the mixer circuit 100 shown in the first embodiment. Therefore, the mixer circuit 500 outputs an output voltage according to the first to fourth input signals.

  Here, as described above, the mixer circuit 500 realizes addition of analog signals input to the input terminals by capacitive coupling and DC coupling. The principle of adding analog signals by capacitive coupling and DC coupling will be described below.

式（２０）ないし式（２３）に示すように、容量、ＤＣ結合によってアナログ信号の加算が実現可能である。そして、実施例１と同様に、ＭＯＳトランジスタの飽和ドレイン電流の二乗特性を前提とすると、出力電流の差I_p-I_nを求めることにより、入力信号であるv₁とｖ₂の乗算を行うことが可能である。すなわち、実施例１と同様に、ミキサの機能を実現可能である。 First, the voltage at each node connected to the gate of each MOS transistor of the mixer circuit 500 shown in FIG. 5 is obtained using Kirchhoff's law. The voltages v _pp , v _nn , v _pn , and v _{np at} each node are expressed by the following equations (20) to (23).

As shown in equations (20) to (23), the addition of analog signals can be realized by capacitance and DC coupling. As in the first embodiment, assuming the square characteristic of the saturation drain current of the MOS transistor, the difference between the output currents I _p -I _n is obtained to multiply the input signals v ₁ and v _2. It is possible. That is, the function of the mixer can be realized as in the first embodiment.

As shown in FIG. 5, the first input signal v ₁ is input to the gate terminal of the transistor via DC coupling, and the second input signal v ₂ is input to the gate terminal of the transistor via capacitive coupling. . As described above, the first input signal v ₁ is assumed to be a baseband signal, and the second input signal v ₂ is assumed to be a high-frequency signal. Therefore, the mixer circuit 500 can be used as a mixer for an RFIC transmission system.

  Further, since the basic configuration of the transistor portion of the mixer circuit 500 is the same as that of the first embodiment, the mixer circuit 500 can operate with low power and low voltage.

  As described above, according to the mixer circuit according to the present embodiment, it is possible to operate at a low voltage and to reduce power as in the first embodiment.

  In the fifth embodiment, the example in which the configuration of the mixer circuit of the first embodiment used in the RFIC reception system is changed for use in the RFIC transmission system has been described.

  In the present embodiment, one of the capacitive couplings of the signal input portion is replaced with DC coupling without changing the basic configuration of the transistors of the mixer circuit shown in the second embodiment. Thus, a mixer circuit that can be used in the RFIC transmission system is configured.

  As in the fifth embodiment, a DC voltage is biased at the gate of each MOS transistor.

  FIG. 6 is a circuit diagram showing a main configuration of a mixer circuit according to a sixth embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 2 was attached | subjected is a structure similar to Example 2. FIG.

  As shown in FIG. 6, in the mixer circuit 600, the first capacitor 213 of the mixer circuit 200 shown in the second embodiment is replaced with a first resistance element 613. Similarly, the third capacitor 216 of the mixer circuit 200 is replaced with a second resistance element 616. Similarly, the fifth capacitor 219 of the mixer circuit 200 is replaced with a third resistance element 619. Similarly, the seventh capacitor 222 of the mixer circuit 200 is replaced with a fourth resistance element 622.

  The other configuration of the mixer circuit 600 is the same as that of the mixer circuit 200 shown in the second embodiment.

  The operation of the mixer circuit 600 having the above configuration is the same as that of the mixer circuit 200 shown in the second embodiment. Therefore, the mixer circuit 600 outputs an output voltage according to the first to fourth input signals.

  Similarly to the fifth embodiment, the mixer circuit 600 realizes addition of analog signals input to the input terminals by capacitive coupling and DC coupling. Therefore, as in the fifth embodiment, the mixer circuit 600 can be used as a mixer for an RFIC transmission system.

  Further, since the basic configuration of the transistor portion of the mixer circuit 600 is the same as that of the second embodiment, the mixer circuit 600 can operate with low power and low voltage.

  As described above, according to the mixer circuit according to the present embodiment, it is possible to operate at a low voltage and to reduce power as in the second embodiment.

  In the fifth embodiment, the example in which the configuration of the mixer circuit of the first embodiment used in the RFIC reception system is changed for use in the RFIC transmission system has been described.

  In the present embodiment, one of the capacitive couplings of the signal input portion is replaced with DC coupling without changing the basic configuration of the transistors of the mixer circuit shown in the third embodiment. Thus, a mixer circuit that can be used in the RFIC transmission system is configured.

  As in the fifth embodiment, a DC voltage is biased at the gate of each MOS transistor.

  FIG. 7 is a circuit diagram showing a main configuration of a mixer circuit according to a seventh embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 3 was attached | subjected is a structure similar to Example 3. FIG.

  As shown in FIG. 7, in the mixer circuit 700, the first capacitor 13 of the mixer circuit 300 shown in the third embodiment is replaced with a first resistance element 713. Similarly, the third capacitor 16 of the mixer circuit 300 is replaced with a second resistance element 716. Similarly, the fifth capacitor 19 of the mixer circuit 300 is replaced with a third resistance element 719. Similarly, the seventh capacitor 22 of the mixer circuit 300 is replaced with a fourth resistance element 722.

  The other configuration of the mixer circuit 700 is the same as that of the mixer circuit 300 shown in the third embodiment.

  The operation of the mixer circuit 700 having the above configuration is the same as that of the mixer circuit 300 shown in the third embodiment. Therefore, the mixer circuit 700 outputs an output voltage according to the first to fourth input signals.

  Similarly to the fifth embodiment, the mixer circuit 700 realizes addition of analog signals input to the input terminals by capacitive coupling and DC coupling. Therefore, as in the fifth embodiment, the mixer circuit 700 can be used as a mixer for an RFIC transmission system.

  Further, since the basic configuration of the transistor portion of the mixer circuit 700 is the same as that of the third embodiment, it can operate with low power and low voltage.

  As described above, according to the mixer circuit of the present embodiment, it is possible to operate at a low voltage and to reduce power as in the third embodiment.

  In the fifth to seventh embodiments, the example in which the configuration of the mixer circuit of the first to third embodiments used in the RFIC receiving system is changed for use in the RFIC transmitting system has been described.

  In the present embodiment, one of the capacitive couplings of the signal input portion is replaced with DC coupling without changing the basic configuration of the transistors of the mixer circuit shown in the fourth embodiment. Thus, a mixer circuit that can be used in the RFIC transmission system is configured.

  FIG. 8 is a circuit diagram showing the main configuration of a mixer circuit according to an eighth embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 4 was attached | subjected is a structure similar to Example 4. FIG.

  As shown in FIG. 8, in the mixer circuit 800, the first capacitor 13 of the mixer circuit 400 shown in the fourth embodiment is replaced with a first resistance element 813a. Similarly, the third capacitor 16 of the mixer circuit 400 is replaced with a second resistance element 816a. Similarly, the fifth capacitor 19 of the mixer circuit 400 is replaced with a third resistance element 819a. Similarly, the seventh capacitor 22 of the mixer circuit 400 is replaced with a fourth resistance element 822a.

  Also, as shown in FIG. 8, in the mixer circuit 800, the ninth capacitor 413 of the mixer circuit 400 shown in the fourth embodiment is replaced with a fifth resistance element 813b. Similarly, the eleventh capacitor 416 of the mixer circuit 400 is replaced with a sixth resistance element 816b. Similarly, the thirteenth capacitor 419 of the mixer circuit 400 is replaced with a seventh resistance element 819b. Similarly, the fifteenth capacitor 422 of the mixer circuit 400 is replaced with an eighth resistance element 822b.

  The other configuration of the mixer circuit 800 is the same as that of the mixer circuit 400 shown in the fourth embodiment.

  The operation of the mixer circuit 800 having the above configuration is the same as that of the mixer circuit 400 shown in the fourth embodiment. Therefore, the mixer circuit 800 outputs an output voltage according to the first to fourth input signals.

  Similarly to the fifth embodiment, the mixer circuit 800 realizes addition of analog signals input to the input terminals by capacitive coupling and DC coupling. Therefore, as in the fifth embodiment, the mixer circuit 800 can be used as a mixer for an RFIC transmission system.

  Further, since the basic configuration of the transistor portion of the mixer circuit 800 is the same as that of the fourth embodiment, it can operate with low power and low voltage.

  As described above, according to the mixer circuit according to the present embodiment, it is possible to operate at a low voltage and to reduce power as in the fourth embodiment.

  In each of the above embodiments, the case where a MOS transistor is used as a transistor constituting the mixer circuit has been described. Here, the collector current of the bipolar transistor has an exponential characteristic as the drain current of the MOS transistor has a square characteristic. Therefore, it is applicable to the present invention, and a bipolar transistor may be used as a transistor constituting the mixer circuit. In this case, the base electrode of the bipolar transistor corresponds to the control electrode. Further, when the first conductivity type corresponds to the NPN type, the second conductivity type corresponds to the PNP type. When the first conductivity type corresponds to the PNP type, the second conductivity type corresponds to the NPN type.

  In the first and fifth embodiments, the example of the configuration of the mixer circuit that can achieve low voltage and low power is described.

  In the mixer circuit, capacitive coupling or coupling is used for the signal input portion to the mixer circuit.

The coupling is composed of a capacitor and a resistance element. Here, even if an inductor is used instead of these elements, frequency mixing can be performed based on the principle described in the first and fifth embodiments. That is, if the coupling by the impedance element is formed in the signal input portion to the mixer circuit, it is possible to reduce the voltage and power of the mixer circuit. Therefore, in this embodiment, the more generalized mixer circuit A configuration example will be described.

  In the present embodiment, the basic configuration of the transistors of the mixer circuit shown in the first and fifth embodiments is not changed, and the coupling by the impedance element is formed in the signal input portion. As described above, the impedance element is any one of a capacitor, a resistance element, and an inductor.

  As in the first embodiment, a DC voltage is biased at the gate of each MOS transistor.

  FIG. 9 is a circuit diagram showing a main configuration of a mixer circuit according to a ninth embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 1 was attached | subjected is a structure similar to Example 1. FIG.

  As shown in FIG. 9, in the mixer circuit 900, the first capacitor 13 of the mixer circuit 100 shown in the first embodiment is replaced with the first impedance element 13A. Similarly, the second capacitor 14 of the mixer circuit 100 is replaced with a second impedance element 14A. Similarly, the third capacitor 16 of the mixer circuit 100 is replaced with a third impedance element 16A. Similarly, the fourth capacitor 17 of the mixer circuit 100 is replaced with a fourth impedance element 17A.

  Similarly, the fifth capacitor 19 of the mixer circuit 100 is replaced with a fifth impedance element 19A. Similarly, the sixth capacitor 20 of the mixer circuit 100 is replaced with a sixth impedance element 20A. Similarly, the seventh capacitor 22 of the mixer circuit 100 is replaced with a seventh impedance element 22A. Similarly, the eighth capacitor 23 of the mixer circuit 100 is replaced with an eighth impedance element 23A.

  The first, third, fifth, and seventh impedance elements 13A, 16A, 19A, and 22A have an impedance Z1. The second, fourth, sixth, and eighth impedance elements 14A, 17A, 20A, and 23A have an impedance Z2.

  The other configuration of the mixer circuit 900 is the same as that of the mixer circuit 100 shown in the first embodiment.

  The operation of the mixer circuit 900 having the above configuration is the same as that of the mixer circuits 100 and 500 shown in the first and fifth embodiments. Therefore, the mixer circuit 900 outputs an output voltage according to the first to fourth input signals.

  Here, as described above, the mixer circuit 900 realizes addition of analog signals input to the input terminals by coupling of impedance elements. The principle of addition of analog signals by the combination of the impedance elements is described in the same manner as in the first and fifth embodiments.

  Further, since the basic configuration of the transistor portion of the mixer circuit 900 is the same as that of the first and fifth embodiments, it can operate with low power and low voltage.

  As described above, according to the mixer circuit of the present embodiment, it is possible to operate at a low voltage and to reduce power as in the first and fifth embodiments.

  In the ninth embodiment, an example of a configuration in which the mixer circuits of the first and fifth embodiments are more generalized has been described.

  In the mixer circuit, capacitive coupling or coupling is used for the signal input portion to the mixer circuit.

  In this embodiment, an example of a configuration in which the mixer circuits of Embodiments 2 and 6 are more generalized will be described.

  In the present embodiment, the basic configuration of the transistors of the mixer circuit shown in the second and sixth embodiments is not changed, and a coupling by an impedance element is formed in the signal input portion. As described above, the impedance element is any one of a capacitor, a resistance element, and an inductor.

  As in the second embodiment, a DC voltage is biased at the gate of each MOS transistor.

  FIG. 10 is a circuit diagram showing the main configuration of a mixer circuit according to a tenth embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 2 was attached | subjected is a structure similar to Example 2. FIG.

  As shown in FIG. 10, in the mixer circuit 1000, the first capacitor 213 of the mixer circuit 200 shown in the second embodiment is replaced with a first impedance element 213A. Similarly, the second capacitor 214 of the mixer circuit 200 is replaced with a second impedance element 214A. Similarly, the third capacitor 216 of the mixer circuit 200 is replaced with a third impedance element 216A. Similarly, the fourth capacitor 217 of the mixer circuit 200 is replaced with a fourth impedance element 217A.

  Similarly, the fifth capacitor 219 of the mixer circuit 200 is replaced with a fifth impedance element 219A. Similarly, the sixth capacitor 220 of the mixer circuit 200 is replaced with a sixth impedance element 220A. Similarly, the seventh capacitor 222 of the mixer circuit 200 is replaced with a seventh impedance element 222A. Similarly, the eighth capacitor 223 of the mixer circuit 200 is replaced with an eighth impedance element 223A.

  The first, third, fifth, and seventh impedance elements 213A, 216A, 219A, and 222A have an impedance Z1. The second, fourth, sixth, and eighth impedance elements 214A, 217A, 220A, and 223A have an impedance Z2.

  The other configuration of the mixer circuit 1000 is the same as that of the mixer circuit 200 shown in the second embodiment.

  The operation of the mixer circuit 1000 having the above configuration is the same as that of the mixer circuits 200 and 500 shown in the second and sixth embodiments. Therefore, the mixer circuit 1000 outputs an output voltage according to the first to fourth input signals.

  Here, as described above, the mixer circuit 1000 realizes addition of analog signals input to the input terminals by coupling impedance elements. The principle of addition of analog signals by the combination of impedance elements is explained in the same manner as in the second and sixth embodiments.

  Further, since the basic configuration of the transistor portion of the mixer circuit 1000 is the same as that of the second embodiment, it can be operated with low power and low voltage.

  As described above, according to the mixer circuit of the present embodiment, it is possible to operate at a low voltage and to reduce power as in the second and sixth embodiments.

  In the ninth and tenth embodiments, an example of a more generalized mixer circuit configuration has been described.

  For example, a resistive load was used for the first and second resistance circuits of the mixer circuits shown in the ninth and tenth embodiments. However, as in the third embodiment, transistors may be used for the first and second resistance circuits.

  Therefore, in this embodiment, a configuration example of a mixer circuit using transistors for the first and second resistor circuits will be described. Here, as an example, an example in which transistors are used for the first and second resistance circuits of the mixer circuit of the first embodiment will be described.

  As in the ninth embodiment, a DC voltage is biased at the gate of each MOS transistor. However, the DC current is not considered here because it is canceled when considering the output characteristics.

  FIG. 11 is a circuit diagram showing the main configuration of a mixer circuit according to Example 11 which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 9 was attached | subjected is a structure similar to Example 9. FIG.

  As shown in FIG. 11, the first resistance circuit and the second resistance circuit of the mixer circuit 1100 are configured by p-type MOS transistors 308 and 309 having control electrodes (gates) connected to a fixed potential Vbias. . These p-type MOS transistors 308 and 309 also function as current sources.

  In the configuration of the mixer circuit 300, assuming that the output impedance of the p-type MOS transistors 308 and 309 is infinite, the first and second output terminals 10 and 11 are current outputs.

  Further, it is possible to obtain a voltage output by arranging a current / voltage conversion circuit in the subsequent stage of the mixer circuit 1100.

  The mixer circuit 1100 having the above configuration outputs an output voltage according to the first to fourth input signals, as in the ninth embodiment.

  Similarly to the ninth embodiment, the mixer circuit 1100 realizes addition of analog signals input to the input terminals by coupling impedance elements.

  Therefore, as in the ninth embodiment, the mixer circuit according to the eleventh embodiment does not require an analog signal adding circuit as in the prior art in which power consumption is caused by the DC bias current of the transistor. Therefore, the mixer circuit according to the eleventh embodiment can operate with lower power than the conventional technology described above.

  As described above, the mixer circuit according to the present embodiment can operate at a low voltage and can reduce power.

  In the ninth and tenth embodiments, examples of configurations in which the mixer circuit is more generalized are described.

  In this embodiment, an example of a more generalized configuration of the mixer circuit of the eighth embodiment will be described.

  In the present embodiment, the basic configuration of the transistors of the mixer circuit shown in the eighth embodiment is not changed, and the coupling by the impedance element is formed in the signal input portion. As described above, the impedance element is any one of a capacitor, a resistance element, and an inductor.

  As in the eighth embodiment, a DC voltage is biased at the gate of each MOS transistor.

  FIG. 12 is a circuit diagram showing the main configuration of a mixer circuit according to a twelfth embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 8 was attached | subjected is a structure similar to Example 8. FIG.

  As shown in FIG. 12, in the mixer circuit 1200, the first capacitor 13 of the mixer circuit 800 shown in the eighth embodiment is replaced with the first impedance element 13A. Similarly, the second capacitor 14 of the mixer circuit 800 is replaced with the second impedance element 14A. Similarly, the third capacitor 16 of the mixer circuit 800 is replaced with a third impedance element 16A. Similarly, the fourth capacitor 17 of the mixer circuit 800 is replaced with a fourth impedance element 17A.

  Similarly, the fifth capacitor 19 of the mixer circuit 800 is replaced with a fifth impedance element 19A. Similarly, the sixth capacitor 20 of the mixer circuit 800 is replaced with a sixth impedance element 20A. Similarly, the seventh capacitor 22 of the mixer circuit 800 is replaced with a seventh impedance element 22A. Similarly, the eighth capacitor 23 of the mixer circuit 800 is replaced with an eighth impedance element 23A.

  Similarly, the ninth capacitor 413 of the mixer circuit 800 is replaced with a ninth impedance element 413A. Similarly, the tenth capacitor 414 of the mixer circuit 800 is replaced with a tenth impedance element 414A. Similarly, the eleventh capacitor 416 of the mixer circuit 800 is replaced with an eleventh impedance element 416A. Similarly, the twelfth capacitor 417 of the mixer circuit 800 is replaced with a twelfth impedance element 417A.

  Similarly, the thirteenth capacitor 419 of the mixer circuit 800 is replaced with a thirteenth impedance element 419A. Similarly, the fourteenth capacitor 420 of the mixer circuit 800 is replaced with a fourteenth impedance element 420A. Similarly, the fifteenth capacitor 422 of the mixer circuit 800 is replaced with a fifteenth impedance element 422A. Similarly, the sixteenth capacitor 423 of the mixer circuit 800 is replaced with a sixteenth impedance element 423A.

  The first, third, fifth, seventh, ninth, eleventh, thirteenth, fifteenth, and seventeenth impedance elements 13A, 16A, 19A, 22A, 413A, 416A, 419A, and 422A have impedance Z1. Have

  The second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth impedance elements 14A, 17A, 20A, 23A, 414A, 417A, 420A, and 423A have an impedance Z2.

  The other configuration of the mixer circuit 1200 is the same as that of the mixer circuit 800 shown in the eighth embodiment.

  The operation of the mixer circuit 1200 having the above configuration is the same as that of the mixer circuit 800 shown in the eighth embodiment. Therefore, the mixer circuit 1200 outputs an output voltage according to the first to fourth input signals.

  Here, as described above, the mixer circuit 1000 realizes addition of analog signals input to the input terminals by coupling impedance elements. The principle of addition of analog signals by the combination of impedance elements is explained in the same manner as in the second and sixth embodiments.

  Further, since the basic configuration of the transistor portion of the mixer circuit 1000 is the same as that of the second embodiment, it can be operated with low power and low voltage.

  As described above, according to the mixer circuit of the present embodiment, it is possible to operate at a low voltage and to reduce power as in the second and sixth embodiments.

  In the twelfth embodiment, an example of a more generalized configuration of the mixer circuit of the eighth embodiment has been described.

  In the present embodiment, an example of a configuration for further stabilizing the common mode voltage of the output terminal of the mixer circuit of the twelfth embodiment will be described.

  FIG. 13 is a circuit diagram showing the main configuration of a mixer circuit according to a thirteenth embodiment which is an aspect of the present invention. In addition, the structure to which the code | symbol similar to Example 12 was attached | subjected is a structure similar to Example 12. FIG.

  As shown in FIG. 13, the mixer circuit 1300 has a first bias resistor element 130, a second bias resistor element 131, and a third bias resistor, as compared with the mixer circuit 1200 of the twelfth embodiment. Element 132, fourth bias resistor element 133, fifth bias resistor element 134, sixth bias resistor element 135, seventh bias resistor element 136, and eighth bias resistor The device further includes an element 137, a ninth biasing resistance element 138, and a tenth biasing resistance element 139.

  One end of the first bias resistance element 130 is connected to the first output terminal 10.

  The second biasing resistance element 131 has one end connected to the second output terminal 11 and the other end connected to the other end of the first biasing resistance element 130.

  The third bias resistance element 132 includes a contact 140 between the other end of the first bias resistance element 130 and the other end of the second bias resistance element 131, and a control electrode of the first transistor 12. , Connected between.

  The fourth bias resistance element 133 is connected between the contact 140 and the control electrode of the second transistor 15.

  The fifth bias resistance element 134 is connected between the contact 140 and the control electrode of the third transistor 18.

  The sixth bias resistance element 135 is connected between the contact 140 and the control electrode of the fourth transistor 21.

  The seventh bias resistance element 136 is connected between the contact 140 and the control electrode of the fifth transistor 412.

  The eighth bias resistance element 137 is connected between the contact point 140 and the control electrode of the sixth transistor 415.

  The ninth bias resistance element 138 is connected between the contact 140 and the control electrode of the seventh transistor 418.

  The tenth bias resistance element 139 is connected between the contact 140 and the control electrode of the eighth transistor 421.

  As described above, the first to eighth transistors 12, 15, 18, 21, 412, 415, 418, 421 are diode-connected in terms of DC. As a result, the common mode voltage of the first and second output terminals 10 and 11 is stabilized at a certain potential divided between the power supply potential Vdd and the ground potential by these diode-connected transistors.

  The first and second bias resistance elements 130 and 131 have a resistance value R3, for example. Further, the third to tenth bias resistance elements 132 to 139 have, for example, a resistance value R2. The first to tenth bias resistance elements 130 are set according to the set value of the common mode voltage of the first and second output terminals 10 and 11.

  Here, each transistor of the mixer circuit 1300 needs to operate in a saturation region. Since each transistor is diode-connected in terms of DC, each transistor is DC-biased so as to operate in the saturation region.

  Further, there is no need for a common mode feedback circuit that must consider the stability of the output voltage.

  The mixer circuit 1300 having the above configuration outputs an output voltage in accordance with the first to fourth input signals, as in the twelfth embodiment.

  Also, the mixer circuit 1300 realizes addition of analog signals input to the respective input terminals by coupling of impedance elements, as in the twelfth embodiment.

  Therefore, the mixer circuit according to the thirteenth embodiment does not require an analog signal adding circuit as in the prior art in which power consumption is caused by the DC bias current of the transistor, as in the twelfth embodiment. Therefore, the mixer circuit according to the thirteenth embodiment can be operated with lower power than the conventional technology described above.

  As described above, the mixer circuit according to the present embodiment can operate at a low voltage and can reduce power.

  In the fourteenth embodiment, an example of a wireless communication terminal to which the mixer circuit described in the above-described embodiments is applied will be described. In addition, although the case where the mixer circuit 100 of Example 1 is applied to a radio | wireless communication terminal is demonstrated here, it applies similarly also to the mixer circuit of another Example.

  FIG. 14 is a diagram illustrating a configuration of a main part of a wireless communication terminal 2000 to which the mixer circuit of the present invention is applied.

  As shown in FIG. 14, the wireless communication terminal 2000 includes a wireless transceiver 2001. The wireless communication terminal 2000 is, for example, a mobile phone or a PDA (Personal Data Assistant).

  The wireless transceiver 2001 receives a signal by the receiving antenna 2004, processes the signal, and outputs the signal to an internal circuit (not shown). The wireless transceiver 2001 processes the signal output from the internal circuit and transmits the signal from the transmission antenna 2002. The mixer circuit 100 provided in the wireless transceiver 2001 is used to mix signals when processing the above signals.

FIG. 3 is a circuit diagram illustrating a main configuration of a mixer circuit according to a first embodiment which is an aspect of the present invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 2 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 3 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 4 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 5 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 6 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 7 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 8 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 9 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 10 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 11 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 12 which is 1 aspect of this invention. It is a circuit diagram which shows the principal part structure of the mixer circuit which concerns on Example 13 which is 1 aspect of this invention. It is a figure which shows the structure of the principal part of the radio | wireless communication terminal 2000 with which the mixer circuit of this invention is applied.

Explanation of symbols

1, 201 1st input terminal 2, 202 2nd input terminal 3, 203 3rd input terminal 4, 204 4th input terminal 5, 205 5th input terminal 6, 206 6th input terminal 7, 207 Seventh input terminal 8, 208 First resistor circuit 9, 209 Second resistor circuit 10, 210 First output terminal 11, 211 Second output terminal 12, 212 First transistor 13, 213 First Capacitors 13A, 213A first impedance elements 14, 214 second capacitors 14A, 214A second impedance elements 15, 215 second transistors 16, 216 third capacitors 16A, 216A third impedance elements 17, 217 Fourth capacitor 17A, 217A Fourth impedance element 18, 218 Third transistor 19, 219 Fifth capacitor Densers 19A, 219A Fifth impedance elements 20, 220 Sixth capacitors 20A, 220A Sixth impedance elements 21, 221 Fourth transistors 22, 222 Seventh capacitors 22A, 222A Seventh impedance elements 23, 223 8 capacitors 23A, 223A 8th impedance element 24, 224 Current source 308, 309 p-type MOS transistor 401 8th input terminal 402 9th input terminal 403 10th input terminal 404 11th input terminal 405 12th Input terminal 406 13th input terminal 407 14th input terminal 412 5th transistor 413 9th capacitor 413A 9th impedance element 414 10th capacitor 414A 10th impedance element 415 6th transistor 416 11th capacitor 416A 11th impedance element 417 12th capacitor 417A 12th impedance element 418 7th transistor 419 13th capacitor 419A 13th impedance element 420 14th capacitor 420A 14th impedance element 421 1st Eight transistors 422 Fifteenth capacitor 422A Fifteenth impedance element 423 Sixteenth capacitor 423A Sixteenth impedance elements 513, 613, 713, 813a First resistance elements 516, 616, 716, 816a Second resistance element 519 , 619, 719, 819a Third resistance element 522, 622, 722, 822a Fourth resistance element 813b Fifth resistance element 816b Sixth resistance element 819b Seventh resistance element 822b Resistive element 100,200,300,400,500,600,700,800,900,1000,1100,1200,1300 mixer circuit
2000 wireless communication terminal 2001 wireless transceiver 2002 transmitting antenna 2004 receiving antenna

Claims (5)

A first input terminal to which a first voltage signal is input;
A second input terminal to which a second voltage signal is input;
A third input terminal to which a third voltage signal equivalent to a signal obtained by inverting the first voltage signal is input;
A fourth input terminal to which a fourth voltage signal equivalent to a signal obtained by inverting the second voltage signal is input;
A fifth input terminal to which the first voltage signal is input;
A sixth input terminal to which the fourth voltage signal is input;
A seventh input terminal to which the second voltage signal is input;
A first resistance circuit having one end connected to the first potential;
A first output terminal connected to the other end of the first resistance circuit;
A first transistor connected between the other end of the first resistance circuit and a second potential;
A first impedance element connected between the first input terminal and a control electrode of the first transistor;
A second impedance element connected between the second input terminal and a control electrode of the first transistor;
A second transistor connected in parallel with the first transistor and having the same conductivity type as the first transistor between the other end of the first resistor circuit and the second potential;
A third impedance element connected between the third input terminal and a control electrode of the second transistor;
A fourth impedance element connected between the fourth input terminal and a control electrode of the second transistor;
A second resistance circuit having one end connected to the first potential;
A second output terminal connected to the other end of the second resistance circuit;
A third transistor connected between the other end of the second resistor circuit and a second potential and having the same conductivity type as the first transistor;
A fifth impedance element connected between the fifth input terminal and a control electrode of the third transistor;
A sixth impedance element connected between the sixth input terminal and a control electrode of the third transistor;
A fourth transistor connected in parallel with the third transistor and having the same conductivity type as the first transistor between the other end of the second resistor circuit and the second potential;
A seventh impedance element connected between the third input terminal and a control electrode of the fourth transistor;
A mixer circuit, comprising: an eighth impedance element connected between the seventh input terminal and a control electrode of the fourth transistor. A first input terminal to which a first voltage signal is input;
A second input terminal to which a second voltage signal is input;
A third input terminal to which a third voltage signal equivalent to a signal obtained by inverting the first voltage signal is input;
A fourth input terminal to which a fourth voltage signal equivalent to a signal obtained by inverting the second voltage signal is input;
A fifth input terminal to which the first voltage signal is input;
A sixth input terminal to which the fourth voltage signal is input;
A seventh input terminal to which the second voltage signal is input;
An eighth input terminal to which the third voltage signal is input;
A ninth input terminal to which the second voltage signal is input;
A tenth input terminal to which the first voltage signal is input;
An eleventh input terminal to which the fourth voltage signal is input;
A twelfth input terminal to which the third voltage signal is input;
A thirteenth input terminal to which the fourth voltage signal is input;
A fourteenth input terminal to which the second voltage signal is input;
A first transistor of a first conductivity type, one end of which is connected to a first potential;
A first output terminal connected to the other end of the first transistor;
A first impedance element connected between the first input terminal and a control electrode of the first transistor;
A second impedance element connected between the second input terminal and a control electrode of the first transistor;
A second transistor connected in parallel with the first transistor between the first output terminal and the first potential and having the same conductivity type as the first transistor;
A third impedance element connected between the third input terminal and a control electrode of the second transistor;
A fourth impedance element connected between the fourth input terminal and a control electrode of the second transistor;
A third transistor having one end connected to the first potential;
A second output terminal connected to the other end of the third transistor;
A fifth impedance element connected between the fifth input terminal and a control electrode of the third transistor;
A sixth impedance element connected between the sixth input terminal and a control electrode of the third transistor;
A fourth transistor connected in parallel with the third transistor between the second output terminal and the first potential and having the same conductivity type as the first transistor;
A seventh impedance element connected between the third input terminal and a control electrode of the fourth transistor;
An eighth impedance element connected between the seventh input terminal and a control electrode of the fourth transistor;
A fifth transistor of a second conductivity type different from the first conductivity type connected between the first output terminal and a second potential;
A ninth impedance element connected between the eighth input terminal and the control electrode of the fifth transistor;
A tenth impedance element connected between the ninth input terminal and a control electrode of the fifth transistor;
A sixth transistor connected in parallel with the fifth transistor and having the same conductivity type as the fifth transistor between the first output terminal and the second potential;
An eleventh impedance element connected between the tenth input terminal and a control electrode of the sixth transistor;
A twelfth impedance element connected between the eleventh input terminal and a control electrode of the sixth transistor;
A seventh transistor connected between the second output terminal and a second potential and having the same conductivity type as the fifth transistor;
A thirteenth impedance element connected between the twelfth input terminal and a control electrode of the seventh transistor;
A fourteenth impedance element connected between the thirteenth input terminal and a control electrode of the seventh transistor;
An eighth transistor connected in parallel with the seventh transistor between the second output terminal and the second potential and having the same conductivity type as the fifth transistor;
A fifteenth impedance element connected between the tenth input terminal and the control electrode of the eighth transistor;
A mixer circuit comprising: a fourteenth impedance element connected between the fourteenth input terminal and a control electrode of the eighth transistor. The mixer circuit according to claim 1, wherein the first impedance element to the eighth impedance element are capacitors. The first, third, fifth, and seventh impedance elements are resistance elements,
The mixer circuit according to claim 2, wherein the second, fourth, sixth, and eighth impedance elements are capacitors. The mixer circuit according to claim 2, wherein the first impedance element to the sixteenth impedance element are capacitors.

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