JP4798843B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a system LSI incorporating a dynamic random access memory (DRAM).
[0002]
[Prior art]
In recent years, a DRAM-embedded system LSI in which logic such as a processor or ASIC (application specific IC) and a DRAM having a large storage capacity are integrated on the same semiconductor substrate has been used.
[0003]
In such a system LSI, a general-purpose DRAM and a logic LSI with a small number of terminals are connected on a printed circuit board by interconnecting logic and DRAM with a multi-bit internal data bus of 128 bits to 512 bits. Compared with the case of using the data, it is possible to realize high-speed data transfer of 1 to 2 digits or more.
[0004]
Further, the number of external pin terminals of the logic can be reduced as compared with a method in which a general-purpose DRAM is externally attached to the logic.
[0005]
Further, in the system LSI, the DRAM block and the logic are connected by internal wiring. Since the length of the internal wiring is sufficiently shorter than the wiring on the printed circuit board and the parasitic impedance is small, the charge / discharge current of the data bus can be greatly reduced and signal transfer can be performed at high speed.
[0006]
For these reasons, DRAM-embedded system LSIs have greatly contributed to improving the performance of information devices that handle large amounts of data such as three-dimensional graphic processing and image / audio processing.
[0007]
When developing such a DRAM-embedded system LSI, the DRAM block is supplied as a DRAM core having a predetermined storage capacity. A system LSI is developed by arranging and wiring the DRAM core in combination with other logic circuits, test circuits, and analog circuits.
[0008]
The DRAM core includes a memory array including memory cells arranged in a matrix, and a control unit that generates a control signal for data transmission and reception based on a signal supplied from a logic circuit or the like and supplies the control signal to the memory array. It is out.
[0009]
The control unit includes a command generation system, a row control system, and a column control system.
[0010]
FIG. 23 is a block diagram showing the configuration of the control unit 500 of the DRAM core command generation system and row control system.
[0011]
Referring to FIG. 23, control unit 500 transmits clock signal ext. In response to CLK and clock enable signal CKE, internal clock signal int. A clock control circuit 522 for generating CLK, and row-related timing signals RXT <3: 0> and SO <3: 0 corresponding to each bank in response to command signals ACT_CMD and PRE_CMD and a bank selection signal BS <3: 0>. >, RXLATCH <3: 0>, and a predecode signal X0 <19: output to each bank in response to the address signal A <12: 0> and the signal RXLATCH <3: 0>. And a row address processing circuit 526 that outputs 0> to X3 <19: 0>. The case where the number of banks is 4 is shown as an example.
[0012]
The clock control circuit 522 receives the clock signal ext. In response to the clock enable signal CKE supplied from the logic circuit or the like. The clock signal int. An internal clock generation circuit 530 that outputs CLK is included.
[0013]
The timing signal generation circuit 524 outputs the bank command signals ACT <3: 0> and PRE <3: 0> for each bank according to the bank selection signals BS <3: 0> based on the command signals ACT_CMD and PRE_CMD. In response to generation circuit 534, command signals ACT <3: 0>, PRE <3: 0>, main word line row control timing signal RXT <3: 0>, sense amplifier activation signals SO <3: 0> and A row related control timing circuit 536 that outputs signals RXLATCH <3: 0> activated during the row active period of the selected bank is included. Each bit of the signals RXT <3: 0>, SO <3: 0> and RXLATCH <3: 0> corresponds to each bank.
[0014]
The row address processing circuit 526 latches the address signal A <12: 0> according to the signal RXLATCH <3: 0>, and row address signals RAF0 <12: 0> to RAF3 <12: 0> corresponding to each bank. And a row address predecode that outputs predecode signals X0 <19: 0> to X3 <19: 0> corresponding to each bank in accordance with the output of the row address input latch circuit 540. Circuit 542.
[0015]
The DRAM core consumes a large amount of current because an internal clock signal is generated even during the standby period. Therefore, the DRAM core mounted on the system LSI also has a clock suspend function as in the case of a synchronous dynamic random access memory (SDRAM) used as an external component such as a CPU.
[0016]
FIG. 24 is a circuit diagram showing a configuration of internal clock generation circuit 530 in FIG.
[0017]
Referring to FIG. 24, internal clock generation circuit 530 receives external clock signal ext. CKE control circuit 552 that takes in clock enable signal CKE in response to CLK and outputs clock control signal CKEd_P; and external clock signal ext. In response to clock control signal CKEd_P. The internal clock signal int. And a gate circuit 554 for outputting CLK.
[0018]
The CKE control circuit 552 receives the external clock signal ext. Inverter 556 that receives and inverts CLK, and external clock signal ext. A flip-flop 558 that takes in the clock enable signal CKE according to CLK, a buffer circuit 560 that buffers the output of the flip-flop 558, and a flip-flop 562 that takes in the output of the buffer circuit 560 according to the output of the inverter 556. Including.
[0019]
Gate circuit 554 provides external clock signal ext. The NAND circuit 564 that receives CLK and the clock control signal CKEd_P, receives and inverts the output of the NAND circuit 564, and inverts the internal clock signal int. And an inverter 566 that outputs CLK.
[0020]
FIG. 25 is an operation waveform diagram illustrating the clock suspend function.
24 and 25, when clock enable signal CKE falls to L level at time t1, CKE control circuit 552 causes next external clock signal ext. The clock control signal CKEd_P is lowered to L level from the falling edge of CLK. Accordingly, the external clock signal ext. Since CLK is masked by NAND circuit 564, internal clock signal int. CLK is fixed at the L level, and the DRAM core is set to the power down mode.
[0021]
Subsequently, when the clock enable signal CKE rises from the L level to the H level at time t3, the internal clock signal int. The supply of CLK is resumed for each bank.
[0022]
That is, by inactivating the clock enable signal CKE, the internal clock signal int. CLK stops and enters power down mode. When the power down mode period is long, self-refreshing of data in the memory cells of each bank is performed according to a self-refresh circuit that operates asynchronously (not shown), and the data is held.
[0023]
Then, when the clock enable signal CKE is activated, the internal clock signal int. The generation of CLK resumes.
[0024]
[Problems to be solved by the invention]
In the configuration of the conventional internal clock generation circuit, when the clock enable signal CKE is activated to H level, the internal clock signal is always generated in response to the external clock signal. In particular, in a multi-bank configuration, a row local control circuit is provided for each bank, and a local clock signal for controlling an address latch circuit in each row local control circuit is generated according to an internal clock signal. The current consumption accompanying the generation of the internal clock signal increases. Therefore, there is a problem that the current consumption during standby cannot be easily reduced even if the frequency of the operation clock is lowered during standby for reducing power consumption. The present invention has been made in view of the above problems, and an object of the present invention is to provide a system LSI equipped with a DRAM capable of reducing current consumption during standby.
[0025]
[Means for Solving the Problems]
  According to this inventionA semiconductor device includes a plurality of memory cells arranged in rows and columns, a memory array that transmits and receives data in accordance with an address signal in synchronization with an internal clock signal, and a basic clock signal in the memory array in accordance with a command. A row activation command for instructing the start of a row selection operation of a plurality of memory cells for data exchange with the memory array.A precharge command that deactivates the activated row in response to the row activation command;And the clock processing circuit outputs an internal clock signal based on the basic clock signal in response to the activation of the internal clock enable signal and an internal clock control circuit that activates the internal clock enable signal in response to the row activation command. And an internal clock generation circuit that deactivates the internal clock signal in response to the deactivation of the internal clock enable signal.The internal clock control circuit activates the internal clock enable signal in response to the external clock enable signal and deactivates the internal clock enable signal in response to the inactivation of the external clock enable signal in the high-speed operation mode (A) (B) In the low-speed operation mode, the internal clock enable signal is activated according to the row activation command after the external clock enable signal is activated, and the internal clock enable signal is deactivated according to the precharge command.
[0026]
  InsideThe internal clock control circuit includes an internal circuit that activates an internal control signal in response to a row activation command and a given clock enable signal;High speed operationIn modeOutsideSelect the clock enable signal,Low speed operationAnd a selection circuit for selecting an internal control signal in the mode and outputting it as an internal clock enable signal.
[0027]
  InsideThe partial circuitLow speed operationIn the mode, the internal control signal is deactivated in response to the precharge command.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.
[0037]
[Embodiment 1]
FIG. 1 is a diagram schematically showing the configuration of a DRAM built-in system LSI according to the present invention.
[0038]
Referring to FIG. 1, a system LSI 1 is coupled to an external pin terminal group LPGA, coupled to a large-scale logic LG that executes a commanded process, and between the large-scale logic LG and the external pin terminal group APG. An analog core ACR that performs processing on an analog signal, a DRAM core MCR that is coupled to the large-scale logic LG via an internal wiring and stores data required by the large-scale logic LG, and a large-scale logic LG in the test mode And a test interface circuit TIC for performing a test operation on DRAM core MCR via test pin terminal group TPG. DRAM core MCR receives power supply voltage VCC via power supply pin terminal PST.
[0039]
The analog core ACR is a phase-locked loop (PLL) that generates an internal clock signal, an analog / digital converter that converts an external analog signal into a digital signal, and a digital signal supplied from a large-scale logic LG into an analog signal. Includes a digital / analog converter for conversion and output.
[0040]
FIG. 2 is a schematic block diagram showing the configuration of DRAM core MCR in FIG.
[0041]
Referring to FIG. 2, DRAM core MCR is arranged outside a plurality of memory arrays MA0-MAn, sense amplifier bands SB1-SBn arranged between memory arrays MA0-MAn, and memory arrays MA0 and MAn. Sense amplifier bands SB0 and SBn + 1. Each of memory arrays MA0-MAn is divided into a plurality of memory sub-arrays MSA by sub-word driver band SWDB.
[0042]
In each of memory arrays MA0-MAn, main word line MWL is arranged in common to memory sub-array MSA divided by sub-word driver band SWDB. Main word line MWL is arranged corresponding to a predetermined number of sub word lines of each memory sub array MSA of the corresponding memory array. A selection signal is input to the sub word driver in the sub word driver band SWDB via the main word line MWL and a predetermined number of sub decode lines SDL arranged on the sense amplifier band, and one sub word line is selected.
[0043]
Each of sense amplifier bands SB1 to SBn is shared by adjacent memory arrays. A row decoder for selecting a main word line and a subdecode line in accordance with a row address signal is arranged corresponding to memory arrays MA0-MAn, and a column for selecting a column from the memory array in alignment with the row decoder according to a column address signal. A column decoder for transmitting a selection signal onto column selection line CSL is arranged.
[0044]
Column selection line CSL is arranged in the sense amplifier band, and connects a predetermined number of sense amplifier circuits to a group of internal data line pairs GIOP when selected. A predetermined number of internal data line pairs GIOP are provided extending over memory arrays MA0 to MAn, and are coupled to a selected sense amplifier circuit via a local data line.
[0045]
Internal data line pair GIOP is provided from 128 bits to 512 bits, and is coupled to a data path band DPB including a preamplifier and a write driver. In this data path band DPB, a preamplifier and a write driver are arranged corresponding to each internal data line pair GIOP. Internal data line pair GIOP may be a transmission line pair for transmitting both write data and read data, and a bus line pair for transmitting read data and a write data line pair for transmitting write data are separately provided. It may be provided as an internal data bus line pair.
[0046]
The DRAM core MCR further receives, for example, 13-bit external addresses A0 to A12 given from the logic, and receives control signals CLK, CKE, ACT_CMD, PRE_CMD, REFA_CMD and other control signals given from the logic to generate internal commands. Control signal processing circuit 10 for performing row address processing, column address input circuit CAK receiving, for example, 13-bit external addresses A0 to A12 given from logic, and data transfer between data path band DPB and logic Includes a data input / output control circuit DIOK.
[0047]
The control signal processing circuit 10 receives a control signal CLK, CKE, ACT_CMD, PRE_CMD, REFA_CMD, and other control signals given from the logic, and generates an internal control signal designating various operations from the logic. For example, a 13-bit external address A0 to A12 to be applied is latched as a row address, and at the time of refresh, a row address input circuit / refresh counter RAFK that internally generates a row address and predecode a row address by predecoding And a row predecoder RPD for outputting to the memory array.
[0048]
The command decoder / control circuit CDC receives the clock signal CLK, the clock enable signal CKE, and the command signals ACT_CMD, PRE_CMD, REFA_CMD, and determines the designated operation mode.
[0049]
The command includes a row active command for setting a row to a selected state, a read command for instructing data reading, a write command for instructing data writing, a precharge command for placing a selected row in a non-selected state, and a refresh operation An auto refresh command for performing self-refresh, a self-refresh command for performing self-refresh, and the like are included.
[0050]
When a row active command is applied, the row address input circuit / refresh counter RAFK takes in as external address bits A0 to A12 and a row address under the control of the command decoder / control circuit CDC, and generates an internal row address signal.
[0051]
The row address input circuit / refresh counter RAFK includes an address buffer for buffering a given address bit and an address latch for latching an output signal of the buffer circuit.
[0052]
A refresh counter included in the row address input circuit / refresh counter RAFK generates a refresh address for designating a refresh row when an auto-refresh command or a self-refresh command is given. After the refresh operation is completed, the count value of the refresh counter is increased or decreased.
[0053]
When a read command or a write command is applied, column address input circuit CAK takes in address bits A0 to A4 which are lower parts of the applied address bits, for example, under the control of command decoder / control circuit CDC. An internal column address signal is generated. Column address input circuit CAK also includes an address buffer and an address latch.
[0054]
An internal row address signal from row address input circuit / refresh counter RAFK is applied to row predecoder RPD, and an internal column address signal from column address input circuit CAK is applied to column predecoder CPD.
[0055]
Row predecoder RPD predecodes the applied internal row address signal and applies the predecode signal to a row decoder included in row / column decoder band RCDB. Column predecoder CPD predecodes the internal column address signal from column address input circuit CAK, and applies the predecode signal to the column decoder included in row / column decoder band RCDB.
[0056]
When command decoder / control circuit CDC receives the command signal, it generates an internal control signal for controlling operations of preamplifier and write driver included in data input / output control circuit DIOK and data path band DPB. Depending on the operation mode, control signals ACTOR, SELF_REF, and the like are output to a block PHK described later. The clock signal CLK is used as a reference signal for determining the internal operation timing of the DRAM core MCR.
[0057]
Data input / output control circuit DIOK inputs / outputs data in synchronization with clock signal CLK, and row address input circuit / column address input circuit CAK of row address input circuit / refresh counter RAFK synchronizes with clock signal CLK. Then, the given address bit is fetched and latched.
[0058]
DRAM core MCR further receives an internal voltage generation circuit for generating internal voltages VPP, VCCS, VCCP, VBL, and VCP, and a self-refresh command SELF_REF from the command decoder / control circuit CDC when the self-refresh mode is designated, that is, A block PHK including a self-refresh timer that activates the refresh request signal FAY at a predetermined interval.
[0059]
Internal voltage VPP is a voltage transmitted onto selected sub word line SWL, and is usually at a voltage level higher than the operating power supply voltage. Voltage VCCS is an operating power supply voltage of the sense amplifier circuit included in sense amplifier bands SB0 to SBn + 1, and is generated by an internal voltage down converter (not shown). Voltage VCCP is a peripheral power supply voltage, and is an operation power supply voltage applied to peripheral circuits such as a row decoder and a column decoder included in row / column decoder band RCDB, and a preamplifier and a write driver included in data path band DPB. It is generated by an internal voltage down converter not shown. The voltage VBL is a bit line precharge voltage. Voltage VCP is a cell plate voltage applied to the cell plate of the memory cell, and is an intermediate level between the H level voltage and the L level voltage of the memory cell data. These voltages VBL and VCP are usually intermediate voltages which are ½ of array power supply voltage (sense power supply voltage) VCCS.
[0060]
When a self-refresh command or an auto-refresh command is issued, the refresh counter operates and a row address to be refreshed is internally generated. In particular, when the self-refresh mode is entered, the self-refresh timer operates, and the refresh request signal FAY is automatically generated so that all rows are refreshed at the maximum refresh time tREFmax.
[0061]
FIG. 3 is a block diagram showing the configuration of the clock control system and row control unit 20 in the control signal processing circuit 10 of FIG.
[0062]
In FIG. 3, for the sake of simplicity, circuit blocks related to refresh control are not shown. Referring to FIG. 3, control unit 20 generates clock signal ext. CLK and a clock enable signal CKE and a command signal ACT_CMD, PRE_CMD, REFA_CMD given from a logic unit or the like, and an internal clock signal int. In response to the clock control circuit 22 for generating CLK, the command signals ACT_CMD and PRE_CMD, and the bank selection signal BA <3: 0>, row-related timing signals RXT <3: 0> and SO <3: 0 corresponding to the respective banks. >, RXLATCH <3: 0>, and a predecode signal X0 <19: output to each bank in response to the address signal A <12: 0> and the signal RXLATCH <3: 0>. And a row address processing circuit 26 that outputs 0> to X3 <19: 0>. The case where the number of banks is 4 is shown as an example.
[0063]
The clock control circuit 22 receives the clock enable signal CKE and the command signals ACT_CMD, PRE_CMD, REFA_CMD from the logic unit or the like and receives the internal clock enable signal int. Internal clock control circuit 28 for outputting CKE and a clock signal ext. CLK is changed to internal clock enable signal int. The clock signal int. And an internal clock generation circuit 30 that outputs as CLK.
[0064]
The timing signal generation circuit 24 sends the command signal ACT_CMD to the clock signal ext. A delay circuit 32 that delays in synchronization with CLK, a command signal PRE_CMD, and a command signal ACT <3: for each bank according to a bank selection signal BA <3: 0> based on the command signal ACT_CMD delayed by the delay circuit 32. 0>, PRE <3: 0> for outputting the bank command generation circuit 34, and the row control timing signal for the main word line corresponding to each bank in response to the command signals ACT <3: 0>, PRE <3: 0>. It includes a row related control timing circuit 36 that outputs RXT <3: 0>, sense amplifier activation signals SO <3: 0> and signals RXLATCH <3: 0> activated during the row active period of the selected bank.
[0065]
The row address processing circuit 26 sends the address signal A <12: 0> to ext. The delay circuit 38 that delays in synchronization with CLK, and the lower 9 bits of the address signal A <12: 0> delayed by the delay circuit 38 are latched according to the signal RXLATCH <3: 0>, A row address input latch circuit 40 that outputs corresponding row address signals RAF0 <8: 0> to RAF3 <8: 0>, and a predecode signal X0 <corresponding to each bank according to the output of the row address input latch circuit 40. The row address predecode circuit 42 that outputs 19: 0> to X3 <19: 0> and the address signal A <12: 9> in the address signal A <12: 0> delayed by the delay circuit 38 are received. And a block decode circuit 43 for decoding and outputting a block decode signal BS <n: 0>.
[0066]
FIG. 4 is a circuit diagram showing a configuration of row address input latch circuit 40 in FIG.
[0067]
Referring to FIG. 4, row address input latch circuit 40 has a flip-flop 54 that holds address signal A <8: 0> according to clock signal CLK, and an output of flip-flop 54 according to signal RXLATCH <0>. Level latch circuit 56 for taking in and holding, level latch circuit 58 for taking in and holding the output of flip-flop 54 in accordance with signal RXLATCH <1>, and the output in flip-flop 54 in accordance with signal RXLATCH <2> A level latch circuit 60 and a level latch circuit 62 that captures and holds the output of the flip-flop 54 in accordance with the signal RXLATCH <3> are included.
[0068]
The row address input latch circuit 40 further includes an inverter 57 that receives the output of the level latch circuit 56, an inverter 59 that receives the output of the level latch circuit 58, an inverter 61 that receives the output of the level latch circuit 60, and a level latch circuit 62. And an inverter 63 that receives the output of.
[0069]
The level latch circuit 56 includes an inverter 64 that receives and inverts the signal RXLATCH <0>, a transmission gate 66 that transmits the output of the inverter 64 and the output of the flip-flop 54 according to the signal RXLATCH <0>, and a transmission gate 66. An inverter 70 that receives and inverts the output of the transferred flip-flop 54 and an inverter 68 that receives and inverts the output of the inverter 70 and feeds back to the input of the inverter 70 are included. From the output of the inverter 57, a row address signal RAF0 <8: 0> corresponding to the bank 0 is output.
[0070]
Level latch circuit 58 includes inverter 74 that receives and inverts signal RXLATCH <1>, transmission gate 76 that transmits the output of inverter 74 and the output of flip-flop 54 in response to signal RXLATCH <1>, and transmission gate 76. An inverter 80 that receives and inverts the output of the transferred flip-flop 54 and an inverter 78 that receives and inverts the output of the inverter 80 and feeds back to the input of the inverter 80 are included. A row address signal RAF1 <8: 0> corresponding to the bank 1 is output from the output of the inverter 59.
[0071]
The level latch circuit 60 includes an inverter 84 that receives and inverts the signal RXLATCH <2>, a transmission gate 86 that transmits the output of the inverter 84 and the output of the flip-flop 54 according to the signal RXLATCH <2>, and a transmission gate 86. An inverter 90 that receives and inverts the output of the transmitted flip-flop 54 and an inverter 88 that receives and inverts the output of the inverter 90 and feeds back to the input of the inverter 90 are included. A row address signal RAF2 <8: 0> corresponding to the bank 2 is output from the output of the inverter 61.
[0072]
Level latch circuit 62 includes inverter 94 that receives and inverts signal RXLATCH <3>, transmission gate 96 that transmits the output of inverter 94 and the output of flip-flop 54 in response to signal RXLATCH <3>, and transmission gate 96. It includes an inverter 100 that receives and inverts the output of the transferred flip-flop 54 and an inverter 98 that receives and inverts the output of the inverter 100 and feeds it back to the input of the inverter 100. From the output of the inverter 63, the row address signal RAF3 <8: 0> corresponding to the bank 3 is output.
[0073]
The operation of the row address input latch circuit 40 will be briefly described. The row address fetched at the rising edge of the clock in the flip-flop 54 is sent to the predecode circuit in each bank. In the row-related control timing circuit 36 described later, when the latch signal RXLATCH <i> for the selected bank i (i is an integer of 0 to 3) is activated, the level latch circuits 56 to 62 are activated and the signal RXLATCH is operated. The address is held while <i> is activated.
[0074]
When the predecode signal is generated, corresponding to bank i, row control timing signal RXT for the main word line, subdecode signal, and sense amplifier activation signal SO are sequentially activated. The address signals sequentially taken in at the rising edge of the clock signal by the flip-flop 54 are continuously sent to the predecode circuits in the other non-selected banks.
[0075]
FIG. 5 is a circuit diagram showing the configuration of flip-flop 54 in FIG.
Referring to FIG. 5, flip-flop 54 receives inverter 112 that receives and inverts clock signal CLK and outputs signal / CLK, and input when clock signal CLK is at L level and signal / CLK is at H level. A transmission gate 114 for transmitting the signal IN; an inverter 116 that receives and inverts the input signal IN transmitted by the transmission gate 114; an inverter 118 that receives and inverts the signal of the inverter 116 and feeds back to the input of the inverter 116; Transmission signal 120 for transmitting the output of inverter 116 when clock signal CLK is at H level and signal / CLK is at L level, and the output of inverter 116 transmitted by transmission gate 120 is received and inverted to output output signal OUT To A converter 122, an inverter 124 is fed back to the input of inverter 122 receives and inverts the output of inverter 122.
[0076]
FIG. 6 is a circuit diagram showing a configuration of predecode circuit 42a for the least significant 2 bits of row address predecode circuit 42 in FIG.
[0077]
Referring to FIG. 6, predecode circuit 42a receives and inverts row address signal RAF0 <0> and outputs signal ZRAD <0>, and receives and inverts output of inverter 132 to invert signal RAD <0. >, An inverter 136 that receives and inverts the row address signal RAF0 <1> and outputs a signal ZRAD <1>, and an inverter that receives and inverts the output of the inverter 136 and outputs a signal RAD <1> 138.
[0078]
The predecode circuit 42a further receives the signals ZRAD <1> and ZRAD <0> and outputs a predecode signal X <0>, and receives the signals ZRAD <1> and RAD <0> and precodes them. An AND circuit 142 that outputs a decode signal X <1>, an AND circuit 144 that receives the signals RAD <1> and RAD <0> and outputs a predecode signal X <3>, and signals RAD <1> and ZRAD < AND circuit 146 that receives 0> and outputs predecode signal X <2>.
[0079]
FIG. 7 is a circuit diagram showing a configuration of predecode circuit 42b on the upper side of row address predecode circuit 42 in FIG.
[0080]
Referring to FIG. 7, predecode circuit 42b receives and inverts row address signal RAF0 <8: 2> and outputs signal ZRAD <8: 2>, and receives and inverts the output of inverter 152. And an inverter 154 that outputs a signal RAD <8: 2>.
[0081]
Further, predecode circuit 42b receives signals ZRAD <2> and ZRAD <3> and outputs predecode signal X <4>, and predecode circuit 42b receives signals RAD <2> and ZRAD <3>. An AND circuit 158 that outputs a decode signal X <5>, an AND circuit 160 that receives the signals ZRAD <2> and RAD <3> and outputs a predecode signal X <6>, and signals RAD <2> and RAD < 3> and an AND circuit 162 that outputs a predecode signal X <7>.
[0082]
Predecode circuit 42b further receives AND signals 164 that receive signals ZRAD <4>, ZRAD <5>, and ZRAD <6> and output predecode signal X <8>, and signals RAD <4>, ZRAD <5. > And ZRAD <6> and outputs predecode signal X <9>, and receives signals ZRAD <4>, RAD <5> and ZRAD <6> and outputs predecode signal X <10>. AND circuit 168 for outputting and AND circuit 170 for receiving signals RAD <4>, RAD <5> and ZRAD <6> and outputting predecode signal X <11>.
[0083]
Predecode circuit 42b further receives AND signals 172 that receive signals ZRAD <4>, ZRAD <5>, and RAD <6> and output predecode signal X <12>, and signals RAD <4>, ZRAD <5. > And RAD <6> and outputs predecode signal X <13>, and receives signals ZRAD <4>, RAD <5> and RAD <6> and outputs predecode signal X <14>. AND circuit 176 for outputting and AND circuit 178 for receiving signals RAD <4>, RAD <5> and RAD <6> and outputting predecoded signal X <15>.
[0084]
Predecode circuit 42b receives signals ZRAD <7> and ZRAD <8> and outputs predecode signal X <16>, and predecode circuit 42b receives signals RAD <7> and ZRAD <8>. An AND circuit 182 that outputs a decode signal X <17>, an AND circuit 184 that receives the signals ZRAD <7> and RAD <8> and outputs a predecode signal X <18>, and signals RAD <7> and RAD < 8> and an AND circuit 186 that outputs a predecode signal X <19>.
[0085]
Although not shown, the highest addresses A9 to A12 are separately decoded to generate a bank selection signal BA <3: 0> and a block decode signal BS <n: 0> for selecting the memory arrays 0 to n. Used.
[0086]
FIG. 8 is a circuit diagram showing a configuration of bank command generation circuit 34 in FIG.
[0087]
Referring to FIG. 8, bank command generation circuit 34 receives a signal passed through delay circuit 195 for delaying bank selection signals BA <3: 0> in synchronization with extCLK and command signal ACT_CMD, and executes a command for each bank. An AND circuit 192 that outputs a signal ACT <3: 0>, and an AND circuit 194 that receives the command signal PRE_CMD and the bank selection signal BA <3: 0> and outputs a command signal PRE <3: 0> for each bank. Including.
[0088]
FIG. 9 is a block diagram showing a configuration of row-related control timing circuit 36 in FIG.
[0089]
9, row-related control timing circuit 36 receives command signals ACT <0>, PRE <0> and outputs signals RXLATCH <0>, RXT <0>, SO <0>. A timing circuit 196, a row control timing circuit 198 that receives the command signals ACT <1> and PRE <1> and outputs signals RXLATCH <1>, RXT <1>, SO <1>, and a command signal ACT <3 >, PRE <3> and a row-related control timing circuit 200 that outputs signals RXLATCH <3>, RXT <3>, SO <3>.
[0090]
FIG. 10 is a circuit diagram showing a configuration of row-related control timing circuit 196 in FIG.
[0091]
Referring to FIG. 10, row related control timing circuit 196 receives composite gate 202 receiving signals ACT <i>, RASE <i>, PRE <i>, and outputs the composite gate 202 to row related control clock signal CLKR. And a flip-flop 204 that takes in and outputs a signal RASE <i>. Composite gate 202 calculates the logical sum of signal ACT <i> and signal RASE <i>, and outputs the logical product of the logical sum and the inverted value of signal PRE <i>. The signal RASE <i> is a signal that is at the H level while the corresponding bank is activated.
[0092]
Row-related control timing circuit 196 further receives a delay circuit 206 that receives and delays signal RASE <i>, a NAND circuit 208 that receives signal RASE <i> and the output of delay circuit 206, and an output of NAND circuit 208. A delay circuit 210 that delays the output signal and a NOR circuit 212 that receives the output of the NAND circuit 208 and the output of the delay circuit 210 and outputs a signal RXLATCH <i>.
[0093]
Row-related control timing circuit 196 further receives delay circuit 216 that receives and delays signal RASE <i>, NAND circuit 218 that receives signal RASE <i> and the output of delay circuit 216, and the output of NAND circuit 218. And a delay circuit 220 for delaying the signal and a NOR circuit 222 for receiving the output of the NAND circuit 218 and the output of the delay circuit 220 and outputting the signal RXT <i>.
[0094]
Row-related control timing circuit 196 further receives delay circuit 226 that receives and delays signal RASE <i>, NAND circuit 228 that receives signal RASE <i> and the output of delay circuit 226, and the output of NAND circuit 228. Delay circuit 230 for delaying the output signal, and NOR circuit 232 for receiving the output of NAND circuit 228 and the output of delay circuit 230 and outputting sense amplifier activation signal SO <i>.
[0095]
Each of delay circuits 206, 210, 216, 220, 226 and 230 includes an even number of stages of inverters connected in series. The delay time of each delay circuit is determined by activation of signal RASE <i>. Are set to different times in accordance with the delay time and activation time until the signals RXLATCH <i>, RXT <i>, SO <i> are activated.
[0096]
In FIG. 10, i represents bank numbers 0 to 3, and i represents 0 when representing row-related control timing circuit 196. The configuration of row related control timing circuits 198 to 200 in FIG. 9 is such that i is the number of the corresponding bank in the configuration of row related control timing circuit 196, and description thereof will not be repeated.
[0097]
FIG. 11 is a circuit diagram showing a configuration of internal clock control circuit 28 in FIG.
[0098]
Referring to FIG. 11, internal clock control circuit 28 includes AND circuit 242 that receives command signals ACT_CMD and REFA_CMD, NOR circuit 244 that receives the output of AND circuit 242 at one input, command signal PRE_CMD and NOR circuit 244. It includes a NOR circuit 246 that receives the output, and an AND circuit 248 that receives the output of the NOR circuit 246 and the clock enable signal CKE. The output of the NOR circuit 246 is given to the other input of the NOR circuit 244.
[0099]
The internal clock control circuit 28 further outputs either the clock enable signal CKE or the output of the AND circuit 248 in response to the mode signal MODE. A selection gate 250 for outputting as CKE is included.
[0100]
FIG. 12 is a circuit diagram showing a configuration of internal clock generation circuit 30 in FIG.
[0101]
Referring to FIG. 12, internal clock generation circuit 30 generates external clock signal ext. The clock enable signal int. CKE control circuit 252 that takes in CKE and outputs clock control signal CKEd_P, and external clock signal ext. In response to clock control signal CKEd_P. CLK is changed to the internal clock signal int. And a gate circuit 254 for outputting as CLK.
[0102]
The CKE control circuit 252 receives the external clock signal ext. Inverter 256 that receives and inverts CLK, and external clock signal ext. The clock enable signal int. It includes a flip-flop 258 that captures CKE, a buffer circuit 260 that buffers the output of flip-flop 258, and a flip-flop 262 that captures the output of buffer circuit 260 in accordance with the output of inverter 256.
[0103]
Gate circuit 254 receives external clock signal ext. The NAND circuit 264 that receives CLK and the clock control signal CKEd_P, receives and inverts the output of the NAND circuit 264, and inverts the internal clock signal int. And an inverter 266 that outputs CLK.
[0104]
FIG. 13 is a circuit diagram showing a configuration of delay circuit 32 in FIG.
Referring to FIG. 13, delay circuit 32 converts command signal ACT_CMD into clock signal ext. Flip-flop 274 for capturing according to CLK, buffer circuit 276 for buffering the output of flip-flop 274, and clock signal ext. An inverter 272 that receives and inverts CLK, a flip-flop 278 that takes in the output of the buffer circuit 276 in accordance with the output of the inverter 272, and either the command signal ACT_CMD or the output of the flip-flop 278 in accordance with the mode signal MODE Command signal int. And a selection gate 280 that outputs as ACT_CMD.
[0105]
Note that delay circuit 38 in FIG. 3 has the same configuration as delay circuit 32, and description thereof will not be repeated.
[0106]
Next, the internal clock signal int. The control of CLK will be described.
[0107]
The DRAM core is designed so that a delay time tRCD (Row to Column Delay) from activation of a row to activation of a column is within two clocks when a clock having the maximum operating frequency is input. That is, when the row active command ACT is input, sensing by the sense amplifier for the selected row is completed, and the read command READ can be input at the second clock after the row active command ACT is input. Therefore, if the operating speed of the array is the same, the delay time tRCD can be equivalent to one clock by lowering the frequency of the input clock from the maximum operating frequency.
[0108]
When the system LSI is used in the low power consumption mode by reducing the clock signal applied to the DRAM core to a clock frequency with a delay time tRCD corresponding to one clock, the mode signal MODE in FIG. 11 is activated.
[0109]
When the clock enable signal CKE is active, when the command signal ACT_CMD or REFA_CMD is input to the DRAM core, the internal signal int. CKE is activated in the internal clock control circuit 28. When the command signal PRE_CMD is input from outside the DRAM core, the signal int. CKE is deactivated. However, the signal int. Even when CKE is activated, the internal clock signal int. The timing for generating CLK is delayed in the internal clock generation circuit 30. Therefore, by delaying the command signal and the address signal by the delay circuits 32 and 38 of FIG. Adjustment is performed so that the operation on the memory array is normally performed at CLK.
[0110]
That is, when the mode signal MODE is activated, the internal row active command signal int.1 is delayed by one clock with respect to the command signal ACT_CMD by the delay circuit 32. ACT_CMD is generated. Similarly to the row active command, the address signal A <12: 0> is also delayed by one clock by the delay circuit 38 and input to the row address input latch circuit 40. Therefore, the inside of the memory array of the DRAM core operates with a delay time tRCD corresponding to one clock signal.
[0111]
On the other hand, when the mode signal MODE is inactive, the signal int. The clock enable signal CKE is transmitted as it is as CKE. Therefore, the internal clock generation circuit 30 is controlled by the clock enable signal CKE as in the conventional case.
[0112]
FIG. 14 shows the internal clock signal int. It is an operation | movement waveform diagram for demonstrating control of CLK.
[0113]
Referring to FIG. 14, first, external clock signal ext. Assume that CLK is input and a clock enable signal CKE supplied from the outside is activated to H level. In this state, the internal clock enable signal int. CKE is inactivated to L level.
[0114]
When command signal ACT_CMD is applied at time t1, internal clock control circuit 28 shown in FIG. CKE is activated.
[0115]
Subsequently, at time t 2, the command signal ACT_CMD is delayed by the delay circuit 32 and transmitted to the bank command generation circuit 34. Further, the CKE control circuit 252 in FIG. CKE is also delayed and a signal CKEd_P is output. Then, in response to the activation of the signal CKEd_P, the external clock signal ext. CLK is the internal clock signal int. It is transmitted to the activated bank as CLK.
[0116]
Subsequently, when the precharge command PRE_CMD is applied at time t3, the internal clock control circuit 28 shown in FIG. CKE is deactivated and this signal is delayed by CKE control circuit 252 in FIG. 12, and signal CKEd_P falls at time t4. After time t4, the internal clock signal int. CLK is deactivated.
[0117]
As described above, according to the first embodiment, when a row active command is input, the clock suspend state is exited and the internal clock signal int. When CLK is generated and a precharge command is input, the state returns to a clock suspend state in which an internal clock is not generated, so that the standby current can be greatly suppressed as compared with the conventional case.
[0118]
[Modification of Embodiment 1]
FIG. 15 is a block diagram showing the configuration of the clock control system and row system control unit 20a and the test interface circuit TIC used in the modification of the first embodiment.
[0119]
Referring to FIG. 15, control unit 20 a includes a clock control circuit 22 a instead of clock control circuit 22 in the configuration of control unit 20 shown in FIG. 3, and a timing signal generation circuit instead of timing signal generation circuit 24. 24a, and a row address processing circuit 26a is included instead of the row address processing circuit 26.
[0120]
The clock control circuit 22a includes an internal clock generation circuit 30, but differs in configuration from the clock control circuit 22 in that the internal clock control circuit 28 is not included. The internal clock control circuit 28 is included in the test interface circuit TIC shown in FIG.
[0121]
The timing signal generation circuit 24a includes a bank command generation circuit 34 and a row-related control timing circuit 36, but differs from the timing signal generation circuit 24 in that the delay circuit 32 is not included. The delay circuit 32 is included in the test interface circuit TIC shown in FIG.
[0122]
The row address processing circuit 26a includes a row address input latch circuit 40 and a row address predecode circuit 42, but differs in configuration from the row address processing circuit 26 in that the delay circuit 38 is not included. The delay circuit 38 is included in the test interface circuit TIC shown in FIG.
[0123]
Although not shown, the test interface circuit TIC includes a signal switching circuit and the like so that a DRAM core test signal can be input from the outside in addition to the internal clock control circuit 28 and the delay circuits 32 and 38.
[0124]
Referring to FIG. 1 again, in the development of the system LSI, a DRAM core MCR, an analog core ACR, a circuit block having a specific function such as a microprocessor (not shown), and a function according to a customer's individual request And a circuit block including a test interface circuit TIC for facilitating the test of these circuit blocks. Circuit blocks having specific functions are registered in a library because they are used for general purposes.
[0125]
Considering that wiring for connecting these circuit blocks to each other is facilitated and the arrangement of the circuit blocks is determined, wiring is performed using a wiring area up to the circuit block. These placement and routing processes are often performed automatically by a computer.
[0126]
With the configuration shown in FIG. 15, the control unit 20a can have the same configuration as the control unit 500 shown in FIG. That is, even if the configuration of the control unit included in the conventional DRAM core is not changed, a latch circuit that shifts the latency of the internal ACT signal and the row address is added to the test interface circuit as in the first embodiment. Effects can be obtained. That is, since it is not necessary to change the DRAM core, it is possible to use a DRAM core of a common library for a system LSI for high-speed operation and a system LSI that requires a power-down function.
[0127]
[Embodiment 2]
FIG. 16 is a block diagram showing a configuration of control unit 300 in the second embodiment.
[0128]
Referring to FIG. 16, control unit 300 includes a clock control circuit 322 instead of clock control circuit 22 in the configuration of control unit 20 shown in FIG. 3, and a timing signal generation circuit instead of timing signal generation circuit 24. 324, and a row address processing circuit 326 is included instead of the row address processing circuit 26.
[0129]
The clock control circuit 322 differs from the clock control circuit 22 in that the clock control circuit 322 includes an internal clock generation circuit 330 instead of the internal clock generation circuit 30 in the configuration of the clock control circuit 22 in FIG.
[0130]
The timing signal generation circuit 324 is different from the configuration of the timing signal generation circuit 24 in that the command signal ACT_CMD is directly supplied to the bank command generation circuit 34 without passing through the delay circuit 32 in the configuration of the timing signal generation circuit 24 shown in FIG. .
[0131]
The row address processing circuit 326 applies the address signal A <12: 0> directly to the row address input latch circuit 40 and the block decoding circuit 43 without passing through the delay circuit 38 in the configuration of the row address processing circuit 26 shown in FIG. This is different from the row address processing circuit 26 in the configuration. Other configurations are similar to those of control unit 20 shown in FIG. 3, and description thereof will not be repeated.
[0132]
FIG. 17 is a circuit diagram showing a configuration of internal clock generation circuit 330 in FIG.
[0133]
Referring to FIG. 17, internal clock generation circuit 330 is different from internal clock generation circuit 30 in that it includes a gate circuit 352 instead of gate circuit 254 in the configuration of internal clock generation circuit 30 shown in FIG.
[0134]
Gate circuit 352 includes external clock signal ext. In addition to the configuration of gate circuit 254 shown in FIG. CLK and signal int. An AND circuit 354 that receives CKE, a NOR circuit 356 that receives the output of the AND circuit 354 and the output of the flip-flop 262, and an inverter 358 that receives and inverts the output of the NOR circuit 356 and outputs a signal CKEd_P. Different from the gate circuit 254 shown in FIG.
Other structures are similar to those of internal clock generation circuit 30 shown in FIG. 12, and description thereof will not be repeated.
[0135]
FIG. 18 shows the internal clock signal int. It is an operation | movement waveform diagram for demonstrating control of CLK.
[0136]
Referring to FIG. 18, when command signal ACT_CMD is applied at time t1, internal clock generation circuit 330 shown in FIG. 17 immediately activates signal CKEd_P. Therefore, after time t1, the clock signal int. Since CLK is generated, there is no need to delay the command signal or address signal.
[0137]
When a precharge command is input at time t2, signal int. CKE is inactivated to L level, but the external clock signal ext. At time t3 is operated by the action of flip-flops 258 and 262 shown in FIG. The signal CKEd_P is deactivated in synchronization with the fall of CLK. Therefore, after time t3, the clock signal int. CLK is deactivated.
[0138]
That is, by activating the signal CKEd_P for generating the internal clock during the setup period of the row active command given from the outside with respect to the external clock, the internal clock int. CLK can be restarted without delaying one cycle.
[0139]
Therefore, even when an external clock having the highest operating frequency is used, the delay time tRCD of the internal operation of the memory array can be ensured to be equivalent to 2 clocks, so that the operating frequency can be increased even in the low power consumption mode.
[0140]
[Embodiment 3]
In the third embodiment, the reduction of power consumption is further examined in the case of a multi-bank configuration.
[0141]
FIG. 19 is a schematic block diagram showing the configuration of a DRAM core in the case of a multi-bank configuration.
[0142]
Referring to FIG. 19, in central control block 402, internal clock signal int. A clock generation circuit 408 is provided that outputs a data bus control clock signal CLKD and a row-related control clock signal CLKR in accordance with CLK.
[0143]
Row local control circuits 406 # 0 to 406 # n corresponding to memory arrays MA # 0 to MA # n are provided in a region 404 called a spinal band, and a row address signal RA transmitted in common to these is provided. There is provided a signal line group for transmitting <9: 0> and block decode signal BS <n: 0> and signal RXLATCH <3: 0> applied to row local control circuit 406 corresponding to each bank.
[0144]
Each bank includes a plurality of memory arrays. For example, in the case of FIG. 19, memory arrays MA # 0 and MA # 1 are memory arrays provided corresponding to bank <0>.
[0145]
FIG. 20 is a circuit diagram showing a configuration of row local control circuit 406 corresponding to bank <i>.
[0146]
Referring to FIG. 20, row local control circuit 406 receives row system control clock signal CLKR, inverts and outputs a local clock, and row address signal RA <8: 2> according to the local clock. Flip-flop 414 that receives and holds the row address signal RA <1: 0> according to the local clock, an inverter 418 that receives and inverts the signal RXLATCH <i>, and a signal RXLATCH <i > And the level latch circuit 420 that latches the output of the flip-flop 414 in accordance with the output of the inverter 418, and the signal RAD <8: 2> that is the output of the level latch circuit 420 is predecoded and the predecode signal X <7: 4 >, X <11: 8>, X <19:12> Including a hard circuit 426, a level latch circuit 422 which outputs a signal RXLATCH <i> and held signal BS_LATCH receiving block decode signal BS in response to the output of the inverter 418.
[0147]
The row local control circuit 406 further receives and holds the output of the flip-flop 416 according to the signal RXLATCH <i> and the output of the inverter 418, and predecodes and predecodes the output of the level latch circuit 424. Predecode circuit 430 that outputs signal X <3: 0>, inverter 428 that receives and inverts signal BS_LATCH, and signal SD_F <3: 0 that receives the output of inverter 428 and predecode signal X <3: 0> AND circuit 432 for outputting>.
[0148]
With such a configuration, the flip-flops 414 and 416 are operated in a row manner and are supplied with a local clock while the internal clock signal is supplied. Current consumption will occur.
[0149]
FIG. 21 is a circuit diagram showing a configuration of the row local control circuit according to the third embodiment.
[0150]
Referring to FIG. 21, the row local control circuit according to the third embodiment receives row control clock signal CLKR in accordance with signal RXLATCH <i> in the configuration of the row local control circuit shown in FIG. On the other hand, it is different from the circuit shown in FIG. Other configurations are similar to those of the circuit shown in FIG. 20, and description thereof will not be repeated.
[0151]
FIG. 22 is an operation waveform diagram showing how the internal clock and the local clock are controlled in the third embodiment.
[0152]
Referring to FIG. 22, when active command signal ACT_CMD is input at time t1, internal clock int. The generation of CLK is the same as in the first embodiment. Here, the local clock corresponding to the selected bank can be stopped by using the circuit shown in FIG. After the bank is selected and the corresponding row address RA <8: 0> is latched by the level latch circuits 420 and 424, the clock supply to the flip-flops 414 and 416 is the next bank <i> selected and the signal RXLATCH Not needed until <i> is activated. Accordingly, the latch circuit 482 fixes the local clock to the L level while the bank <i> is active after the rise of the signal RXLATCH <i> at time t3, and the internal clock int. The local clock rises to H level according to CLK.
[0153]
In response to the input of the precharge command at time t4, the internal clock int. The generation of CLK is stopped.
[0154]
As described above, since the local clock can be stopped for each bank for a bank that does not require clock input, not only the current consumption during standby but also the current consumption during active can be suppressed.
[0155]
[Other application examples]
The memory mounted on the system LSI in the present invention is not limited to the DRAM, but may be a burst SRAM (Static Random Access Memory) that operates in synchronization with the clock signal, or another memory such as a flash memory, and is the same as the logic. The present invention can be applied to any memory integrated on a semiconductor substrate.
[0156]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0157]
【The invention's effect】
  According to the present inventionSince the semiconductor device generates an internal clock signal only when a command is inputted and an access to the memory array occurs, power consumption can be reduced.
[0158]
  AdditionIn addition, two modes, a high speed operation and a low speed operation, are provided, and the current consumption can be reduced as a whole by reducing the current consumption during the low speed operation.
[0159]
  AdditionIn addition, read and write operations can be performed in the memory array in accordance with the generation of the internal clock.
[0160]
  AdditionMoreover, a low power consumption system LSI can be realized without changing the DRAM core.
[0162]
  TheIn addition, high-speed operation can be maintained while reducing power consumption.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a configuration of a DRAM built-in system LSI according to the present invention;
2 is a schematic block diagram showing a configuration of a DRAM core MCR in FIG. 1. FIG.
3 is a block diagram illustrating a configuration of a clock control system and a row control unit 20 in the control signal processing circuit 10 of FIG. 2;
4 is a circuit diagram showing a configuration of a row address input latch circuit 40 in FIG. 3. FIG.
5 is a circuit diagram showing a configuration of flip-flop 54 in FIG. 4. FIG.
6 is a circuit diagram showing a configuration of a predecode circuit 42a for the least significant 2 bits of the row address predecode circuit 42 in FIG. 3. FIG.
7 is a circuit diagram showing a configuration of predecode circuit 42b on the upper side of row address predecode circuit 42 in FIG. 3. FIG.
8 is a circuit diagram showing a configuration of bank command generation circuit 34 in FIG. 3. FIG.
9 is a block diagram showing a configuration of a row-related control timing circuit 36 in FIG. 3. FIG.
10 is a circuit diagram showing a configuration of row-related control timing circuit 196 in FIG. 9. FIG.
11 is a circuit diagram showing a configuration of internal clock control circuit 28 in FIG. 3. FIG.
12 is a circuit diagram showing a configuration of internal clock generation circuit 30 in FIG. 3. FIG.
13 is a circuit diagram showing a configuration of delay circuit 32 in FIG. 3. FIG.
14 shows an internal clock signal int. It is an operation | movement waveform diagram for demonstrating control of CLK.
15 is a block diagram showing a configuration of a clock control system and a row control unit 20a and a test interface circuit TIC used in a modification of the first embodiment. FIG.
FIG. 16 is a block diagram showing a configuration of a control unit 300 in the second embodiment.
17 is a circuit diagram showing a configuration of internal clock generation circuit 330 in FIG. 16. FIG.
18 shows an internal clock signal int. It is an operation | movement waveform diagram for demonstrating control of CLK.
FIG. 19 is a schematic block diagram showing a configuration of a DRAM core in the case of a multi-bank configuration.
FIG. 20 is a circuit diagram showing a configuration of a row local control circuit 406 corresponding to bank <i>.
FIG. 21 is a circuit diagram showing a configuration of a row local control circuit in the third embodiment.
FIG. 22 is an operation waveform diagram showing how internal clocks and local clocks are controlled in the third embodiment.
FIG. 23 is a block diagram showing a configuration of a control unit 500 of a DRAM core command generation system and row control system.
24 is a circuit diagram showing a configuration of internal clock generation circuit 530 in FIG. 23. FIG.
FIG. 25 is an operation waveform diagram illustrating a clock suspend function.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 System LSI, 10 Control signal processing circuit, 20, 20a, 300 Control part, 22, 22a, 322 Clock control circuit, 24, 24a, 324 Timing signal generation circuit, 26, 26a, 326 Row address processing circuit, 28, 30 , 330 Internal clock generation circuit, 32, 38, 206, 210, 216, 220, 226, 230 delay circuit, 34 bank command generation circuit, 36 row control timing circuit, 40 row address input latch circuit, 42a, 42b predecode Circuit, 42 row address predecode circuit, 52 input buffer, 56, 58, 60, 62 level latch circuit, 196-200 row system control timing circuit, 250, 280 selection gate, 252, 352 control circuit, 254 gate circuit, 402 Center Control block, 406 row local control circuit, 408 clock generation circuit, 420-424 level latch circuit, 426, 430 predecode circuit, 482 latch circuit, ACR analog core, CAK column address input circuit, CDC control circuit, DIOK data input / output Control circuit, DPB data path band, GIOP internal data line pair, LG large-scale logic, MA memory array, MCR DRAM core, MSA memory sub-array, RPD row predecoder, TIC test interface circuit, TPG test pin terminal group.

Claims (8)

A memory array including a plurality of memory cells arranged in rows and columns, and performing data exchange according to an address signal in synchronization with an internal clock signal;
A clock processing circuit for transmitting a basic clock signal to the memory array as the internal clock signal in response to a command;
The command is
A row activation command for instructing start of a row selection operation of the plurality of memory cells for data exchange with the memory array ;
A precharge command for deactivating an activated row in response to the row activation command ,
The clock processing circuit includes:
And internal clock control circuit,
And outputting the internal clock signal based on the basic clock signal in response to activation of internal clock enable signal, the internal clock generation deactivating said internal clock signal in response to the inactivation of the internal clock enable signal only contains the circuit,
The internal clock control circuit activates the internal clock enable signal in response to an external clock enable signal and deactivates the internal clock enable signal in response to the inactivation of the external clock enable signal in (A) high-speed operation mode. Activated (B) In the low-speed operation mode, the internal clock enable signal is activated in response to the row activation command after activating the external clock enable signal, and the internal clock enable signal is activated in response to the precharge command. Deactivate
The internal clock control circuit includes:
An internal circuit for activating an internal control signal in response to the row activation command and the external clock enable signal;
A selection circuit that selects the external clock enable signal in the high-speed operation mode, selects the internal control signal in the low-speed operation mode, and outputs the internal clock enable signal;
The semiconductor device, wherein the internal circuit deactivates the internal control signal in response to the precharge command in the low speed operation mode . Before Symbol internal circuit,
A latch circuit that is set in response to the row activation command and reset in response to the precharge command;
Said external clock enable signal and a gate circuit for transmitting the output of the latch circuit upon activation, the semiconductor device according to claim 1. In the low-speed operation mode , the row activation command is delayed by a time corresponding to a first delay time from when the clock processing circuit receives the row activation command until generation of the internal clock signal is started. 1 delay circuit;
Further comprising a row control timing circuit for instructing a timing of row activation in said memory array in response to an output of said first delay circuit, a semiconductor device according to claim 1. A second delay circuit for delaying a row address signal applied to specify a row of the memory array for a time corresponding to the first delay time in the low-speed operation mode ;
4. The semiconductor device according to claim 3 , further comprising: a row address processing circuit that captures and holds an output of the second delay circuit in accordance with an output of the row-related control timing circuit. The memory array, the internal clock generation circuit, the row-related control timing circuit, and the row address processing circuit are arranged in a first region,
The internal clock control circuit, the first and second delay circuits are arranged in a second region outside the first region,
The internal clock control circuit and the internal clock generation circuit are connected, the first delay circuit and the row control timing circuit are connected, and the second delay circuit and the row address processing circuit are connected. The semiconductor device according to claim 4 , further comprising a wiring group disposed in a wiring region outside the first and second regions. The semiconductor device operates according to the basic clock signal having a first frequency in the high-speed operation mode , and operates according to the basic clock signal having a second frequency lower than the first frequency in the low-speed operation mode . The semiconductor device according to claim 1 . The internal clock generation circuit
A holding circuit that captures the internal clock enable signal according to the basic clock signal;
The semiconductor device according to claim 1, further comprising: a gate circuit that outputs the basic clock signal as the internal clock signal in accordance with an output of the holding circuit. The internal clock generation circuit
A holding circuit that captures the internal clock enable signal according to the basic clock signal;
When the internal clock enable signal is activated, the basic clock signal is immediately output as the internal clock signal, and when the internal clock enable signal is deactivated, the basic clock signal is output according to the output of the holding circuit. The semiconductor device according to claim 1, further comprising a gate circuit that outputs a signal as the internal clock signal.

Images