JP4798505B2 - Digital system design system and digital system manufacturing method - Google Patents

Description

  The present invention relates to a digital system design system and a digital system manufacturing method, and more particularly to a design system in which a delay time of a programmable delay circuit is set using a genetic algorithm for a digital system having a programmable delay circuit. And effective technology.

For example, Patent Document 1 discloses a digital system in which a delay element is provided in a clock input unit of each flip-flop. The delay time of each delay element can be set, for example, from an external device after the digital system is manufactured. At this time, a plurality of register values for setting the delay time of each delay element are collectively regarded as one chromosome, and an optimal chromosome (that is, based on a probabilistic search method represented by a genetic algorithm, for example) The optimum delay time of each delay element is determined. Specifically, the logic level of each node is observed while performing, for example, a logic test on the digital system, and a chromosome with which this evaluation function becomes high is determined by using the ratio that matches the expected value as an evaluation function. Search by genetic algorithm. By using such a digital system, it is possible to suppress a decrease in functions and performance of the digital system due to manufacturing variations, and to improve manufacturing yield.
International Publication No. 04/109916 Pamphlet

  In recent years, with the increase in speed and miniaturization of digital LSI (Large Scale Integration) and the like, the problem of clock skew, which is a shift in the propagation time of a clock signal, has become serious. As a result, the operation yield of digital LSIs (the ratio of chips that can operate with the specifications as designed) decreases, leading to an increase in chip prices. One of the main causes of clock skew is manufacturing variation, which causes fluctuations in delay time and drive capability of individual transistors, wiring resistance, parasitic capacitance, and the like.

  In order to solve the clock skew problem of the digital LSI, for example, it is conceivable to use the technique of Patent Document 1. FIG. 13 is a block diagram showing a configuration example of a digital system design system examined as a premise of the present invention. The design system shown in FIG. 13 has the same configuration as that shown in FIG.

  The design system shown in FIG. 13 includes a digital system 1, a power supply device 2, a digital test signal generation device 3, an adjustment device 4, a digital signal observation device 5, and the like. The digital system 1 is provided with various logical operation functions such as a microcomputer, for example, and may be a single semiconductor chip. A plurality of semiconductor chips each performing a desired logical operation are arranged on a circuit board. It may be connected. The digital system 1 includes a plurality of flip-flops FF1a to FF1d, FF2a, and FF2b, a plurality of delay circuits DLY1a to DLY1d, a plurality of holding circuits (for example, registers) REG1a to REG1d, and the like.

  FF1a to FF1d are flip-flops that perform clock adjustment, and FF2a and FF2b are flip-flops that do not perform clock adjustment. FF1a to FF1d are circuits that store 1 bit in synchronization with the clock signal CLK, and correspond to circuits having various configurations including, for example, a D flip-flop and an SR flip-flop. The delay circuits DLY1a to DLY1d are connected to the clock input portions of the flip-flops FF1a to FF1d, respectively, and are programmable delay circuits that can set delay times according to the set values of the holding circuits REG1a to REG1d. As described in Patent Document 1, the programmable delay circuit can be realized in various configurations that are generally known, such as those that use inverter delay and those that use CR delay of capacitance and resistance. Each of the holding circuits REG1a to REG1d is a circuit that stores a plurality of bits. For example, the holding circuits REG1a to REG1d may be a RAM or a rewritable nonvolatile memory, in addition to being realized by a register including a plurality of flip-flops.

  The values of the holding circuits REG1a to REG1d are set by the adjustment circuit 4. The adjustment circuit 4 may be any circuit that can execute program processing and has an external input / output function, such as a personal computer. The digital test signal generator 3 receives a start signal from the adjustment device 4 and gives a test signal (data input signal) Din and a clock signal CLK to the digital system 1. The output voltage value of the power supply device 2 is controlled by the adjustment device 4 to supply power 6 to the digital system 1. The digital signal observation device 5 observes the data output signal Dout from the digital system 1 and the logic level 7 of the internal node of the digital system 1 and gives the observation result to the adjustment device 4.

  The power supply device 2, the digital test signal generation device 3, and the digital signal observation device 5 may be individually configured using, for example, a general DC power supply generation device, a pattern generator, a logic analyzer, etc. A logic tester having all of these functions may be used. Further, some or all of the power supply device 2, the digital test signal generation device 3, the digital signal observation device 5, and the adjustment device 4 can be incorporated in the digital system 1.

  By using such a design system, the digital system 1 can be tested while changing the delay time of the delay circuits DLY1a to DLY1d and also changing the power supply voltage supplied to the digital system 1, and based on the test result. Thus, the optimum delay time of DLY1a to DLY1d can be determined. FIG. 14 shows a pipeline type circuit as an example of the digital system 1 of FIG. 13, and (a) to (c) show cases where the operating conditions are different. Taking the circuit of FIG. 14 as an example, the state of adjusting the delay time of the delay circuit DLY after manufacture will be described.

  The circuits shown in FIGS. 14A to 14C are configured to transfer the data input signal Din via four stages of flip-flops FFa to FFd. Combination circuits CCa, CCb, and CCc that perform desired calculations are provided between FFa and FFb, between FFb and FFc, and between FFc and FFd, respectively. In addition, delay circuits DLYa to DLYd are provided at the input portions of the clock signals CLK of the flip-flops FFa to FFd. Here, even if the combinational circuits CCa to CCc have the same circuit configuration, CCa to CCc have different path delay times when manufacturing variations occur. Here, the path delay times of CCa, CCb, and CCc are 90 ps, 100 ps, and 80 ps, respectively.

  When the delay time of DLYa to DLYd is zero, the period of the clock signal that can hold accurate data in FFa to FFd is 100 ps in accordance with the slowest combinational circuit CCb as shown in FIG. That is, the entire circuit operates at a cycle of 100 ps. Here, as shown in FIG. 14B, the cycle of the entire circuit is changed to 90 ps. Then, the data passing through the combinational circuit CCb operating at 100 ps is not in time for the arrival of the clock signal CLK at FFc. Therefore, malfunction occurs in the entire circuit. Therefore, as shown in FIG. 14C, the delay circuit DLYc delays the clock signal CLK to the FFc having no time margin from the arrival of the data signal to the arrival of the clock signal CLK by 10 ps.

  By doing so, a time margin of 10 ps can be created for the combinational circuit CCb operating at 100 ps, and malfunction of the entire circuit can be eliminated. However, since the clock arrival timing of FFc is delayed by 10 ps due to the delay circuit DLYc, the combinational circuit CCc immediately after that must operate at 80 ps which is 10 ps earlier than the normal cycle. However, since the combinational circuit CCc originally operates at 80 ps, no malfunction occurs. Therefore, the clock frequency of the entire circuit can be improved by delaying the clock timing of one flip-flop. As a result, it is possible to improve the manufacturing yield or realize a clock speed faster than the design.

  It is possible to reduce the power consumption of the LSI based on the same principle. The power consumption of LSI has the property of increasing in proportion to the square of the power supply voltage. That is, power consumption can be reduced if the power supply voltage of the LSI can be lowered. However, when the power supply voltage is lowered, the driving capability of the transistors inside the circuit is lowered, and due to the delay caused by this, some combinational circuits cannot keep up with the clock signal reaching the flip-flop, resulting in malfunction. . Therefore, using the delay circuit based on the same principle as that for increasing the clock speed, the circuit can be operated normally despite the power supply voltage being lowered. This reduction in power consumption is particularly beneficial for mobile devices such as mobile phones.

  In this way, various beneficial effects can be obtained by adjusting the delay time of the clock signal after manufacturing. However, in actual digital LSIs, etc., many flip-flops are included, and each flip-flop has a complicated influence. Therefore, it is necessary to solve a huge search space with this adjustment. That is, in an actual digital LSI or the like, a plurality of flip-flops are connected to the next stage of one flip-flop. Therefore, changing the clock arrival time of one flip-flop circuit affects many flip-flop circuits. It will be.

  Therefore, in Patent Document 1, a stochastic search method such as a genetic algorithm (GA) or genetic programming is used to adjust the delay time, and automatic search processing using this method is performed as shown in FIG. The adjustment device 4 is made to perform. This makes it possible to obtain an optimum solution for the delay time of the delay circuit DLY at high speed. Note that details of the probabilistic search method are described in Patent Document 1, and therefore, an outline thereof will be described here.

  FIG. 15 is a schematic diagram illustrating a configuration example of chromosomes used in the genetic algorithm. FIG. 16 shows an example of operations performed on chromosomes in the genetic algorithm, and (a) and (b) are schematic diagrams showing examples of crossover and mutation operations, respectively. FIG. 17 is a conceptual diagram showing how the operation proceeds with the genetic algorithm.

  As shown in the upper part of FIG. 17, in the genetic algorithm, a plurality (here, 5) of chromosomes CH <b> 1 a to CH <b> 5 a are generated by random numbers or the like as an initial population. Each chromosome CH has a structure in which the values of a plurality of registers REG1a to REG1d are combined into one as shown in FIG. Each of the registers REG1a to REG1d corresponds to, for example, the holding circuits (registers) REG1a to REG1d in FIG. 13, and the value stored in each of them is the delay time. That is, each chromosome CH is an aggregate made up of information (delay information) held by all delay circuits included in the digital system 1 of FIG. In FIG. 15, minus (for example, −350 ps) is set as the delay time. This minus can be realized, for example, by relatively speeding up the reference clock signal CLK itself generated from the PLL circuit or the like. .

  In the genetic algorithm, as shown in FIG. 17, the superiority or inferiority of each chromosome is evaluated by the magnitude of fitness (evaluation function) fit. Here, as shown in FIG. 17, it is assumed that there is a relationship as shown in function F between the variation of chromosome CH (that is, the combination of bit values included therein) and fitness fit. Here, if a genetic algorithm is not used, for example, only one chromosome (for example, CH1a) in the upper part of FIG. 17 is generated as an initial value. When searching for a high fitness fit based on a hill-climbing method or the like from here, the point 170 is usually a solution, and a solution with a high fitness fit is not always obtained.

  Therefore, in the genetic algorithm, multiple chromosomes (that is, chromosomes with different bit values) are generated as an initial population by random numbers, etc., and operations such as selection (選 択), crossover, and mutation are performed on the chromosomes from there. While repeating, search for chromosomes with high overall fitness. As shown in FIG. 16 (a), crossover means that, for example, chromosome CH1a and chromosome CH3a are extracted from the upper stage of FIG. 17, and new chromosomes CH1b and CH3b are generated by exchanging some bits of the chromosome. It is an operation like this. As shown in FIG. 16 (b), the mutation is an operation in which, for example, a chromosome CH4a is extracted from the upper part of FIG. 17, and a new chromosome CH4b is generated by inverting appropriate bits thereof. Selection (淘汰) refers to an operation to leave a chromosome with a high fitness by leaving a chromosome with a low fitness as shown in the chromosome CH2a from the top to the middle of FIG. 17 or the chromosome CH3b from the interruption to the bottom. It is.

  It can be expected that more excellent chromosomes can be generated by performing operations such as crossover and mutation on the excellent chromosomes that survive after being deceived. Therefore, when such operations as selection (、), crossover, and mutation are repeated, it is possible to search for chromosomes with high fitness in a wide range as shown in the upper part → middle part → lower part of FIG. Finally, as shown in the lower chromosome CH3c in FIG. 17, it is possible to obtain a final solution with the highest fitness fit in the global range. Note that this fitness (evaluation function) fit is, for example, observed using digital signal observation apparatus 5 in FIG. 13 and fit = (number of nodes and data output signals matching expected value) / (observed) The total number of nodes and data output signals). In this case, the maximum value of the evaluation function fit is “1”.

  When the design system as described above is used, it is possible to obtain a beneficial effect as described above particularly for a medium / small-scale digital system. However, when such a design system is applied to, for example, a large-scale digital system (digital LSI) having tens of thousands to millions of gates, the following two points become problems. The first point is that if a delay circuit is inserted into all flip-flops (or registers), the area overhead becomes large. Second, as the number of delay circuits increases, the number of chromosome bits increases, and the adjustment time increases exponentially. For example, in the mass production process of LSI, assuming that the delay circuit is adjusted using a logic tester or the like in a test process after manufacturing the LSI, the adjustment time is desirably as short as possible from the viewpoint of throughput.

Both of these problems lead to an increase in manufacturing costs. If a delay circuit is inserted into all flip-flops (or registers) and the optimum solution can be set, the cost can be reduced along with the yield improvement as described above, but the manufacturing cost may increase further. There is. Also, if the search space becomes too wide, the optimal solution cannot be obtained in a practical time, and the effect may not be fully exhibited. Therefore, it is conceivable to limit the number of delay circuits built in the LSI in consideration of the area overhead and the adjustment time, but it is unclear how much the location and number should be limited. In other words, at the LSI design stage, the time and area overhead required for the adjustment can be easily calculated with respect to the number of delay circuits, but how much yield improvement effect can be obtained by this can be predicted. Because it is not possible, it is not possible to determine how much to make in which place.
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital system design system and manufacturing method capable of reducing the manufacturing cost. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The digital system design system of the present invention is realized by program processing by a computer system, and a programmable delay circuit is provided at a clock input section of a plurality of flip-flops, so that a timing margin of a path between the plurality of flip-flops can be adjusted. The digital system is designed for. This design system uses a timing analysis result at the design stage for a digital system, generates a simulation model of the digital system, and can confirm various effects by providing a programmable delay circuit on the simulation model. It is a major feature.

  That is, the set time of the programmable delay circuit is searched based on a probabilistic search method such as a genetic algorithm, for example. In such a probabilistic search method, it is necessary to repeat a test on the digital system an enormous number of times. Therefore, when the delay time adjustment operation by this probabilistic search method is simulated on a computer, it is important how short the simulation can be performed. In particular, since the simulation time becomes longer as the LSI becomes larger, this requirement becomes stronger.

  Therefore, in this design system, in order to enable high-speed simulation operation, a simulation model that expresses the flip-flops included in the timing analysis results as nodes and the connection between the flip-flops (that is, combinational circuits) as directional arcs. Is used. Since this simulation model does not simulate logic information related to the combinational circuit, it can operate at high speed.

  Each arc holds the propagation time obtained from the path delay time obtained from the timing analysis result, the first delay time reflecting the manufacturing variation, and the second delay time reflecting the set time of the programmable delay circuit. Here, when the propagation time of the arc satisfies a predetermined specification, the first information is stored in the node connected to the tip of the arc, and when the propagation time has not satisfied, the second information is stored in the node connected to the tip of the arc. Remember. If there is a node storing the second information, the second information is transmitted between the nodes according to the directionality of the arc.

  Whether each node is the first information or the second information is a material for determining the simulation result. In an ideal state, each node is all the first information. As described above, since this simulation model performs only simple calculation processing, comparison processing, and transmission processing, it can exhibit sufficiently high speed even when targeting a large-scale LSI. When simulating the adjustment operation of the delay circuit using the stochastic search technique, the search result using the stochastic search technique is reflected in the second delay time, and the first information and the first information of each node are accordingly reflected. Since the simulation model in which two information changes is used, the adjustment operation can be simulated by using the ratio of the first information of each node as the fitness.

  If simulation of the adjustment operation can be performed at high speed, it is possible to determine at what time a delay circuit should be provided in the digital system at the time of design. As described above, especially in a large-scale LSI, the insertion of a delay circuit causes an increase in area overhead and an increase in adjustment time, resulting in an increase in manufacturing cost. Therefore, the delay circuit to be inserted is limited at the design stage. It is desirable. In the past, there was no practical technique for confirming the effect of this limitation at the design stage, but this problem can be solved by using the design system of the present invention, and the yield is improved by a minimum delay circuit. Thus, the manufacturing cost can be reduced.

  Specifically, for example, based on the timing analysis result at the design stage, a plurality of paths with a small timing margin are selected, and a state in which a delay circuit is inserted into these paths is created by the design system of the present invention. A simulation may be performed on the above. Then, by performing simulation while changing the number of delay circuits to be inserted, the optimum number of delay circuits can be found. At this time, it is desirable to use the yield as a judgment material. Therefore, in order to be able to verify the yield, the design system of the present invention includes the first delay time reflecting the manufacturing variation in the above-described arc propagation time. Specifically, the first delay time is determined by a normal random number, for example.

  By giving variation by this first delay time, it becomes possible to generate a plurality of virtual chips based on the simulation model described above, and to create a state in which the amount of variation is different for each virtual chip. Therefore, if the adjustment operation by the genetic algorithm is successful for the plurality of virtual chips as a non-defective product, a failure case, and a defective product, the yield can be derived on the simulation.

  Further, the digital system manufacturing method of the present invention is characterized in that it includes a step of performing the effectiveness check when the delay circuit as described above is limited by using the design system of the present invention. Yes. In addition to this, in the adjustment operation using a genetic algorithm after manufacture, another characteristic is that the initial population has a distribution based on manufacturing variations. It is known that actual LSIs have manufacturing variations such as a normal distribution, for example, and in addition to this, the initial group has the same variations to shorten the time until the adjustment operation converges. It becomes possible. Thereby, the manufacturing cost can be reduced.

  If the effects obtained by typical ones of the inventions disclosed in the present application are briefly described, the manufacturing cost of the digital system can be reduced.

  In the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and in principle limited to a specific number in principle, It is not limited to the specific number, and it may be more or less than the specific number. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

The design system and manufacturing method of the digital system according to this embodiment have the following three main features.
(1) For example, the number of delay circuits to be adjusted is limited to the time of LSI design using results such as static timing analysis (STA). Thereby, the adjustment time can be shortened, and the circuit area required for the delay circuit can be reduced. As a result, the manufacturing cost can be reduced.
(2) A simulator capable of confirming various adjustment effects in a short time without performing circuit simulation (dynamic timing analysis) is realized. By using this simulator, the effect of (1) can be easily confirmed at the time of LSI design, and the optimum number of delay circuits can be determined. As a result, the manufacturing cost can be reduced.
(3) Devise the distribution of the initial population of GA during adjustment. With this device, the convergence speed of GA can be increased, and the adjustment time after LSI manufacturing can be shortened. As a result, the manufacturing cost can be reduced.

  Hereinafter, these details will be described.

  FIG. 1 is a process flow diagram showing an example of the processing in a method for manufacturing a digital system according to an embodiment of the present invention. In FIG. 1, first, circuit design is performed without the delay circuit DLY and the holding circuit REG described in the digital system 1 of FIG. 13 (S101). This circuit design includes logic design, logic verification, and subsequent logic synthesis. Next, verification such as static timing analysis (STA) that does not give a test pattern and dynamic timing analysis that gives a test pattern is performed on the circuit thus completed (S102).

  In this static timing analysis (STA), the path delay time between the flip-flops can be obtained for all the flip-flops included in the circuit. This STA generally performs processing such as simply adding the approximate delay time of the gate (combination circuit) included between the flip-flops and the approximate delay time of the wiring, so that even in a large-scale circuit, the STA is high-speed. It is possible to perform processing. If an error occurs in the verification (S102), the process returns to the circuit design (S101) again.

  Next, limitation and adjustment simulation of the delay circuit DLY provided in the digital system 1 is performed (S103 and S104). This processing is a characteristic part of the present embodiment. Although details will be described later, for example, a simulator capable of high-speed operation using the result of STA is created, and by inserting a delay circuit DLY on this simulator, where and how much delay circuit can be created, it is practical Verify how much yield improvement can be expected with a reasonable adjustment time. Although not shown, the insertion position and the number of the delay circuits DLY obtained by the processing here are reflected in the circuit design in S101, or in some cases in the subsequent physical design (S105). It is also possible to make it. In this case, it is not necessary to cause a design return.

Subsequently, physical design such as circuit layout and clock tree formation is performed (S105). In this processing, the timing is finely adjusted according to the circuit arrangement, or the timing is finely adjusted by inserting a buffer or the like into the clock tree using a technique called optimization design (optimization processing). Therefore, in some cases, it is possible to insert a delay circuit DLY together with this buffer or the like. Next, a mask design is performed (S106), and an LSI is manufactured based on the mask (S107).
Thereafter, in a test process for the manufactured LSI, the delay circuit DLY is adjusted by a genetic algorithm (GA) using an LSI tester (logic tester) or the like. Although details will be described later, in this processing, the use of normal random numbers for the initial population generation processing in the genetic algorithm is another main feature of the present embodiment. Then, the LSI for which the adjustment process has been performed is shipped through an inspection process (S109) such as electrical characteristics (S110).

  FIG. 2 is a flowchart showing an example of detailed processing contents when the delay circuit is limited (S103) in the digital system manufacturing method shown in FIG. In this processing, the insertion time of the delay circuit is limited to shorten the adjustment time in S108 of FIG. 1, and the overhead of the chip area in the digital system 1 as shown in FIG. 13 can be reduced. The main purpose. This process is automatically performed by a program process in a computer system, for example.

In FIG. 2, first, a list of path delay times is generated from the result of the static timing analysis (STA) in S102 of FIG. 1 (S201). The path delay time is a time required for a data signal to pass through a combinational circuit between flip-flops and the like. Next, the path delay times are ranked with respect to timing margin based on the created list (S202). After that, N locations are sequentially determined from the flip-flops at both ends of the path delay time with the least margin (S203).
That is, as the program contents of the computer system, for example, sorting is performed on a list of path delay times (and information specifying flip-flops at both ends thereof) obtained by the STA result. When N is designated from the user or a program that executes an adjustment simulation described later, the flip-flop is determined with reference to the sorting result.

  Note that in S203, the flip-flops at both ends are targeted because the flip-flops included in the actual LSI have a close influence on each other as described above. This is because adjustment is possible with less adverse effect on other flip-flops. Alternatively, the margin is appropriately allocated to the flip-flops at both ends, thereby making it possible to perform adjustment so that the adverse effect on other flip-flops is reduced as a whole. Furthermore, if the path delay time between the two ends becomes very large due to variations, the adjustment can be made with the maximum adjustment width of the two delay circuits located at both ends. It is to do.

  As described above, it is most desirable to perform the adjustment simulation in S104 in FIG. 1 assuming that delay circuits are inserted at both ends. Of course, in some cases, the adjustment simulation is performed assuming that the delay circuit is inserted only on one side. It is also possible to do this. In other words, the path timing margin can be expanded by inserting only at the path start point and setting a negative delay time, or inserting it only at the path end point and setting a positive delay time. is there. If a negative delay time is expected to be set in the adjustment simulation, the negative delay time may be realized by adjusting a PLL circuit or the like on an actually manufactured chip.

  As described above, by limiting the adjustment location only to the location where the effect of adjustment can be expected, the adjustment time is shortened and the surface overhead is reduced. However, at this time, the optimum value of the number N of adjustment points to be limited is determined by a trade-off between an improvement in yield due to adjustment and an increase in adjustment time (and area overhead), and therefore differs depending on the target LSI. Therefore, in S104 of FIG. 1, the yield improvement effect when the number N of delay circuits are inserted is estimated using adjustment simulation, and the optimum N is found by performing adjustment simulation while changing the number N.

  FIG. 3 is a conceptual diagram showing an example of a simulation model used in the adjustment simulation in the digital system manufacturing method shown in FIG. In order to confirm the effect of adjustment at the time of design, it is necessary to perform adjustment simulation using a genetic algorithm (GA). In the GA, as described above, the degree of normal operation of the circuit is used as the fitness (evaluation function) fit, and after the chromosome is corrected by genetic operation, the fitness is calculated again. Since such repeated work will be performed thousands of times, in order to investigate whether the circuit operates normally, timing simulation (dynamic timing analysis) including transfer of the data pattern by the combinational circuit was performed. It takes time to calculate the evaluation function once, and it takes a long time to complete the adjustment simulation.

  Therefore, a simulator that models only timing information is created to determine whether the flip-flop can transmit normal information. This simulator is realized by program processing in a computer system, has only the minimum functions necessary for verifying the insertion effect of the delay circuit, and can operate at high speed.

  That is, this simulator represents the digital system 1 with a simulation model as shown in FIG. In the simulation model of FIG. 3, the state until the input data passes through the combinational circuit or flip-flop and is output is represented by a directed graph. The circles in FIG. 3 represent the flip-flops included in the digital system 1 (that is, flip-flops included in the STA result) as nodes. Each node holds 1 or 0 when a timing condition described later is satisfied and when it is not satisfied.

  The arrows in FIG. 3 represent paths (combination circuits) between flip-flops included in the digital system 1 as arcs (sides). Each arc retains the time it takes for the signal to pass through the path. Although details will be described later, this time is a time obtained by processing the path delay time based on the result of the STA. In this way, the simulation model of FIG. 3 omits the logic information of each combinational circuit and the detailed timing relationship of the passing data such as the setup / hold timing of the flip-flop, for example. Confirmation of operation is possible. Specifically, an operation check is performed on the simulation model of the digital system 1 (hereinafter also referred to as a chip or a virtual chip) in the following procedure.

[1A] In the initial state of simulation, it is assumed that all flip-flops i (0 ≦ i ≦ n−1, where n is the total number of flip-flops) all operate normally. Here, a value indicating whether or not the flip-flop i operates normally is Si, and is 1 if the flip-flop i operates normally and 0 if it does not operate normally. Therefore, for example, in the case of normal operation, Equation (1) is obtained.
Si = 1 (1)

[2A] FIG. 4 is a diagram for explaining the processing contents when the operation check is performed on the simulation model of FIG. 3, and shows the operation model of the flip-flop. As shown in FIG. 4, if the time Dij passing through the combinational circuit having flip-flops i and j in the chip is less than or equal to the time Tclk for one cycle of the clock signal, the calculated data is normally transmitted. Assuming that the flip-flop j operates normally, a value Sj indicating whether the flip-flop j operates normally is set to 1. Further, a mark Sj = 0 indicating that the data is not normal is attached to the flip-flop j in which the data is not normally transmitted. Thereby, the relationship of Formula (2) and Formula (3) is formed.
Dij ≦ Tclk: Sj = 1 (2)
Dij> Tclk: Sj = 0 (3)

[3A] FIG. 5 is a diagram for explaining the processing contents when the operation confirmation is performed on the simulation model of FIG. 3, and shows a transition model of the operation state of the flip-flop. As shown in FIG. 5, since the combinational circuit Djk having as input the flip-flop j with the mark Sj = 0 that does not have normal data cannot output a normal value, the output value of the flip-flop j is Similarly, a mark Sk = 0 is attached to the flip-flop k as an input. In this way, it is checked whether data is normally transmitted in all combinational circuits in the chip.
For example, adding the mark Sk = 0 to the flip-flop k corresponds to holding 0 in the node corresponding to the flip-flop k in FIG. Here, as shown in FIG. 3, when there is a path (arc) in which a feedback loop (corresponding to a sequential circuit or the like) occurs between the nodes, 0 in the subsequent stage is fed back by the processing here, and the feedback Even if correct transmission occurs so that the preceding preceding stage becomes 0, erroneous transmission such that the succeeding 1 is returned and the preceding stage of the returning destination is changed from 0 to 1 does not occur. That is, if the preceding stage is 0, the succeeding stage is always 0.

[4A] After the above processes [1A] to [3A], if each flip-flop out_i included in the output data in FIG. 3 can hold all normal data Sout_i = 1, the chip. Is determined to be operating normally. If even one flip-flop out_i cannot hold normal data (Sout_i = 0), it is determined that the chip is a malfunctioning chip.
Here, out of the total number Nout of each flip-flop out_i, the ratio nout / Nout of the number nout of flip-flops out_i holding normal data is made to correspond to the fitness fit in the genetic algorithm. In this way, in the genetic algorithm, the genetic operation is repeated until a chromosome whose fitness fit becomes 1 appears.

  Next, a model related to the timing of the combinational circuit (arc in FIG. 3) will be described.

When the delay values of the delay circuits inserted in the clock lines of the flip-flops i and j are Di and Dj, the adjusted path delay time Dij ′ between the flip-flops i and j is obtained by Expression (4).
Dij ′ = Dij + Dj−Di (4)
At this time, for the delay time Dij, for example, an analysis result of the STA at the time of LSI design may be used. If the variation in Var_ij occurs in the path delay time between two flip-flops in the manufacturing process, the delay time Dij ″ considering the variation can be defined as in equation (5).
Dij ″ = Dij ′ + Var_ij (5)
For the sake of simplicity, the variation value Var_ij is assumed to be normally distributed with the relative value σrel, and is obtained by Expression (6) using a normal random number N (0, 1).
Var_ij = Dij × σrel × N (0,1) (6)
The Dij '' obtained in this way is held in each arc in FIG. 3 and further used in place of Dij in the timing conditions of Equations (2) and (3) to verify whether each node in FIG. 3 is 0 or 1 Then, the 0 or 1 is transmitted as in the procedure [3A] described above.

  As described above, by reflecting the variation value Var_ij in the equation (6) in the delay time of each arc in FIG. 3, it is possible to generate a plurality of chips (virtual chips) in FIG. 3 having different variations in path delay time. . Here, this variation is based on a normal distribution considered to be close to actual manufacturing variation. Further, when the delay values Di and Dj are reflected in the delay time of each arc in FIG. 3 as shown in the equation (4), a delay circuit is inserted into the virtual chip. Therefore, it can be said that the generated virtual chip accurately reflects the digital system 1 (digital LSI) manufactured with the delay circuit inserted.

  Therefore, similarly to the clock adjustment (S108) in the real chip of FIG. 1, the delay time of the delay circuit is adjusted by the genetic algorithm (GA) for the plurality of virtual chips described above, and the adjustment is successful (ie, It is possible to estimate the yield improvement effect due to the insertion of the delay circuit by determining the ratio (the fitness fit can be set to 1). Furthermore, by performing the same evaluation while limiting the number of delay circuits inserted in the virtual chip by the method described in FIG. 2 and the like, the trade-off between the yield improvement effect and the adjustment time and area overhead is taken into consideration. However, the optimum number of delay circuits can be determined. At this time, the above-described simulator performs a simple process such as calculation of a simple mathematical formula and transmission of 1 and 0, so that high speed operation is possible.

  Here, the normal distribution is used as the manufacturing variation. However, when the distribution is based on another distribution, the normal random number may be replaced with a random number representing the distribution. In addition, as the delay time Dij of each arc in FIG. 3, the result of static timing analysis (STA) is used here, but it is not always necessary to be the result of STA, and information on path delay time between each flip-flop and Any data having information that can identify each flip-prop corresponding to the data can be substituted. For example, it is possible to substitute a result of a dynamic timing analysis for verifying a path delay time using a data pattern. In some cases, it is possible to use the path delay time obtained by the physical design (S105) of FIG. In this case, a more accurate adjustment simulation is possible. However, in this case, as described with reference to FIG. 1, it is desirable to realize a mechanism capable of inserting a delay circuit during physical design (S105) so as not to cause a return to circuit design (S101).

  FIG. 6 is a flowchart showing an example of detailed processing of post-manufacturing clock adjustment (S108) using the genetic algorithm (GA) in the manufacturing method of the digital system shown in FIG. This processing is realized by, for example, program processing by a computer system, and similarly used in the adjustment simulation (S104) of FIG. 1 as described above. However, as described with reference to FIG. 13, when the genetic algorithm is incorporated in the digital system 1, the post-manufacturing clock adjustment (S 108) processing using the GA is performed by the digital system 1 itself. The processing content of FIG. 6 is the same as the processing described in Patent Literature 1 except for the generation processing (S601) of the population (initial population) described later. Since the details are described in Patent Document 1, a brief description will be given here.

  After starting adjustment of the genetic algorithm (S600), first, a population (initial population) is generated (S601). Here, the population means an aggregate made up of a predetermined number of chromosomes used in the genetic algorithm, and each chromosome is sequentially replaced by being selected (淘汰) through crossover or mutation. The initial population means an aggregate made up of a predetermined number of chromosomes generated first before this selection (淘汰) is performed, in other words, an initial state of the population.

In Patent Document 1, the initial parameter value set for each chromosome of the initial population is determined by a uniform random number. However, the manufacturing error generally varies from front to back around the design value. Therefore, in this embodiment, in order to take advantage of this property, the initial parameter values of each chromosome included in the initial population are distributed with normal random numbers with the design value as the center. Specifically, each of the set values Di (0 ≦ i ≦ N−1) of the N delay circuits is normally distributed with the relative value σGA, and an equation ( 7).
Di = σGA × N (0, 1) (7)

  FIG. 7 is a schematic diagram showing the difference in distribution of the initial population between uniform random numbers and normal random numbers in the population generation processing (S601) in FIG. When uniform random numbers are used, the initial parameter value (initial delay value of the delay circuit) of each chromosome included in the initial population varies with an almost equal probability over the adjustment range, as in the variation characteristic 71 of FIG. It will be. On the other hand, when a normal random number is used, the initial parameter value of each chromosome (the initial delay value of the delay circuit) is the design center value (ie, corresponds to a zero delay time) as shown in the variation characteristic 72 of FIG. The probability of having it is the highest, and it will vary in a normal distribution from the lower limit to the upper limit around this.

  As described above, by distributing the initial delay value of the delay circuit by the normal random number with the design value as the center, the convergence speed of the GA is increased, and the solution candidate can be found more quickly. Therefore, the time required for the post-manufacturing clock adjustment (S108) in FIG. 1 can be shortened. Or, compared with the case of uniform random numbers, the probability that an optimal solution can be obtained in the same adjustment time is higher. This means that if the adjustment time is constant, it can contribute to the improvement of the chip yield.

  Further, in S601 of FIG. 6, the fitness fit of each of the generated population (here, the initial population) is obtained. Here, fitness fitness is determined (S602), and if there is a chromosome whose fitness fitness is 1.0, the adjustment is regarded as successful and ends (S608). If no chromosome has a fitness fit of 1.0, the process proceeds to S603.

  In S603, two chromosomes are selected at random from the population, and the two chromosomes are used as parents to perform crossover and mutation processes as shown in FIG. 16 to generate two child chromosomes. Furthermore, fitness fitness is obtained for the two chromosomes of the child. Here, the fitness fit is determined (S604). If the fitness fit is 1.0 on one of the child chromosomes, the adjustment is deemed successful and ends (S608). If the fitness fit of both chromosomes is less than 1.0, the process proceeds to S605.

  In S605, the fitness fitness is compared between the parent two chromosomes and the child two chromosomes, and the two chromosomes having the large fitness fitness are returned to the original population. That is, replacement is performed in the population. In other words, a chromosome to be left in the population is selected, and a chromosome with a low fitness fit is selected. If the processes of S603 to S605 are repeated the number of times (number of populations) / 2, it is considered that one generation has been completed. Then, it is determined whether or not a predetermined number of generations has been reached (S606), and if it has been reached, the adjustment is regarded as a failure and ends (S607).

  FIG. 8 is a block diagram showing a configuration example of a simulator used in the adjustment simulation (S104) in the digital system manufacturing method shown in FIG. This simulator performs various processes as described in FIGS. 3 to 5, and further executes a genetic algorithm (GA) as described in FIG. 6, and is realized by a program process by a computer. The Of course, the simulator is not limited to the configuration described below, and functions similar to the following can be realized in various forms by program processing.

  The simulator shown in FIG. 8 includes, for example, an I / O unit 100, a timing simulator unit 101, a genetic algorithm (GA) execution unit 102, and the like. The timing simulator unit 101 obtains the number of nodes, connection information between nodes, input / output node information, Dij of each arc, and σrel of Expression (6) from the outside through the I / O unit 100. Information excluding σrel may be appropriately acquired from the result of STA, for example. With respect to σrel, the degree of variation in the assumed LSI manufacturing process is obtained through input from the user, for example. The value of σrel is, for example, 5% (σrel = 0.05) in a process with a large variation.

  In addition, the timing simulator unit 101 also obtains which node is the adjustment target from the outside. This information may be obtained from the result of the adjustment location limiting method in FIG. An assumed operating frequency, which is an adjustment condition, is also acquired from the outside. As the Dij of each arc, a typical value calculated in advance by, for example, STA may be used according to the assumed operating power supply voltage.

  The genetic algorithm execution unit 102, through the I / O unit 100, receives the number of populations, chromosome length, number of truncation evaluations, crossover probability, mutation probability, σGA of Equation (7), and delay circuit setting value Di from the outside. The upper and lower limit values and the total number Nout of output terminals are acquired. The chromosome length is determined according to the adjustment location (number of delay circuits to be inserted) N.

  FIG. 9 is a block diagram showing a detailed configuration example of the genetic algorithm (GA) execution unit in the simulator of FIG. The genetic algorithm (GA) execution unit 102 illustrated in FIG. 9 includes, for example, an initial population generation unit 110, a genetic operation processing unit 111, a fitness calculation unit 112, an end condition determination unit 113, and the like.

  The initial group generation unit 110 performs the processing of “generation of population” (S601) in the flow of FIG. The initial parameter value (setting value of the delay circuit) of each chromosome included in the generated initial population is sent to the timing simulator unit 101. The genetic operation processing unit 111 performs the processes of “selection cross mutation” (S603) and “replacement” (S605) in the flow of FIG. Information on the chromosomes to be children generated here is sent to the timing simulator unit 101.

  The fitness calculation unit 112 executes “processing for obtaining an evaluation value fit for each chromosome” performed in “generation of population” (S601) and “selective cross mutation” (S603) in the flow of FIG. To do. Specifically, for the information of each chromosome sent from the initial population generation unit 110 or the genetic operation processing unit 111 to the timing simulator unit 101, the timing simulator unit 101 holds normal data as the simulation result. The number nout of flip-flops out_i that are present is sent back. Therefore, the fitness calculation unit 112 calculates the fitness fit = nout / Nout corresponding to each chromosome using the total number Nout of the flip-flops out_i, and the fitness fit is calculated using the genetic operation processing unit 111 or the initial population generation unit. 110.

The termination condition determination unit 113 performs determination processing of “fit == 1.0” (S602 and S604) and “repetition of generations” (S606) in the flow of FIG. Specifically, the determination “if there is an individual whose fit is 1.0” in S602, the determination “if the evaluation value fit is 1.0” in S604, and “ Judgment is made even if a certain number of generations are repeated. As a result of the determination here, information indicating whether the adjustment has succeeded or failed is output to the outside through the I / O unit 100.
Although not shown, the genetic algorithm (GA) execution unit 102 requires a memory for storing all chromosome information and fitness information in the population in pairs.

  FIG. 10 is a block diagram showing a detailed configuration example of the timing simulator unit in the simulator of FIG. 10 includes, for example, a network generation unit 120, a timing information propagation unit 121, a virtual chip generation unit 122, a delay value setting unit 123, an output information determination unit 124, and the like.

  The network generation unit 120 is activated only once per series of adjustment simulations. Here, the directed graph of FIG. 3 is generated and stored based on the number of nodes, inter-node connection information, and input / output node information acquired from the outside. This information is shared with other processing units.

  The virtual chip generation unit 122 is activated once for each virtual chip having an assumed operating power supply voltage having an assumed operating frequency. Here, Tclk in equations (2) and (3) is calculated from the assumed operating frequency given from the outside, and is sent to the timing information propagation unit 121. Further, the Dij value of each arc corresponding to the assumed operating power supply voltage is acquired from the outside and sent to the delay value setting unit 123. This Dij value is stored in the memory in the virtual chip generation unit 122, and when the assumed operating power supply voltage value is the same when generating the virtual chip, the Dij value is not acquired from the outside. The Dij value held in the memory may be used. Further, the virtual chip generation unit 122 calculates Var_ij of all arcs according to the equation (6) and sends it to the delay value setting unit 123.

  The delay value generator 123 is activated each time chromosome information is sent from the genetic algorithm (GA) execution unit 102. Here, the delay value Di is set in the delay circuit of the node to be adjusted from the given chromosome information. A delay value 0 is set for a node that is not an adjustment target. After setting the delay value for all nodes, using the Dij value and Var_ij value sent from the virtual chip generation unit 122, the Dij '' of all arcs according to the equations (4) and (5). And is sent to the timing information propagation unit 121.

  The timing information propagation unit 121 uses the Tclk value and the Dij ″ value sent from the virtual chip generation unit 122 and the delay value setting unit 123 to propagate timing correctness information. Specifically, the processes [1A] to [3A] described in the explanation of FIG. 3 are performed.

  As a result of the timing information propagating unit 121 propagating the timing information, the output information determining unit 124 determines the number of nodes that can hold normal data among the nodes in the output data of FIG. 3, and inherits the number nout. To the local algorithm (GA) execution unit 102. Specifically, the process [4A] described in FIG. 3 is performed.

  As described above, the simulator shown in FIGS. 8 to 10 inserts a delay circuit by the delay value generator 123 into a plurality of virtual chips generated by the virtual chip generator 122 or the like as its main operation, and this delay. While searching for the delay time of the circuit by the genetic algorithm (GA) execution unit 102, the end condition determination unit 113 determines whether the adjustment is successful for each virtual chip. The yield of a plurality of virtual chips can be determined based on the success or failure of the adjustment. Therefore, based on the information obtained from the limitation of the delay circuit in FIG. 2, the chromosome length used in the genetic algorithm (GA) execution unit 102 is changed, and the node corresponding to this chromosome length is adjusted in the delay value generation unit 123. By inserting a delay circuit as an object and performing a similar simulation, it is possible to determine the yield improvement effect with respect to the number of delay circuits.

  Further, the simulator acquires data (for example, STA result) including the number of nodes, connection information between nodes, input / output node information, Dij of each arc, and the like from the outside, and a virtual chip corresponding to the acquired data It is possible to evaluate the yield as described above. Accordingly, even when various LSIs are targeted, since simulation can be performed if the STA result is available, it can be used for general purposes.

  Furthermore, this simulator can acquire the number of populations, the number of censored evaluations, the crossover probability, the mutation probability, etc. from the outside, and execute a genetic algorithm according to this information. Therefore, it is possible to search for optimum conditions by performing simulation while changing various conditions of such a genetic algorithm. The conditions obtained in this way can actually be used in the post-manufacturing clock adjustment (S108) in FIG. That is, since the conditions of the genetic algorithm that is actually performed after the manufacturing can be verified at the design stage, the manufacturing process can be made more efficient.

  Next, we will explain the experimental results that verified the effectiveness of applying the delay circuit limitation and adjustment simulation and the improvement of the initial population distribution of GA as described above to the actually designed large-scale LSI. .

  In this experiment, design information of a prototype LSI incorporating a delay circuit was used based on a DCT arithmetic circuit used for image compression / decompression processing designed at a design operation frequency of 200 MHz and a design operation power supply voltage of 1.0 V. The scale of this circuit is 30,000 gates and the number of flip-flops is 1031. Based on the results of the STA of this circuit, 100 virtual chips were created on the simulator as shown in FIGS. 8 to 10, and (1) the effect when the adjustment location was limited and (2) the GA initial population The effect of improving the distribution was compared in an adjustment experiment in the operating frequency direction.

In the adjustment experiment in the direction of the operating frequency, the operating power supply voltage was fixed at 1.0 V, the operating frequency was increased from 200 MHz to 320 MHz in increments of 10 MHz, and the yield was investigated for each operating frequency.
The GA conditions were set as follows.
Number of population: 50
Chromosome length: N adjustment points
Number of censored evaluations: 3000 (60 generations)
Crossover method: Uniform crossover probability: 0.5
Mutation method: Gaussian Mutation (mutation using normal distribution)
Mutation probability: 1.0
σGA: 72 ps
Upper and lower limit values of Di: -504 ps to 576 ps
The reason for setting the number of abort evaluations to 3000 is that, in an actual LSI, it is estimated that about 1 millisecond is required for one evaluation time. Therefore, the adjustment time per chip is suppressed to a practical limit of about several seconds. This is because about 3000 times is considered appropriate.

  Under the above conditions, the experiment was performed according to the following procedure.

[1B] The operating frequency is set, and it is confirmed whether or not normal operation is performed in a state where the adjustment value of the delay circuit is 0 (no adjustment state).
[2B] Since there is no need to adjust the chip that has normally operated in [1B], the process proceeds to [4B], and the chip that has not operated normally in [1B] proceeds to [3B].
[3B] The delay circuit using GA is adjusted. If the adjustment is successful, it is determined that the chip operates normally, and the process proceeds to [4B]. If the adjustment fails, it is determined that the chip does not operate normally, and the process proceeds to [4B].
[4B] Move to the next chip and repeat [1B] to [3B]. However, when the experiment with a certain number of chips is completed, the process proceeds to [5B].
[5B] Change the operating frequency and repeat [1B] to [4B]. When all the operating frequencies to be investigated are finished, the experiment is finished.

  Here, regarding the adjustment simulation time, the time taken to complete one trial of the above experimental procedure was about 14 hours on average. It can be said that the time required for the simulation experiment for confirming the optimal number of adjustment points is sufficiently realistic.

  Subsequently, regarding the yield improvement effect due to the limitation of the adjustment points, four adjustments of 100, 300, 600, 1031 (all points adjustment) were set for the limited number N of adjustment points, and each adjustment experiment was performed. FIG. 11 is a graph showing the adjustment experiment results when adjustment points are limited in the operating frequency direction. In FIG. 11, the operating frequency is set on the horizontal axis and the yield of the chip is set on the vertical axis, and the average yield before adjustment obtained by the adjustment experiment and the adjusted yield for each number of adjustment points are each represented by a line graph.

  As shown in FIG. 11, it can be seen that the yield is hardly improved by adjusting all of the 1031 positions. This is presumably because the search space is wide and the GA is not sufficiently converged under the censoring condition of 3000 times. Compared to that, it can be seen that the improvement in yield can be confirmed and the effect of adjustment can be obtained in the adjustment in the case where the adjustment location is limited. For example, at the operating frequency of 270 MHz, the yield is about 60% in the case where no adjustment is performed or in the adjustment of all the 1031 locations, whereas in the adjustment of 100 locations or 300 locations, the yield of 90% or more is obtained. ing. These results are because the convergence speed of the GA can be improved by reducing the search space.

Next, regarding the effect when the distribution of the GA initial population was improved, the adjustment experiment when the distribution of the GA initial population was improved in the adjustment experiments at 100 locations and 300 locations, which had a large effect due to the limitation of the adjustment locations described above. Went. FIG. 12 is a graph showing the adjustment experiment result when the GA is improved in the operating frequency direction. In FIG. 12, the operating frequency is set on the horizontal axis, and the chip yield is set on the vertical axis. In addition to the yields of the 100-point adjustment and the 300-point adjustment, which are relatively effective in the above-described experiment, The yield of the 100-point adjustment and the yield of the 300-point adjustment when the distribution of the GA initial population obtained in (2) is improved are respectively represented by line graphs.
As shown in FIG. 12, it can be seen that by improving the distribution of the initial population of GA, the yield at the adjustment of 300 locations is significantly increased. In particular, when looking at the yield of the chip at the operating frequency of 280 MHz, the yield of about 15% in the adjustment of the 300 locations by the GA before the improvement was about 10% by adjusting the 300 locations by the improved GA. It improved to about 90%. This is because by improving the distribution of the initial population of GA, the GA was sufficiently converged within the number of truncations of 3000 times.

  On the other hand, the adjustment yield at 100 locations hardly increased after the distribution improvement of the initial population. This is because the necessary delay circuits are not sufficient in the adjustment at 100 locations, and the yield cannot be further improved. Therefore, in this experiment, the result that the adjustment effect was the greatest when the adjustment location was limited to 300 locations was obtained.

As described above, this experiment confirmed that beneficial effects can be obtained when the delay circuit limitation and adjustment simulation and the improvement of the initial population distribution of GA are applied to a large-scale LSI.
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The digital system design system and manufacturing method of the present invention is a technology that is particularly useful when applied to a large-scale digital system design system and manufacturing method having a programmable delay circuit whose value is adjusted by a genetic algorithm. However, the present invention is not limited to this, and can be widely applied to all digital systems having a programmable delay circuit.

It is a process flow figure showing an example of the processing in the manufacturing method of the digital system by one embodiment of the present invention. FIG. 3 is a flowchart showing an example of detailed processing contents when limiting the delay circuit (S103) in the digital system manufacturing method shown in FIG. 1; FIG. 2 is a conceptual diagram showing an example of a simulation model used in the adjustment simulation in the digital system manufacturing method shown in FIG. 1. It is a figure explaining the processing content at the time of confirming operation | movement with respect to the simulation model of FIG. 3, and represents the operation | movement model of a flip-flop. It is a figure explaining the processing content at the time of confirming operation | movement with respect to the simulation model of FIG. 3, and represents the transition model of the operation state of a flip-flop. FIG. 2 is a flowchart showing an example of detailed processing of post-manufacturing clock adjustment using the genetic algorithm (GA) in the digital system manufacturing method shown in FIG. 1. FIG. 7 is a schematic diagram illustrating a difference in distribution of an initial population between a uniform random number and a normal random number in the population generation processing in FIG. 6. FIG. 2 is a block diagram illustrating a configuration example of a simulator used in the adjustment simulation in the digital system manufacturing method illustrated in FIG. 1. FIG. 9 is a block diagram illustrating a detailed configuration example of a genetic algorithm (GA) execution unit in the simulator of FIG. 8. FIG. 9 is a block diagram illustrating a detailed configuration example of the timing simulator unit in the simulator of FIG. 8. It is a graph which shows the adjustment experiment result at the time of the adjustment location limitation in an operating frequency direction. It is a graph which shows the adjustment experiment result at the time of GA improvement in an operating frequency direction. 1 is a block diagram showing a configuration example of a digital system design system studied as a premise of the present invention. FIG. FIG. 14 shows a pipeline type circuit as an example of the digital system of FIG. 13, and (a) to (c) show cases where operating conditions are different from each other. It is the schematic which shows the structural example of the chromosome used by a genetic algorithm. In the genetic algorithm, an example of an operation performed on a chromosome is shown, and (a) and (b) are schematic diagrams showing an example of an operation of crossover and mutation, respectively. It is a conceptual diagram which shows a mode that operation advances with a genetic algorithm.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Digital system 2 Power supply device 3 Digital test signal generator 4 Adjustment apparatus 5 Digital signal observation apparatus 6 Power supply 7 Logic level 71,72 distribution of internal node 100 I / O part 101 Timing simulator part 102 Genetic algorithm execution part 110 Initial stage Group generation unit 111 Genetic operation processing unit 112 Fitness calculation unit 113 End condition determination unit 120 Network generation unit 121 Timing information propagation unit 122 Virtual chip generation unit 123 Delay value setting unit 124 Output information determination unit FF Flip-flop REG register DLY Delay Circuit Din Data input signal Dout Data output signal CLK Clock signal CC Combinational circuit CH Chromosome

Claims (19)

Realized by computer program processing,
The digital system in which the timing margin of the path between the plurality of flip-flops can be adjusted by providing a programmable delay circuit in the clock input unit of the plurality of flip-flops,
A first function for obtaining a connection relationship between the plurality of flip-flops and a path delay time between the plurality of flip-flops from a timing analysis result at a design stage for the digital system;
Based on the connection relationship between the plurality of flip-flops acquired in the first function, a path from the preceding flip-flop to the succeeding flip-flop is an arc, and the preceding flip-flop and the succeeding flip-flop are respectively set as nodes. A second function for generating a simulation model of the directed graph,
When the arc has propagation time information and the arc has a propagation time satisfying a predetermined specification, the first information is stored in a node connected to the end of the arc to satisfy the predetermined specification. If there is no node, the second information is stored in a node connected to the tip of the arc. If there is a node in which the second information is stored, the second information is transmitted between the nodes according to the direction of the arc. A third function to perform,
A fourth function for searching the set time based on a probabilistic search method so that the node can store the first information while changing the set time of the programmable delay circuit;
The propagation time of the arc is the second delay reflecting the path delay time acquired by the first function, the first delay time reflecting manufacturing variation, and the set time of the programmable delay circuit by the fourth function. A digital system design system characterized by being determined based on time. The digital system design system according to claim 1,
Furthermore, based on the size of the path delay time acquired by the first function, a fifth function for limiting the path to be adjusted by the programmable delay circuit,
The design system of a digital system, wherein the second delay time of an arc corresponding to a path limited by the fifth function is determined by a probabilistic search method based on the fourth function. The digital system design system according to claim 2,
The fifth function is a digital system design system characterized in that sorting is performed in descending order of the path delay time, and the paths are limited in the order obtained by the sorting. The digital system design system according to claim 2,
The design system of the digital system, wherein the programmable delay circuit is provided at both ends of a path defined by the fifth function. The digital system design system according to claim 1,
The digital system design system, wherein the probabilistic search method is a method based on a genetic algorithm. The digital system design system according to claim 1,
The digital system design system, wherein the timing analysis result in the first function is a result of static timing analysis. The digital system design system according to claim 1,
The digital system design system, wherein the first delay time is determined based on a normal random number. Realized by computer program processing,
The digital system in which the timing margin of the path between the plurality of flip-flops can be adjusted by providing a programmable delay circuit in the clock input unit of the plurality of flip-flops,
Based on manufacturing variation with respect to the path delay time, using the connection relationship between the plurality of flip-flops obtained from the timing analysis result of the design stage for the digital system and the path delay time between the plurality of flip-flops Reflecting the distribution and the adjustment value by the programmable delay circuit, a first function for generating a plurality of virtual chips each having a different amount of variation in the path delay time and the path delay time being adjustable by the programmable delay circuit; ,
An adjustment value of the programmable delay circuit is searched for the plurality of virtual chips based on a probabilistic search method, and an adjustment value of the programmable delay circuit is obtained such that the path delay time falls within a predetermined specification. a second function of determining was whether to each of the plurality of virtual chips,
A third function for limiting a path to be adjusted by the programmable delay circuit based on the size of the path delay time used in the first function;
The digital system design system , wherein the second function performs a search based on a probabilistic search method for the programmable delay circuit corresponding to the path limited by the third function . 9. The digital system design system according to claim 8, wherein:
The design system of the digital system, wherein the programmable delay circuit is provided at both ends of a path defined by the third function. 9. The digital system design system according to claim 8, wherein:
The digital system design system, wherein the probabilistic search method is a method based on a genetic algorithm. 9. The digital system design system according to claim 8, wherein:
The digital system design system, wherein the timing analysis result in the first function is a result of static timing analysis. 9. The digital system design system according to claim 8, wherein:
A distribution system based on manufacturing variation in the first function is determined based on normal random numbers. A first step of manufacturing a digital system in which a programmable delay circuit is provided in a clock input section of a plurality of flip-flops, so that a timing margin of a path between the plurality of flip-flops can be adjusted;
While testing the electrical characteristics of the digital system manufactured in the first step, the delay time of the programmable delay circuit is determined based on a probabilistic search method so that the test result satisfies a predetermined specification. A second step of searching;
A third step of performing timing analysis on the digital system in the design stage of the digital system, which is a step before the first step;
A fourth process is performed between the third process and the first process, and a predetermined number of paths having a small timing margin are selected from the paths between the plurality of flip-flops based on the result of the timing analysis. Process,
Generate virtual chips on the simulation in which the programmable delay circuit is inserted for the predetermined number of paths selected in the fourth step, and simulate the yield that is the ratio of the virtual chips that satisfy a predetermined timing specification. A fifth step of predicting the optimum number of insertions of the programmable delay circuit that can obtain a high yield by performing the evaluation while changing the predetermined number selected in the fourth step. Yes, and
In the first step, a digital system having the number of insertions of the programmable delay circuit predicted in the fifth step is manufactured . The method of manufacturing a digital system according to claim 13 ,
The probabilistic search method is a method based on a genetic algorithm,
In the second step, the initial group generated based on the genetic algorithm is given a distribution based on manufacturing variation, and the digital system manufacturing method is characterized in that: 15. The method of manufacturing a digital system according to claim 14 ,
The method for manufacturing a digital system, wherein the distribution based on the manufacturing variation is a normal distribution. The method of manufacturing a digital system according to claim 13 ,
The fifth step includes
Using the connection relationship between the plurality of flip-flops obtained from the result of the timing analysis in the third step and the path delay time between the plurality of flip-flops, and further manufacturing variations with respect to the path delay time By reflecting the distribution based on the above and the adjustment value by the programmable delay circuit, a plurality of virtual chips in which the variation amount of the path delay time is different and the path delay time can be adjusted by the programmable delay circuit are generated. Processing,
Using the plurality of virtual chips, an adjustment value of the programmable delay circuit corresponding to the predetermined number of paths selected in the fourth step is searched based on a probabilistic search method, and the path delay time is determined in advance. It is determined whether or not the predetermined number selected in the fourth step is appropriate by determining, for each of the plurality of virtual chips, whether or not the adjustment value of the programmable delay circuit that is within the specifications is obtained. And a second process. A method for manufacturing a digital system, comprising: The method of manufacturing a digital system according to claim 16 ,
The probabilistic search method is a method based on a genetic algorithm,
In the second step, the initial group generated based on the genetic algorithm is given a distribution based on manufacturing variation, and the digital system manufacturing method is characterized in that: The method of manufacturing a digital system according to claim 17 ,
The method for manufacturing a digital system, wherein the distribution based on the manufacturing variation is a normal distribution. The method of manufacturing a digital system according to claim 16 ,
The method of manufacturing a digital system, wherein the result of the timing analysis in the third step is a result of a static timing analysis.

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