JP4783199B2 - Voltage controlled oscillator - Google Patents

Description

  The present invention relates to a voltage controlled oscillator (hereinafter referred to as “VCO”) whose oscillation frequency changes according to a control voltage, and more particularly to a technique for expanding the oscillation frequency range.

FIG. 2 is a configuration diagram of a conventional VCO.
In this VCO, a resonant tank circuit composed of an inductor 2 and a variable capacitor 3 is connected in parallel to a negative resistance circuit 1, and fixed capacitors 4a, 4b, and 4c are used as switch MOSs in order to expand the oscillation frequency range. The transistors are connected in parallel via transistors (hereinafter simply referred to as “MOS”) 5a, 5b, 5c.

  The variable capacitor 3 uses, for example, a MOS gate capacitance, and the capacitance can be changed by applying a control voltage VC to the gate. In this variable capacitor 3, the capacitance value monotonously decreases from 2 pF to 1 pF by sweeping the control voltage VC from 0V to 2V.

  On the other hand, the capacitance values of the fixed capacitors 4a, 4b, and 4c are set to have a power-of-two relationship of 0.3 pF, 0.6 pF, and 1.2 pF, respectively. As a result, the capacitance value of the fixed capacitor can be switched in 8 steps from the maximum of 2.1 pF in units of 0.3 pF by the combination of the control signals S1 to S3 given to the gates of the switching MOSs 5a to 5c. The voltage across the negative resistance circuit 1 is amplified by a buffer amplifier (AMP) 6 and output from the amplifier 6 as an oscillation signal OUT.

  In this VCO, when a voltage (for example, a power supply voltage) sufficiently higher than the threshold voltages of the MOSs 5a to 5c is applied as the control signals S1 to S3, the MOSs 5a to 5c are turned on and the fixed capacitors 4a and 4b are turned on. , 4c are connected to the resonant circuit. When a low voltage (for example, ground voltage) is applied as the control signals S1 to S3, the MOSs 5a to 5c are turned off and the fixed capacitors 4a, 4b, and 4c are disconnected. Thereby, the range of the oscillation frequency can be switched by switching the voltages of the control signals S1 to S3, and the oscillation frequency is continuously changed within the frequency range by continuously changing the control voltage VC. Can be controlled.

Japanese Patent Application No. 2004-325385

  In the VCO, the capacitance values of the fixed capacitors 4a, 4b, and 4c are set to have a power-of-two relationship, and this is switched by the switching MOSs 5a to 5c and connected in parallel to the resonance circuit. Yes. However, due to the effect of the switching MOS connected in series with the fixed capacitor, the oscillation frequency range shifts because it does not match the intended capacitance. That is, even when the switch MOS is turned off, the MOS has a parasitic capacitance.

  The parasitic capacitance of the MOS includes an overlap capacitance Cgs between the gate portion and the source portion, an overlap capacitance Cgd between the gate portion and the drain portion, a junction capacitance Csb between the source portion and the bulk portion, and a junction capacitance Cdb between the drain portion and the bulk portion. . The overlap capacitances Cgs and Cgd connected in series and the junction capacitances Csb and Cdb are effective drain-source capacitances.

  For this reason, the series circuit of the capacitance of the MOS and the corresponding fixed capacitor is connected to the resonance circuit, and the fixed capacitor that should have been turned off cannot be completely separated. For this reason, when the control signals S1 to S3 are used to switch on / off the switching MOSs 5a to 5c to switch the frequency range, and the oscillation frequency is controlled by the control voltage VC within a certain range, the predetermined oscillation frequency range is covered. There was a problem that it was impossible.

  FIG. 3 is a voltage-frequency characteristic diagram of the VCO of FIG. 2, in which the horizontal axis represents the control voltage VC [V] and the vertical axis represents the oscillation frequency [MHz]. In this figure, the parameter n represents the control signals S1 to S3 as a 3-bit value of (S3 S2 S1). As shown in FIG. 3, when a range of 0.5 to 1.0 V is used as the control voltage VC, an oscillation frequency of, for example, 1400 MHz cannot be obtained regardless of how the frequency range is switched.

  An object of the present invention is to provide a VCO that can obtain a wide range of continuous oscillation frequencies by switching the frequency range according to a control signal.

The VCO of the present invention includes a negative resistance circuit connected between a first node and a second node, an inductor connected between the first node and the second node, and the first node and the second node. And a first variable capacitor whose capacitance value is controlled according to a control voltage, and a switch for the switch controlled by an independent control signal between the first node and the second node. The n fixed capacitors from 1 to n (where n is an integer of 2 or more) connected via the MOS and each of the n fixed capacitors are provided in parallel, and the control voltage is depending from a first value of the capacitance is controlled by a second variable capacitor up to the n, the first node and Bei Eteiru an amplifier for amplifying the signal of the second node to output an oscillation signal.
Then, the i-th of the fixed capacitor (where, i is an integer from 2 to n) fixed capacitor has a capacitance Ci, the capacitance Ci-1 of the (i-1) of the fixed capacitor The capacity ratio Ci / Ci-1 is set to a value of 1 or more and 2 or less . Furthermore, the i-th second variable capacitor among the second variable capacitors has a capacitance CVi at a specific control voltage, and the electrostatic capacitance at the specific control voltage of the (i−1) -th second variable capacitor. The capacity ratio CVi / CVi-1 with the capacity CVi-1 is set to be a value between 1 and 2.

According to the present invention , the capacitance of the fixed capacitor connected between the first node and the second node via the switching MOS in order to switch the oscillation frequency range is not a power of 2 relationship. The capacity ratio is set to be 1 or more and 2 or less . Thereby, the influence of the parasitic capacitance of the MOS for the switch in the off state is suppressed, and a continuous wide range of oscillation frequencies can be obtained by switching the frequency range .
Further, the capacitance ratio CVi / CVi−1 between the electrostatic capacitance CVi of the i-th second variable capacitor and the electrostatic capacitance CVi−1 of the i−1th variable capacitor is a value of 1 or more and 2 or less. Is set. Thereby, especially in the range where the oscillation frequency is low, the reduction of the frequency variable range can be suppressed.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a configuration diagram of a VCO showing Embodiment 1 of the present invention.
In this VCO, a negative resistance circuit 10, an inductor 20, and a variable capacitor 30 are connected in parallel between a node N1 and a node N2, and fixed capacitors 41, 42, and 43 for switching a frequency range are respectively connected to a switching MOS 51. , 52, 53 to be connected in parallel.

  In the negative resistance circuit 10, for example, two sets of CMOS inverters I1 and I2 are connected in the opposite direction between nodes N1 and N2. That is, a CMOS inverter I1 composed of a P-channel MOS (hereinafter referred to as “PMOS”) 11 and an N-channel MOS (hereinafter referred to as “NMOS”) 12, and a CMOS composed of PMOS 13 and NMOS 14 between the power supply potential VDD and the ground potential GND. Inverter I2 is connected. The input side of the CMOS inverter I1 is connected to the node N2, and the output side is connected to the node N1. On the other hand, the input side of the CMOS inverter I2 is connected to the node N1, and the output side is connected to the node N2.

  For example, the inductor 20 is a fixed inductor having an inductance of 4.5 nH.

  The variable capacitor 30 uses, for example, a MOS gate capacitance, and the capacitance can be changed by applying a control voltage VC to the gate. In the variable capacitor 30, the capacitance value monotonously decreases from 2 pF to 1 pF by sweeping the control voltage VC from 0 V to 2 V.

  On the other hand, the capacitance values C1, C2, and C3 of the fixed capacitors 41, 42, and 43 are 0.35 pF, 0.6 pF, and 1.06 pF, respectively, and the capacitance value ratio C2 / C1, C3 / C2 is 1 respectively. .7, 1.78, and the capacity ratio is set to be 1 or more and less than 2.

  The switching MOSs 51, 52 and 53 are of the same size, and are turned on when the control signals S1 to S3 applied to the respective gates are at the power supply voltage VDD (logic ground 1), and the ground voltage GND (logic It is in the off state at the time of the ground 0). The MOSs 51, 52, and 53 are designed to exhibit a parasitic capacitance of 0.2 pF in the off state. A buffer amplifier 60 is connected to the nodes N1 and N2, and an oscillation signal OUT is output from the amplifier 60.

  In this VCO, when a voltage sufficiently higher than the threshold voltage of the MOSs 51 to 53 (that is, the power supply voltage VDD) is applied as the control signals S1 to S3, the MOSs 51 to 53 are turned on and the fixed capacitors 41 and 42 are turned on. , 43 are connected between the nodes N1 and N2, the capacitance of the resonance circuit increases and the oscillation frequency decreases.

  Further, when a low voltage (that is, the ground voltage GND) is applied to the control signals S1 to S3, the MOSs 51 to 53 are turned off, and the parasitic capacitance of the MOSs 51 to 53 and the electrostatic capacitance generated by the series circuit of the fixed capacitors 41, 42, and 43. A capacitor is connected between the nodes N1 and N2.

  Thereby, the range of the oscillation frequency can be switched by switching the voltages of the control signals S1 to S3, and the oscillation frequency is continuously changed within the frequency range by continuously changing the control voltage VC. Can be controlled.

  FIG. 4 is a voltage-frequency characteristic diagram of the VCO of FIG. 1, in which the horizontal axis represents the control voltage VC [V] and the vertical axis represents the oscillation frequency [MHz]. In this figure, the parameter n represents the control signals S1 to S3 as a 3-bit value of (S3 S2 S1). As shown in FIG. 4, the characteristic curves corresponding to the values 0 to 7 of the parameter n are arranged at almost equal intervals. For example, even when the variable range of the control voltage VC is 0.5 to 1.0 V, the frequency range is changed. By switching, the frequency range from the lowest 1230 MHz to the highest 1680 MHz can be completely covered.

  Next, the relationship between the range of the oscillation frequency in the first embodiment and the value n of the control signals S1 to S3 will be described.

The oscillation frequency f (n) is fixed to the parasitic capacitance connected between the nodes N1 and N2 by the MOSs 51 to 53 controlled by the control signals S1 to S3, and the inductance of the inductor 20 is L, the capacitance value of the variable capacitor 30 is Cx. When the combined capacitance value of the capacitors is C (n), the following proportional relationship is established.
f (n) ∝1 / √ {L (Cx + C (n))} (1)
When Cx is larger than Cn, the following approximate expression holds.
f (n) / f (n + 1) ≈1 + {C (n) −C (n + 1)} / 2Cx
Therefore, in order to make the rate of change of f (n) constant when n is changed, it is necessary to make the change of C (n) constant. In the case of Example 1, the operation is as follows.
C (0) = 1.24 pF
C (1) = 1.47 pF, C (1) -C (0) = 0.23 pF
C (2) = 1.69 pF, C (2) -C (1) = 0.22 pF
C (3) = 1.91 pF, C (3) -C (2) = 0.22 pF
C (4) = 2.14 pF, C (4) -C (3) = 0.23 pF
C (5) = 2.36 pF, C (5) -C (4) = 0.22 pF
C (6) = 2.58 pF, C (6) -C (5) = 0.22 pF
C (7) = 2.80 pF, C (7) -C (6) = 0.22 pF

  Thus, it can be seen that C (n + 1) -C (n) is substantially constant. This can be explained as follows.

The combined capacitance value C (n) is the sum of the capacities of the on-state MOSs 51-53 and the fixed capacitors 41-43, Cf, the number of off-state MOSs 51-53 is k, and the parasitic capacitance of the off-state MOSs 51-53 is Cp. Then, when Cp is smaller than Cf, it can be approximated as follows.
C (n) ≈k × Cp + Cf
Here, the number k of the MOSs 51 to 53 which are turned off is as follows depending on the value of n.
When n = 0 k = 3
When n = 1, k = 2
When n = 2, k = 2
When n = 3, k = 1
When n = 4, k = 2
When n = 5, k = 1
When n = 6, k = 1
When n = 7, k = 0

  Therefore, when the MOS 51 changes from off to on, that is, when n is switched from 0 to 1, 2 to 3, or 4 to 5, the contribution of the parasitic capacitance Cp is reduced, whereas the MOS 52 is off. When turning on, i.e., when n is switched from 1 to 2 or from 5 to 6, the contribution of the parasitic capacitance Cp does not change. On the other hand, when the MOS 53 changes from off to on, that is, when n is switched from 3 to 4, the contribution of the parasitic capacitance Cp increases. The difference between these changes is offset by setting the capacitance ratio to a value of 1 or more and less than 2 without making the capacitances of the fixed capacitors 41 to 43 a power of 2, and the combined capacitance value C (n) is It becomes possible to change smoothly, and voltage-frequency characteristics as shown in FIG. 4 can be obtained.

  As described above, in the VCO according to the first embodiment, the capacitance ratio C2 / C1, of the capacitance values C1, C2, and C3 of the fixed capacitors 41 to 43 inserted in parallel between the nodes N1 and N2 according to the control signals S1 to S3. C3 / C2 is set to be 1 or more and less than 2. As a result, the influence of the parasitic capacitance Cp of the MOSs 51 to 53 in the off state is reduced, and variation in the frequency change width when the control signals S1 to S3 are switched is suppressed. There is an advantage that a VCO capable of outputting a wide range of oscillation frequencies can be obtained.

  FIG. 5 is a configuration diagram of a VCO showing Embodiment 2 of the present invention, and elements common to those in FIG. 1 are denoted by common reference numerals.

  This VCO is obtained by adding variable capacitors 71, 72, 73 in parallel via the switching MOSs 81, 82, 83 between the node N1 and the node N2 of the VCO of FIG. Similar to the variable capacitor 30, the control voltage VC is commonly applied to the variable capacitors 71, 72, and 73. Similarly to the MOSs 51, 52, and 53, control signals S1, S2, and S3 are supplied to the gates of the switching MOSs 81, 82, and 83, respectively. Other configurations are the same as those in FIG. 1 except for the inductance of the inductor 20 and the capacitance value of each capacitor.

  Here, the capacitance value of the variable capacitor 30 monotonously decreases from 1.05 pF to 0.53 pF by sweeping the control voltage VC from 0V to 2V. The capacitance values C1, C2, and C3 of the fixed capacitors 41, 42, and 43 are set to 0.25 pF, 0.41 pF, and 0.70 pF, respectively, and the capacitance ratios C2 / C1, C3 / C2 are values of 1 or more and 2 or less. It has become. The switching MOSs 51 to 53 and 81 to 83 are all the same size, and the parasitic capacitance Cp in the off state is 0.2 pF.

  Furthermore, the variable capacitors 71, 72, 73 sweep the control voltage VC from 0V to 2V, so that their capacitance values are 0.25-0.12 pF, 0.40-0.20 pF, 0.69-0. Each of them decreases monotonously between 34 pF. The capacitance values CV1, CV2, and CV3 of these variable capacitors 71, 72, and 73 have a capacitance ratio CV2 when the control voltage VC is the same (for example, when the voltage is a specific voltage such as 0.5 V or 1.0 V). / CV1, CV3 / CV2 are set to be 1 or more and 2 or less.

  FIG. 6 is a voltage-frequency characteristic diagram of the VCO of FIG. 5, in which the horizontal axis represents the control voltage VC [V], and the vertical axis represents the oscillation frequency [MHz] corresponding to the control voltage VC. Here, the inductance of the inductor 20 is set to 3.5 nH.

  As shown in FIG. 6, the characteristic curves corresponding to the values 0 to 7 of the parameter n are arranged at almost equal intervals. For example, even when the variable range of the control voltage VC is 0.5 to 1.0 V, the frequency range By switching, it is possible to completely cover the frequency range from the lowest 1230 MHz to the highest 1680 MHz.

  Further, as shown in FIG. 6, in this VCO, the ratio of the frequency change to the change in the control voltage VC, that is, the slope of the voltage-frequency characteristic curve corresponding to each value 0 to 7 of the parameter n is substantially constant. I understand that there is.

  Next, the relationship between the oscillation frequency f in Example 2 and the value n of the control signals S1 to S3 will be described.

The oscillation frequency f is the combined capacitance value of the fixed capacitor and the parasitic capacitance connected between the nodes N1 and N2 by the MOS controlled by the control signals S1 to S3, and the inductance value of the inductor 20 is L, the capacitance value of the variable capacitor 30 is CV. Is C (n), the expression (1) shown in the first embodiment is established. Therefore, the ratio of the frequency when the control voltage VC is v1 and the frequency when v2 is as follows.
f (v2) / f (v1)
∝1 / √ {(CV (v1) + C (n)) / (CV (v2) + C (n))}
Increasing the value n from 0 increases the value of C (n). At this time, as the value n increases, CV (v) also increases, so f (v2) / f (v1) does not decrease and is maintained at substantially the same value. Thereby, the dependence of the oscillation frequency f on the value n of the control signals S1 to S3 is suppressed. For example, in the frequency range where the oscillation frequency is low, such as when the value n = 7, the frequency variable range is set as compared with the VCO in FIG. Can be enlarged.

  As described above, in the VCO according to the second embodiment, the variable capacitors 71, 72, and 73 whose capacitance values are changed by the control voltage VC are provided in parallel with the fixed capacitors 41 to 43 for switching the frequency range. Then, the capacitance ratios C2 / C1, C3 / C2 of the capacitance values C1, C2, and C3 of the fixed capacitors 41 to 43 are set to be 1 or more and 2 or less, and the capacitances of the variable capacitors 71, 72, and 73 are set. The capacity ratios CV2 / CV1 and CV3 / CV2 of the values CV1, CV2, and CV3 are also set to be 1 or more and 2 or less. Thereby, in addition to the same advantages as those of the first embodiment, there is an advantage that the frequency variable widths in the respective frequency ranges switched by the control signals S1 to S3 can be set to substantially the same value. Accordingly, since the variable frequency range is not narrowed particularly in the range where the oscillation frequency is low, stable operation can be performed when applied to a phase locked loop or the like.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) The number of the fixed capacitors 41 to 43 in the first embodiment, and the number of the fixed capacitors 41 to 43 and the variable capacitors 71 to 73 in the second embodiment is not limited to three, and an arbitrary plural n may be used. Can do. In this case, of the n fixed capacitors, the i-th fixed capacitor (where i is an integer from 2 to n) has a capacitance Ci, and the capacitance Ci− of the i−1th fixed capacitor. What is necessary is just to set so that the capacity ratio Ci / Ci-1 with 1 may become the value of the range of 1-2. Also, the capacitance of the variable capacitor needs to be set to have the same relationship as that of the fixed capacitor.
(B) In the second embodiment, the fixed capacitors 41 to 43 and the variable capacitors 71 to 73 are connected between the nodes N1 and N2 via different switch MOSs 51 to 53 and 81 to 83, respectively. If the capacitors 41 to 43 and the variable capacitors 71 to 73 are connected in parallel, the switching MOSs 81 to 83 are unnecessary.
(C) The configuration of the negative resistance circuit 10 is not limited to that illustrated in FIG. In other words, any circuit that feeds back the signal of the node N1 to the node N2 and causes an oscillation operation may be used.

It is a block diagram of VCO which shows Example 1 of this invention. It is a block diagram of the conventional VCO. FIG. 3 is a voltage-frequency characteristic diagram of the VCO in FIG. 2. FIG. 2 is a voltage-frequency characteristic diagram of the VCO in FIG. 1. It is a block diagram of VCO which shows Example 2 of this invention. FIG. 6 is a voltage-frequency characteristic diagram of the VCO in FIG. 5.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Negative resistance circuit 20 Inductor 30,71-73 Variable capacitor 41-43 Fixed capacitor 51-53, 81-83 MOS
60 amplifier

Claims (1)

A negative resistance circuit connected between the first node and the second node;
An inductor connected between the first node and the second node;
A first variable capacitor connected between the first node and the second node and having a capacitance value controlled according to a control voltage;
The first to nth (where n is an integer of 2 or more) n connected between the first node and the second node via switching MOS transistors controlled by independent control signals. Fixed capacitors,
First to n-th second variable capacitors provided in parallel to each of the n fixed capacitors, the capacitance value of which is controlled according to the control voltage;
An amplifier for amplifying signals of the first node and the second node and outputting an oscillation signal;
Among the fixed capacitors, the i-th (where i is an integer from 2 to n) fixed capacitor has a capacitance Ci, and the capacitance ratio of the i-1th fixed capacitor with the capacitance Ci-1. the ci / ci-1, set to be 1 to 2 values,
The i-th second variable capacitor among the second variable capacitors has a capacitance CVi at a specific control voltage, and the capacitance CVi− at the specific control voltage of the (i−1) -th second variable capacitor. 1. A voltage controlled oscillator characterized in that a capacity ratio CVi / CVi−1 to 1 is set to a value of 1 or more and 2 or less .

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