JP4775162B2 - Clock data recovery circuit and electronic device - Google Patents

Description

  The present invention relates to a clock data recovery circuit and an electronic apparatus, and more particularly to a clock data recovery circuit and an electronic apparatus for recovering a clock and data at a high speed with respect to a received signal.

  Conventionally, as disclosed in, for example, Japanese Patent Laid-Open No. 2001-251286, a technique for adding a preamble including a predetermined signal sequence prior to data to be transmitted is known. FIG. 9 shows the configuration of a conventional clock data recovery circuit for processing an input signal with such a preamble. FIG. 10 shows the configuration of an input signal accompanied by a preamble.

  When signals are transmitted intermittently (the same applies to packet-like signals), a preamble may be added to the input signal as shown in FIG. 10 in order to facilitate clock recovery on the receiving side. In the receiving apparatus, signal processing is performed with a clock that fluctuates at a frequency equivalent to the frequency of the input signal. However, since the phase of the input signal and the phase of the clock are usually not synchronized, the receiving side must adjust the synchronization of the input signal and the clock before performing signal processing.

  The preamble is composed of, for example, alternating signals “0” and “1”. FIG. 11 shows the waveform of such a preamble added to the input signal. When a clock is recovered from an intermittent input signal, generally, the phase timing of the input signal is first estimated using the preamble portion. If the phase timing is properly estimated, then the phase timing and the clock are adjusted synchronously.

  The conventional clock data recovery circuit 10 shown in FIG. 9 includes a phase timing detection circuit 12 and a recovery clock generation circuit 14. The phase timing detection circuit 12 detects the phase timing of the input signal as shown in FIG. Here, FIG. 11 shows a waveform of a preamble composed of alternating signals “0” and “1”. The “phase timing” refers to the timing at which the signal value switches between “0” and “1” as shown in FIG.

  FIG. 12 shows a case where the phase timing of the input signal (preamble) matches the trigger edge (here, the up edge) of the clock. In the receiving device, signal latching is performed in synchronization with the trigger edge of the clock. Therefore, when the input signal and the clock have a relationship as shown in FIG. 12, the value of the input signal cannot be correctly processed on the receiving side.

  FIG. 13 is a timing chart for explaining a method in which the phase timing detection circuit 12 detects the phase of the input signal. Specifically, FIG. 13A shows a waveform of an input signal (preamble), and FIGS. 13B to 13D show waveforms of delayed signals obtained by delaying the input signal in stages. . FIG. 13E shows the waveform of the receiving clock.

  The phase timing detection circuit 12 generates multi-stage delay signals as shown in FIGS. 13B to 13D based on the input signal, and latches each signal according to the clock. Alternatively, the phase timing detection circuit 12 generates a multi-stage delay clock based on the reference clock, and latches the input signal in accordance with each clock.

  In this case, for a signal whose phase timing overlaps with the trigger edge of the clock, the signal value to be latched becomes unstable. On the other hand, for signals whose phase timing deviates from the trigger edge, the latched value is the preamble signal value, that is, the alternating value of “0” and “1”. Therefore, the phase timing detection circuit 12 compares the degree of coincidence between the latched signal sequence and the alternating signal sequence of “0” and “1” for each combination of signal and clock, and thereby the phase relationship between the input signal and the clock. Can know.

  The reproduction clock generation circuit 14 shown in FIG. 9 is a circuit that generates a clock whose phase is adjusted with respect to an input signal. That is, when the phase timing detection circuit 12 is a type of circuit that generates a multi-stage delay clock, it is a circuit that selects a clock that can latch the input signal most correctly as a reproduction clock. In this case, the reproduction clock generation circuit 14 specifically latches the signal sequence having the highest degree of coincidence with the alternating signal sequence of “0” and “1” among the reference clock and all the delayed clocks. The clock is the playback clock.

  The clock and the input signal thus selected satisfy the relationship as shown in FIGS. 13D and 13E. Thereafter, on the receiving side, data included in the input signal can be correctly processed by performing signal processing with the clocks adjusted in synchronization as described above.

JP 2001-251286 A

  FIG. 14 is a diagram for explaining a problem of the conventional clock data recovery circuit shown in FIG. In wireless communication, signal values often fluctuate greatly due to noise or fading. For this reason, when the phase timing detection circuit 12 detects the phase timing of the input signal, it is necessary to perform phase comparison processing over a sufficiently long phase timing detection period T.

  In FIG. 14, T (1), T (2), T (3), and T (4) indicate periods during which phase timing is detected in the conventional circuit. That is, the conventional circuit always waits for input of a signal, and repeatedly performs the phase timing detection process for each phase timing detection period T until it is determined that the phase timing detection is completed, as shown in FIG. .

  In wireless communication assuming a noisy environment, a phase timing detection period T that enables comparison of several hundred bits may be required to ensure the accuracy of phase timing detection. In FIG. 14, signal input is started in the middle of the period T (3), and a desired number of comparisons cannot be obtained in the period T (3), and the phase timing can be detected by the process in the period T (4). An example is shown.

  As shown in the above example, the phase timing detection period T on the receiving side and the generation timing of the input signal are not synchronized. For this reason, depending on the generation time of the input signal, a situation in which most of the phase timing detection period T is spent for useless comparison may occur. More specifically, for example, when an input signal is generated immediately after the start of the phase timing detection period T (n) and a desired number of comparisons cannot be obtained in the period T (n), the phase timing is detected. It can happen that approximately 2 * T of time is required to complete the detection.

  On the receiving side, it is necessary to finish detecting the phase timing before starting to process the data portion of the input signal. That is, it is necessary to finish the detection of the phase timing during the preamble reception period. For this reason, if 2 * T time is required to detect the phase timing, it is necessary to add a preamble for 2 * T time to the input signal prior to data. For this reason, the conventional system has a problem that the amount of data transmission is greatly reduced due to the enlargement of the preamble, particularly when phase timing detection with high accuracy is required.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a clock data recovery circuit that enables clock recovery and data recovery with a short preamble.

In order to achieve the above object, a first invention is a clock data recovery circuit that receives an input signal including a preamble and data and recovers synchronization of a clock and data.
At each first set time, it is determined whether or not the preamble has been input based on a comparison between the signal sequence input during the first time and the specific signal sequence included in the preamble. Preamble detection means for generating a preamble detection signal when
Triggered by the reception of the preamble detection signal, the internal clock is regarded as a recovered clock, and synchronization adjustment means for adjusting the synchronization of both based on the input signal and the clock over the second set time,
The first set time is shorter than the second set time.

A second invention is a clock data recovery circuit that receives an input signal including a preamble and data, and recovers the synchronization of the clock and data.
At each first set time, it is determined whether or not the preamble has been input based on a comparison between the signal sequence input during the first time and the specific signal sequence included in the preamble. Preamble detection means for generating a preamble detection signal when
Synchronization adjustment means that regards the internal clock as a recovered clock and adjusts the synchronization of both based on the input signal and the clock over a second set time after reset;
Synchronization adjustment reset means for resetting the synchronization adjustment means when the preamble detection signal is not generated when the preamble detection means counts the first set time,
The first set time is shorter than the second set time.

The third invention is the second invention, wherein
The preamble detection means includes a first counter that counts the first set time,
The synchronization adjustment reset means includes
A second counter that counts the first set time after the first counter;
A reset signal generating means for generating a reset signal toward the synchronization adjusting means when the first set time is counted by the second counter;
And reset prohibiting means for receiving the preamble detection signal and prohibiting the generation of the reset signal.

According to a fourth invention, in any one of the first to third inventions,
The preamble detection means includes
Delay means for delaying the input signal to generate at least one delayed signal;
Comparison means for comparing a signal value at the time of occurrence of a trigger edge of an internal clock, which is regarded as a reproduction clock, with respect to the input signal and the at least one delayed signal, and a signal value constituting the specific signal sequence;
On the basis of the result of the comparison, for each of the input signal and the at least one delayed signal, coincidence output means for outputting a coincidence with the specific signal sequence,
Signal generating means for generating the preamble detection signal when a degree of coincidence exceeding a determination value is recognized for at least one of the input signal and the at least one delayed signal;
It is characterized by providing.

The fifth invention is the fourth invention, wherein
Parallelizing means for acquiring a signal value for each occurrence of a trigger edge of the internal clock and parallelizing those signal values for at least one of the input signal and the at least one delayed signal Including
The comparing means compares the parallelized signal value with the specific signal sequence for the input signal and the at least one delayed signal that are to be parallelized. .

According to a sixth invention, in any one of the first to third inventions,
The preamble detection means includes
Clock delay means for delaying an internal clock regarded as a reproduction clock to generate at least one delay clock;
Comparing means for comparing the value of the input signal at the time of occurrence of a trigger edge with a signal value constituting the specific signal sequence for each of the internal clock and the at least one delayed clock;
Based on the result of the comparison, a coincidence degree output means for outputting a coincidence degree between the input signal and the specific signal sequence for each of the internal clock and the at least one delayed clock;
Signal generating means for generating the preamble detection signal when a degree of coincidence exceeding a determination value is recognized for at least one of the internal clock and the at least one delayed clock;
It is characterized by providing.

The seventh invention is the sixth invention, wherein
Including at least one of the clock and the at least one delayed clock as a target, acquiring a signal value of the input signal every time a trigger edge occurs, and parallelizing the signal value ,
The comparison means compares the parallelized signal value with the specific signal sequence for the clock and the at least one delayed clock that are to be parallelized.

Further, an eighth invention is any one of the first to seventh inventions,
The synchronization adjusting means includes
Second delay means for delaying the input signal over the second set time to generate at least one delayed signal;
Second comparison means for comparing the signal value at the time of occurrence of the trigger edge of the internal clock with the signal value constituting the specific signal sequence for the input signal over the second set time and the at least one delay signal When,
A second coincidence degree output means for outputting a degree of coincidence with the specific signal sequence for each of the input signal and the at least one delayed signal over the second set time based on the result of the comparison;
A signal determination unit that uses the input signal over the second set time and the at least one delayed signal having the highest degree of coincidence as the synchronization adjustment signal, and
The clock data reproduction means outputs at least one of the signal obtained by latching the synchronization adjustment signal with the internal clock and the synchronization adjustment signal together with the internal clock.

The ninth invention is the eighth invention, wherein
For at least one of the input signal over the second set time and the at least one delayed signal, a signal value is obtained every time the trigger edge of the internal clock occurs, and those signal values are parallelized. Including second parallelizing means for
The second comparison unit is configured to use a parallel signal value of the input signal and the at least one delayed signal over the second set time as the specific signal sequence for the parallel signal. It is characterized by comparing with.

According to a tenth invention, in any one of the first to seventh inventions,
The synchronization adjusting means includes
Second clock delay means for delaying the clock to generate at least one delay clock;
Second comparing means for comparing a value of the input signal at the time of occurrence of a trigger edge over a second set time with a signal value constituting the specific signal sequence for each of the clock and the at least one delayed clock; ,
A second coincidence degree output means for outputting a coincidence degree between the input signal and the specific signal sequence over the second set time for each of the clock and the at least one delayed clock based on the result of the comparison;
A signal determination unit that uses the clock and the at least one delayed clock having the highest degree of coincidence as the synchronization adjustment clock; and
And a clock data recovery means for outputting at least one of the input signal latched with the synchronization adjustment clock and the input signal together with the synchronization adjustment clock.

The eleventh aspect of the invention is the tenth aspect of the invention,
For at least one of the clock and the at least one delayed clock, the signal value of the input signal over the second set time is obtained every time a trigger edge occurs, and the signal values are parallelized Second parallelizing means for
The second comparing means compares the parallelized signal value with the specific signal sequence for the clock and the at least one delayed clock that are to be parallelized. To do.

The twelfth invention is the fourth or fifth invention, wherein
The synchronization adjusting means includes
Second delay means for delaying the input signal over the second set time to generate at least one delayed signal;
Second comparison means for comparing the signal value at the time of occurrence of the trigger edge of the internal clock with the signal value constituting the specific signal sequence for the input signal over the second set time and the at least one delay signal When,
A second coincidence degree output means for outputting a degree of coincidence with the specific signal sequence for each of the input signal and the at least one delayed signal over the second set time based on the result of the comparison;
Among the input signal over the second set time and the at least one delay signal, a signal determination unit that uses a signal having the highest degree of coincidence as a synchronization adjustment signal, and
A clock data reproducing means for outputting at least one of the signal obtained by latching the synchronization adjustment signal with the internal clock and the synchronization adjustment signal together with the internal clock;
At least one of the delay means and the second delay means, and the comparison means and the second comparison means is composed of the same thing.

The thirteenth invention is the fifth invention, in which
The synchronization adjusting means includes
Second delay means for delaying the input signal over the second set time to generate at least one delayed signal;
Second comparison means for comparing the signal value at the time of occurrence of the trigger edge of the internal clock with the signal value constituting the specific signal sequence for the input signal over the second set time and the at least one delay signal When,
A second coincidence degree output means for outputting a degree of coincidence with the specific signal sequence for each of the input signal and the at least one delayed signal over the second set time based on the result of the comparison;
Among the input signal over the second set time and the at least one delay signal, a signal determination unit that uses a signal having the highest degree of coincidence as a synchronization adjustment signal,
For at least one of the input signal over the second set time and the at least one delayed signal, a signal value is obtained every time the trigger edge of the internal clock occurs, and those signal values are parallelized. Second parallelizing means for converting to
The second comparison unit is configured to use a parallel signal value of the input signal and the at least one delayed signal over the second set time as the specific signal sequence for the parallel signal. Compared to
A clock data reproducing means for outputting at least one of the signal obtained by latching the synchronization adjustment signal with the internal clock and the synchronization adjustment signal together with the internal clock;
At least one of the delay means and the second delay means, the comparison means and the second comparison means, and the parallelization means and the second parallelization means is composed of the same thing. .

The fourteenth invention is the sixth or seventh invention, wherein
The synchronization adjusting means includes
Second clock delay means for delaying the clock to generate at least one delayed clock;
Second comparison means for comparing the value of the input signal at the time of occurrence of a trigger edge over the second set time with the signal value constituting the specific signal sequence for each of the clock and the at least one delay clock. When,
A second coincidence degree output means for outputting a coincidence degree between the input signal and the specific signal sequence over the second set time for each of the clock and the at least one delayed clock based on the result of the comparison;
A signal determining unit that uses the clock and the at least one delayed clock having the highest degree of coincidence as the synchronization adjustment clock; and
A clock data recovery means for outputting at least one of the input signal and the synchronization adjustment clock together with a signal obtained by latching the input signal with the synchronization adjustment clock;
At least one of the clock delay unit and the second clock delay unit, and the comparison unit and the second comparison unit is formed of the same thing.

The fifteenth invention is the seventh invention, in the seventh invention,
The synchronization adjusting means includes
Second clock delay means for delaying the clock to generate at least one delayed clock;
Second comparison means for comparing the value of the input signal at the time of occurrence of a trigger edge over the second set time with the signal value constituting the specific signal sequence for each of the clock and the at least one delay clock. When,
A second coincidence degree output means for outputting a coincidence degree between the input signal and the specific signal sequence over the second set time for each of the clock and the at least one delayed clock based on the result of the comparison;
Among the clock and the at least one delay clock, a signal determination unit that uses the one having the highest degree of coincidence as the synchronization adjustment clock;
For at least one of the clock and the at least one delayed clock, the signal value of the input signal over the second set time is obtained every time a trigger edge occurs, and the signal values are parallelized Second parallelizing means for
The second comparing means compares the parallelized signal value with the specific signal sequence for the clock and the at least one delayed clock that are to be parallelized; and
A clock data recovery means for outputting at least one of the input signal and the synchronization adjustment clock together with a signal obtained by latching the input signal with the synchronization adjustment clock;
At least one of the clock delay means and the second clock delay means, the comparison means and the second comparison means, and the parallelization means and the second parallelization means is configured by the same thing. Features.

The sixteenth invention is an electronic device,
A clock data recovery circuit according to any one of the first to fifteenth inventions;
A signal processing circuit that operates using a combination of a signal and a clock that are output in a synchronously adjusted state from the synchronization adjusting means;
It is characterized by providing.

  According to the present invention, it is possible to determine whether or not a preamble is input based on a comparison between a signal sequence input during the first set time and a specific signal sequence included in the preamble. Then, the synchronization adjustment over the second set time can be performed with the detection of the preamble. In this case, it is sufficient that the preamble is secured by the sum of the first set time and the second set time. If the synchronization adjustment is to be realized only by the synchronization adjustment process, a preamble corresponding to almost twice the second set time is required. In the present invention, since the first set time is shorter than the second set time, the preamble is shortened.

  According to the second aspect, it is possible to determine whether or not the preamble has been input based on the comparison between the signal sequence input during the first set time and the specific signal sequence included in the preamble. When the preamble is not detected, the preamble detection process is newly started and the synchronization adjustment process is reset every time the first set time elapses. When the preamble is detected as the first set time elapses, the synchronization adjustment process is continued while using the synchronization adjustment process performed during the first set time. In this case, it is sufficient that the preamble is secured for the second set time. Thus, according to the present invention, shortening of the preamble is realized.

  According to the third invention, the second counter included in the synchronization adjustment reset unit counts the first set time behind the first counter included in the preamble detection unit, and outputs the reset signal when the first set time is counted. appear. As long as the preamble is not detected, this reset signal is issued every first set time. Accordingly, in this case, the synchronization adjustment process is newly started every first set time. When the preamble is detected, the generation of the reset signal is prohibited, so that the synchronization adjustment unit continues the synchronization adjustment process even after the first count time has elapsed. Thus, according to the present invention, the function required in the second invention can be realized with a simple configuration.

  According to the fourth invention, the presence of a signal synchronized with the clock can be ensured by generating a delay signal in the preamble detection means. In this case, if there is a preamble, any signal inevitably matches the specific signal sequence. In the present invention, the presence / absence of a preamble can be accurately determined based on whether or not the match is recognized.

  According to the fifth aspect, by providing the preamble detecting means with the parallelizing means, it is possible to reduce the processing speed required for the preamble detecting means at the subsequent stage of the parallelizing means.

  According to the sixth aspect, the presence of a clock synchronized with the input signal can be ensured by generating a delay clock in the preamble detection means. In this case, if there is a preamble, it is recognized that the input signal processed with any clock matches the specific signal sequence. In the present invention, the presence / absence of a preamble can be accurately determined based on whether or not the match is recognized.

  According to the seventh aspect, by providing the parallel detection means in the preamble detection means, it is possible to reduce the processing speed required for the preamble detection means in the subsequent stage of the parallelization means.

  According to the eighth aspect, the presence of a signal synchronized with the clock can be ensured by generating the delay signal in the synchronization adjusting means. In this case, during the reception of the preamble, any signal inevitably matches with the specific signal sequence. In the present invention, it is possible to reliably generate a signal synchronized with a clock in an environment where the coincidence is recognized.

  According to the ninth aspect, by providing the second parallelizing means in the synchronization adjusting means, it is possible to reduce the processing speed required for the synchronization adjusting means in the subsequent stage.

  According to the tenth aspect, by generating a delay clock in the synchronization adjusting means, it is possible to guarantee the existence of a clock synchronized with the input signal. In this case, during reception of the preamble, it is inevitably recognized that the signal processed with any clock matches the specific signal sequence. According to the present invention, it is possible to reliably generate a synchronization adjustment clock that is synchronized with the input signal in an environment where the coincidence is recognized.

  According to the eleventh invention, by providing the second parallelizing means in the synchronization adjusting means, the processing speed required for the synchronization adjusting means can be lowered in the subsequent stage.

  According to the twelfth or fourteenth aspect, at least one of the delay means in the preamble detection means and the second delay means in the synchronization adjustment means, or the comparison means in the preamble detection means and the second comparison means in the synchronization adjustment means is shared. Can be Therefore, according to the present invention, the scale of the clock data recovery circuit can be reduced.

  According to the thirteenth or fifteenth invention, the delay means in the preamble detection means and the second delay means in the synchronization adjustment means, the comparison means in the preamble detection means and the second comparison means in the synchronization adjustment means, or the parallel in the preamble detection means At least one of the second parallelizing means in the converting means and the synchronization adjusting means can be shared. Therefore, according to the present invention, the scale of the clock data recovery circuit can be reduced.

  According to the sixteenth aspect, it is possible to realize an electronic device that can operate properly even if the preamble is sufficiently shortened.

Embodiment 1 FIG.
[Overview of Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a clock data recovery circuit 20 according to the first embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation principle of the clock data recovery circuit 20 shown in FIG.

  The clock data recovery circuit 20 is a circuit for performing synchronization adjustment between the input signal and the clock on the receiving side on the receiving side of the communication system. In particular, this circuit is a suitable circuit for realizing efficient synchronization adjustment in a wireless communication system that is susceptible to noise.

  As in the conventional clock data recovery circuit 10 (see FIG. 9), the clock data recovery circuit 20 of the present embodiment receives an input signal in a format in which a preamble is added to data, that is, an input signal in the format shown in FIG. handle. Here, the “preamble” is a signal set at the head of the input signal or a position close to the head, and is generally composed of alternating signals of “0” and “1”. However, in the present embodiment, the preamble is not limited to such an alternating signal. That is, as long as the receiving side apparatus can handle the preamble symbol string as a known one, the preamble may be composed of a unique word or random data arbitrarily determined by the user.

  As shown in FIG. 1, the clock data recovery circuit 20 of the present embodiment includes a preamble detection circuit 22 and a clock data generation circuit 24. The preamble detection circuit 22 constantly monitors the input signal including the no-signal period, and determines whether or not a preamble is received every predetermined preamble detection period T2, as shown in FIG. This process is repeated until a preamble is detected. When the preamble detection circuit 22 detects the preamble, the preamble detection circuit 22 outputs a preamble detection signal to the clock data generation circuit 24 as shown in FIG.

  The clock data generation circuit 24 detects the phase relationship between the input signal and the clock during the phase timing detection period T when the preamble detection signal is received. Subsequently, the circuit 24 adjusts the synchronization of the input signal and the clock, and outputs the signal and the clock that have been subjected to the synchronization adjustment.

  As shown in FIG. 2, the preamble detection period T2 is set to a period sufficiently shorter than the phase timing detection period T. For example, the former is set to a period corresponding to a 16-bit symbol string, and the latter is set to a period corresponding to a 512-bit symbol string.

  Presence / absence of the preamble is determined based on whether or not a series of sequentially inputted signal values match a known symbol string of the preamble. In this embodiment, the preamble is detected in order to determine the generation of a genuine input signal, that is, to determine the generation of an input signal that is not mere noise. If a match is recognized in a symbol string of about 16 bits, it can be determined that the input signal is not a noise but a preamble. Therefore, the preamble detection period T2 can be a short period of about 16 bits as described above.

  On the other hand, the detection accuracy of the phase timing is improved as the number of input signals serving as the basis of the detection increases. In order to obtain desired accuracy in wireless communication in a noisy environment, an input signal for several hundred bits is required as described in the section of the prior art. For this reason, in this embodiment, the phase timing detection period T is set to 512 bits as described above.

  According to the clock data recovery circuit 20 of the present embodiment, after the input signal is generated, the presence of the preamble is detected after the preamble detection period T2, and then the phase timing can be detected after the phase timing detection period T. . For this reason, it is sufficient that the preamble is secured by the number of bits corresponding to the sum (T2 + T) of the preamble detection period T2 and the phase timing detection period T.

  Since the preamble detection period T2 is shorter than the phase timing detection period T, the preamble period (T2 + T) required in this embodiment is the period 2 * T required in the conventional clock data recovery circuit 10. It is shorter than that. Therefore, according to the clock data recovery circuit 20 of the present embodiment, a communication system with a shorter preamble than that of the conventional circuit 10 is realized, and as a result, a communication system with high effective transmission throughput is realized. be able to.

  In the clock data recovery circuit 20 of the present embodiment, the operation period of the clock data generation circuit 24 can be limited to the phase timing detection period T after the preamble is detected. The clock data generation circuit 24 is a circuit that has a large amount of processing and a large amount of power consumption. According to this embodiment, since the operation period of the circuit can be minimized, an effect of reducing the power consumption of the communication system can be obtained.

[Details of Embodiment 1]
FIG. 3 is a block diagram showing in detail the configuration of the clock data recovery circuit 20 of the present embodiment. As shown in FIG. 3, the preamble detection circuit 22 includes a delay circuit group 30, a statistical circuit group 32, and a preamble determination circuit 34. The preamble detection circuit 22 includes an internal clock 36 for generating a reference clock and a T2 timer 38 for counting the preamble detection period T2 described above.

The delay circuit group 30 includes n−1 delay circuits 30 ₋₁ to 30- _(n−1) together with a transmission path for passing an input signal as it is to a subsequent circuit. These delay circuits _{30 -1 ~30 - (n-1} ) are connected in series. For this reason, the delay circuit group 30 can generate n−1 types of delayed signals delayed in multiple stages. That is, according to the delay circuit group 30, it is possible to generate n types of signals having different phases from each other together with the input signal.

When the transmission rate of the input signal is 2 Gbps, the transmission time for 1 bit is 500 psec. Delay circuit _{30 -1 ~30 - (n-1} ) are respectively set to generate a delay of (500 / n) psec. For example, if it is n = 8, the delay circuit _{30 -1 ~30 - (n-1} ) generates a delay of 62.5psec respectively. In this case, the eight types of signals generated by the delay circuit group 30 are multistage phase shift signals with equal phase shifts.

The statistical circuit group 32 includes n statistical circuits 32 _{-1 to} 32 _-n . Each of the statistical circuits 32 _{-1 to} 32 _-n is provided with a latch circuit 40, a comparison value storage circuit 42, and a comparison addition accumulation circuit 44.

N types of phase shift signals output from the delay circuit group 30 are supplied to the statistical circuits 32 _{-1 to} 32 _-n , respectively. That is, the input signal that has passed through the delay circuit group 30 is supplied to the first statistical circuit _32-1 . Further, the second and subsequent statistical circuits 32 _{-2 to} 32 _-n are respectively supplied with signals delayed in multiple stages by (500 / n) psec.

The signals supplied to the statistical circuits 32 _{-1 to} 32 _-n reach the respective latch circuits 40. The latch circuit 40 operates in accordance with a clock supplied from the internal clock 36, and latches the value of the signal upon occurrence of a trigger edge (in this case, an up edge) of the clock.

  The frequency of the internal clock 36 is set according to the frequency of the input signal. Due to various variations, the frequencies of the two do not completely match, but the signals exchanged in this embodiment are intermittent signals, and the period for receiving a set of input signals is extremely short. . For this reason, in the relationship with each input signal, the frequency and the frequency of the internal clock 36 can be handled as being the same.

  The relationship between the phase of the input signal and the phase of the clock changes according to the timing at which the input signal is generated. That is, the input signal may be generated at a timing at which the phase timing (see FIG. 12) coincides with the up edge of the clock, or the phase signal is positioned at the center of two adjacent up edges. May occur. In the latter case, the value of the input signal can be correctly captured by performing a latch process in synchronization with the internal clock 36. However, in the former case, the up-edge timing coincides with the signal value change timing. Due to the latch processing synchronized with the internal clock 36, the value of the input signal cannot be properly captured.

However, in this embodiment, multistage phase shift signals with equal phase shifts are given to the statistical circuits 32 _{-1 to} 32 _-n . All of these statistical circuits 32 _{-1 to} 32 _-n receive the up edge generated by the internal clock 36 and latch the signal at the same timing. In this case, in some statistical circuits, the phase timing of the received signal overlaps with the up edge, but in one or more statistical circuits, the phase timing of the received signal does not necessarily overlap with the up edge. It becomes a state. Therefore, according to the preamble detection circuit 22 in the present embodiment, the signal sequence included in the input signal can be correctly latched by the latch circuit 40 in at least one statistical circuit regardless of the timing of the input signal. it can.

  The comparison value storage circuit 42 stores the symbol string included in the preamble by a predetermined number of bits. Here, for convenience of explanation, it is assumed that the preamble is an alternating signal of “0” and “1”, and the comparison value storage circuit 42 stores the alternating signal of 01 for 16 bits corresponding to the preamble detection period T2. To do. It is also possible to generate a 01 alternation inside each time and use it as a comparison value.

  The data latched by the latch circuit 40 and the signal value stored in the comparison value storage circuit 42 are sequentially supplied to the comparison and accumulation circuit 44 for each clock. Further, the comparison / accumulation circuit 44 is supplied with a reset signal from the T2 timer every preamble detection period T2. The comparison and accumulation circuit 44 is reset to the initial state by receiving the reset signal, and thereafter performs processing such as comparison of the latch data with the comparison value, addition of the comparison result, and accumulation of the addition result for each clock. To do.

  Specifically, after receiving the reset signal, the comparison and accumulation circuit 44 sequentially compares the latch data with the comparison value over 16 bits. As a result, if a match between the two is recognized, the number of matches is incremented. On the other hand, if a mismatch is found between the two, the number of mismatches is incremented. In the process of 16-bit comparison, the comparison results are sequentially added according to the above rules. As a result, if all comparisons match, the number of matches is 16, while if all results do not match, the number of mismatches is 16.

  As long as the reset signal is not received, the comparison / addition accumulation circuit 44 shifts the number of matches and the number of mismatches to the accumulated result each time the comparison and addition of 16 bits is completed, and sets the addition values related to match and mismatch to zero. Thereafter, the comparison / accumulation circuit 44 executes again the comparison between the latch data and the comparison value, and increments the number of matches and the number of mismatches based on the result of the comparison.

  In the present embodiment, since the preamble detection period T2 corresponds to 16 bits, the comparison and accumulation circuit 44 is reset every time the comparison of 16 bits is completed. For this reason, in this embodiment, the added value of the number of matches and the number of mismatches is not accumulated. However, the preamble detection period T2 may be set to a bit number longer than 16 bits, for example, a period corresponding to 32 bits. In this case, the comparison / addition accumulation circuit 44 can calculate the final number of matches and the number of mismatches when the comparison for 32 bits is completed using the above-described accumulation function.

  The preamble used in this embodiment is an alternating signal of “0” and “1” as described above. Therefore, the comparison value storage circuit 42 also stores alternating signals “0” and “1”. For this reason, in the statistical circuit in which the preamble signal string is properly latched, the comparison between the latch data and the comparison value may be the same for each clock, or may not be the same.

That is, in the present embodiment, as the latched data approaches the preamble signal string, one of the number of matches and the number of mismatches increases, and at the same time, the other of them decreases. In this case, the larger of the number of matches and the number of mismatches more correctly represents the possibility that the latch data matches the preamble signal string. Therefore, the comparison and accumulation circuit 44 compares them and outputs the larger value of the number of matches and the number of mismatches as comparison data. Therefore, in the present embodiment, it is possible to accurately determine whether or not the signal latched by the statistical circuits 32 _{-1 to} 32 _-n matches the preamble signal string by looking at the comparison data. it can.

Comparison data generated in each of the statistical circuits 32 _{-1 to} 32 _-n is supplied to the preamble determination circuit 34. The preamble determination circuit 34 is supplied with a determination timing signal from the T2 timer 38 every preamble detection period T2. Upon receiving this determination timing signal, the preamble determination circuit 34 determines whether comparison data exceeding a determination value (for example, 14) is output for each of the statistical circuits 32 _{-1 to} 32 _-n .

If relative preamble detection circuit 22 begins to be transmitted is a signal not noise, the statistics circuit 32 _-1 to 32 _-n, signal having a preamble signal sequence is supplied. In this case, in any of the statistical circuits 32 _{-1 to} 32 _-n , the preamble signal string is inevitably latched appropriately. Therefore, comparison data exceeding the determination value is output from at least one statistical circuit. On the other hand, if no appropriate signal is input to the preamble detection circuit 22, comparison data exceeding the determination value is not output from any statistical circuit.

  For this reason, when the comparison data exceeding the determination value is output from at least one statistical circuit, the preamble determination circuit 34 determines the detection of the preamble and outputs the preamble detection signal. On the other hand, when no comparison data exceeding the determination value is output from any statistical circuit, the preamble detection signal is not output. In this case, thereafter, the above-described processing is repeated for each preamble detection period T2.

  When the preamble detection signal described above is generated by the preamble detection circuit 22, the operation of the clock data generation circuit 24 is triggered by this. As illustrated in FIG. 3, the clock data generation circuit 24 includes a delay circuit group 50, a statistical circuit group 52, and a signal determination circuit 54. The clock data generation circuit 24 includes an internal clock 56 for generating a reference clock and a T timer 58 for counting the phase timing detection period T.

The delay circuit group 50 and the statistical circuit group 52 are substantially the same as the delay circuit group 30 and the statistical circuit group 32 in the preamble detection circuit 22, respectively. The internal clock 56 is substantially the same as the internal clock 36 in the preamble detection circuit 22. That is, the delay circuit group 50 includes (n−1) delay circuit delay circuits 50 ₋₁ to 50 _{− (n−1)} , and n types whose phases are delayed in stages at equal intervals. Generate a signal. The statistical circuit group 52 has n statistics circuit ₅₂ -1 _{to 52 -n} provided corresponding to each of the n types of signals, each of the statistical circuits ₅₂ -1 _{to 52 -n} Includes a latch circuit 60 that operates in response to the internal clock 56, a comparison value storage circuit 62, and a comparison addition accumulation circuit 64.

  The comparison and accumulation circuit 64 is supplied with a reset signal from the T timer 58 for each phase timing detection period T. The phase timing detection period T (equivalent to 512 bits) is a period sufficiently longer than the preamble detection period T2 (equivalent to 16 bits). The comparison and accumulation circuit 64 compares the latch data with the comparison value for each clock, and adds the number of matches or the number of mismatches. Then, unless a reset signal is received, the added values are accumulated every 16 bits, and the above-described comparison process and addition process are repeated again. As a result, when the phase timing detection period T expires, the comparison addition accumulation circuit 64 accumulates the number of matches and the number of mismatches based on the comparison for 512 bits.

  In the comparison and accumulation circuit 64, for the same reason as in the case of the comparison and accumulation circuit 44, one of the number of matches and the number of mismatches increases as the latched data approaches the preamble signal sequence. A phenomenon occurs in which the other of the two becomes smaller. That is, also here, the larger of the number of matches and the number of mismatches more accurately represents the possibility that the latch data matches the preamble signal string. Therefore, the comparison / addition accumulation circuit 64 compares them, and outputs the larger value of the number of matches and the number of mismatches to the signal determination circuit 54 together with the latch data as comparison data.

As described above, the clock data generation circuit 24 is a circuit that operates after the occurrence of a preamble is detected. Therefore, each of the statistical circuits 52-1 to 52 _{- n} generates comparison data while receiving a signal having a preamble signal sequence. In this case, the comparison data has a large value in the statistical circuit in which the preamble signal string is correctly latched, and a small value in the statistical circuit in which the latch is not correctly performed. That is, the comparison data in the clock data generation circuit 24 has a meaning as a characteristic value indicating the degree of synchronization between the signal processed by each of the statistical circuits 52 _{-1 to} 52 _-n and the internal clock 56. Yes.

The signal determination circuit 54 detects the largest one from the comparison data generated from each of the statistical circuits 52 _{-1 to} 52 _-n . The statistical circuit emitting the maximum comparison data is the circuit that latches the input signal, that is, the preamble most correctly among all the statistical circuits 52 _{-1 to} 52 _-n . Then, the signal determination circuit 54 outputs the signal processed by the statistical circuit thus detected (hereinafter referred to as “synchronization signal”) to the subsequent circuit together with the clock generated by the internal clock 56. More precisely, the signal determination circuit 54 outputs the synchronization signal latched by the internal clock 56 together with the clock as a synchronization adjustment signal.

  The synchronization adjustment signal is a signal that is guaranteed to be synchronized with the internal clock 56. In this way, the clock data recovery circuit 20 can provide a combination of a signal and a clock that are guaranteed to be synchronized to a subsequent device. For this reason, the latter apparatus can correctly process the data provided from the transmission source by using them as a set.

  Furthermore, in this embodiment, a preamble is added to a signal exchanged by communication with a minimum number of bits corresponding to the sum of the preamble detection period T2 and the phase timing detection period T. Then, according to the clock data generation device 20 of the present embodiment, during such a short preamble transmission period, the synchronization adjustment of the input signal and the clock is always finished, and all the data is transferred to the subsequent device. Can be provided in a state of being guaranteed. For this reason, according to the clock data recovery circuit 20 of this embodiment, communication with excellent transmission efficiency can be realized.

By the way, in the first embodiment described above, both the preamble detection circuit 22 and the clock data generation circuit 24 maintain the phases of the internal clocks 36 and 56 and generate a delay signal of the input signal, thereby detecting the preamble, and The synchronization adjustment of the signal and the clock is realized. However, these methods are not limited to this. That is, the preamble detection circuit 22 may realize a similar function by generating a delay clock while maintaining the phase of the input signal. Specifically, the delay circuit _{30 -1 ~30 - (n-1} ) in place, the clock delay circuit for generating a multi-stage delayed clock provided statistics circuit ₃₂ -2 _{to 32 -n,} their It is good also as detecting a preamble by operating with a delay clock. Similarly, the clock data generation circuit 24 is provided with a clock delay circuit for generating a multi-stage delay clock instead of the delay circuits 50 _-1 to 50- _(n−1) , and the statistical circuit 52 _−2. The detection of phase timing may be realized by operating ˜52 _−n with these delay clocks.

  In the first embodiment described above, the clock data recovery circuit 20 is mainly realized by hardware, but the present invention is not limited to this. That is, the clock data recovery circuit 20 having the above configuration may be realized using software. This also applies to other embodiments described below.

  In the first embodiment described above, the preamble detection circuit 22 includes the internal clock 36 and the clock data generation circuit 24 includes the internal clock 56. However, these internal clocks are not necessarily separate. There is no need to prepare. That is, the internal clock of the preamble detection circuit 22 and the internal clock of the clock data generation circuit 24 may be shared.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram for explaining the detailed configuration of the clock data recovery circuit 70 of the present embodiment. The clock data recovery circuit 70 of this embodiment includes a preamble detection circuit 72 and a clock data generation circuit 74. The circuit, except that the parallel circuit 76 _-1 to 76 _-n are inserted into the preamble detection circuit 72, and a clock data generator 74, a point at which the parallel circuit group 78 is inserted, substantially This is the same as the circuit 20 of the first embodiment.

In other words, in the present embodiment, the parallel detection circuits 76 _{−1 to} 76 _−n are arranged in the preamble detection circuit 72 after the delay circuit group 30. Each of the parallelizing circuits 76 _{-1 to} 76 _-n stores a comparison value for the same number of M bits (M = 16) as the register 80 having the number of M bits (M = 16 here) constituting the shift register. A container 82 is provided.

For example, the input signal coming through a delay circuit group 30 is supplied to the register 80 disposed in the forefront of the parallel circuit 76 _-1. The foremost register 80 receives the trigger edge (up edge) of the internal clock 36 and latches the value of the input signal. In response to the up edge, the second and subsequent registers 80 sequentially latch the values of the resists 80 of the previous stage and send them to the subsequent stage. In the other parallel circuits 76 _{-2 to} 76 _-n , the same processing is executed for the delay signal supplied from the delay circuit group 30.

The parallel circuits 76-1 to 76 _{- n} store the values latched in the 16 registers 80 and the 16 comparison value storage units 82 every time 16 clocks are input. Are sent to the statistical circuit group 84 at a time. Hereinafter, the former 16-bit signal is referred to as “parallel input signal sequence”, and the latter 16-bit signal is referred to as “parallel comparison signal sequence”.

The statistics circuit group 84, n pieces of statistical circuit ₈₄ -1 _{-84 -n} is prepared. Each of the statistical circuits 84 _{-1 to} 84 _-n has a function similar to that of the comparison addition accumulation circuit 44 in the first embodiment except that the parallel input signal sequence and the parallel comparison signal sequence can be compared at a time. . That is, statistics circuit 84 _-1, when the parallel input signal sequence and the parallel comparison signal sequence is input from the parallel circuit 76 _-1 compares the two and adds the matching number and the number of mismatched bits values. Then, every time the process is repeated until the reset signal is received from the T2 timer 38, the addition value of the coincidence number and the addition value of the mismatch number are accumulated, and the larger one of the match number and the mismatch number is used as comparison data. This is provided to the preamble determination circuit 34.

  The preamble determination circuit 34 determines the presence / absence of a preamble based on the comparison data supplied in this way, and generates a preamble detection signal when the occurrence is detected, as in the first embodiment. be able to.

According to the above configuration, when the rate of the input signal is 2 Gbps, the operating frequency of the statistical circuits 84 _{-1 to} 84 _-n is 125 MHz that is 1/16 of that. As described above, according to the clock data recovery circuit 70 of the present embodiment, the operating frequencies of the statistical circuits 84 _{-1 to} 84 _-n can be significantly reduced as compared with the case of the first embodiment.

In the clock data recovery circuit 70 of this embodiment, the clock data generation circuit 74 also includes a parallelization circuit group 78. The parallel circuit group 78 has a configuration similar to that of the parallel circuits 76 _{-1 to} 76 _-n described above, and is parallel input at a frequency of 1/16 of the clock frequency with respect to the statistical circuit group 86. A signal sequence and a parallel comparison signal sequence are supplied. For this reason, according to this circuit 70, even in the clock data generation circuit 74, the operating frequency of the statistical circuit group 86 can be significantly reduced.

The design of the statistical circuits 84 _{-1 to} 84 _-n or the statistical circuit group 86 becomes easier as their operating frequency is slower. On the other hand, according to the circuit configuration that can slow down the operating frequency of these circuits, the upper limit of the frequency that can be processed by the clock data recovery circuit 70 can be increased. According to the clock data recovery circuit 70 of the present embodiment, these effects can be obtained in addition to the effects achieved by the circuit 20 of the first embodiment.

By the way, in the second embodiment described above, both the preamble detection circuit 72 and the clock data generation circuit 74 maintain the phases of the internal clocks 36 and 56 and generate a delay signal of the input signal, thereby detecting the preamble, and The synchronization adjustment of the signal and the clock is realized. However, these methods are not limited to this. That is, in the preamble detection circuit 72, the same function may be realized by maintaining the phase of the input signal and generating a delay clock. Specifically, the delay circuit ₃₀ -1 _{30 -} instead of _(n-1), a clock delay circuit for generating a multi-stage delayed clock provided, the parallel circuit 76 _-2 to 76 _-n, they It is also possible to detect the preamble by operating with a delay clock of. Similarly, the clock data generation circuit 74 is provided with a clock delay circuit group that generates multi-stage delay clocks instead of the delay circuit group 50, and the parallelization circuit group 78 is operated with these delay clocks. The phase timing may be detected as described above.

  In the second embodiment described above, the internal clock 36 is built in the preamble detection circuit 72 and the internal clock 56 is built in the clock data generation circuit 74. However, these internal clocks are not necessarily separate. There is no need to prepare. That is, the internal clock of the preamble detection circuit 72 and the internal clock of the clock data generation circuit 74 may be shared.

Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram for explaining the configuration of the clock data recovery circuit 90 of the present embodiment. In the clock data recovery circuit 70 of the second embodiment described above, the preamble detection circuit 72 and the clock data generation circuit 74 are provided with overlapping blocks for realizing the same function.

Specifically, the delay circuit group 30 in the preamble detection circuit 72 and the delay circuit group 50 in the clock data generation circuit 74 are both for generating a multi-stage phase shift signal, and are realized with the same configuration. be able to. Further, the parallelization circuit groups 76 _{-1 to} 76 _-n in the preamble detection circuit 72 and the parallelization circuit group 78 in the clock data generation circuit 74 also store a 16-bit parallel comparison value signal string and store a 16-bit parallel input. It is common in the function of generating signals, and can be realized with the same configuration. Further, the statistical circuits 84 _{-1 to} 84 _-n included in the preamble detection circuit 72 have a function of comparing the parallel input signal sequence and the parallel comparison signal sequence, and the addition value of the coincidence number and the mismatch number from the comparison result. The function for calculating the added value is common to the function required for the statistical circuit of the clock data generation circuit 74.

  The clock data recovery circuit 90 of the present embodiment is characterized in that the circuit scale is significantly reduced as a whole as compared with the circuit 70 of the second embodiment by sharing those overlapping elements. Yes. Hereinafter, the circuit configuration used in the present embodiment will be described in detail with reference to FIG. In FIG. 5, the same elements as those shown in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

That is, the clock data recovery circuit 90 of this embodiment includes a delay circuit group 30 for generating n types of phase shift signals based on an input signal, as shown in FIG. The n types of signals generated by the delay circuit group 30 are respectively supplied to the parallelizing circuits 76-1 to 76 _{- n} . Each of the parallelization circuits 76 _{-1 to} 76 _-n outputs a 16-bit parallel input signal sequence and a 16-bit parallel comparison signal sequence every time 16 clock inputs are received.

A statistical circuit group 92 is provided at the subsequent stage of the parallelization circuits 76 _{-1 to} 76 _-n . The statistical circuit group 92 includes n statistical circuits 92 _{-1 to} 92 _-n . Each of the statistical circuits 92 _{-1 to} 92 _-n includes a comparison and addition circuit 94 and an accumulation circuit 96.

The comparison / addition circuit 94 compares the parallel input signal string and the parallel comparison signal string supplied from the parallelizing circuits 76 _{-1 to} 76 _-n , that is, compares them with each other every 16 clock inputs, The added value of the number of matches and the added value of the number of mismatches are calculated. Then, the comparison / addition circuit 94 supplies the larger one of the addition values to the preamble determination circuit 34 and the accumulation circuit 96 as a value representing the degree of coincidence between the received signal and the preamble.

The preamble determination circuit 34 receives the determination timing signal from the T2 timer 38 and operates in the same manner as in the first or second embodiment. Or specifically, the preamble decision circuit 34, each preamble detection period T2, receives the decision timing signal from either the statistics circuit 92 _-1 to 92 _-n, addition value exceeds the determination value is outputted Judging. In this embodiment, the preamble detection period T2 is set to 16 clock cycles. More specifically, a setting is made so that the preamble detection period T2 expires every time an addition value is output from the comparison and addition circuit 94. For this reason, every time a comparison result for 16 bits is output from the comparison / addition circuit 94, the preamble determination circuit 34 compares the comparison result (addition value) with the determination value.

  However, the timing at which the comparison / addition circuit 94 outputs the added value and the timing at which the determination timing is issued from the T2 timer 38 are not necessarily the same as in the first and second embodiments. That is, the preamble detection period T2 may be, for example, 32 clock cycles. In this case, a desired comparison can be executed if the addition values generated from the comparison / addition circuit 94 every 16 clocks are accumulated in the preamble determination circuit 34 for a comparison of 32 bits.

Preamble decision circuit 34, if the sum value exceeds the determination value from any statistics circuit 92 _-1 to 92 _-n are determined not to be outputted, without outputting the preamble detection signal, waiting again added value It becomes a state. When observed the occurrence of the sum which exceeds the judgment value in any of the statistics circuit 92 _-1 to 92 _-n, preamble detection signal is generated from the preamble decision circuit 34.

In the present embodiment, the preamble detection signal is supplied to an accumulation circuit 96 and a T timer 58 provided in each of the statistical circuits 92 _{-1 to} 92 _-n . These circuits are in a reset state or a stopped state until the preamble detection signal is received, and start to operate when the signal is received.

In each of the statistical circuits 92 _{-1 to} 92 _-n , the comparison / addition circuit 94 operates in the same manner regardless of before and after the generation of the preamble detection signal. For this reason, the accumulating circuit 96 is supplied with an added value representing the degree of coincidence between the parallel input signal sequence and the parallel comparison signal sequence every 16 clocks even after the preamble detection signal is generated. The accumulation circuit 96 starts accumulation of the added value after generation of the preamble detection signal, and provides the accumulation result to the signal determination circuit 54 together with the latch data.

  As in the case of the first or second embodiment, the T timer 58 performs signal determination when a phase timing detection period T (for example, a period corresponding to 512 clock cycles) has elapsed after receiving the preamble detection signal. A determination timing signal is output to the circuit 54. In the meantime, in the accumulation circuit 96, the addition value output from the comparison and addition circuit 94 is accumulated a plurality of times (for example, 32 times). Then, the signal determination circuit 54 selects the statistical circuit that generates the largest cumulative value at the time of receiving the signal at the above-described determination timing, and strictly speaking, the signal processed by the circuit is A signal obtained by latching the signal with the internal clock 36 is supplied to the subsequent circuit together with the internal clock 36 as a synchronization adjustment signal.

  As described above, according to the circuit configuration shown in FIG. 5, the delay circuit group 30, the parallelizing circuits 76-1 to 76 -n, the comparison and adder circuit 94, etc., both detect the preamble and detect the phase timing. Can be used in common. That is, according to the circuit configuration illustrated in FIG. 5, the circuit configuration that is provided redundantly in the first or second embodiment can be shared. Therefore, according to the configuration of the present embodiment, the clock data recovery circuit 90 capable of realizing a high transmission rate can be realized with a small circuit.

By the way, in Embodiment 3 described above, when detecting the preamble and detecting the phase timing of the input signal, the phase of the internal clock 36 is maintained and the delayed signal of the input signal is generated. The invention is not limited to this. That is, instead of the delay circuit group 30 for generating a delay signal, a clock delay circuit group for generating a multi-stage delayed clock provided, the parallel circuit 76 _-2 to 76 _-n, in their delayed clock It is good also as detecting a preamble and a phase timing by operating.

Embodiment 4 FIG.
Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 6 is a diagram for explaining the configuration of the electronic apparatus according to the present embodiment. As shown in FIG. 6, the electronic device of the present embodiment includes an antenna 100 for receiving a signal transmitted by wireless communication. The antenna 100 is connected to a high frequency circuit 102 for converting a received signal into an electric signal.

  The signal generated by the high frequency circuit 102 is supplied to the clock data recovery circuit 20 of the first embodiment described above. This signal includes a preamble having the number of bits corresponding to the sum of the preamble detection period T2 and the phase timing detection period T. The clock data recovery circuit 20 can finish the synchronization adjustment of the clock and the signal during the reception period of the preamble, and can start outputting the clock and the synchronization adjustment signal to the subsequent stage.

  A baseband processing circuit 104 is disposed following the clock data recovery circuit 20. The baseband processing circuit 104 analyzes data from the synchronization adjustment signal and the clock supplied from the previous stage. Specifically, the baseband processing circuit 104 performs control of signal transmission and reception, disassembly and assembly of Ethernet signals, interface processing for processing video signals, and the like.

  The baseband processing circuit 104 is not necessarily required for the electronic device according to the present invention. On the contrary, the electronic device according to the invention can also comprise further processing circuits. In Embodiment 4, the electronic device is limited to a device that performs wireless communication. However, the present invention is not limited to this, and any communication can be performed as long as the device can perform data communication. The present invention can be applied even with a system.

  In the fourth embodiment described above, the clock data recovery circuit 20 according to the first embodiment is used. However, the clock data recovery circuit that can be used here is not limited to this. That is, the electronic circuit of this embodiment may be combined with the clock data recovery circuit 70, 90 of the second or third embodiment, or the clock data recovery circuit 110 of the fifth embodiment described below.

  In the first to fourth embodiments described above, the description is made using the phrase “synchronization”, but “synchronization” in these descriptions does not mean only constant synchronization. That is, the “synchronization” includes synchronization in a short period in the period in which the received packet exists.

Embodiment 5 FIG.
Next, Embodiment 5 of the present invention will be described with reference to FIG. 7 and FIG. FIG. 7 is a block diagram for explaining a detailed configuration of the clock data recovery circuit 110 of the present embodiment. The clock data recovery circuit 110 of the present embodiment is the same as the clock data recovery circuit 20 of the first embodiment, except that the clock data generation circuit 24 is replaced with the clock data generation circuit 112.

  The clock data generation circuit 24 according to the first embodiment is a circuit that executes synchronization adjustment processing triggered by a preamble detection signal generated from the preamble detection circuit 22. The clock data generation circuit 112 according to the present embodiment is implemented in that the synchronization adjustment processing is always executed, the second T2 timer 114 is provided, and the T timer 58 is replaced with the T timer 116. This is different from the circuit 24 of the first embodiment.

  The second T2 timer 114 repeatedly counts the preamble detection period T2 with a delay of one clock from the T2 timer 38 provided in the preamble detection circuit 22. The second T2 timer 14 generates a reset signal every time the count value reaches T2 unless a preamble detection signal is received, and stops the operation when the preamble detection signal is received.

  The reset signal generated by the second T2 timer 114 is supplied to the T timer 116. Therefore, a reset signal is supplied to the T timer 116 every preamble detection period T2 unless a preamble is detected. When the preamble is detected, the supply of the reset signal to the T timer 116 is stopped.

  When receiving the reset signal from the second T2 timer 114, the T timer 116 outputs the reset signal toward the comparison and accumulation circuit 64, clears the count value, and starts counting the phase timing detection period T again. For this reason, when the second T2 timer 114 issues a reset signal, the synchronization processing (cumulative value of the added value of the comparison result) executed over the period of T2 is cleared inside the clock data generation circuit 112, and is synchronized again. The process starts from the beginning.

When the preamble is detected and the supply of the reset signal to the T timer 116 is stopped, the T timer 116 counts up the count value over the preamble detection period T2. In this case, the T timer 116 performs the following processing when the count value reaches the phase timing detection period T.
1. The count value is reset and counting of the phase timing detection period T is newly started.
2. A determination timing is issued toward the signal determination circuit 54.
3. A reset signal is issued toward the comparison and accumulation circuit 64.

  As in the case of the first embodiment, the comparison / addition accumulation circuit 64 calculates an accumulation value representing the degree of coincidence between the input signal and the comparison value until a reset signal is received. Further, the signal determination circuit 54 receives the determination timing and detects the synchronization signal based on the accumulated value. Therefore, when the phase timing detection period T is counted in the T timer 116, the synchronization signal is detected in the signal determination circuit 54 at that time.

  FIG. 8 is a timing chart for explaining the operation of the clock data recovery circuit 110 of this embodiment. As shown in FIG. 8, the preamble detection period T2 is a period sufficiently shorter than the phase timing detection period T. Here, as in the first embodiment, the preamble detection period T2 is a period corresponding to a 16-bit symbol string, and the phase timing detection period T is a period corresponding to a 512-bit symbol string. .

  During a period when the clock data recovery circuit 110 is not receiving a signal, that is, during a no-signal period, the T2 timer 38 is used inside the preamble detection circuit 22 and the second T2 timer 114 is used inside the clock data generation circuit 112. In each case, the preamble detection period T2 is repeatedly counted. However, the second T2 timer 114 counts the preamble detection period T2 with a delay of one clock with respect to the T2 timer 38.

  While the second T2 timer 114 repeatedly counts the preamble detection period T2, the T timer 116 is also reset every T2. As shown in FIG. 8, when the preamble occurs at time t1, the preamble detection circuit 22 performs the preamble at the time when the preamble detection period T2 started immediately after time t1 ends (time t2 + T2 in FIG. 8). Detect and generate a preamble detection signal. As a result, the second T2 timer 114 stops operating immediately before the count value reaches T2.

  When the operation of the second T2 timer 114 is stopped, the count value of the T timer 116 increases beyond T2. When the count value reaches the phase timing detection period T, the tuning process by the clock data generation circuit 112 is completed. In the above processing, the clock data generation circuit 112 can end the tuning processing when the period of T−t3 has elapsed after time t3, which is one clock after time t2.

  The clock data recovery circuit 20 according to the first embodiment described above starts the tuning process triggered by the generation of the preamble detection signal. In this case, the shortest period from the occurrence of the preamble to the end of the tuning process is “T2 + T”. On the other hand, in the circuit 110 of this embodiment, the shortest period can be shortened to “T + 1 clock period”. Therefore, according to the circuit 110 of the present embodiment, the preamble can be further shortened compared to the case of the first embodiment.

  In the fifth embodiment described above, the second T2 timer 114 is added and the T timer 116 is replaced based on the clock data recovery circuit 20 of the first embodiment. However, the present invention is not limited to this. Is not to be done. That is, the circuit 110 of this embodiment may be configured based on the circuits 70 and 90 of the second or third embodiment.

It is a block diagram which shows the structure of the clock data reproduction circuit of Embodiment 1 of this invention. 2 is a timing chart for explaining the operating principle of the clock data recovery circuit shown in FIG. 1 is a block diagram showing in detail the configuration of a clock data recovery circuit according to a first embodiment of the present invention. It is a block diagram showing in detail the configuration of the clock data recovery circuit according to the second embodiment of the present invention. It is a block diagram showing in detail the configuration of the clock data recovery circuit according to the third embodiment of the present invention. It is a figure for demonstrating the structure of the electronic device of Embodiment 4 of this invention. It is a block diagram showing in detail the configuration of the clock data recovery circuit according to the fifth embodiment of the present invention. 8 is a timing chart for explaining the operation of the clock data recovery circuit shown in FIG. It is a figure which shows the structure of the conventional clock data reproduction circuit. It is a figure for demonstrating the data format of the input signal to which the preamble was added. It is a figure which shows the waveform of the general preamble comprised by the alternating signal of "0" "1". It is the figure which showed the case where the phase timing of a preamble and the trigger edge (here, up edge) of a clock correspond. It is a timing chart for demonstrating the method in which a phase timing detection circuit detects the phase of an input signal. It is a figure explaining the problem of the conventional clock data reproduction circuit shown in FIG.

Explanation of symbols

20,70,90 clock and data recovery circuit 22, 72 the preamble detection circuit 24, 74 a clock data generating circuit 30, 50 a delay circuit group _{30 -1 ~30 - (n-1} ), 50 -1 ~50 - (n-1 ₎ delay circuits 32,52,84,86,92 statistical circuit group _{32 -1 ~32 -n 52 -1 ~52 -n} 84 -1 ~84 -n 92 -1 ~92 -n statistics circuit 34 preamble decision circuit 36 , 56 Internal clock 38 T2 timer 40, 60 Latch circuit 42, 62 Comparison value storage circuit 44, 64 Comparison addition accumulation circuit 54 Signal determination circuit 58 T Timer 76-1 to 76 _{- n} Parallelization circuit 78 Parallelization circuit group 94 Comparison Adder circuit 96 Accumulator circuit 102 High frequency circuit 104 Baseband processing circuit

Claims (16)

A clock data recovery circuit that receives an input signal including a preamble and data and recovers synchronization of the clock and data,
At each first set time, it is determined whether or not the preamble has been input based on a comparison between the signal sequence input during the first time and the specific signal sequence included in the preamble. Preamble detection means for generating a preamble detection signal when
Triggered by the reception of the preamble detection signal, the internal clock is regarded as a recovered clock, and synchronization adjustment means for adjusting the synchronization of both based on the input signal and the clock over the second set time,
The clock data recovery circuit, wherein the first set time is shorter than the second set time. A clock data recovery circuit that receives an input signal including a preamble and data and recovers synchronization of the clock and data,
At each first set time, it is determined whether or not the preamble has been input based on a comparison between the signal sequence input during the first time and the specific signal sequence included in the preamble. Preamble detection means for generating a preamble detection signal when
Synchronization adjustment means that regards the internal clock as a recovered clock and adjusts the synchronization of both based on the input signal and the clock over a second set time after reset;
Synchronization adjustment reset means for resetting the synchronization adjustment means when the preamble detection signal is not generated when the preamble detection means counts the first set time,
The clock data recovery circuit, wherein the first set time is shorter than the second set time. The preamble detection means includes a first counter that counts the first set time,
The synchronization adjustment reset means includes
A second counter that counts the first set time after the first counter;
A reset signal generating means for generating a reset signal toward the synchronization adjusting means when the first set time is counted by the second counter;
3. The clock data recovery circuit according to claim 2, further comprising reset prohibiting means for receiving the preamble detection signal and prohibiting generation of the reset signal. The preamble detection means includes
Delay means for delaying the input signal to generate at least one delayed signal;
Comparison means for comparing a signal value at the time of occurrence of a trigger edge of an internal clock, which is regarded as a reproduction clock, with respect to the input signal and the at least one delayed signal, and a signal value constituting the specific signal sequence;
On the basis of the result of the comparison, for each of the input signal and the at least one delayed signal, coincidence output means for outputting a coincidence with the specific signal sequence,
Signal generating means for generating the preamble detection signal when a degree of coincidence exceeding a determination value is recognized for at least one of the input signal and the at least one delayed signal;
The clock data recovery circuit according to claim 1, further comprising: Parallelizing means for acquiring a signal value for each occurrence of a trigger edge of the internal clock and parallelizing those signal values for at least one of the input signal and the at least one delayed signal Including
The comparing means compares the parallelized signal value with the specific signal sequence for the input signal and the at least one delayed signal that are to be parallelized. The clock data recovery circuit according to claim 4. The preamble detection means includes
Clock delay means for delaying an internal clock regarded as a reproduction clock to generate at least one delay clock;
Comparing means for comparing the value of the input signal at the time of occurrence of a trigger edge with a signal value constituting the specific signal sequence for each of the internal clock and the at least one delayed clock;
Based on the result of the comparison, a coincidence degree output means for outputting a coincidence degree between the input signal and the specific signal sequence for each of the internal clock and the at least one delayed clock;
Signal generating means for generating the preamble detection signal when a degree of coincidence exceeding a determination value is recognized for at least one of the internal clock and the at least one delayed clock;
The clock data recovery circuit according to claim 1, further comprising: Including at least one of the clock and the at least one delayed clock as a target, acquiring a signal value of the input signal every time a trigger edge occurs, and parallelizing the signal value ,
The comparison means compares the signal value parallelized with the specific signal sequence for the clock and the at least one delayed clock that are to be parallelized. Item 7. The clock data recovery circuit according to Item 6. The synchronization adjusting means includes
Second delay means for delaying the input signal over the second set time to generate at least one delayed signal;
Second comparison means for comparing the signal value at the time of occurrence of the trigger edge of the internal clock with the signal value constituting the specific signal sequence for the input signal over the second set time and the at least one delay signal When,
A second coincidence degree output means for outputting a degree of coincidence with the specific signal sequence for each of the input signal and the at least one delayed signal over the second set time based on the result of the comparison;
A signal determination unit that uses the input signal over the second set time and the at least one delayed signal having the highest degree of coincidence as the synchronization adjustment signal, and
8. The clock data reproducing means for outputting at least one of the signal obtained by latching the synchronization adjustment signal with the internal clock and the synchronization adjustment signal together with the internal clock. The clock data recovery circuit according to the item. For at least one of the input signal over the second set time and the at least one delayed signal, a signal value is obtained every time the trigger edge of the internal clock occurs, and those signal values are parallelized. Including second parallelizing means for
The second comparison unit is configured to use a parallel signal value of the input signal and the at least one delayed signal over the second set time as the specific signal sequence for the parallel signal. 9. The clock data recovery circuit according to claim 8, wherein The synchronization adjusting means includes
Second clock delay means for delaying the clock to generate at least one delay clock;
Second comparing means for comparing a value of the input signal at the time of occurrence of a trigger edge over a second set time with a signal value constituting the specific signal sequence for each of the clock and the at least one delayed clock; ,
A second coincidence degree output means for outputting a coincidence degree between the input signal and the specific signal sequence over the second set time for each of the clock and the at least one delayed clock based on the result of the comparison;
A signal determination unit that uses the clock and the at least one delayed clock having the highest degree of coincidence as the synchronization adjustment clock; and
8. The clock data reproducing means for outputting at least one of the signal obtained by latching the input signal with the synchronization adjustment clock and the input signal together with the synchronization adjustment clock. The clock data recovery circuit according to the item. For at least one of the clock and the at least one delayed clock, the signal value of the input signal over the second set time is obtained every time a trigger edge occurs, and the signal values are parallelized Second parallelizing means for
The second comparing means compares the parallelized signal value with the specific signal sequence for the clock and the at least one delayed clock that are to be parallelized. The clock data recovery circuit according to claim 10. The synchronization adjusting means includes
Second delay means for delaying the input signal over the second set time to generate at least one delayed signal;
Second comparison means for comparing the signal value at the time of occurrence of the trigger edge of the internal clock with the signal value constituting the specific signal sequence for the input signal over the second set time and the at least one delay signal When,
A second coincidence degree output means for outputting a degree of coincidence with the specific signal sequence for each of the input signal and the at least one delayed signal over the second set time based on the result of the comparison;
Among the input signal over the second set time and the at least one delay signal, a signal determination unit that uses a signal having the highest degree of coincidence as a synchronization adjustment signal, and
A clock data reproducing means for outputting at least one of the signal obtained by latching the synchronization adjustment signal with the internal clock and the synchronization adjustment signal together with the internal clock;
6. The clock data recovery circuit according to claim 4, wherein at least one of the delay means and the second delay means, and the comparison means and the second comparison means is composed of the same thing. The synchronization adjusting means includes
Second delay means for delaying the input signal over the second set time to generate at least one delayed signal;
Second comparison means for comparing the signal value at the time of occurrence of the trigger edge of the internal clock with the signal value constituting the specific signal sequence for the input signal over the second set time and the at least one delay signal When,
A second coincidence degree output means for outputting a degree of coincidence with the specific signal sequence for each of the input signal and the at least one delayed signal over the second set time based on the result of the comparison;
Among the input signal over the second set time and the at least one delay signal, a signal determination unit that uses a signal having the highest coincidence as a synchronization adjustment signal,
For at least one of the input signal over the second set time and the at least one delayed signal, a signal value is obtained every time the trigger edge of the internal clock occurs, and those signal values are parallelized. Second parallelizing means for converting to
The second comparison unit is configured to use a parallel signal value of the input signal and the at least one delayed signal over the second set time as the specific signal sequence for the parallel signal. Compared to
A clock data reproducing means for outputting at least one of the signal obtained by latching the synchronization adjustment signal with the internal clock and the synchronization adjustment signal together with the internal clock;
At least one of the delay means and the second delay means, the comparison means and the second comparison means, and the parallelization means and the second parallelization means is composed of the same thing. The clock data recovery circuit according to claim 5. The synchronization adjusting means includes
Second clock delay means for delaying the clock to generate at least one delayed clock;
Second comparison means for comparing the value of the input signal at the time of occurrence of a trigger edge over the second set time with the signal value constituting the specific signal sequence for each of the clock and the at least one delay clock. When,
A second coincidence degree output means for outputting a coincidence degree between the input signal and the specific signal sequence over the second set time for each of the clock and the at least one delayed clock based on the result of the comparison;
A signal determining unit that uses the clock and the at least one delayed clock having the highest degree of coincidence as the synchronization adjustment clock; and
A clock data recovery means for outputting at least one of the input signal and the synchronization adjustment clock together with a signal obtained by latching the input signal with the synchronization adjustment clock;
8. The clock data reproduction according to claim 6, wherein at least one of the clock delay means and the second clock delay means, and the comparison means and the second comparison means is composed of the same thing. circuit. The synchronization adjusting means includes
Second clock delay means for delaying the clock to generate at least one delayed clock;
Second comparison means for comparing the value of the input signal at the time of occurrence of a trigger edge over the second set time with the signal value constituting the specific signal sequence for each of the clock and the at least one delay clock. When,
A second coincidence degree output means for outputting a coincidence degree between the input signal and the specific signal sequence over the second set time for each of the clock and the at least one delayed clock based on the result of the comparison;
Among the clock and the at least one delay clock, a signal determination unit that uses the one having the highest degree of coincidence as the synchronization adjustment clock;
For at least one of the clock and the at least one delayed clock, the signal value of the input signal over the second set time is obtained every time a trigger edge occurs, and the signal values are parallelized Second parallelizing means for
The second comparing means compares the parallelized signal value with the specific signal sequence for the clock and the at least one delayed clock that are to be parallelized; and
A clock data recovery means for outputting at least one of the input signal and the synchronization adjustment clock together with a signal obtained by latching the input signal with the synchronization adjustment clock;
At least one of the clock delay means and the second clock delay means, the comparison means and the second comparison means, and the parallelization means and the second parallelization means is configured by the same thing. 8. The clock data recovery circuit according to claim 7, wherein: A clock data recovery circuit according to any one of claims 1 to 15,
A signal processing circuit that operates using a combination of a signal and a clock that are output in a synchronously adjusted state from the synchronization adjusting means;
An electronic device comprising:

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