JP4774056B2 - トランザクショナルなメモリアクセスのハイブリッドハードウェア・ソフトウェア実現のための方法及び装置 - Google Patents
トランザクショナルなメモリアクセスのハイブリッドハードウェア・ソフトウェア実現のための方法及び装置 Download PDFInfo
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Description
Claims (28)
- トランザクショナルキャッシュ及びレギュラーキャッシュを含むプロセッサと、
トランザクショナルなメモリアクセスを実現するためにハードウェアモード又はソフトウェアモードのうちの一方を選択するポリシマネージャと
を具備する装置であって、
前記ハードウェアモードでは、トランザクショナルなメモリ読出し動作及びメモリ書込み動作を実行するために前記トランザクショナルキャッシュが利用され、前記ソフトウェアモードでは、通常の(regular)読出し命令及び書込み命令による通常のメモリ読出し動作及びメモリ書込み動作を実行するために前記レギュラーキャッシュが利用される、装置。 - 前記トランザクショナルキャッシュにおいて、前記トランザクショナルなメモリ読出し動作及び書込み動作を実行するために十分なメモリ資源が存在する場合、前記トランザクショナルなメモリアクセスを完了するためにコミット命令が発行される、請求項1に記載の装置。
- 競合するトランザクショナルなメモリ読出し動作及びメモリ書込み動作が検出される場合、アボート命令が発行される、請求項1または2に記載の装置。
- 前記トランザクショナルキャッシュに不十分なメモリ資源が検出される場合、アボート命令が発行される、請求項1から3のいずれかに記載の装置。
- 前記ハードウェアモードに対してアボート命令が発行される場合、前記ポリシマネージャは前記ソフトウェアモードを選択し、そこでは、前記レギュラーキャッシュにおいて通常の(regular)読出し命令及び書込み命令を使用して通常のメモリ読出し動作及びメモリ書込み動作が実行される、請求項3または4に記載の装置。
- 前記ソフトウェアモードで動作している時、競合する書込みトランザクションが検出される場合、アボート命令が発行される、請求項5に記載の装置。
- 競合する書込みトランザクションが検出されない場合、前記メモリアクセスを完了するためにコミット命令が発行される、請求項5または6に記載の装置。
- ポリシマネージャが、トランザクショナルなメモリアクセスを実現するためにハードウェアモード又はソフトウェアモードのうちの一方を選択すること、
プロセッサが、前記ハードウェアモードにおいてトランザクショナルキャッシュを利用してトランザクショナルなメモリ読出し動作及びメモリ書込み動作を実行すること、並びに
前記プロセッサが、前記ソフトウェアモードにおいてレギュラーキャッシュを利用して通常の読出し命令及び書込み命令による通常のメモリ読出し動作及びメモリ書込み動作を実行すること
を含む方法。 - 前記プロセッサが、前記トランザクショナルキャッシュにおいて、前記トランザクショナルなメモリ読出し動作及びメモリ書込み動作を実行するために十分なメモリ資源が存在する場合、前記トランザクショナルなメモリアクセスを完了するためにコミット命令を発行することをさらに含む、請求項8に記載の方法。
- 前記プロセッサが、競合するトランザクショナルなメモリ読出し動作及びメモリ書込み動作が検出される場合、アボート命令を発行することをさらに含む、請求項8または9に記載の方法。
- 前記プロセッサが、前記トランザクショナルキャッシュに不十分なメモリ資源が検出される場合、アボート命令を発行することをさらに含む、請求項8から10のいずれかに記載の方法。
- 前記ハードウェアモードにおいてアボート命令が発行される場合、
前記ポリシマネージャが、前記ソフトウェアモードを選択すること、並びに
前記プロセッサが、通常の読出し命令及び書込み命令を使用して前記レギュラーキャッシュにおいて通常のメモリ読出し動作及びメモリ書込み動作を実行すること
をさらに含む、請求項10または11に記載の方法。 - 前記プロセッサが、前記ソフトウェアモードで動作している間、競合する書込みトランザクションが検出される場合、アボート命令を発行することをさらに含む、請求項12に記載の方法。
- 前記プロセッサが、競合する書込みトランザクションが検出されない場合、前記メモリアクセスを完了するコミット命令を発行することをさらに含む、請求項12または13に記載の方法。
- コンピュータシステムにより実行されるプログラムであって、
当該プログラムは、前記コンピュータシステムに、
トランザクショナルなメモリアクセスを実現するためにハードウェアモード又はソフトウェアモードのうちの一方を選択すること、
前記ハードウェアモードにおいてトランザクショナルキャッシュを利用してトランザクショナルなメモリ読出し動作及びメモリ書込み動作を実行すること、並びに
前記ソフトウェアモードにおいてレギュラーキャッシュを利用して通常の読出し命令及び書込み命令による通常のメモリ読出し動作及びメモリ書込み動作を実行すること
を実行させるプログラム。 - 当該プログラムは、前記コンピュータシステムに、前記トランザクショナルキャッシュにおいて前記トランザクショナルなメモリ読出し動作及びメモリ書込み動作を実行するために十分なメモリ資源が存在する場合に、前記トランザクショナルなメモリアクセスを完了するコミット命令を発行する動作を実行させる、請求項15に記載のプログラム。
- 当該プログラムは、前記コンピュータシステムに、競合するトランザクショナルなメモリ読出し動作及びメモリ書込み動作が検出される場合にアボート命令を発行する動作を実行させる、請求項15または16に記載のプログラム。
- 当該プログラムは、前記コンピュータシステムに、前記トランザクショナルキャッシュにおいて不十分なメモリ資源が検出される場合にアボート命令を発行する動作を実行させる、請求項15から17のいずれかに記載のプログラム。
- 当該プログラムは、前記コンピュータシステムに、
前記ハードウェアモードにおいてアボート命令が発行される場合、
前記ソフトウェアモードを選択する動作と、
通常の読出し命令及び書込み命令を使用して前記レギュラーキャッシュにおいて通常のメモリ読出し動作及びメモリ書込み動作を実行する動作と
をさらに実行させる、請求項17または18に記載のプログラム。 - 当該プログラムは、前記コンピュータシステムに、前記ソフトウェアモードで動作している間、競合する書込みトランザクションが検出される場合にアボート命令を発行する動作を実行させる、請求項19に記載のプログラム。
- 当該プログラムは、前記コンピュータシステムに、競合する書込みトランザクションが検出されない場合に前記メモリアクセスを完了するコミット命令を発行する動作を実行させる、請求項19または20に記載のプログラム。
- トランザクショナルキャッシュ及びレギュラーキャッシュを含むプロセッサと、
データベースのメモリにアクセスするアプリケーションプログラムインタフェース(API)要求に応じてトランザクショナルなメモリアクセスを実現するためにハードウェアモード又はソフトウェアモードのうちの一方を選択するポリシマネージャと
を具備するコンピュータシステムであって、
前記ハードウェアモードでは、トランザクショナルなメモリ読出し動作及びメモリ書込み動作を実行するために前記トランザクショナルキャッシュが利用され、前記ソフトウェアモードでは、通常の読出し命令及び書込み命令による通常のメモリ読出し動作及びメモリ書込み動作を実行するために前記レギュラーキャッシュが利用される、コンピュータシステム。 - 前記トランザクショナルキャッシュにおいて、前記トランザクショナルなメモリ読出し動作及びメモリ書込み動作を実行するために十分なメモリ資源が存在する場合、前記トランザクショナルなメモリアクセスを完了するためにコミット命令が発行される、請求項22に記載のコンピュータシステム。
- 競合するトランザクショナルなメモリ読出し動作及びメモリ書込み動作が検出される場合、アボート命令が発行される、請求項22または23に記載のコンピュータシステム。
- 前記トランザクショナルキャッシュに不十分なメモリ資源が検出される場合、アボート命令が発行される、請求項22から24のいずれかに記載のコンピュータシステム。
- 前記ハードウェアモードに対してアボート命令が発行される場合、前記ポリシマネージャは前記ソフトウェアモードを選択し、そこでは、前記レギュラーキャッシュにおいて通常の読出し命令及び書込み命令を使用して通常のメモリ読出し動作及びメモリ書込み動作が実行される、請求項24または25に記載のコンピュータシステム。
- 前記ソフトウェアモードで動作している時、競合する書込みトランザクションが検出される場合、アボート命令が発行される、請求項26に記載のコンピュータシステム。
- 競合する書込みトランザクションが検出されない場合、前記メモリアクセスを完了するためにコミット命令が発行される、請求項26または27に記載のコンピュータシステム。
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US10/956,179 | 2004-09-30 | ||
US10/956,179 US7856537B2 (en) | 2004-09-30 | 2004-09-30 | Hybrid hardware and software implementation of transactional memory access |
PCT/US2005/033917 WO2006039174A1 (en) | 2004-09-30 | 2005-09-21 | Hybrid hardware and software implementation of transactional memory access |
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US7921407B2 (en) * | 2004-08-10 | 2011-04-05 | Oracle America, Inc. | System and method for supporting multiple alternative methods for executing transactions |
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