JP4770766B2 - Cache memory device, cache management method thereof, and cache management program - Google Patents

Description

  The present invention relates to a cache memory device that temporarily stores and transfers data in response to an I / O command from a host device to a main storage device, a cache management method thereof, and a cache management program. The present invention relates to a cache memory device that executes exclusive control on the cache, a cache management method thereof, and a cache management program.

  Conventionally, a disk array device is equipped with a cache memory for processing I / O instructions at high speed, and if a cache hit occurs in response to a read I / O instruction from a host, data is not accessed without accessing a low-speed disk array. Is output to the host, and high-speed response is possible. The write I / O instruction completion is output when data is written to the cache memory in response to a write I / O instruction from the host. The high-speed response is possible by transferring to and storing in the disk array.

  For example, Patent Document 1 discloses a storage control device that enables faster response by recording management information in a cache memory in a local memory and performing two-way management as an example using such a conventional technique. Has been.

  Patent Document 2 discloses a storage subsystem in which controllers are multiplexed, and I / O instructions from different controllers compete with the cache memory by individually allocating a cache area to be used for each controller. A storage subsystem is disclosed in which the response delay is reduced.

  Further, Patent Document 3 discloses a disk array device equipped with a plurality of host directors and a shared memory of a disk cache shared by these host directors, and management information indicating cache page open / close processing in the shared memory. Is disclosed in the disk array device which shortens the access time to the management information of the cache page by recording the cache page in the local memory of each host director without recording it in the shared memory and keeping the cache page in a steady open state. Has been.

JP 2001-166993 A JP-A-9-146842 JP 2003-228461 A

  However, these disclosed prior arts have a problem that the response delay due to the exclusive control when the I / O instruction conflicts with the same cache page when using the cache memory is not improved.

  For example, as shown in FIG. 11, a conventional storage apparatus including a main control unit 250 that performs exclusive control of memory use by dividing a data storage area 241 of a cache memory 240 into cache pages 0 to N of fixed-length partitions. When a write I / O instruction is input from the server 100 on the host side, the cache page 1 that can process the I / O length is acquired and data is received, and RAID processing is performed using the data to perform internal processing within the disk enclosure 300. Writing to the physical disk (PD) was performed.

  In such a conventional apparatus, assuming that cache pages 0 to N have a fixed length of 64 sectors (32 KB) per page, a sequential write I / O instruction of 1 sector is continuously issued from the server 100 on the host side. In this case, the cache page 1 for processing the first sector is selected, and the cache page 1 is excluded until the one sector is processed and written to the physical disk (PD), and the write I / I of the next one sector is excluded. The O command enters a standby state.

  This exclusive control for each cache page is a process for preventing another I / O instruction from accessing a cache page in use or executing an eviction process. There is a problem in that a response delay occurs due to waiting for a write I / O instruction, and an I / O error occurs if the response is further deteriorated.

[the purpose]
Therefore, the present invention improves the above-described problems of the prior art, reduces the delay in the write I / O instruction completion response caused by the exclusive control of the cache page in the disk cache, and always guarantees the response performance of the cache hit write. Is the purpose.

To achieve the above object, a cache memory device according to the present invention includes a cache memory that temporarily stores data input and output between a host device and a main memory, and the cache memory is divided into a plurality of cache pages. had cache area, a cache memory device, writes the data the following write I / O instruction to the main memory from the previous SL host device to the corresponding cache page, the cache memory management means for transferring to said main memory asynchronously A completion notification means for outputting a completion notification of the I / O instruction to the upper device at the timing when the data is written to the cache page, and this processing during the processing of the I / O instruction from the upper device. The cache page is prevented from being accessed by another I / O instruction. And a cache page exclusive control means for exclusively controlling Yasshupeji, said cache memory has a pseudo cache page is a separate storage area from that of the cache area, the cache memory management means, before Symbol cache page exclusive control means The write I / O instruction rejected by the function is received and data is written to the pseudo cache page, and the pseudo cache page is designated as the write I / O instruction for the data at the timing of writing the data to the pseudo cache page. is provided with a function to be associated with the cache page, the completion notification means includes a function of outputting a completion notification of the I / O instruction by the data in the pseudo-cache pages are written timing, the cache memory management means Is the pseudo-cache The data stored in the over-di, characterized in that the exclusive state of the cache page that correlated with the pseudo-cache page is provided with a function of writing to the cache page is released timing by the cache page exclusive control unit.

According to such a cache memory device, the cache memory has a pseudo cache page as a separate storage area to the cache page, the write I / O instruction was rejected by the key Yasshupeji exclusive control unit, the cache memory management means Accept and write data to the pseudo cache page, and when the data is written to the pseudo cache page, the completion notification means outputs a completion notification of the I / O instruction, so the write I / O instruction completion caused by the exclusive control of the cache page is completed. Response delay can be reduced.

Pseudo cache pages, because the cache page may be stored time only data to complete the I / O processing, it is possible to reduce the storage capacity.

  In the above cache memory device, the above-described pseudo cache page may be a fixed-length partition similar to the cache page. In this way, the pseudo cache page can be linked to one of the cache pages, and data can be easily transferred to the corresponding cache page.

Data can be linked to a cache page in a pseudo cache page that stores the data in a pseudo cache page can be directly transferred to the corresponding cache page.

  Further, in the above cache memory device, when the above-mentioned cache memory management unit newly conflicts with a write I / O instruction for an exclusive cache page, data is stored in a pseudo cache page associated with the cache page. May be provided with a function of integrating the data in the pseudo cache page. In this way, no matter how much the write I / O instruction competes with the cache page in the exclusive state, the completion response is not delayed.

Next, the cache management method of the present invention includes a cache memory for temporarily storing data input / output between the host device and the main memory, and the cache memory has a cache area divided by a plurality of cache pages. In the cache memory device, during the processing of the I / O instruction from the host device, the cache management for exclusive control of the cache page so that the cache page related to this processing is not accessed by another I / O instruction A storage area of the cache memory when a write I / O instruction for the main memory from the host device is input and a cache page specified by the write I / O instruction is set to an exclusive state. Among the cache pages that are allocated separately from the cache page. Write the data according to the I / O instruction, correspondence to the cache page write I / O command according to the pseudo-cache page to the data is designated, the in the said pseudo-cache page data is written timing I / O instruction completion notification is output to the host device, and the data stored in the pseudo cache page associated with the cache page is written to the cache page at the timing when the exclusive state of the cache page is released It is characterized by that.

  In the above cache management method, the above-described pseudo cache page may be a fixed-length partition similar to the cache page.

  In the above cache management method, when a new write I / O instruction conflicts with an exclusive cache page, data is written to the pseudo cache page associated with the cache page. A data integration step for integrating the data in the page may be provided.

  According to such a cache management method, when the cache page specified by the write I / O instruction is in the exclusive state, the data indicated by the write I / O instruction is written to the pseudo cache page previously secured in the cache memory. Since the completion notification of the I / O instruction is output at the timing when the data is written to the pseudo cache page, the write I / O instruction completion response delay caused by the exclusive control of the cache page is delayed as in the cache memory device described above. Can be reduced.

Next, a cache management program according to the present invention includes a cache memory for temporarily storing data input / output between a host device and a main memory, and the cache memory has a cache area divided by a plurality of cache pages. I / O command input processing for inputting a write I / O command for the main memory from the host device to a computer that controls the operation of the cache memory device provided, and the data corresponding to the write I / O command Data write processing to be written to the cache page, completion notification processing to output a completion notification of the I / O instruction to the host device at the timing when the data is written to the cache page, and data stored in the cache page Data transfer processing for asynchronously transferring data to the main memory, and the host device A cache page exclusive control processing cache page according to the process during processing of I / O instruction is performing exclusive control of the cache page so that it is not subject to access by another I / O commands from the previous SL cache page exclusive control accept the write I / O instruction was rejected by the process, and a pseudo cache page program process to write data to the pseudo cache page and the cache page of the storage area which is an area that is reserved separately from the cache memory, wherein A pseudo cache page association process for associating the pseudo cache page with the cache page specified in the write I / O instruction for the data at the timing of writing the data to the pseudo cache page, and the data is written to the pseudo cache page. I / A pseudo completion notification process of outputting a completion notification of the instruction, the data stored in the pseudo cache page, at the timing when the exclusive state is released by the cash scan page exclusive control processing of the cache page that correlated with the pseudo-cache page A cache page writing process for writing to the cache page is executed.

  In the above cache management program, the above-described pseudo cache page may be a fixed-length partition similar to the cache page.

  In the above cache management program, when a new write I / O instruction competes with an exclusive cache page, data is written to the pseudo cache page associated with the cache page. You may make a computer perform the data integration process which integrates the data in this.

According to the cache management program, key Yasshupeji exclusive control processing dismissed was accepted the write I / O instruction by the pseudo cache page cache page of the storage area of the cache memory is an area that is reserved separately Since the I / O instruction completion notification is output at the timing when the data is written to the pseudo cache page, the write I / O instruction completion caused by the exclusive control of the cache page is completed as in the cache memory device described above. Response delay can be reduced.

To present invention is constituted as described above functions, by which, by accepting a write I / O instruction was rejected by the exclusive control without waiting separately secured to the cache page of the storage area of the cache memory Data is written to the pseudo cache page, which is the specified area, a notification of completion of the I / O instruction is output at the timing when the data is written to the pseudo cache page, and when the exclusive control of the cache page is released, Since the data written in the associated pseudo cache page is written to the cache page, the write I / O instruction completion response delay caused by the exclusive control of the cache page is eliminated, and the response performance of the cache hit write is always improved. It can be guaranteed and pseudo cache page, cache Since Yupeji is may be stored time only data to complete the I / O processing, it can be set small storage capacity of the pseudo cache page.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of the cache memory device of this embodiment. As shown in FIG. 1, the cache memory device 200 of this embodiment is mounted in a storage device 400 connected to a server 100 that is a host device, and a disk enclosure 300 and a disk mounted with a desk array corresponding to a main memory. The connection is made through the adapter 402, and the connection with the server 100 is made through the host adapter 401.

  The cache memory device 200 of this embodiment includes a main control unit 230 that controls the operation of the cache memory device 200 and a cache memory 240 that temporarily stores data input and output between the server 100 and the disk enclosure 300. Configured.

  The cache memory 240 has a cache area 241 divided by fixed-length cache pages 0 to N, and stores control data 240A for managing the cache pages 0 to N. Further, the cache memory 240 has a pseudo cache area 242 composed of fixed-length pseudo cache pages A to J separately from the cache pages 0 to N, and a pseudo cache control for managing the pseudo cache pages A to J. Data 240B is stored.

  The main control unit 230 writes data to the corresponding page among the cache pages 0 to N in accordance with a write I / O command for the disk enclosure 300 from the server 100 and transfers the data to the disk enclosure 300 for asynchronous writing to the corresponding logical disk. A cache memory management unit 231, a completion notification unit 232 that outputs an I / O instruction completion notification to the server 100 at a timing when data is written to the cache pages 0 to N, and an I / O instruction from the server 100 being processed Cache page exclusive control means 233 for performing exclusive control of the cache pages 0 to N so that one of the cache pages 0 to N related to this processing is not accessed by another I / O instruction.

  The cache memory management unit 231 receives the write I / O instruction that competes with one of the cache pages 0 to N and is rejected by the cache page exclusive control unit 233, and stores data in any of the pseudo cache pages A to J. , A function of associating one of the pseudo cache pages A to J with one of the corresponding cache pages 0 to N at a timing when data is written to one of the pseudo cache pages A to J, and a cache page 0 When a write I / O instruction newly conflicts with a page in the exclusive state among .about.N, data is written to one of the pseudo cache pages A to J associated with the page and the data in this pseudo cache page. Stored in one of the pseudo cache pages A to J of the pseudo cache area 242 Over data to the exclusive state of the cache page associated with one of its pseudo cache page A~J and a function of writing to the cache page at the timing is canceled by the cache page exclusive control unit 233.

  The completion notifying unit 232 has a function of outputting an I / O instruction completion notification at a timing when data is written to the pseudo cache area 242.

  Each of the cache pages 0 to N and the pseudo cache pages A to J in the cache memory 240 is a fixed-length block area. In the present embodiment, this fixed length is set to 64 sectors (32 KB). As shown in FIG. 2, the control data 240A stored in the cache memory 240 includes an associated logical disk number (LDN) and an associated leading logical sector address (for each cache page 0 to N). LSN), logical sector address (Dirty) indicating the storage range of the written data, logical sector address (Clean) indicating the storage range of the transferred data, and information indicating whether or not the exclusive state is set (Size) The corresponding item is rewritten in synchronization with the data being recorded in any one of the cache pages 0 to N by the cache memory management means 231.

  Further, as shown in FIG. 3, the pseudo cache control data 240B includes, for each of the pseudo cache pages A to J, an associated logical disk number, an associated head logical sector address, and written data. This is information in which a logical sector address indicating a storage range and a corresponding cache page number are associated with each other. Corresponding to data recorded in any one of the pseudo cache pages A to J by the cache memory management unit 231 By rewriting the item to be performed, the pseudo cache page is associated with one of the cache pages 0 to N. In addition, the pseudo cache control data 240B is reset in synchronization with the data stored in any of the pseudo cache pages A to J being transferred to the corresponding cache page by the cache memory management unit 231.

  Here, the above-described main control unit 230, that is, the cache memory management unit 231, the completion notification unit 232, and the cache page exclusion control unit 233 may be configured such that the function content is programmed and executed by a computer.

  Next, the overall operation of this embodiment will be described. Here, the cache management method will be described at the same time by showing each step.

  FIG. 4 is a flowchart showing the operation of the cache memory device 200 of this embodiment. 5 to 10 exemplify a case where write I / O instructions for each sector are continuously issued from the host server 100 to the logical disk managed by the cache memory device 200. 6 is an explanatory diagram showing a processing operation of the cache memory device 200 of FIG.

  First, as shown in [Procedure 1] in FIG. 5, the host server 100 continuously issues a write I / O command for each sector from the logical sector address 0 × 210 of the logical disk number 4. When the cache memory device 200 inputs this write I / O command (Yes in step S1 in FIG. 4, I / O command input step), as shown in [Procedure 2] in FIG. The memory management unit 231 refers to the control data 240A and searches for a cache page associated with 64 sectors from the logical sector address 0 × 200 of the logical disk (step S2 in FIG. 4).

  As a result of the search, cache hit write is possible when the associated cache page is found and the cache page is not used by other tasks, or when there is no associated page and a newly associated cache page is created If not (No in step S3 in FIG. 4), the associated cache page is acquired as it is. In this embodiment, the cache page 1 is acquired.

  When the acquisition of the cache page 1 is completed, as shown in [Procedure 3] in FIG. 6, the cache memory management unit 231 stores the data from the server 100 in the cache page 1 and the write range address of the control data 240A. The exclusive state information is updated (step S4 in FIG. 4).

  Then, as shown in [Procedure 4] in FIG. 6, the completion notifying means 232 of the cache memory device 200 notifies the server 100 of the completion of the write processing (step S5 in FIG. 4), and then stored in the cache page 1. In order to write the data to the corresponding logical disk, the cache memory management unit 231 transfers the data to the disk enclosure 300 (step S6 in FIG. 4).

  On the other hand, as a result of searching for the cache pages 0 to N, the associated cache page 1 is found, and the cache page 1 is being used by another task, that is, the cache page 1 is set to the exclusive state (see FIG. 4), the conventional disk array apparatus needs to wait for the release of the cache page 1 as shown in FIG. 7, but in this embodiment, no waiting for release is performed here. As shown in [Procedure 8], the cache memory management unit 231 acquires the pseudo cache page A among the pseudo cache pages A to J.

  The pseudo cache pages A to J are fixed-length areas like the cache pages 0 to N, and are temporarily used until one of the cache pages 0 to N in the exclusive state is released. As shown in [Procedure 9] in FIG. 8, the cache memory management unit 231 stores the data in the pseudo cache page A (step S9 in FIG. 4, pseudo cache page write step), and updates the pseudo cache page control data. Then, the cache page 1 is associated with the pseudo cache page A (pseudo cache page association step). Then, the completion notification means 232 notifies the server 100 of the completion of the write process (step S10 in FIG. 4, pseudo completion notification step). As a result, the response performance in the cache hit write state is always guaranteed.

  The data of the pseudo cache page A is held until the exclusive state of the cache page 1 is released by the cache page exclusive control means 233. As shown in [Procedure 11] in FIG. 9, when a competing write I / O instruction is issued and received before the cache page 1 is released (Yes in step S8 in FIG. 4), cache memory management means 231 writes data to the pseudo cache page A, and merges (integrates) the data in the pseudo cache page A (step S14 in FIG. 4, data integration step).

  Then, as shown in [Procedure 13] in FIG. 10, at the timing when the cache page 1 is released by the cache page exclusive control means 233 (step S11 in FIG. 4), the cache memory management means 231 The data is replaced with the cache page 1 (step S12 in FIG. 4, cache page writing step). When the cache memory management unit 231 stores the data in the pseudo cache page A in the cache page 1, the cache memory management unit 231 updates the write range address and the exclusive state information of the control data 240A. Thereafter, in order to write the data stored in the cache page 1 to the corresponding logical disk, the cache memory management unit 231 transfers the data to the disk enclosure 300 (step S13 in FIG. 4).

  Since the cache memory device 200 of the present embodiment is configured and operates as described above, there is no response delay due to I / O instruction contention to the same cache page, and the cache hit write response performance is always guaranteed. it can.

  Here, the cache memory device 200 according to the present embodiment has a configuration that is mounted in the storage device 400 that stores data from the server 100. However, the present invention is not limited to this, and may be installed in an information processing terminal such as a client terminal.

It is a block diagram which shows the structure of the cache memory apparatus of one Embodiment in this invention. It is a figure which shows the control data in embodiment disclosed by FIG. It is a figure which shows the pseudo control data in embodiment disclosed by FIG. 2 is a flowchart illustrating an operation of the cache memory device according to the embodiment disclosed in FIG. 1; It is explanatory drawing which shows a part of example of the whole operation | movement of embodiment disclosed by FIG. It is explanatory drawing which shows a part of example of the whole operation | movement of embodiment disclosed by FIG. It is explanatory drawing which shows a part of example of the whole operation | movement of embodiment disclosed by FIG. It is explanatory drawing which shows a part of example of the whole operation | movement of embodiment disclosed by FIG. It is explanatory drawing which shows a part of example of the whole operation | movement of embodiment disclosed by FIG. It is explanatory drawing which shows a part of example of the whole operation | movement of embodiment disclosed by FIG. It is a block diagram which shows the conventional storage apparatus.

Explanation of symbols

0-N Cache page 100 Server 110 Host bus adapter 200 Cache memory device 230 Main controller 231 Cache memory management means 232 Completion notification means 233 Cache page exclusive control means 240 Cache memory 240A Control data 240B Pseudo cache control data 241 Cache area 242 Pseudo Cache area 300 Disk enclosure 400 Storage device 401 Host adapter 402 Disk adapter A to J Pseudo cache page

Claims (9)

In a cache memory device that includes a cache memory that temporarily stores data input and output between a host device and a main memory, and the cache memory has a cache area divided by a plurality of cache pages,
Writing the data according to the write I / O command for the main memory from the previous SL host device to the corresponding cache page, the cache memory management means for transferring to said main memory asynchronously, the data in the cache page is written Completion notification means for outputting a completion notification of the I / O instruction to the higher-level device at a timing, and a cache page related to this processing accessed by another I / O command during processing of the I / O command from the higher-level device Cache page exclusive control means for exclusive control of the cache page so as not to receive,
Said cache memory has a pseudo cache page is a separate storage area from that of the cache area, the cache memory management means, before Symbol cache page exclusive control unit by rejected is write I / O the instruction accepting pseudo A function of writing data to a cache page, and a function of associating the pseudo cache page with a cache page specified in a write I / O instruction related to the data at a timing of writing the data to the pseudo cache page Means has a function of outputting a completion notification of the I / O instruction at a timing when the data is written to the pseudo cache page;
A function in which the cache memory management unit writes data stored in the pseudo cache page to the cache page at a timing when the exclusive state of the cache page associated with the pseudo cache page is released by the cache page exclusive control unit cache memory device characterized by comprising a. The cache memory device according to claim 1,
The cache memory device, wherein the pseudo cache page is a fixed-length partition similar to the cache page. In the cache memory device according to claim 1 or 2,
When the cache memory management means further conflicts with a write I / O instruction for the cache page in the exclusive state, the cache memory management means writes data to the pseudo cache page associated with the cache page and stores the data in the pseudo cache page. A cache memory device having a function of integrating. A cache memory device having a cache memory for temporarily storing data input / output between a host device and a main memory, the cache memory having a cache area divided by a plurality of cache pages, the host device In a cache management method for exclusive control of the cache page so that the cache page related to this process is not accessed by another I / O instruction during the processing of an I / O instruction from
Input a write I / O command for the main memory from the host device ,
When the cache page specified by the write I / O instruction is set to the exclusive state, the write I / O is added to the pseudo cache page which is an area secured separately from the cache page in the storage area of the cache memory. write the data according to the O instruction, associating the specified cache pages in the write I / O command according to the pseudo-cache page in the data,
Output the completion notification of the I / O instruction to the host device at the timing when the data is written to the pseudo cache page
A cache management method , wherein data stored in the pseudo cache page associated with the cache page is written to the cache page at a timing when the exclusive state of the cache page is released . In the cache management method according to claim 4,
A cache management method, wherein the pseudo cache page is set to a fixed-length partition similar to the cache page. In the cache management method according to claim 4 or 5,
If the further light I / O command to the cache page of the exclusive state is conflict, and Turkey to integrate the data in the pseudo-cache page write data to the pseudo cache page associated with that cache page A cache management method characterized by the above. A computer having a cache memory for temporarily storing data input / output between a host device and a main memory, and the cache memory having a cache area divided by a plurality of cache pages. ,
I / O command input processing for inputting a write I / O command for the main memory from the host device, data write processing for writing the data to a corresponding cache page according to the write I / O command, and the cache page A completion notification process for outputting the completion notification of the I / O instruction to the host device at a timing when the data is written to the host device, and a data transfer process for asynchronously transferring the data stored in the cache page to the main memory. A cache page exclusive control process for performing exclusive control of the cache page so that the cache page related to this process is not accessed by another I / O instruction during processing of the I / O instruction from the host device ;
Previous Stories cache page exclusive control dismissed was accepted the write I / O instruction by the processing, the pseudo cache pages from said cache page of the storage area of the cache memory and writes the data to the pseudo cache page is an area that is reserved separately A write process, a pseudo cache page associating process for associating the pseudo cache page with the cache page specified in the write I / O instruction for the data at the timing of writing the data to the pseudo cache page, and the pseudo cache page A pseudo-completion notification process for outputting a notification of completion of the I / O instruction at the timing when the data is written to the cache page, and an exclusive state of the cache page in which the data stored in the pseudo-cache page is associated with the pseudo-cache page Is the above-mentioned Program cache management, characterized in that to execute a cache page program process of writing at the timing is canceled by di exclusive control processing to the cache page. In the cache management program according to claim 7,
A cache management program, wherein the pseudo cache page is set to a fixed-length partition similar to the cache page. In the cache management program according to claim 7 or 8,
When a write I / O instruction conflicts with the cache page in the exclusive state, a data integration process is performed in which data is written to the pseudo cache page associated with the cache page and the data in the pseudo cache page is integrated. A cache management program which is executed by the computer.

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