JP4757835B2 - Differential transmission circuit - Google Patents

Differential transmission circuit Download PDF

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JP4757835B2
JP4757835B2 JP2007125136A JP2007125136A JP4757835B2 JP 4757835 B2 JP4757835 B2 JP 4757835B2 JP 2007125136 A JP2007125136 A JP 2007125136A JP 2007125136 A JP2007125136 A JP 2007125136A JP 4757835 B2 JP4757835 B2 JP 4757835B2
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differential transmission
circuit
transmission circuit
capacitor
resistors
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JP2008283411A (en
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稔 富樫
純 寺田
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Nippon Telegraph and Telephone Corp
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Description

本発明は、送信回路の第１および第２の送端トランジスタのエミッタと、受信回路の第１および第２の終端抵抗の片端が接続された入力バッファの２個の入力端子との間に、差動伝送線路を接続して構成した差動伝送回路に関するものである。   According to the present invention, between the emitters of the first and second transmission end transistors of the transmission circuit and the two input terminals of the input buffer to which one ends of the first and second termination resistors of the reception circuit are connected, The present invention relates to a differential transmission circuit configured by connecting differential transmission lines.

伝送回路に関する従来技術として、特許文献１に示す伝送回路がある。この伝送回路は送信回路の送端トランジスタのエミッタと受信回路の入力バッファとの間を１本の伝送線路で接続して構成したものである。   As a conventional technique related to a transmission circuit, there is a transmission circuit disclosed in Patent Document 1. This transmission circuit is constructed by connecting a single transmission line between the emitter of the transmitting transistor of the transmitting circuit and the input buffer of the receiving circuit.

この技術を用いた従来の差動伝送回路の一例を図５に示す。この従来例は、集積回路からなる送信回路１０の送端トランジスタＱ１１，Ｑ１２のエミッタと、集積回路からなる受信回路２０の終端抵抗Ｒ２１，Ｒ２２をもつ入力バッファ２１との間を、プリント基板上において、２本の線路３１，３２からなる差動伝送線路３０で接続したものである。終端抵抗Ｒ２１，Ｒ２２の他端は電圧端子ＶＧ２１（例えば、ＧＮＤ端子）に接続されている。
特開平６−１５２３７８号公報 An example of a conventional differential transmission circuit using this technique is shown in FIG. In this conventional example, between the emitters of the transmitting transistors Q11 and Q12 of the transmitting circuit 10 made of an integrated circuit and the input buffer 21 having the terminating resistors R21 and R22 of the receiving circuit 20 made of the integrated circuit, on the printed circuit board. A differential transmission line 30 composed of two lines 31 and 32 is connected. The other ends of the termination resistors R21 and R22 are connected to a voltage terminal VG21 (for example, a GND terminal).
JP-A-6-152378

ところが、この差動伝送線路３０の線路３１，３２を経由して、送信回路１０から受信回路２０に対して１０Ｇｂ／ｓのランダム信号（図６(a)参照）を送信するとき、同相の５ＧＨｚのノイズが混入すると、図７(a)に示すように、アイパターンがうねる問題が発生する。また、５ＧＨｚのノイズでなく、１００ＭＨｚのノイズが混入するときは、図７(b)に示すように、アイパターンの開口が劣化してしまう。   However, when a 10 Gb / s random signal (see FIG. 6A) is transmitted from the transmission circuit 10 to the reception circuit 20 via the lines 31 and 32 of the differential transmission line 30, the in-phase 5 GHz is transmitted. When the noise is mixed, there arises a problem that the eye pattern swells as shown in FIG. Further, when 100 MHz noise is mixed instead of 5 GHz noise, the opening of the eye pattern deteriorates as shown in FIG.

本発明の目的は、このようなノイズによる悪影響を回避し、ノイズ耐性が高く良好なアイパターンで信号伝送ができるようにした差動伝送回路を提供することである。   SUMMARY OF THE INVENTION An object of the present invention is to provide a differential transmission circuit that avoids such an adverse effect caused by noise and that can perform signal transmission with a good eye pattern with high noise resistance.

上記目的を達成するために、請求項１にかかる発明の差動伝送回路は、送信回路の第１、第２の送端トランジスタのエミッタと、受信回路の終端用の第１、第２の抵抗のそれぞれの片端との間に、差動伝送線路又は差動伝送配線を接続して構成した差動伝送回路において、前記第１、第２の抵抗の各他端を、共通に、電流源に接続すると共に第３の抵抗の片端に接続し、該第３の抵抗の他端を第１のキャパシタを介して第１の電圧端子に接続したことを特徴とする。
請求項２にかかる発明は、請求項１に記載の差動伝送回路において、前記送信回路の前記第１、第２の送端トランジスタ、前記差動伝送線路又は差動伝送配線、前記受信回路の前記第１、第２の抵抗、前記電流源、前記第３の抵抗、および前記第１のキャパシタを、１個の集積回路内に構成したことを特徴とする。
請求項３にかかる発明は、請求項１又は２に記載の差動伝送回路において、前記第１、第２の送端トランジスタのコレクタをそれぞれ第４、第５の抵抗を介して第２の電圧端子に接続し、および／又は前記第１、第２の送端トランジスタのコレクタをそれぞれ第２、第３のキャパシタを介して第３の電圧端子に接続したことを特徴とする。
請求項４にかかる発明は、請求項３に記載の差動伝送回路において、前記第１、第２の送端トランジスタのコレクタを共通接続して、前記第４、第５の抵抗を共通の１個の抵抗とし、および／又は前記第２、第３のキャパシタを共通の１個のキャパシタとしたことを特徴とする。
請求項５にかかる発明は、請求項１又は２に記載の差動伝送回路において、前記第１、第２の送端トランジスタのコレクタをそれぞれ第４、第５の抵抗を介して第２の電圧端子に接続し、該第４、第５の抵抗の前記コレクタと反対側の端子を第２、第３のキャパシタを介して第３の電圧端子に接続したことを特徴とする。
請求項６にかかる発明は、請求項５に記載の差動伝送回路において、前記第１、第２の送端トランジスタのコレクタを共通接続して、前記第４、第５の抵抗を共通の１個の抵抗とし、前記第２、第３のキャパシタを共通の１個のキャパシタとしたことを特徴とする。 In order to achieve the above object, a differential transmission circuit according to a first aspect of the present invention includes an emitter of first and second transmission end transistors of a transmission circuit, and first and second resistors for termination of a reception circuit. In the differential transmission circuit configured by connecting a differential transmission line or a differential transmission wiring between one end of each of the first and second resistors, the other ends of the first and second resistors are commonly used as a current source. The third resistor is connected to one end of the third resistor, and the other end of the third resistor is connected to the first voltage terminal via the first capacitor.
According to a second aspect of the present invention, in the differential transmission circuit according to the first aspect, the first and second transmission end transistors of the transmission circuit, the differential transmission line or the differential transmission wiring, and the reception circuit The first and second resistors, the current source, the third resistor, and the first capacitor are configured in one integrated circuit.
According to a third aspect of the present invention, in the differential transmission circuit according to the first or second aspect, the second voltage is applied to the collectors of the first and second transmission end transistors via the fourth and fifth resistors, respectively. It is characterized in that it is connected to a terminal and / or the collectors of the first and second transmission end transistors are connected to a third voltage terminal via second and third capacitors, respectively.
According to a fourth aspect of the present invention, in the differential transmission circuit according to the third aspect, the collectors of the first and second transmission end transistors are connected in common, and the fourth and fifth resistors are connected in common. And / or the second and third capacitors are one common capacitor.
According to a fifth aspect of the present invention, in the differential transmission circuit according to the first or second aspect, the second voltage is applied to the collectors of the first and second transmission end transistors via the fourth and fifth resistors, respectively. The fourth and fifth resistors are connected to the terminal on the opposite side of the collector, and connected to the third voltage terminal via the second and third capacitors.
According to a sixth aspect of the present invention, in the differential transmission circuit according to the fifth aspect, the collectors of the first and second transmission end transistors are connected in common, and the fourth and fifth resistors are connected in common. It is characterized in that it is a single resistor and the second and third capacitors are one common capacitor.

本発明によれば、終端用の第１、第２の抵抗の各他端を、共通に、電流源に接続すると共に第３の抵抗の片端に接続し、該第３の抵抗の他端を第１のキャパシタを介して第１の電圧端子に接続したことにより、１０Ｇｂ／ｓ以上の信号伝送においても、従来回路よりよりノイズ耐性の高く開口の広いアイパターン特性の差動伝送回路を実現できる。   According to the present invention, the other ends of the first and second resistors for termination are commonly connected to the current source and one end of the third resistor, and the other end of the third resistor is connected to the other end of the third resistor. By connecting to the first voltage terminal via the first capacitor, it is possible to realize a differential transmission circuit with eye pattern characteristics having a higher noise resistance and a wider opening than conventional circuits even in signal transmission of 10 Gb / s or more. .

＜第１の実施例＞
図１は本発明の第１の実施例の差動伝送回路の構成を示す回路図である。本実施例の差動伝送回路は、集積回路からなる送信回路１０の送端トランジスタＱ１１，Ｑ１２のエミッタと、集積回路からなる受信回路２０の終端抵抗Ｒ２１，Ｒ２２をもつ入力バッファ２１との間を、プリント基板上において、２本の線路３１，３２からなる差動伝送線路３０で接続し、終端抵抗Ｒ２１，Ｒ２２の他端を、共通に、電流源Ｉ２１を介して電圧端子ＶＧ２２に、また抵抗Ｒ２３と安定化用のキャパシタＣ２１の直列回路を介して電圧端子ＶＧ２３に、それぞれ接続したものである。電圧端子ＶＧ２２，ＶＧ２３は、例えばＧＮＤ端子である。なお、差動伝送線路３０はプリント基板上のパターン配線に限らず、ケーブルであっても良い。 <First embodiment>
FIG. 1 is a circuit diagram showing a configuration of a differential transmission circuit according to a first embodiment of the present invention. The differential transmission circuit of the present embodiment is provided between the emitters of the transmission end transistors Q11 and Q12 of the transmission circuit 10 made of an integrated circuit and the input buffer 21 having the termination resistors R21 and R22 of the reception circuit 20 made of an integrated circuit. On the printed circuit board, a differential transmission line 30 composed of two lines 31 and 32 is connected, and the other ends of the terminating resistors R21 and R22 are connected in common to the voltage terminal VG22 via the current source I21 and to the resistance. R23 and a stabilizing capacitor C21 are connected to a voltage terminal VG23 through a series circuit. The voltage terminals VG22 and VG23 are, for example, GND terminals. The differential transmission line 30 is not limited to the pattern wiring on the printed board, and may be a cable.

ここで、線路３１，３２のインピーダンスが５０Ωのとき、Ｒ２１＝Ｒ２２＝５０Ω、Ｒ２３＝２５Ω、Ｃ２１＝５ｐＦとすると、図６(a)に示す１０Ｇｂ／ｓのランダム信号を送信回路１０から受信回路２０に向けて線路３１，２２を経由して送信するとき、その線路３１，３２に同相や逆相の５ＧＨｚのノイズあるいは１００ＭＨｚのノイズが重畳した場合、それら抵抗Ｒ２１，Ｒ２２，Ｒ２３、キャパシタＣ２１でノイズに対するマッチング回路が構成されるため、図６(b）に示すように、受信回路２０の入力バッファ２１では、うねりやノイズを除去した波形の信号を受信することができる。しかも、電流源Ｉ２１で定電流を引き抜いているので、伝送電流を所定量以上（例えば、４０％以上）削減でき、消費電力も低減することができる。   Here, when the impedances of the lines 31 and 32 are 50Ω, assuming that R21 = R22 = 50Ω, R23 = 25Ω, and C21 = 5 pF, a 10 Gb / s random signal shown in FIG. When transmitting to the line 20 via the lines 31 and 22, if in-phase or reverse-phase 5 GHz noise or 100 MHz noise is superimposed on the lines 31 and 32, the resistors R 21, R 22, R 23 and the capacitor C 21 Since a matching circuit for noise is configured, as shown in FIG. 6B, the input buffer 21 of the receiving circuit 20 can receive a signal having a waveform from which swell and noise are removed. In addition, since the constant current is drawn by the current source I21, the transmission current can be reduced by a predetermined amount or more (for example, 40% or more), and the power consumption can also be reduced.

一般的に差動伝送回路では、ｆを周波数（ＧＨｚ）とすると、配線長が（１０×１００／ｆ）μｍを超えると配線のインダクタンスを考慮した設計が必要となるが、本実施例によれば、これが緩和される。なお、差動伝送線路３０は、特定の特性インピーダンスをもつ伝送線路ではなく、通常の差動伝送配線に代えてもよい。   In general, in a differential transmission circuit, when f is a frequency (GHz), if the wiring length exceeds (10 × 100 / f) μm, it is necessary to design in consideration of the wiring inductance. This will be mitigated. The differential transmission line 30 may be replaced with a normal differential transmission line instead of a transmission line having a specific characteristic impedance.

＜第２の実施例＞
図２は本発明の第２の実施例の差動伝送回路を示す回路図である。本実施例では、１個の集積回路（半導体チップ）４０内に、前記送信回路１０にと同じ構成の送信回路１０Ａ、前記受信回路１０と同じ構成の受信回路２０Ａおよび前記差動伝送線路３０と同様の差動伝送線路３０Ａをそれぞぞれ構成したものであり、図１と同じ要素には同じ符号を付けた。ここでは、差動伝送線路３０Ａはチップ内配線となる。 <Second embodiment>
FIG. 2 is a circuit diagram showing a differential transmission circuit according to a second embodiment of the present invention. In this embodiment, in one integrated circuit (semiconductor chip) 40, a transmission circuit 10A having the same configuration as the transmission circuit 10, a reception circuit 20A having the same configuration as the reception circuit 10, and the differential transmission line 30 are provided. The same differential transmission line 30A is configured, and the same elements as those in FIG. Here, the differential transmission line 30A serves as an intra-chip wiring.

本実施例でも、前記第１の実施例で説明したと同様にノイズ耐性が向上するので、このように１個の集積回路４０内に構成すると、１０Ｇｂ／ｓの高速なランダム信号を伝送する場合であっても、差動伝送線路３０の配線長を１００μｍ以上に長くすることが可能となる。また、第１の実施例と同様に、差動伝送線路３０Ａは、特定の特性インピーダンスをもつ伝送線路ではなく、通常の差動伝送配線に代えてもよい。   Also in this embodiment, noise resistance is improved in the same manner as described in the first embodiment. Therefore, when configured in one integrated circuit 40 in this way, a high-speed random signal of 10 Gb / s is transmitted. Even so, the wiring length of the differential transmission line 30 can be increased to 100 μm or more. Similarly to the first embodiment, the differential transmission line 30A may be replaced with a normal differential transmission line instead of a transmission line having a specific characteristic impedance.

＜第３の実施例＞
図３は本発明の第３の実施例の差動伝送回路の送信回路１０の一部を示す回路図である。本実施例では、送信回路１０において、送端トランジスタＱ１１のコレクタを抵抗Ｒ１１を介して電圧端子ＶＣＣに接続すると共に、キャパシタＣ１１を介して電圧端子ＶＧ１１に接続し、また、送端トランジスタＱ１２のコレクタを抵抗Ｒ１２を介して電圧端子ＶＣＣに接続すると共に、キャパシタＣ１２を介して電圧端子ＶＧ１２に接続したものである。電圧端子ＶＧ１１，ＶＧ１２は、例えばＧＮＤ端子である。 <Third embodiment>
FIG. 3 is a circuit diagram showing a part of the transmission circuit 10 of the differential transmission circuit according to the third embodiment of the present invention. In the present embodiment, in the transmission circuit 10, the collector of the sending transistor Q11 is connected to the voltage terminal VCC through the resistor R11, and is connected to the voltage terminal VG11 through the capacitor C11. Is connected to the voltage terminal VCC via a resistor R12 and to the voltage terminal VG12 via a capacitor C12. The voltage terminals VG11 and VG12 are, for example, GND terminals.

このようにすると、送端トランジスタＱ１１，Ｑ１２のコレクタに直接ワイヤを介して電圧端子ＶＣＣを接続した場合に、ワイヤの寄生素子成分により発振現象の恐れがあったが、これを予防できる。   In this case, when the voltage terminal VCC is directly connected to the collectors of the transmission end transistors Q11 and Q12 via a wire, there is a fear of an oscillation phenomenon due to a parasitic element component of the wire, but this can be prevented.

なお、抵抗Ｒ１１，Ｒ１２とキャパシタＣ１１，Ｃ１２の一方は削除可能である。また、送端トランジスタＱ１１，Ｑ１２のコレクタを共通接続して、抵抗Ｒ１１とＲ１２を共通の１個の抵抗とし、キャパシタＣ１１とＣ１２を共通の１個のキャパシタとしても、同様の効果がある。   One of the resistors R11 and R12 and the capacitors C11 and C12 can be deleted. The same effect can be obtained by connecting the collectors of the transmission end transistors Q11 and Q12 in common, making the resistors R11 and R12 one common resistor, and the capacitors C11 and C12 one common capacitor.

＜第４の実施例＞
図４は本発明の第４の実施例の差動伝送回路の送信回路１０の一部を示す回路図である。本実施例では、送信回路１０において、送端トランジスタＱ１１のコレクタを抵抗Ｒ１１を介して電圧端子ＶＣＣに接続し、その抵抗Ｒ１１のコレクタと反対側の接続点をキャパシタＣ１１介して電圧端子ＶＧ１１に接続し、また、送端トランジスタＱ１２のコレクタを抵抗Ｒ１２を介して電圧端子ＶＣＣに接続し、その抵抗Ｒ１２のコレクタと反対側の接続点をキャパシタＣ１２介して電圧端子ＶＧ１２に接続したものである。このような構成も、第３の実施例と同様の作用効果を得ることができる。 <Fourth embodiment>
FIG. 4 is a circuit diagram showing a part of the transmission circuit 10 of the differential transmission circuit according to the fourth embodiment of the present invention. In this embodiment, in the transmission circuit 10, the collector of the sending transistor Q11 is connected to the voltage terminal VCC via the resistor R11, and the connection point on the opposite side of the collector of the resistor R11 is connected to the voltage terminal VG11 via the capacitor C11. Further, the collector of the sending transistor Q12 is connected to the voltage terminal VCC via the resistor R12, and the connection point on the opposite side of the collector of the resistor R12 is connected to the voltage terminal VG12 via the capacitor C12. Such a configuration can also obtain the same effects as those of the third embodiment.

なお、送端トランジスタＱ１１，Ｑ１２のコレクタを共通接続して、抵抗Ｒ１１とＲ１２を共通の１個の抵抗とし、キャパシタＣ１１とＣ１２を共通の１個のキャパシタとしても、同様の効果がある。   The same effect can be obtained by connecting the collectors of the transmission end transistors Q11 and Q12 in common, the resistors R11 and R12 as one common resistor, and the capacitors C11 and C12 as one common capacitor.

本発明の第１の実施例の差動伝送回路の回路図である。1 is a circuit diagram of a differential transmission circuit according to a first embodiment of the present invention. 本発明の第２の実施例の差動伝送回路の回路図である。It is a circuit diagram of the differential transmission circuit of the 2nd Example of this invention. 本発明の第３の実施例の差動伝送回路の送信回路の一部の回路図である。It is a circuit diagram of a part of transmission circuit of the differential transmission circuit of the third embodiment of the present invention. 本発明の第４の実施例の差動伝送回路の送信回路の一部の回路図であるIt is a circuit diagram of a part of transmission circuit of the differential transmission circuit of the fourth embodiment of the present invention. 従来の差動伝送回路の回路図である。It is a circuit diagram of the conventional differential transmission circuit. アイパターンについて、(a)は送信信号の波形図、(b)は第１の実施例の受信信号の波形図である。Regarding the eye pattern, (a) is a waveform diagram of a transmission signal, and (b) is a waveform diagram of a reception signal of the first embodiment. アイパターンについて、(a)は５GHｚのノイズ重畳時の受信信号の波形図、(b)は１００ＭＨｚのノイズ重畳時の受信信号の波形図である。Regarding the eye pattern, (a) is a waveform diagram of a reception signal when noise is superimposed at 5 GHz, and (b) is a waveform diagram of a reception signal when noise is superimposed at 100 MHz.

符号の説明Explanation of symbols

１０，１０Ａ：送信回路
２０，２０Ａ：受信回路、２１：入力バッファ
３０，３０Ａ：差動伝送線路
４０：集積回路 10, 10A: Transmission circuit 20, 20A: Reception circuit, 21: Input buffer 30, 30A: Differential transmission line 40: Integrated circuit

Claims (6)

送信回路の第１、第２の送端トランジスタのエミッタと、受信回路の終端用の第１、第２の抵抗のそれぞれの片端との間に、差動伝送線路又は差動伝送配線を接続して構成した差動伝送回路において、
前記第１、第２の抵抗の各他端を、共通に、電流源に接続すると共に第３の抵抗の片端に接続し、該第３の抵抗の他端を第１のキャパシタを介して第１の電圧端子に接続したことを特徴とする差動伝送回路。 A differential transmission line or a differential transmission line is connected between the emitters of the first and second transmitting end transistors of the transmitting circuit and the respective one ends of the first and second resistors for terminating the receiving circuit. In the differential transmission circuit configured as
The other ends of the first and second resistors are connected in common to a current source and to one end of a third resistor, and the other end of the third resistor is connected to the first capacitor via a first capacitor. A differential transmission circuit connected to a voltage terminal of 1. 請求項１に記載の差動伝送回路において、
前記送信回路の前記第１、第２の送端トランジスタ、前記差動伝送線路又は差動伝送配線、前記受信回路の前記第１、第２の抵抗、前記電流源、前記第３の抵抗、および前記第１のキャパシタを、１個の集積回路内に構成したことを特徴とする差動伝送回路。 The differential transmission circuit according to claim 1,
The first and second transmission end transistors of the transmission circuit, the differential transmission line or the differential transmission wiring, the first and second resistances of the reception circuit, the current source, the third resistance, and A differential transmission circuit, wherein the first capacitor is configured in one integrated circuit. 請求項１又は２に記載の差動伝送回路において、
前記第１、第２の送端トランジスタのコレクタをそれぞれ第４、第５の抵抗を介して第２の電圧端子に接続し、および／又は前記第１、第２の送端トランジスタのコレクタをそれぞれ第２、第３のキャパシタを介して第３の電圧端子に接続したことを特徴とする差動伝送回路。 The differential transmission circuit according to claim 1 or 2,
The collectors of the first and second transmission end transistors are connected to the second voltage terminal through fourth and fifth resistors, respectively, and / or the collectors of the first and second transmission end transistors are respectively connected. A differential transmission circuit, wherein the differential transmission circuit is connected to a third voltage terminal via a second capacitor and a third capacitor. 請求項３に記載の差動伝送回路において、
前記第１、第２の送端トランジスタのコレクタを共通接続して、前記第４、第５の抵抗を共通の１個の抵抗とし、および／又は前記第２、第３のキャパシタを共通の１個のキャパシタとしたことを特徴とする差動伝送回路。 The differential transmission circuit according to claim 3,
The collectors of the first and second transmission end transistors are connected in common, the fourth and fifth resistors are used as one common resistor, and / or the second and third capacitors are used as a common one. A differential transmission circuit characterized in that it is a single capacitor. 請求項１又は２に記載の差動伝送回路において、
前記第１、第２の送端トランジスタのコレクタをそれぞれ第４、第５の抵抗を介して第２の電圧端子に接続し、該第４、第５の抵抗の前記コレクタと反対側の端子を第２、第３のキャパシタを介して第３の電圧端子に接続したことを特徴とする差動伝送回路。 The differential transmission circuit according to claim 1 or 2,
The collectors of the first and second transmission end transistors are connected to the second voltage terminal via fourth and fifth resistors, respectively, and the terminals of the fourth and fifth resistors opposite to the collector are connected. A differential transmission circuit, wherein the differential transmission circuit is connected to a third voltage terminal via a second capacitor and a third capacitor. 請求項５に記載の差動伝送回路において、
前記第１、第２の送端トランジスタのコレクタを共通接続して、前記第４、第５の抵抗を共通の１個の抵抗とし、前記第２、第３のキャパシタを共通の１個のキャパシタとしたことを特徴とする差動伝送回路。 The differential transmission circuit according to claim 5,
The collectors of the first and second transmission end transistors are connected in common, the fourth and fifth resistors are used as one common resistor, and the second and third capacitors are used as one common capacitor. A differential transmission circuit characterized by that.
JP2007125136A 2007-05-10 2007-05-10 Differential transmission circuit Expired - Fee Related JP4757835B2 (en)

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