JP4751700B2 - Solid-state image sensor - Google Patents

Description

  The present invention relates to a CCD type solid-state imaging device having a line memory.

  A CCD type solid-state imaging device having a line memory is known (see Patent Document 1).

FIG. 5 is a schematic plan view showing a schematic configuration of a CCD solid-state imaging device having a line memory.
The solid-state imaging device shown in FIG. 5 transfers a large number of photoelectric conversion elements 102 arranged in a square lattice shape and charges generated in each of the large number of photoelectric conversion elements 102 in the column direction (Y direction in FIG. 5). A vertical transfer unit 103; a charge reading unit 104 for reading charges from each of a large number of photoelectric conversion elements 102 to the vertical transfer unit 103; a line memory unit 105 for accumulating charges transferred through the vertical transfer unit 103; A horizontal transfer unit 106 that transfers charges accumulated in the line memory unit 105 in a row direction (X direction in FIG. 5) orthogonal to the column direction, and a signal corresponding to the charges transferred through the horizontal transfer unit 106 are output. The output circuit 107 is formed on the n-type semiconductor substrate 101.

  FIG. 6 is an enlarged view of the vicinity of the line memory unit of the solid-state imaging device shown in FIG. FIG. 7 is a diagram showing a cross section taken along line ABC and a line DE shown in FIG. The right side from the line descending vertically from points C and D shown in FIG. 7 is the cross section of the ABC line, and the left side is the cross section of the DE line.

  A p-type impurity layer 31 is formed on the n-type semiconductor substrate 101. The vertical transfer unit 103 includes a transfer channel 21 made of n-type impurities formed on the p-type impurity layer 31, and vertical transfer electrodes 22, 23, 24, and 25 formed on the transfer channel 21. The vertical transfer electrode 22 is supplied with a drive pulse φV1, the vertical transfer electrode 23 is supplied with a drive pulse φV2, the vertical transfer electrode 24 is supplied with a drive pulse φV3, and the vertical transfer electrode 25 is supplied with a drive pulse φV4. Is done. By controlling the drive pulses φV <b> 1 to φV <b> 4, charges read from the photoelectric conversion element 102 into the transfer channel 21 can be transferred in the column direction. A portion of the transfer channel 21 that overlaps the vertical transfer electrodes 22, 23, 24, and 25 in plan view is hereinafter referred to as a vertical transfer channel.

  The line memory unit 105 includes a transfer channel 21 and line memory electrodes 26 and 27 formed on the transfer channel 21. In the transfer channel 21 below the line memory electrode 26, an n − type impurity region 32 made of an n − type impurity having a lower concentration than the transfer channel 21 is formed by ion implantation or the like.

  A drive pulse φLM is supplied to each of the line memory electrodes 26 and 27. By controlling the drive pulse φLM to deepen the potential of the n − -type impurity region 32, charges can be transferred from the vertical transfer channel to the transfer channel 21 below the line memory electrode 27 and accumulated. . The drive pulse φLM is, for example, 0 V at the low level (L) and 5 V at the high level (H). The portion of the transfer channel 21 that overlaps the line memory electrode 27 in plan view is a portion that accumulates charges, and this portion is hereinafter referred to as a line memory.

  The horizontal transfer unit 106 includes a transfer channel 21 and horizontal transfer electrodes 28 and 29 formed on the transfer channel 21. The horizontal transfer electrodes 28 and the horizontal transfer electrodes 29 are alternately arranged in the row direction. The horizontal transfer electrode 28 includes an electrode 28a and an electrode 28b arranged in the row direction. The horizontal transfer electrode 29 includes an electrode 29a and an electrode 29b arranged in the row direction. An n − type impurity region 33 having the same concentration as the n − type impurity region 32 is formed below the electrode 28a and the electrode 29a by ion implantation or the like. A potential barrier for determining the capacity of the line memory (hereinafter, the potential of the line memory) is defined by the n − -type impurity region 32 and the n − -type impurity region 33 formed below the electrodes 28a and 29a adjacent to the line memory electrode 27. Abbreviated as a barrier). In the transfer channel 21, a region that overlaps with a hatched region in FIG. 6 is a region where a potential barrier of the line memory is formed (hereinafter referred to as a barrier region).

  A drive pulse φH2 is supplied to the electrodes 28a and 28b, and a drive pulse φH1 is supplied to the electrodes 29a and 29b. By controlling the drive pulses φH1 and φH2 to deepen the potential of the n − -type impurity region 33 formed in the barrier region, the charges accumulated in the line memory are transferred to the transfer channel below the electrode 28b and the electrode 29b. 21 can be moved. After the charge is transferred to the transfer channel 21 below the electrode 28b and the electrode 29b, the charge moved from the line memory can be transferred in the row direction by controlling the drive pulses φH1 and φH2. The drive pulses φH1 and φH2 are, for example, 0V at the low level (L) and 3.3V at the high level (H). Of the transfer channel 21, a part for transferring charges accumulated in the line memory in the row direction (a part of the transfer channel 21 excluding the vertical transfer channel, the line memory, and the barrier region) is a horizontal transfer channel below. That's it. This horizontal transfer channel corresponds to the transfer channel in the claims.

  The vertical transfer electrodes 22 to 25, the line memory electrodes 26 and 27, the electrodes 28 a and 28 b, and the electrodes 29 a and 29 b described above are insulated from each other by the insulating film 30.

FIG. 8 is a diagram showing the potential in the section taken along the line B-C shown in FIG. 6 and the potential in the section taken along the line DE. In FIG. 8, the same components as those of FIG.
The symbol a shown in FIG. 8 indicates the potential when the drive pulses φH1, φH2, and φLM are L. A symbol b indicates a potential when the drive pulses φH1, φH2, and φLM are H. As shown in FIG. 8, the potential below the electrode 28a adjacent to the line memory electrode 27 and the potential below the line memory electrode 26 become the potential barrier of the line memory, respectively, and the line depends on the depth of this potential barrier. Memory capacity is determined.

  In recent years, solid-state imaging devices tend to have a wide dynamic range, and the amount of charge generated in photoelectric conversion devices is increasing. For this reason, it is necessary to increase the line memory capacity as the charge amount increases. Conventionally, in order to increase the line memory capacity, the impurity concentration of the n − type impurity regions 32 and 33 shown in FIG. 7 is made lower. FIG. 9 is a diagram showing both the potential in the section taken along the line B-C and the potential in the section taken along the line DE shown in FIG. 6 when the impurity concentration of the n − type impurity regions 32 and 33 is further lowered. It is. In FIG. 9, the electrodes are not shown.

  The symbol c shown in FIG. 9 indicates the potential when the drive pulses φH1, φH2, and φLM are L. Symbol d indicates the potential when the drive pulses φH1, φH2, and φLM are H. The broken line shown in FIG. 9 shows a state before the impurity concentration of the n − -type impurity regions 32 and 33 is lowered. By reducing the impurity concentration of the n − -type impurity regions 32 and 33, the potential barrier of the line memory becomes shallow, so that the line memory capacity can be increased.

Next, the charge transfer operation of the solid-state imaging device having a configuration in which the line memory capacity is increased will be described.
FIG. 10 is a timing chart of drive pulses at the time of charge transfer of the solid-state imaging device having the potential as shown in FIG. FIG. 11 is a diagram showing a change in potential during the charge transfer operation based on the drive pulse shown in FIG. FIG. 11A is a diagram showing the potential in the section taken along the line B-C shown in FIG. 6 and the potential in the section taken along the line CE. FIG. 11B is a diagram showing both the potential in the section of the FG line and the potential in the section of the HE line shown in FIG.

  As shown in FIG. 11, when the charge is transferred from the vertical transfer channel to the line memory by time t1, the drive pulse φLM becomes L and the drive pulse φH2 becomes H at time t2 and t3, and the line memory transfers to the horizontal transfer channel. Charge is transferred. After time t4, the drive pulses φH1 and φH2 are switched between L and H, whereby charges are transferred in the row direction in the horizontal transfer channel.

  If the line memory capacity as shown in FIG. 8 is used, the solid-state imaging device can be operated without problems even if the time during which φLM is set to L is short as shown in FIG. However, when the line memory capacity is increased, if the time during which φLM is set to L remains short, charges are left in the line memory as shown in FIG. As a result, a vertical line defect occurs and the image is disturbed.

  In order to prevent charge from being left behind in the line memory, a method of increasing the voltages of the drive pulses φH1 and φH2 can be considered. FIG. 12 is a diagram showing a change in potential during the charge transfer operation when the voltages of the drive pulses φH1 and φH2 are increased in the solid-state imaging device having the potential as shown in FIG. The broken line shown in FIG. 12 is the potential indicating the state before the drive pulses φH1 and φH2 are raised. By increasing the voltage at the high level of the drive pulses φH1 and φH2 from 3.3V to 4V, for example, the gradient from the line memory to the horizontal transfer channel can be made steep as shown in FIG. It is possible to prevent the charge from being left behind.

Japanese Patent Laid-Open No. 2004-200592

  However, if the voltages of the drive pulses φH1 and φH2 are increased in order to prevent charge from being left in the line memory, there arises a problem that power consumption increases.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a solid-state imaging device capable of increasing line memory capacity and improving image quality without increasing power consumption.

The solid-state imaging device of the present invention is a CCD solid-state imaging device having a line memory, and between the line memory and a transfer channel for transferring charges accumulated in the line memory in a predetermined direction, A stepped potential formed of a first potential barrier having a relatively shallow potential formed on the line memory side and a potential barrier having a second potential deeper than the first potential barrier formed on the transfer channel side. Provide a barrier.

In the solid-state imaging device of the present invention, the concentration of the impurity forming the first potential barrier is lower than the concentration of the impurity forming the second potential barrier. It is formed.

  According to the present invention, it is possible to provide a solid-state imaging device capable of increasing the line memory capacity and improving the image quality without increasing the power consumption.

  When the charge is transferred from the line memory to the horizontal transfer channel, even if the drive pulse φLM is set to L for a long time, the performance of the solid-state imaging device is not significantly affected. Therefore, in the present embodiment, as a method for preventing the charge memory from being left behind in the line memory when the line memory capacity is increased, a method of extending the time for which the drive pulse φLM is set to L is adopted. When this method is employed, charges can be transferred without being left even if the step between the potential barrier of the line memory and the potential of the horizontal transfer channel is small. Therefore, it is possible to make the potential barrier of the line memory shallower than that shown in FIG. On the other hand, the horizontal transfer unit 106 optimizes the voltage values of the drive pulses φH1 and φH2 and the depth of the potential barrier formed in the horizontal transfer channel so that the charge of the saturated capacitance of the photoelectric conversion element 102 can be transferred efficiently. It has been decided. For this reason, it is difficult to further reduce the depth of the potential barrier formed by the n − -type impurity region 33 formed in the horizontal transfer channel.

  As described above, the depth of the potential barrier formed in the horizontal transfer channel is limited by the charge transfer efficiency in the horizontal transfer channel, but the depth of the potential barrier of the line memory depends on the charge transfer efficiency in the horizontal transfer channel. Not limited by. Conventionally, according to the charge transfer efficiency in the horizontal transfer channel, the depth of the potential barrier formed in the horizontal transfer channel and the depth of the potential barrier of the line memory are reduced at a uniform level, thereby reducing the line memory capacity. Was increasing. However, it has been found that there is room for further reducing the depth of the potential barrier of the line memory by adjusting the time during which the drive pulse φLM is set to L. Therefore, in the present embodiment, by using this space, the depth of the potential barrier of the line memory is further shallower than the depth of the potential barrier formed in the horizontal transfer channel, thereby suppressing the power consumption and reducing the power consumption. Made it possible to increase the capacity.

  Hereinafter, embodiments of the solid-state imaging device of the present invention will be described. The schematic plan view showing the schematic configuration of the solid-state imaging device of this embodiment and the enlarged view near the line memory unit are the same as those shown in FIGS.

FIG. 1 is a schematic cross-sectional view of the vicinity of a line memory section of a solid-state imaging device for explaining an embodiment of the present invention. The cross section taken along the line ABC and the line DE shown in FIG. FIG. The right side from the line descending vertically from the points C and D shown in FIG. 1 is a cross section taken along the line ABC, and the left side is a cross section taken along the line DE. In FIG. 1, the same components as those in FIG.
1 differs from FIG. 7 in that the n − type impurity region 32 formed in the barrier region is changed to an n − type impurity region 32 ′, and the n − type impurity region 33 formed in the barrier region is changed to an n − type. The impurity region 33 ′ is changed, and the n − type impurity region 33 formed in the horizontal transfer channel is changed to an n − type impurity region 33 ″.

  The n − type impurity region 33 ″ is a region having a lower impurity concentration than the n − type impurity region 33. The impurity concentration of the n − -type impurity region 33 ″ is set to such a level that the charge transfer efficiency of the horizontal transfer channel can be maintained while the drive pulses φH1 and φH2 are respectively the same as conventional L = 0V and H = 3.3V. Is set.

  The n − type impurity regions 32 ′ and 33 ′ are regions where the impurity concentration is lower than that of the n − type impurity region 33 ″.

FIG. 2 is a diagram illustrating the potential in the section taken along the line B-C and the potential in the section taken along the line DE shown in FIG. 6 in the solid-state imaging device for explaining the embodiment of the present invention. 2, the same components as those in FIG. 6 are denoted by the same reference numerals. The symbol e shown in FIG. 2 indicates the potential when the drive pulses φH1, φH2, and φLM are L. A symbol f indicates a potential when the drive pulses φH1, φH2, and φLM are H.
As shown in FIG. 2, the potential barrier of the line memory is shallower than the potential barrier formed in the horizontal transfer channel. Conventionally, considering that the potential barrier of the line memory and the potential barrier formed in the horizontal transfer channel are at the same depth, it can be seen that the configuration of this embodiment increases the line memory capacity compared to the conventional one. .

Next, the charge transfer operation of the solid-state imaging device of this embodiment will be described.
FIG. 3 is a timing chart of drive pulses at the time of charge transfer of the solid-state imaging device having the potential as shown in FIG. FIG. 4 is a diagram showing a change in potential during the charge transfer operation based on the drive pulse shown in FIG. FIG. 4A is a diagram showing the potential in the section taken along the line B-C shown in FIG. 6 and the potential in the section taken along the line DE. FIG. 4B is a diagram showing the potential in the section of the FG line and the potential in the section of the HE line shown in FIG. In the present embodiment, in order to prevent the charge from being left in the line memory due to the increase in the line memory capacity, the charge transfer time from the line memory to the horizontal transfer channel is set to a transient voltage due to the CR time constant. The length is long enough to be ignored.

  As shown in FIG. 4, when charge is transferred from the vertical transfer channel to the line memory by time t1, the drive pulse φLM becomes L and the drive pulse φH2 becomes H at time t2 and t3, and the line memory is transferred to the horizontal transfer channel. Charge is transferred. At this time, since the drive pulse φLM is L for a sufficiently long time, the charges accumulated in the line memory are almost completely transferred to the horizontal transfer channel. After time t4, the drive pulses φH1 and φH2 are switched between L and H, whereby charges are transferred in the row direction in the horizontal transfer channel.

  As described above, according to the solid-state imaging device of the present embodiment, the potential formed in the barrier region is obtained by using the above-described room generated by extending the charge transfer time from the line memory to the horizontal transfer channel. By making it shallower, the line memory capacity can be increased than before. Further, since the depth of the potential barrier formed in the horizontal transfer channel is suppressed to such an extent that the charge transfer efficiency can be maintained with the conventional driving voltage, charge transfer in the horizontal transfer channel can be performed without any problem. In addition, since the charge transfer time from the line memory to the horizontal transfer channel is lengthened, it is possible to prevent the charge from being left in the line memory. From the above, it is possible to provide a solid-state imaging device capable of increasing the line memory capacity without increasing the power consumption.

  In the present embodiment, the method of reducing the impurity concentration of the n − -type impurity regions 32 ′ and 33 ′ is adopted as a method of reducing the potential of the barrier region, but is not limited thereto. For example, the impurity concentration of the n − -type impurity regions 32 ′ and 33 ′ is made the same as the impurity concentration of the n − -type impurity region 33 ″, and the width of the barrier region in the row direction (the length indicated by W1 and W4 in FIG. 6). ) May be made narrower than the width of the line memory in the row direction (lengths indicated by W2 and W3 in FIG. 6), and the potential formed in the barrier region may be made shallower by the narrow channel effect.

1 is a schematic cross-sectional view of the vicinity of a line memory portion of a solid-state imaging device for explaining an embodiment of the present invention. In the solid-state image sensor for demonstrating embodiment of this invention, the figure which combined the potential in the cross section of the BC line shown in FIG. 6, and the potential in the cross section of the DE line | wire shown in FIG. Timing chart of driving pulse at the time of charge transfer of a solid-state imaging device having a potential as shown in FIG. The figure which shows the change of the potential at the time of the charge transfer operation | movement based on the drive pulse shown in FIG. A schematic plan view showing a schematic configuration of a CCD solid-state imaging device having a line memory. FIG. 5 is an enlarged view of the vicinity of the line memory section of the solid-state imaging device shown in FIG. The figure which combined the cross section of the ABC line shown in FIG. 6, and the cross section of the DE line | wire. The figure which combined the potential in the cross section of the BC line shown in FIG. 6, and the potential in the cross section of the DE line | wire. The figure which combined the potential in the cross section of the BC line shown in FIG. 6, and the potential in the cross section of the DE line | wire when the impurity concentration of an n type impurity region is made lower. Timing chart of drive pulse at the time of charge transfer of a solid-state imaging device having a potential as shown in FIG. The figure which shows the change of the potential at the time of the charge transfer operation | movement based on the drive pulse shown in FIG. FIG. 9 is a diagram showing a change in potential during charge transfer operation when the voltages of the drive pulses φH1 and φH2 are increased in the solid-state imaging device having the potential as shown in FIG.

Explanation of symbols

101 n-type semiconductor substrate 102 photoelectric conversion element 103 vertical transfer unit 104 charge reading unit 105 line memory unit 106 horizontal transfer unit 107 output circuits 22 to 25 vertical transfer electrodes 26 and 27 line memory electrodes 28 and 29 horizontal transfer electrode 33 '' n− type impurity regions 32 ′ and 33 ′ n− type impurity regions

Claims (2)

A CCD type solid-state imaging device having a line memory,
A first shallow potential barrier formed on the line memory side between the line memory and a transfer channel for transferring charges accumulated in the line memory in a predetermined direction, and the transfer A solid-state imaging device comprising a stepped potential barrier formed on the channel side and comprising a potential barrier of a second potential deeper than the first potential barrier . The solid-state imaging device according to claim 1,
The concentration of the first impurity to form a potential barrier, the second is that it is lower than the concentration of the impurity for forming the potential barrier, the solid-state imaging device in which the step-like potential barrier is formed.

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