JP4751427B2 - Communications system - Google Patents

Description

  The present invention relates to a communication system applicable to a reception system or a transmission system. More specifically, the present invention includes a reception or transmission frequency tuning means without adding a new circuit to a signal passing path, and a reception state or a transmission state. The present invention relates to a communication system capable of maintaining a good state.

  As a method for optimizing reception conditions in a conventional communication system, an adjustment method in which a reception filter is added and a capacitance value of a varactor that is a component of the reception filter is varied is well known. This is described in detail in Patent Document 1, for example.

  FIG. 17 is a diagram showing a conventional receiving circuit, which is a receiving circuit disclosed in Patent Document 1. In FIG. This receiving circuit uses the output of the oscillator as a signal source 6 and adjusts the capacity of the receiving filter composed of the inductor 3 and the varactor 4 using a signal down-converted by a local oscillator 25 different from the signal source 6. The reception state is kept good.

  That is, in the reception standby state, the reception input is cut off by turning off the variable attenuator 1, and the output of the transmission local oscillation circuit 6 is used as the input to the frequency converter 24 with the switch 2 set to the a side. The level of the converted output is detected by the amplifier 29, and the control circuit 5 adjusts the voltage applied to the varactor 4 so that this level becomes maximum. By this automatic tuning, the reception state is always kept good even if there is a change in element characteristics over time or a temperature change.

  The idea of adjusting the filter using the VCO / PLL is an idea first introduced in Non-Patent Document 1.

JP-A-9-298480 KHEN-SNAG TAN, Paul Gray "Fully Integrated Analog Filters Using Bipolar-JFET Technology" JSSC SC-13, pp. 814-821, Dec. 1978 B. Gilbert, “A preference four-quad multiple with with sub-nanosecond response,” JSSC SC-3, pp. 365-373, Dec. 1968. Jri Lee, Behzad Razavi “A 40-GHz Frequency Divider in 0.18-um CMOS Technology” JSSC VOL. 39 NO. 4, pp594-601, April 2004 Hua Wang, Ali Hajimiri “A Wideband CMOS Linear Digital Phase Rotator” CICC 2007, pp 671-674, 2007

  However, in the reception method described in Patent Document 1 described above, an oscillator other than a local oscillator is required as a signal source, and it is necessary to add a filter circuit for adjusting the band separately. Invited, there was a problem that the realization cost increased.

  The above-described non-patent document 1 relates to the tuning of the center frequency / bandwidth of the filter and a method for realizing the tuning, and the receiving frequency tuning means and the optimization of the receiving band as in the present invention. And a communication system comprising means is not disclosed.

  The present invention has been made in view of such a situation, and an object of the present invention is to provide reception or transmission frequency tuning means without adding a new circuit to a signal passing path, and An object of the present invention is to provide a communication system capable of maintaining a good transmission state.

  In addition, the present invention is rich in expandability that can be controlled independently without affecting the tuning system by adding one variable resistance element to each circuit element even when adding optimization of the signal band. It is also possible to provide a system.

  The present invention has been made to achieve such an object, and the invention according to claim 1 is directed to a first LC tank circuit (FIG. 2) including a first character (V1 to V4 in FIG. 2). And a second LC tank circuit including a phase locked loop (100) having voltage controlled oscillation means (106) having Lpv, Lnv and V1 to V4), and a second character (V5 to V8 in FIG. 3). A third LC tank circuit (FIG. 4) including amplifying means (101) having a load of Lpa, Lna and V5 to V8 of FIG. 3 and a third character (V9 to V12 of FIG. 4) of FIG. LPM, LNM and V9 to V12) as a load, and a fourth LC tank circuit (LPD in FIG. 4) that constitutes the phase synchronization circuit and includes a fourth varactor (V13 to V16 in FIG. 5). , LND and V13 to V16) A frequency control signal (c1) from the phase synchronization circuit (100) so as to control the oscillation frequency of the voltage controlled oscillation means (106). Receiving frequency tuning means, and receiving band optimizing means for controlling the tuning frequency of the second LC tank, the third LC tank, and the fourth LC tank. (FIG. 1, FIG. 6, FIG. 13, FIG. 14, Examples 1, 2, 3, 4)

Further, the invention described in claim 2 is a voltage controlled oscillation means comprising a first LC tank circuit (Lpv, Lnv and V1 to V4 in FIG. 2) including a first character (V1 to V4 in FIG. 2). (106) and a second LC tank circuit (Lpa, Lna and V5 to V8 in FIG. 3) including a second character (V5 to V8 in FIG. 3) and a second LC tank circuit (106). Amplifying means (101) as a load, and a frequency converting means using as a load a third LC tank circuit (LPM, LNM and V9 to V12 in FIG. 4) including a third character (V9 to V12 in FIG. 4). The frequency dividing means that constitutes the phase synchronization circuit and uses the fourth LC tank circuit (LPD, LND and V13 to V16 in FIG. 4) including the fourth character (V13 to V16 in FIG. 5) as a load; Communication system which is a transmission system having A transmission frequency tuning means using a frequency control signal (c1) from the phase synchronization circuit (100) so as to control the oscillation frequency of the voltage controlled oscillation means (106); A transmission band optimization means for controlling the tuning frequency of the LC tank, the third LC tank, and the fourth LC tank is provided (FIGS. 1, 6, 13, and 14). Examples 1, 2, 3, 4)

  According to the present invention, a phase-locked loop circuit having a voltage-controlled oscillating means having a first LC tank circuit including a first varactor, and an amplifier circuit having a second LC tank circuit including a second varactor as a load And a frequency converting means having a third LC tank circuit including a third varactor as a load, and a frequency dividing means having a fourth LC tank circuit including a fourth varactor as a load. The components in the LC tank of the already built-in voltage controlled oscillator (VCO), the varactor in the LC load of the amplifier, the varactor in the LC load of the frequency converter and the varactor in the LC load of the frequency divider The receiver (transmission) frequency tuning is not affected by the frequency fluctuation factor of the circuit characteristics by using the oscillation frequency control signal of the voltage-controlled oscillator. It is possible to realize a high accuracy, yield improvement of product can be expected. In addition, if necessary, optimization of the reception (transmission) band can be realized by changing the minimum unit by adding one variable resistor to the LC tank, so that the band, that is, the signal-to-noise ratio can be easily optimized. be able to. Therefore, a high-quality receiver and transmitter with few data errors can be realized.

  Embodiments of the present invention will be described below with reference to the drawings.

<Example 1>
FIG. 1 is a block configuration diagram for explaining a receiving system according to a first embodiment which is a communication system of the present invention. The receiving system according to the first embodiment includes a phase locked loop 100, an amplifier 101, and a frequency converter 107. The phase locked loop (PLL) 100 includes a loop filter (LF) 102 and a charge. A pump (CP) 103, a phase frequency detector (PFD) 104, a voltage-controlled oscillator (VCO) 106, a voltage-controlled oscillator 108, a frequency divider 108, and a frequency divider 109 with an arbitrary frequency divider It is configured.

  The amplifier 101 receives the input signal d and the frequency control signal c1 and outputs an output signal e. This output signal e is input to the frequency converter 107 and an output signal m is output. The frequency control signal c1, which is a control signal fed back to the voltage controlled oscillator 106 and the amplifier 101, is a voltage controlled oscillator 106, a divide-by-2 divider 108, a divider 109, a phase frequency detector 104, a charge pump 103, and a loop filter 102. Are output signals from the loop filter 102 that controls the oscillation frequency of the voltage controlled oscillator 106. The reference clock signal a1 is a signal that is input from the outside and serves as a reference for the phase of the phase synchronization circuit 100.

  That is, the communication system of the present invention includes the phase locked loop 100 having the voltage controlled oscillator 106 having the first LC tank circuit including the first character (V1 to V4 in FIG. 2), and the second character (FIG. 3). Frequency converter 107 having a load of a second LC tank including V5 to V8) and a third LC tank including a third character (V9 to V12 of FIG. 4) and a fourth LC tank. The divide-by-two 108 is loaded with a fourth LC tank including a varactor (V13 to V16 in FIG. 5A or FIG. 5B). A varactor is also referred to as a varicap (a varactor diode or a varactor), and refers to a capacitive element whose capacitance changes with voltage.

  The reception frequency is tuned by using the frequency control signal c1 from the phase locked loop 100 so as to control the oscillation frequency of the voltage controlled oscillator 106.

  As described above, in the receiving system according to the first embodiment, since the control signals of the amplifier 101 and the voltage controlled oscillator 106 are the same, the amplification frequency of the amplifier 101 and the output frequency of the frequency converter 107 are the oscillation frequency of the voltage controlled oscillator 106. And the output frequency of the divide-by-two 108 is a receiving system having a relationship that is half the oscillation frequency of the voltage-controlled oscillator 106.

  2 is a circuit diagram of the voltage controlled oscillator shown in FIG. 1, FIG. 3 is a circuit diagram of the amplifier shown in FIG. 1, FIG. 4 is a circuit diagram of the frequency converter shown in FIG. FIG. 5B is a circuit diagram of the divide-by-2 circuit shown in FIG.

  In the figure, CNTP is a positive varactor control signal, CNTN is a negative varactor control signal, CBIASP is a positive varactor DC bias voltage, CBIASN is a negative varactor DC bias voltage, QCNT is a Q value control signal, and R1 to R16 are for DC bias application. Resistors, Ra to Rh are DC bias applying resistors, RQ2 to RQ4 are Q value control variable resistors, NVP is a VCO negative resistance generating transistor, NVN is a VCO negative resistance generating transistor, NAP is an amplifying transistor, NAN Is an amplification transistor, M1M is a MixerRF input transistor, M2M is a MixerRF input transistor, M3M to M6M are local clock input transistors, M1D is a Divider divided signal input transistor, M2D is a Divider divided signal input transistor, M D to M6D are Divider local clock input transistors, IBIASP is a DC bias current terminal, PB0 is a current mirror transistor, PB1 is a current mirror transistor, IBIASN is a DC bias current terminal, NB0 is a current mirror transistor, and NB00 is a current mirror. Transistor, NB1 is a current mirror transistor, CIP is a DC blocking capacitor, CIN is a DC blocking capacitor, RIP is a DC bias applying resistor, RIN is a DC bias applying resistor, IBM is a DC bias current, IBD is also a DC bias current Is shown.

  Hereinafter, in order to simplify the description, the description will be given by taking a reception system when the ratio of the frequency of the signal d and the frequency of the signal m is 3: 1 as an example. For example, this corresponds to the case where the frequency of the signal d is 9 GHz, the frequency of the signal m is 3 GHz, the oscillation signal of the voltage control generator is 6 GHz, and the output of the frequency divider is 3 GHz.

In FIG. 2, the oscillation frequency (Fosc) of the voltage controlled oscillator 106 is a tank circuit composed of inductors Lpv and Lnv having inductance values Lpv and Lnv, DC blocking capacitors C1 to C4 having capacitance values C1 to C4, and characters V1 to V4. The value is determined by the following equation (1). Below, for ease of explanation,
V1 capacity = V2 capacity = Cv1
V3 capacity = V4 capacity = Cv3
Lpv = Lnv = Lv
C1 = C2 = C3 = C4 = C0
C0 >> Cv1, Cv3
And
Fosc = (1 / Sqrt (Lv × (Cv1 + Cv3)) (1)

Also, the frequency (Famax) indicating the maximum gain of the amplifier 101 shown in FIG. 3 is set to the inductors Lpa and Lna having the inductance values Lpa and Lna, and the DC blocking capacitors C5 to C8 having the capacitance values C5 to C8, as in the voltage controlled oscillator 106. And a value determined by a tank circuit composed of varactors V5 to V8, is represented by the following equation (2). Again here for simplicity,
V5 capacity = V6 capacity = Cv5
V7 capacity = V8 capacity = Cv7
Lpa = Lna = La
C5 = C6 = C7 = C8 = C0A
C0A >> Cv5, Cv7
And
At this time, RQ2 may be a fixed value or not.
Famax = (1 / Sqrt (La * (Cv5 + Cv7)) (2)

  The ratio between the frequency of the signal d and the frequency of the voltage controlled oscillator output f in FIG. 1 is determined to be 3: 2 from the above assumption. Therefore, the LC element constant ratio between the second LC tank circuit of the amplifier 101 and the first LC tank circuit of the voltage controlled oscillator 106 is expressed as Lv = (1 / 1.5) * La, (C1 to C4) = ( 1 / 1.5) * (C5 to C8), (V1 to V4) = (1 / 1.5) * (V5 to V8). It can be controlled to the optimum value by the control signal C1 that does not depend on the process variation.

Similarly, the frequency (Fmmax) indicating the maximum gain of the frequency converter 107 shown in FIG. 4 also includes inductance values Lpm, inductors Lpm and Lnm with Lnm, capacitors C9 to C12 for DC blocking with capacitance values C9 to C12, and varactors V9 to V12. The value is determined by a tank circuit consisting of: Again, for simplicity of explanation,
V9 capacity = V10 capacity = Cv9
V11 capacity = V12 capacity = Cv11
Lpm = Lnm = Lm
C9 = C10 = C11 = C12 = C0M
C0M >> Cv9, Cv11
And
At this time, RQ3 may be a fixed value or not.
Fmmax = (1 / Sqrt (Lm * (Cv9 + Cv11)) (3)

  The ratio between the frequency of the signal m and the frequency of the voltage controlled oscillator output f in FIG. 1 is determined to be 1: 2 from the above assumption. Therefore, the LC element constant ratio between the third LC tank circuit of the frequency converter and the first LC tank circuit of the voltage controlled oscillator 106 is Lv = (2.0) * Lm, (C1 to C4) = (2. 0) * (C9 to C12), (V1 to V4) = (2.0) * (V9 to V12) so that the frequency at which each circuit should operate does not depend on temperature and process fluctuations. It can be controlled to an optimum value by the control signal C1.

Similarly, the output signal frequency (Fdmax) of the divide-by-two 108 shown in FIGS. 5A and 5B also includes inductors Lpd and Lnd with inductance values Lpd and Lnd, capacitors C13 to C16 for DC blocking with capacitance values C13 to C16, and a character V13. The value determined by the tank circuit consisting of ˜V16 is shown by the following equation (4). Again, for simplicity of explanation,
V13 capacity = V14 capacity = Cv13
V15 capacity = V16 capacity = Cv16
Lpd = Lnd = Ld
C13 = C14 = C15 = C16 = C0D
C0D >> Cv9, Cv11
And
At this time, RQ4 may be a fixed value or not.
Fmmax = (1 / Sqrt (Lm * (Cv9 + Cv11)) (4)

  The ratio between the output frequency of the divide-by-2 frequency divider and the frequency of the voltage-controlled oscillator output f in FIG. 1 is determined to be 1: 2 from the above assumption. Therefore, the LC element constant ratio between the fourth LC tank circuit of the frequency converter and the first LC tank circuit of the voltage controlled oscillator 106 is Lv = (2.0) * Ld, (C1 to C4) = (2. 0) * (C13 to C16), (V1 to V4) = (2.0) * (V3 to V16) so that the frequency at which each circuit should operate does not depend on temperature and process fluctuations. It can be controlled to an optimum value by the control signal C1.

  The difference between FIG. 5A and FIG. 5B is in the operation of the divide-by-2 circuit only in that the output feedback is applied to M1D and M2D constituting the differential pair or to the four-dimensional elements M3D to M6D. There is no difference.

  From the embodiments described so far, all the blocks of the amplifier 101, the frequency converter 107, and the divide-by-2 108 are controlled by the control signal C1 that is not related to the process fluctuation / temperature fluctuation, and the operating frequency thereof is the signal a1 with high accuracy. It is shown that it has a characteristic controlled by C1 that determines the oscillation signal f of the voltage controlled oscillator which is a component of the PLL 100 with reference to.

  Normally, a single-end frequency control system is used in an LC tank type voltage-controlled oscillator. However, in the realization of this reception system, a differential control system that can keep the device sensitivity low is preferable. The circuit diagram of the voltage controlled oscillator 106 shown in FIG. 2, the circuit diagram of the amplifier 101 shown in FIG. 3, the circuit diagram of the frequency converter shown in FIG. 4, and the circuit of the frequency divider shown in FIGS. 5A and 5B The figure shows a circuit example employing the above-described differential control method.

  In the present invention, the second LC including the second varactor is determined by using the C1 that determines the first LC tank resonance frequency including the first varactor of the voltage controlled amplifier governed by the accurate reference signal. Controlling a second frequency amplifier including a second LC having a tank as a load, a third LC tank including a third varactor as a load, and a fourth frequency divider including a fourth varactor. Thus, stable reception independent of manufacturing errors and temperature fluctuations was achieved.

<Example 2>
FIG. 6 is a block diagram for explaining a receiving system according to the second embodiment which is a communication system of the present invention. In the receiving system according to the second embodiment, a control circuit Q value control circuit 110 for band optimization is added to the block configuration diagram shown in FIG. 1, and the amplifier 101 and the frequency converter in FIG. The difference is that the band 107 can be optimized.

  The amplifier 101 receives an input signal d, a frequency control signal c1, and a Q value control signal b1, and outputs an output signal e. The output signal e and the above-described Q value control signal b1 are input to the frequency converter 107, and an output signal m is output. The frequency control signal c1, which is a control signal fed back to the voltage controlled oscillator 106 and the amplifier 101, is a voltage controlled oscillator 106, a divide-by-2 divider 108, a divider 109, a phase frequency detector 104, a charge pump 103, and a loop filter 102. Are output signals from the loop filter 102 that controls the oscillation frequency of the voltage controlled oscillator 106. The reference clock signal a1 is a signal that is input from the outside and serves as a reference for the phase of the phase synchronization circuit 100.

  The Q value control circuit 110 receives the phase data a2, the bandwidth data a3, the frequency control signal c1 and the output signal f of the voltage controlled oscillator 106 as inputs, and outputs the Q value control signal b1. The output signal b1 is fed back to the amplifier 101 and the frequency converter 107.

  That is, the band optimization of the receiving system in the second embodiment is performed by the Q value generated by the Q value control circuit 110 that receives the phase data a2, the bandwidth data a3, the center frequency control signal C1, and the voltage controlled oscillator output f. This is done by controlling the bands of the amplifier 101 and the frequency converter 107 with the control signal b1.

  The voltage controlled oscillator 106, the amplifier 101, the frequency converter 107, and the frequency divider 108 in FIG. 6 are the same as those in FIGS. 2, 3, 4, and 5A and 5B in the first embodiment. The operation of this circuit diagram is also the same except that RQ2 to RQ4 are changed from fixed values to variable values.

  The Q value control signal b1 is preferably input to both the amplifier 101 and the frequency converter 107 as shown in FIG. 6 from the viewpoint of performing control with a high degree of freedom. You can just type in

First, a band optimization method will be described.
FIG. 7 is a configuration diagram of a Q value control circuit for band optimization, and FIG. 8 is a diagram illustrating a circuit example of an arbitrary phase generator + voltage-current converter, and FIGS. 9 (a) to 9 (c). Is an explanatory diagram of the operation of the arbitrary phase generator, FIGS. 10A to 10C are explanatory diagrams of LC bandpass filter amplitude / phase transfer functions, and FIG. 11 is a diagram showing a circuit example of the phase comparator. FIGS. 12A and 12B are explanatory diagrams of the operation of the phase comparator. Table 1 shows a truth table of the phase comparator.

  The Q value control circuit in FIG. 6 includes an arbitrary phase generator 201, a phase comparator 202, an arbitrary phase generator 203, a voltage-current converter 204, and an LC bandpass filter 205 shown in FIG.

  In the figure, symbol f is the output clock of the voltage controlled oscillator (f (t) = Cos (ωot)), c1 is the output control signal of the loop filter, b1 is the Q value control signal, and g is the phase comparator input 1 (g (t ) = Cos (ω2t)) Bandwidth BW = (ω2−ω0) / 2π, h is phase comparator input 1 with phase variation (h (t) = Cos (ω2t + Θ1))), Θ1 is phase variation amount, i is Phase comparator input 2 (i (t) = Cos (ω2t + Θ1 + Θ2)) and Θ2 are phase fluctuation amounts due to the LC bandpass filter.

  The relationship between the frequency and the phase is f = dΘ / dt, and the time variation component of the phase is the frequency. Therefore, when phase data of 0 to 360 ° is temporally varied at a constant rate and given to the arbitrary phase generator, a new frequency signal of “input frequency + constant frequency” can be created.

  The arbitrary waveform generator 201 receives the input signal f and the bandwidth data a3 and outputs a signal g. The output signal g is input to the phase comparator 202, and the phase comparison result of the phase comparator 202 is fed back to the LC bandpass filter 205 as a signal b1 and is another block in FIG. And used as a control signal for the frequency converter 107.

  The output g of the arbitrary waveform generator 201 is also input to another arbitrary phase generator 203. The arbitrary phase generator 203 outputs a signal h having the same frequency and a different phase as the input signal g in accordance with the phase data a2, which is another input. This signal h is converted into a current signal by the voltage / current converter 204, and then subjected to current / voltage conversion by the LC bandpass filter 205 and input to the other terminal of the phase comparator. Here, the center frequency fo of the LC bandpass filter follows the oscillation frequency of the voltage controlled oscillator 106 of FIG. 6 by the control signal C1.

Also, the role of the arbitrary phase generator 201 will be described. The arbitrary phase generator 201 is to generate a new frequency using the following phase-frequency relational expression (5).
fo = dΘo / dt (5)
Here, fo; frequency, Θo; phase, t; time.

  From this equation (5), it was found that a frequency obtained by adding the frequency corresponding to the time variation can be created by varying the phase of the arbitrary phase generator with time. The bandwidth data a3 in FIG. 7 is data that accompanies time variation to create this new frequency. On the other hand, the phase data a2 input to the arbitrary phase generator 203 is fixed data that does not vary with time.

  The arbitrary phase generator circuit shown in FIG. 8 receives the signal f of FIG. 7 as input, and has the same frequency as shown in FIG. 9A, and the phases are shifted by I / 2, Q, IB, A quadrature signal generator 301 that generates four signals of QB, and phase data a2I for I branch and phase data a2Q for Q branch out of the data divided from the signal a2 of FIG. The transistors M1I to M4I and M1Q to M4Q constituting the phase adder and current sources IIP, IIN, IQP, and IQN that supply a bias current modulated by the phase data to the transistors.

  M1I constituting the four-quadrant phase adder on the I branch side has a drain connected to IOP, a gate connected to I, a source connected to CS1, and M2I having a common source with M1I has a gate connected to IB and a drain connected to ION Connected to. In M3I, the drain is connected to IOP, the gate is connected to IB, the source is connected to CS2, and M4I, which shares the source with M3I, has a gate connected to I and a drain connected to ION.

  Similarly, M1Q that constitutes a four-quadrant phase adder on the Q branch side has a drain connected to IOP, a gate connected to Q, a source connected to CS3, and M2Q that shares the source with M1Q has a gate connected to QB and a drain Is connected to the ION. In M3Q, the drain is connected to IOP, the gate is connected to QB, the source is connected to CS4, and M4Q, which shares the source with M3Q, has a gate connected to Q and a drain connected to ION.

  In addition, a current source IIP modulated with phase data I (a2I) is connected between CS1 and VSS, and an IIN modulated with phase data I (a2I) is also connected between CS2 and VSS. A current source IQP modulated with phase data Q (a2Q) is connected between VSS and VSS, and an IQN modulated with phase data Q (a2Q) is also connected between CS4 and VSS.

  FIGS. 9A to 9C show the relationship between the above-described modulation data and the synthesized new phase. FIG. 9A shows the phase relationship of the four signals I, Q, IB, and QB generated by the above-described quadrature signal generator, and FIG. 9B shows the operation when the π / 4 phase is shifted. FIG. 9C illustrates an operation when no phase difference is generated between the input and output.

If the time variation of the bandwidth data a3 in FIG. 6 is BW [Hz], the input / output frequency difference of the arbitrary waveform generator is expressed by the following equation (6).
g = f + BW (6)
Here, f; the output clock of the voltage controlled oscillator 106 in FIG. 6 has a frequency of fo [Hz].
g: Output signal frequency [Hz] of the arbitrary phase generator 201 in FIG.
BW; frequency [Hz] defined by the bandwidth data a3 in FIG.
When f (t) = Cos (ωot), ωo = 2 * π * fo, g (t) = Cos (ω2t) (7)
ω2 = 2 * π * (fo + BW)
That is, the bandwidth BW is BW = (ω2−ωo) / (2 * π).

Next, the output h from the arbitrary waveform generator 203 to which “g (t) = Cos (ω2t)” and the phase data a2 are input is expressed by the following equation (8), where Θ1 is the amount of phase fluctuation due to a2. Indicated.
h (t) = Cos (ω2t + Θ1) (8)
Here, the amount of phase fluctuation due to Θ1; a2

Further, in consideration of the phase fluctuation Θ2 in the LC bandpass filter 205, the signal i which is the other input to the phase comparator is given by the following equation (9).
i (t) = Cos (ω2t + Θ1 + Θ2) (9)
Here, Θ2: Phase fluctuation amount due to LC bandpass filter

  Therefore, since the output of the phase comparator 202 is gXORi, it is given by the following equation (10).

  here,

Indicates exclusive logic and its truth table is shown in Table 1.

According to FIG. 7, b1 is input to the LC bandpass filter 205 and used to vary the variable resistor RQ in FIG. Here, the center frequency fo and the Q value Q of the LC tank filter shown in FIG.
fo = 1 / {2 * π * Sqrt (LC)} (10−a)
Q = RQ * Sqrt (C / L) (10-b)
From these equations, it was shown that the bandwidth of the LC tank can be controlled without changing the center frequency of the LC tank 205 by using the Q value control signal in FIG.

Finally, where the Q value control circuit of FIG. 7 is stabilized will be described.
The phase comparator 202 in FIG. 7 is composed of an exclusive OR circuit, and FIG. 11 shows the diagram and Table 1 shows the truth table.

  In addition, referring to Table 1, timing charts relating to the phase comparator inputs g and i and the output b1 in FIG. 7 are shown in FIGS. From this timing chart, it was found that the output of the phase comparator takes a maximum value when the phase difference between g and i is π / 2. When g and i are in phase, the output is zero. Accordingly, as shown in FIG. 10C, the band data a3 and the phase data a2 in FIG. 7 are set so that the phase at the desired frequency fo + BW is delayed by π / 2 compared to the phase at the frequency fo. A desired operation can be achieved by setting and configuring a feedback loop that stabilizes the loop of FIG. 7 at the maximum value.

  In the present invention, the amplifier, frequency converter, and divide-by-2 load shown in FIG. 6 are tuned to a desired frequency in the first embodiment. The bandwidth of the two circuit elements of the frequency converter can be controlled arbitrarily and accurately.

  As a result, it is possible to optimize the reception band, thereby achieving stable reception characteristics.

<Example 3>
FIG. 13: is a block block diagram for demonstrating the receiving system based on Example 3 which is a communication system of this invention. The reception system in the third embodiment is added with a Q value control circuit 2 (111) so that the system of the block configuration diagram of the second embodiment shown in FIG. 6 can be further optimally received, and the Q value control circuit in FIG. 1 (110) to control the bandwidth of the amplifier 101 in FIG. 13, and the Q value control signal d1 from the Q value control circuit 2 (111) in FIG. 13 to the frequency converter 107 in FIG. The difference is that each band control can be performed independently.

  The amplifier 101 receives an input signal d, a frequency control signal c1, and a Q value control signal b1, and outputs an output signal e. The output signal e and the above-described Q value control signal b1 are input to the frequency converter 107, and an output signal m is output. The frequency control signal c1, which is a control signal fed back to the voltage controlled oscillator 106 and the amplifier 101, is a voltage controlled oscillator 106, a divide-by-2 divider 108, a divider 109, a phase frequency detector 104, a charge pump 103, and a loop filter 102. Are output signals from the loop filter 102 that controls the oscillation frequency of the voltage controlled oscillator 106. The reference clock signal a1 is a signal that is input from the outside and serves as a reference for the phase of the phase synchronization circuit 100.

  The Q value control circuit 1 (110) receives the phase data a2, the bandwidth data a3, the frequency control signal c1 and the output signal f of the voltage controlled oscillator 106 as inputs, and outputs the Q value control signal b1. This output signal b1 is fed back to the amplifier 101 described above. On the other hand, the Q value control circuit 2 (111) receives the phase data b2, the bandwidth data b3, the frequency control signal c1 and the output signal f of the voltage controlled oscillator 106 as inputs, and outputs the Q value control signal d1. This output signal d1 is fed back to the frequency converter 107 described above.

  The voltage controlled oscillator 106, the amplifier 101, the frequency converter 107, and the frequency divider 108 shown in FIG. 13 are the same as those shown in FIGS. 2, 3, 4 and 5A, 5B in the first embodiment. The operation of this circuit diagram is also the same except that RQ2 to RQ4 are changed from fixed values to variable values. Similarly, the Q-value control circuit 1 (110) and the Q-value control circuit 2 (111) in FIG. 13 are the same as those in FIGS. 8, 9, 10, and 11 in the second embodiment. Is the same.

  That is, the band optimization of the receiving system in the third embodiment is made by the Q value control circuit 1 (110) that receives the phase data a2, the bandwidth data a3, the center frequency control signal C1, and the voltage controlled oscillator output f. The Q value control signal b1 sets the band of the amplifier 101, and the Q value control circuit 2 (111) having the phase data b2, the bandwidth data b3, the center frequency control signal C1, and the voltage controlled oscillator output f as inputs. This is done by controlling the band of the frequency converter 107 with the value control signal d1.

<Example 4>
FIG. 14: is a block block diagram for demonstrating the receiving system which concerns on Example 4 which is a communication system of this invention. The receiving system in the fourth embodiment includes a Q value control circuit 2 (111) and a Q value control circuit 3 (112) so that the system of the block configuration diagram of the second embodiment shown in FIG. In addition, the band control of the amplifier 101 in FIG. 14 is controlled by the Q value control signal b1 from the Q value control circuit 1 (110) in FIG. 14, and the Q value control from the Q value control circuit 2 (111) in FIG. The band control of the frequency converter 107 in FIG. 14 is added by the signal d1, and the band control of the two-frequency divider 108 in FIG. 14 is made independent by the Q value control signal e1 from the Q value control circuit 3 (112) in FIG. It is different in that it can be done.

  The amplifier 101 receives an input signal d, a frequency control signal c1, and a Q value control signal b1, and outputs an output signal e. The output signal e and the above-described Q value control signal b1 are input to the frequency converter 107, and an output signal m is output. The frequency control signal c1, which is a control signal fed back to the voltage controlled oscillator 106 and the amplifier 101, is a voltage controlled oscillator 106, a divide-by-2 divider 108, a divider 109, a phase frequency detector 104, a charge pump 103, and a loop filter 102. Are output signals from the loop filter 102 that controls the oscillation frequency of the voltage controlled oscillator 106. The reference clock signal a1 is a signal that is input from the outside and serves as a reference for the phase of the phase synchronization circuit 100.

  The Q value control circuit 1 (110) receives the phase data a2, the bandwidth data a3, the frequency control signal c1 and the output signal f of the voltage controlled oscillator 106 as inputs, and outputs the Q value control signal b1. This output signal b1 is fed back to the amplifier 101 described above. On the other hand, the Q value control circuit 2 (111) receives the phase data b2, the bandwidth data b3, the frequency control signal c1 and the output signal f of the voltage controlled oscillator 106 as inputs, and outputs the Q value control signal d1. This output signal d1 is fed back to the frequency converter 107 described above. Further, the Q value control circuit 3 (112) receives the phase data c2, the bandwidth data c3, the frequency control signal c1 and the output signal f of the voltage control oscillator 106 as inputs, and outputs the Q value control signal e1. The output signal e1 is fed back to the above-described frequency divider 108.

  The voltage controlled oscillator 106, the amplifier 101, the frequency converter 107, and the frequency divider 108 in FIG. 14 are the same as those in FIGS. 2, 3, 4, and 5A, 5B in the first embodiment. The operation of this circuit diagram is also the same except that RQ2 to RQ4 are changed from fixed values to variable values. Similarly, the Q-value control circuit 1 (110) and the Q-value control circuit 2 (111) in FIG. 13 are the same as those in FIGS. 8, 9, 10, and 11 in the second embodiment. Is the same.

  That is, the band optimization of the receiving system in the third embodiment is made by the Q value control circuit 1 (110) that receives the phase data a2, the bandwidth data a3, the center frequency control signal C1, and the voltage controlled oscillator output f. The Q value control signal b1 sets the band of the amplifier 101, and the Q value control circuit 2 (111) having the phase data b2, the bandwidth data b3, the center frequency control signal C1, and the voltage controlled oscillator output f as inputs. It is created by the Q value control circuit 3 (112) which receives the frequency converter 107 band by the value control signal d1 and the phase data c2, the bandwidth data c3, the center frequency control signal C1 and the voltage controlled oscillator output f. This is done by controlling the band of the two-frequency divider 102 with the Q value control signal e1.

<Example 5>
FIG. 15 is a block diagram for explaining a receiving system according to the fifth embodiment which is a communication system of the present invention. The receiving system in the fifth embodiment is the same as the block configuration diagram of the second embodiment shown in FIG. The difference between the second embodiment and the fifth embodiment is that, in the second embodiment described above, the signal c1, which is the oscillation frequency control voltage of the voltage controlled amplifier from the loop filter, is supplied to the amplifier 101, the frequency converter 107, and the two-frequency divider 108. Is different from the first embodiment in that c1 is input only to the amplifier 101 and the frequency converter 107 and is not input to the two-frequency divider 108.

  The amplifier 101 receives an input signal d, a frequency control signal c1, and a Q value control signal b1, and outputs an output signal e. The output signal e and the above-described Q value control signal b1 are input to the frequency converter 107, and an output signal m is output. The frequency control signal c1, which is a control signal fed back to the voltage controlled oscillator 106 and the amplifier 101, is a voltage controlled oscillator 106, a divide-by-2 divider 108, a divider 109, a phase frequency detector 104, a charge pump 103, and a loop filter 102. Are output signals from the loop filter 102 that controls the oscillation frequency of the voltage controlled oscillator 106. The reference clock signal a1 is a signal that is input from the outside and serves as a reference for the phase of the phase synchronization circuit 100.

  The Q value control circuit 110 receives the phase data a2, the bandwidth data a3, the frequency control signal c1 and the output signal f of the voltage controlled oscillator 106 as inputs, and outputs the Q value control signal b1. The output signal b1 is fed back to the amplifier 101 and the frequency converter 107.

  That is, the band optimization of the receiving system in the second embodiment is performed by the Q value generated by the Q value control circuit 110 that receives the phase data a2, the bandwidth data a3, the center frequency control signal C1, and the voltage controlled oscillator output f. This is done by controlling the bands of the amplifier 101 and the frequency converter 107 with the control signal b1.

  The voltage controlled oscillator 106, the amplifier 101, the frequency converter 107, and the frequency divider 108 shown in FIG. 6 are the same as those shown in FIGS. 2, 3, 4 and 5A, 5B in the first embodiment. The operation of this circuit diagram is also the same except that RQ2 to RQ4 are changed from fixed values to variable values.

  The Q value control signal b1 is preferably input to both the amplifier 101 and the frequency converter 107 as shown in FIG. 6 from the viewpoint of performing control with a high degree of freedom. You can just type in

<Example 6>
FIG. 16: is a block block diagram for demonstrating the receiving system based on Example 6 which is a communication system of this invention. The receiving system in the sixth embodiment is added with a Q value control circuit 2 (111) so that the system of the block configuration diagram of the fifth embodiment shown in FIG. 15 can be optimally received, and the Q value control circuit in FIG. 1 (110) to control the bandwidth of the amplifier 101 in FIG. 15, and the Q value control signal d1 from the Q value control circuit 2 (111) in FIG. 15 to the frequency converter 107 in FIG. The difference is that each band control can be performed independently.

  The amplifier 101 receives an input signal d, a frequency control signal c1, and a Q value control signal b1, and outputs an output signal e. The output signal e and the above-described Q value control signal b1 are input to the frequency converter 107, and an output signal m is output. The frequency control signal c1, which is a control signal fed back to the voltage controlled oscillator 106 and the amplifier 101, is a voltage controlled oscillator 106, a divide-by-2 divider 108, a divider 109, a phase frequency detector 104, a charge pump 103, and a loop filter 102. Are output signals from the loop filter 102 that controls the oscillation frequency of the voltage controlled oscillator 106. The reference clock signal a1 is a signal that is input from the outside and serves as a reference for the phase of the phase synchronization circuit 100.

  The Q value control circuit 1 (110) receives the phase data a2, the bandwidth data a3, the frequency control signal c1 and the output signal f of the voltage controlled oscillator 106 as inputs, and outputs the Q value control signal b1. This output signal b1 is fed back to the amplifier 101 described above. On the other hand, the Q value control circuit 2 (111) receives the phase data b2, the bandwidth data b3, the frequency control signal c1 and the output signal f of the voltage controlled oscillator 106 as inputs, and outputs the Q value control signal d1. This output signal d1 is fed back to the frequency converter 107 described above.

  The voltage controlled oscillator 106, the amplifier 101, the frequency converter 107, and the frequency divider 108 in FIG. 15 are the same as those in FIGS. 2, 3, 4 and 5A, 5B in the first embodiment described above. The operation of this circuit diagram is also the same except that RQ2 to RQ4 are changed from fixed values to variable values. Similarly, the Q value control circuit 1 (110) and the Q value control circuit 2 (111) in FIG. 15 are the same as those of the second embodiment shown in FIGS. Is the same.

  That is, the band optimization of the receiving system in the sixth embodiment is made by the Q value control circuit 1 (110) that receives the phase data a2, the bandwidth data a3, the center frequency control signal C1, and the voltage controlled oscillator output f. The Q value control signal b1 sets the band of the amplifier 101, and the Q value control circuit 2 (111) having the phase data b2, the bandwidth data b3, the center frequency control signal C1, and the voltage controlled oscillator output f as inputs. This is done by controlling the band of the frequency converter 107 with the value control signal d1.

It is a block block diagram for demonstrating the receiving system which concerns on Example 1 which is a communication system of this invention. FIG. 2 is a circuit diagram of the voltage controlled oscillator shown in FIG. 1. FIG. 2 is a circuit diagram of the amplifier shown in FIG. 1. FIG. 2 is a circuit diagram of the frequency converter shown in FIG. 1. FIG. 2 is a circuit diagram of the frequency divider shown in FIG. 1. FIG. 2 is a circuit diagram of the frequency divider shown in FIG. 1. It is a block block diagram for demonstrating Example 2 which is a communication system of this invention. It is a block diagram of the Q value control circuit shown in FIG. FIG. 8 is a circuit diagram of the arbitrary phase generator + voltage-current converter shown in FIG. 7. FIG. 6 is a diagram for explaining the operation of an arbitrary phase generator, where (a) shows the operation when IIP = IQP, (b) shows the operation when IIP = I0 and IIQ = 0, and (c) shows the input. The operation when no phase difference is generated between the outputs is shown. FIG. 8 is a diagram for explaining the details of the LC bandpass filter shown in FIG. 7, where (a) is a detailed circuit diagram of the LC bandpass filter, (b) is a frequency characteristic schematic diagram of an amplitude transfer function, and (c) is a phase diagram. It is a frequency characteristic schematic diagram of a transfer function. It is a figure which shows the exclusive OR shown in FIG. FIG. 8 is a diagram for explaining the operation of the phase comparator shown in FIG. 7, where (a) shows the operation when the phase difference between C1 and e is π / 2 [rad], and (b) shows the order of C1 and e. The operation when the phase difference is larger than π / 2 [rad] is shown. It is a block block diagram for demonstrating Example 3 which is a communication system of this invention. It is a block block diagram for demonstrating Example 4 which is a communication system of this invention. It is a block block diagram for demonstrating Example 5 which is a communication system of this invention. It is a block block diagram for demonstrating Example 6 which is a communication system of this invention. It is a figure which shows the conventional receiving circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Variable attenuator 2 Switch 3 Inductor 4 Variable 6 Transmission local oscillation circuit (signal source)
24 Frequency converter 25 Local oscillator 29 Amplifier 100, 200 Phase synchronization circuit 101, 201 Amplifier 102, 202 Loop filter 103, 203 Charge pump 104, 204 Phase frequency detector 105, 205 Bit error rate 106, 206 Voltage controlled oscillator 107 Frequency Converter 108 Frequency divider 109 Frequency divider 110, 111, 112 Q-value control circuit 201, 203 Arbitrary phase generator 202 Phase comparator 204 Voltage-current converter 205 LC bandpass filter 301 Quadrature signal generator

Claims (2)

A phase-locked loop circuit having voltage-controlled oscillation means having a first LC tank circuit including a first varactor; an amplifying means having a second LC tank circuit including a second varactor as a load; and a third varactor A frequency conversion means having a third LC tank circuit including a load as a load, and a frequency dividing means constituting the phase synchronization circuit and having a fourth LC tank circuit including a fourth varactor as a load. A communication system,
Receiving frequency tuning means using a frequency control signal from the phase-locked loop so as to control the oscillation frequency of the voltage controlled oscillating means;
A communication system comprising: a receiving band optimizing unit that controls a tuning frequency of the second LC tank, the third LC tank, and the fourth LC tank. A phase-locked loop circuit having voltage-controlled oscillation means having a first LC tank circuit including a first varactor; an amplifying means having a second LC tank circuit including a second varactor as a load; and a third varactor A frequency conversion means having a third LC tank circuit including a load as a load, and a frequency dividing means constituting the phase synchronization circuit and having a fourth LC tank circuit including a fourth character as a load. A communication system,
A transmission frequency tuning means using a frequency control signal from the phase locked loop so as to control the oscillation frequency of the voltage controlled oscillation means;
A communication system comprising: a transmission band optimizing unit that controls a tuning frequency of the second LC tank, the third LC tank, and the fourth LC tank.

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