JP4748557B2 - Absolute encoder - Google Patents

Description

【００３５】
絶対位置合成部６は、上記の関係を利用してλｍアドレスＡｊを特定するとともに、上記φｍをもとに生成された分解能１μｍのパルス列ＳＡＰｍとにより、１μｍの分解能Ｒで１６λｍ区間の絶対位置を生成する。例えば、図７に示すようにカウンタ機能（タイマー）を備えるマイクロコンピュータ（ＣＰＵ）６３を用いてソフトウエア処理で実現することができる。
【００３６】
ここで、絶対位置合成部６におけるλｍアドレスＡｊの検出にかかる基本原理について説明する。
【００３７】
この絶対位置合成部６は、上記第１のゲート回路５から出力される１μｍ分解能のパルス列ＳＡＰｍをカウントするパルスカウンタ６１と、第２のゲート回路１１から出力されるパルス列ＳＡＰａをカウントするパルスカウンタ６２を備え、該パルスカウンタ６１，６２の計測値をＣＰＵ６３に取り込むためのトリガ信号として、パルス幅変調信号ＰＷＳｍ，ＰＷＳａのセット入力となる基準信号ＭＯＤＳがタイミング信号生成部１２からＣＰＵ６３への割り込み端子に供給されている。
【００３８】
サンプリング時刻ｔｉにおいて、上記（２）式に示す位相量φｍ（ｔｉ）のリセットタイミングに対応した基準信号ＭＯＤＳが入力されると、ＣＰＵ６３が割り込み動作を開始し、パルスカウンタ６１で計測された第１のスケール１の波長λｍ内の絶対位置に対応するデータＤｍ（ｔｉ）と、パルスカウンタ６２で計測された上記２つの位相変調信号の位相差Δφに対応したパルス列ＳＡＰｍの計測値ΔＤ（ｔｉ）がＣＰＵ６３に取り込まれ、ＲＡＭ６４内の所定のメモリ領域に格納される。
【００３９】
次に、ＣＰＵ６３は、上記位相差Δφに対応したこれらの計数値の差ΔＤをＲＡＭ６４内の所定の領域に格納するとともに、上記区間パルス数Ｍ／１６で除算し、その商としてλｍアドレスＡｊを特定し、該求められたＡｊをλｍ倍し、さらに、タイミングｔｉにおけるλｍ内の絶対値Ｄｍ（ｔｉ）とを加算し、１６λｍ区間全域に亘る分解能１μｍの絶対位置を生成する。
【００４０】
このようにして生成された絶対位置は、ＲＡＭ６４内の所定のメモリ領域内に格納するとともに、例えば、測定データとして外部に出力する。
【００４１】
ところで、上記の絶対位置合成部６の動作は理想的な状態で述べたものであり、実際のシステムにおいては検出された信号の不完全さ、例えば、各々の検出ヘッド２，８に重畳するＤＣや出力レベルのアンバランス等に起因する内挿誤差の影響により、λｍアドレスＡｊの判定に誤動作を起こすことがある。
【００４２】
そこで、本発明において適用される誤動作のないλｍアドレスの生成方法について述べる。
【００４３】
まず、位相変調信号が理想的な状態から外れた際に生ずる内挿誤差について説明する。
【００４４】
上述の（１）式及び（２）式に示した位相変調信号は、２チャンネルの検出ヘッドから理想的な信号が得られることを前提にした理論式である。
【００４５】
しかしながら、実際のシステムでは各の検出ヘッドに重畳するＤＣや出力レベルのアンバランスにより、（１）式や（２）式に示すような完全な位相変調信号とのずれを生じ、結果として内挿誤差を生ずる。
【００４６】
ここで、内挿誤差の発生要因として、上記の如くＤＣ成分の重畳、出力レベルのアンバランスと仮定し、一般式として波長λのトラックにおけるＣＨ１検出ヘッド及びＣＨ２検出ヘッドから得られる平衡変調信号を各々ｅ１，ｅ２とすると、平衡変調信号ｅ１，ｅ２は、
ｅ１＝｛Ａ＋（１＋ａ）×Ｓｉｎ（２πｘ／λ）｝×Ｃｏｓωｔ （６）
ｅ２＝｛Ｂ＋（１＋ｂ）×Ｃｏｓ（２πｘ／λ）｝×Ｓｉｎωｔ （７）
ただし、
ａ：ＣＨ１の振幅ずれ、ｂ：ＣＨ２の振幅ずれ
Ａ：ＣＨ１のＤＣ重畳、Ｂ：ＣＨ２のＤＣ重畳
となり、２πｘ／λ＝Ｘ、ωｔ＝Ｔとおけば、（６）式及び（７）式は
ｅ１＝｛Ａ＋（１＋ａ）×ＳｉｎＸ｝×ＣｏｓＴ （６）’
ｅ２＝｛Ｂ＋（１＋ｂ）×ＣｏｓＸ｝×ＳｉｎＴ （７）’
と表すことができる。
【００４７】
ここで、説明を簡単にするため、ＤＣのみにずれがあったときの位相変調信号をｅｐｍ（Ｄ）とすれば、（６）’式及び（７）’式において、ａ＝ｂ＝０とおいて加算した信号であり、次のように表すことができる。
【００４８】

ただし、
α＝ｔａｎ^−１（Ａ／Ｂ）
θ＝ｔａｎ^−１｛（Ａ＋ＳｉｎＸ）／（Ｂ＋ＣｏｓＸ）｝ （９）
ここで、（８）式の｛ ｝の中は、位相変調信号ｅｐｍ（Ｄ）のエンベロープを表しており、基準振幅１に対しＸの基準位置から位相がαだけ遅れた振幅が√（Ａ^２＋Ｂ^２）のリップルが重畳した、Ｘに対して一次の成分を有する正弦波状の信号であることが分かる。
【００４９】
また、（９）式のθは変位量を表しているので、誤差がないときの理論値｛θ＝ｔａｎ^−１（ＳｉｎＸ／ＣｏｓＸ）｝から減算すると、位相変調信号が理想からずれた時の誤差を表すことになる。
【００５０】
今、Ｘに対して０から２πにわたる１波長内の内挿誤差をΔＸとおくと、内挿誤差ΔＸは、
ΔＸ＝ｔａｎ^−１｛（Ａ＋ＳｉｎＸ）／（Ｂ＋ＣｏｓＸ）｝
−ｔａｎ^−１（ＳｉｎＸ／ＣｏｓＸ） （１０）
であり、ここで、
α＝｛（Ａ＋ＳｉｎＸ）／（Ｂ＋ＣｏｓＸ）｝、
β＝ＳｉｎＸ／ＣｏｓＸ
とおけば
ΔＸ＝ｔａｎ^−１（α−β）／（１−α×β）
ゆえ、
ΔＸ＝−ｔａｎ^−１｛（Ｂ×ＣｏｓＸ−Ａ×ＳｉｎＸ）／（１＋Ａ×ＳｉｎＸ ＋ＢＸＣｏｓ×）｝
となる。そして、（Ａ×ＳｉｎＸ＋Ｂ×ＣｏｓＸ）が１より十分小さいことを考慮してΔＸの近似式を求めると、
ΔＸ＝−ｔａｎ^−１（Ｂ×ＣｏｓＸ−Ａ×ＳｉｎＸ）
＝−ｔａｎ^−１｛√（Ａ^２＋Ｂ^２）×Ｓｉｎ（Ｘ＋γ）｝ （１１）
となる。ただし、
γ＝−ｔａｎ^−１（Ａ／Ｂ）
である。
【００５１】
ここで、簡単にするためＡ＝Ｂの場合について整理してみると、
ΔＸ＝−ｔａｎ^−１｛√２×Ｓｉｎ（Ｘ−π／４）｝ （１２）
となる。
【００５２】
すなわち、内挿誤差ΔＸは、Ｘの１周期に対して同一周期の成分を有する正弦波状に変化する信号であり、その大きさがＤＣの重畳量Ａ及びＢの大きさによって変化する信号であることが分かる。
【００５３】
ところで、図５にも示したように、λｍアドレスＡｊの切替え部は、第１のスケール１の波長λｍの整数倍に対応した位置であるが、第２のスケール７に対しては波長λａの１／１６の整数倍の位置に対応しているため、λｍアドレス切替え部において検出されるΔφには、第２のスケール７の波長λａの内挿誤差が重畳し、結果として内挿誤差の影響に伴う位相差Δφの逆転現象が生じることがある。
【００５４】
したがって、上述の表１に示した関係をもとに、単純に検出されたΔφを区間位相量φＺ（＝２π／１６）に対する商を求めるだけでは、入ｍアドレスＡｊの検出に誤動作を生じることになる。
【００５５】
図８は、第２のスケール７の波長λａに上記（１１）式で表される内挿誤差ΔＸをＸの１周期区間、すなわち、ｘ＝λａの区間に亘ってプロットしたもので、波長λａ内の各の位置における内挿誤差Ｉｅが、λｍアドレスＡｊの切替え位置に対応して重畳する様子を示したものであり、次の表２はその対応関係を示したものである。
【００５６】
【表２】

【００５７】
次に、本発明において適用される実際のシステム、すなわち、内挿誤差が発生した場合でも正しくλｍアドレスＡｊを検出可能とする絶対位置合成部６の構成及び動作について説明する。
【００５８】
先ず、図９を参考にしながらλｍアドレスＡｊの確定にかかる基本的な考え方を説明する。
【００５９】
（１）λｍアドレスＡｊの切替え部、すなわち、λｍの両端部において検出される位相差Δφは、第２のスケール７の内挿誤差Ｉｅ（ａ）に対応する位相量φｉｅ（ａ）だけ変動する。したがって、実際にはλｍアドレスＡｊがｊとして検出されるべきものが、その前後、すなわち、ｊ−１又はｊ＋１として検出される可能性がある。
【００６０】
（２）しかしながら、上記誤検出される可能性を有する領域に対し、さらに第１のスケール１における内挿誤差Ｉｅ（ｍ）に対応する位相量φｉｅ（ｍ）だけ内側の領域においては、内挿誤差の影響を受けず、λｍアドレスＡｊを一義的に決定できる領域がある。
【００６１】
（３）さらに、上記（１）においても、第１のスケール１において検出された位相φｍが、波長λｍ内のどの位置に属するかを、例えば、λｍの中央値に対して左側（ｘ≦λｍ）又は右側（ｘ＞λｍ）に位置するかの判定条件を加え、該判定結果をもとに補正することにより、正しくλｍアドレスＡｊを判定できる。
【００６２】
すなわち、λｍアドレスＡｊの切替え部において、λｍアドレスＡｊの判定領域にヒステリシスを持たせ、該ヒステリシス領域内においては、第１のスケール１の位置による判定条件を付加することにより、内挿誤差の影響を受けず、誤動作のないλｍアドレスＡｊの検出が実現できる。
【００６３】
次に、本発明におけるλｍアドレスＡｊの切替え部に付与すべきヒステリシス及びその他の判定条件の設定について、具体的な数値を適用し説明する。
【００６４】
上述のように、位相量φはパルス数ΔＤとして検出され、区間位相量φＺ（＝２π／１６）は区間パルス数ＮＤ（＝６４）に対応している。
【００６５】
第１のスケール１及び第２のスケール７の波長が略等しいので、システムにおいて想定される内挿誤差が略等しいとして、その振幅（Ｐ−Ｐ）をＩｅとすれば、内挿誤差に対応する位相量φｉｅ及びパルス数Ｄｉｅは次のように表すことができる。
【００６６】
φｉｅ＝２π×（Ｉｅ／λｍ） （１０）
Ｄｉｅ＝Ｍ×Δφｉ／２π＝１，０２４×（Ｉｅ／λｍ） （１１）
すなわち、λｍアドレスＡｊの切替え部においては、パルス数ΔＤは、Ｄｉｅ／２ずつ変動する可能性がある。
【００６７】
ここで、波長λに対する内挿誤差（Ｉｅ／λｍ）は通常２％程度であり、そのときのＤｉｅは、（１１）式から約２０パルスであり、λｍアドレスＡｊの切替え部においては、第２のスケール７の内挿誤差により、区間パルス数Ｍ／１６（＝６４）に対して±１０パルスの変動が生ずると考えることができる。
【００６８】
さらに、第１のスケール１における内挿誤差の影響に伴うパルス数Ｄｉｅも２０パルスとすれば、この値を加えた区間パルス数ＮＤ（＝６４）に対して±２０パルス分内側の領域、すなわち、パルス数ΔＤが２０以上（＝０＋２０）から４４未満（＝６４−２０）の区間は、内挿誤差の影響を受けず一義的にλｍアドレスＡｊを決定できる領域（以下、無条件判別領域）である。
【００６９】
また、上記無条件判別領域の外側、即ち、ΔＤが０以上２０未満の下側領域及びΔＤが４４以上６４未満の上端領域においては、第１のスケール１において検出される位相量φｍが、λｍの中間値、すなわち、５１２パルス（１，０２４／２）位置を基準にして大小を判別する条件を付加し、該判定結果に応じて仮決定されたλｍアドレスＡｊを補正すれば良い。
【００７０】
以下、図１０に示す処理フローに従い本発明におけるλｍアドレスＡｊの判定手順を説明する。
【００７１】
先ず、最初のステップＳ１では、サンプリング時刻ｔｉにおいて、基準信号ＭＯＤＳが入力されると、ＣＰＵ６３が割り込み動作を開始し、上記第１のパルスカウンタ６１の計数値Ｄｍ（ｔｉ）及び第２のパルスカウンタ６２の計数値ΔＤ（ｔｉ）を取り込み、ＲＡＭ６４の所定のメモリ領域に格納する。
【００７２】
次のステップＳ２において、ＣＰＵ６３は、ΔＤを区間パルス数６４で除算し、商ｊをλｍアドレスの候補として、また、剰余Ｒｅｓをλｍアドレス確定用のデータとしてＲＡＭ６４の所定のメモリ領域に格納する。
【００７３】
次のステップＳ３において、ＣＰＵ６３は、剰余Ｒｅｓの値に応じて３つの領域に分別し、次の判定処理によりλｍアドレスＡｊを確定する。
【００７４】
すなわち、０≦Ｒｅｓ＜２０のときには（ステップＳ４１）、Ｄｍ（ｔｉ）が中央値５１２を超えているか否かについての判定を行う（ステップＳ５１）。
【００７５】
そして、このステップＳ５１における判定結果が”Ｙｅｓ”すなわちＤｍ（ｔｉ）≧５１２である場合は、上記ステップＳ２において算出された商ｊから１を減算し、この値をλｍアドレスＡｊとし（ステップＳ６１）、また、判定結果が”Ｎｏ”すなわちＤｍ（ｔｉ）＜５１２である場合には、上記ステップＳ２で検出されたＡｊをそのままλｍアドレスＡｊとする（ステップＳ６２）。
【００７６】
また、２０≦Ｒｅｓ＜４４のときには（ステップＳ４２）、ステップＳ２で検出された商ｊをそのままλｍアドレスＡｊとする（ステップＳ６２）。
【００７７】
さらに、４４≦Ｒｅｓ＜６４のときには（ステップＳ４３）、Ｄｍ（ｔｉ）が中央値５１２より小さいか否かについて判定を行う。
【００７８】
そして、このステップＳ５３における判定結果が”Ｙｅｓ”すなわちＤｍ（ｔｉ）＜５１２である場合には、上記ステップＳ２において算出された商ｊに１を加算し、この値をλｍアドレスＡｊとし（ステップＳ６３）、また、判定結果が”Ｎｏ”すなわちＤｍ（ｔｉ）≧５１２である場合は、上記ステップＳ２で検出されたＡｊをそのままλｍアドレスＡｊとする（ステップＳ６２）。
【００７９】
次のステップＳ７では、上記の手順によってλｍアドレスＡｊを確定した後、ＣＰＵ６３はλｍアドレスＡｊに波長λｍを乗じたのち、上記Ｄｍ（ｔｉ）と加算し、時刻ｔｉにおける１６λｍ区間内における絶対位置Ｘ（ｔｉ）を生成する。
【００８０】
以下、サンプリング時刻ごとに同様の手順（Ｓ１〜Ｓ７）を繰り返し、１６λｍ区間内における絶対位置を求める。また、生成された絶対位置Ｘ（ｔｉ）は、例えば表示として利用する、又は測定データとして外部のシステムに出力するなど、必要に応じて利用できる。
【００８１】
なお、上記絶対位置合成部６は、マイクロコンピュータ（ＣＰＵ）６３を用いてソフトウエア処理で実現したが、図１１に示すようにハードウエアにより構成することもできる。
【００８２】
すなわち、図１１に示す絶対位置合成部６は、上記第１のゲート回路５から出力される１μｍ分解能のパルス列ＳＡＰｍをカウントする第１のカウンタ１６１と、第２のゲート回路１１から出力されるパルス列ＳＡＰａをカウントする第２のカウンタ１６２、タイミング信号生成部１２から基準信号ＭＯＤＳが供給されるカウンタ制御回路１６４を備える。
【００８３】
第１のカウンタ１６１は、Ｍ＝１，０２４とした場合、第１のスケール１の波長λｍ内の位置に対応するパルス列ＳＡＰｍを計数する１，０２４進（１０ｂｉｔ）カウンタと、該カウンタの計数値をラッチする１０ｂｉｔのラッチ回路からなり、ラッチ回路の出力（Ｄｍ（ｔｉ））を、第１の比較器１６５に供給するとともに、合成された絶対位置の下位桁（１０ｂｉｔ）として出力する。
【００８４】
上記第１の比較器１６５は、波長λｍ内の所定の位置、この例では波長λｍ内の所定の位置と比較する比較器である。
【００８５】
この例では、中央値（５１２）と比較し、
（ａ１） Ｄｍ（ｔｉ）＜５１２
（ａ２） Ｄｍ（ｔｉ）＝５１２
（ａ３） Ｄｍ（ｔｉ）＞５１２
に対応する判定信号を補正回路１６８に出力する。
【００８６】
第２のカウンタ１６２は、Ｍ＝１，０２４とした場合、第１のスケール１と第２のスケール７から出力される位相変調信号の位相差に等しいバルス列ＳＡＰａを計数する６４進（６ｂｉｔ）カウンタと、該カウンタの計数値をラッチする６ｂｉｔラッチ回路からなり、上記６４進カウンタの桁上げ信号（Ｃａ２）を第３のカウンタ１６３に供給し、また、ラッチ回路の出力（Ｒｅｓ）を第２及び第３の比較器１６６，１６７に供給する。
【００８７】
第３のカウンタ１６３は、ＳＡＰａ／６４の商を計数するラッチ出力機能付のカウンタ（Ｍ＝１，０２４とした時は１６進）であり、第２のカウンタ１６２の桁上げ信号（Ｃａ２）を計数する１６進（４ｂｉｔ）カウンタと、該カウンタの計数値をラッチする４ｂｉｔラッチ回路からなり、ラッチ回路の出力を仮決定アドレス（ｊ）として、加算回路１６９の一方の入力端子に供給する。
【００８８】
カウンタ制御回路１６４は、サンプリング周期Ｔ（＝１／ｆ）毎に入力されるＭＯＤＳ信号から、上記カウンタ計数値をラッチ回路に転送するためのラッチ信号と、カウンタの計数値を初期化（リセット）するリセット信号を生成し、このリセット信号を上記第１乃至第３のカウンタ１６１〜１６３に供給する。
【００８９】
比較器１６６は、剰余（Ｒｅｓ）を下側ゾーン設定用の下限値と比較するための比較器であり、この例では下限値（２０）との比較を行い、
（ｂ１） Ｒｅｓ＜２０
（ｂ２） Ｒｅｓ＝２０
（ｂ３） Ｒｅｓ＞２０
に対応する判定信号を補正回路１６８に出力する。
【００９０】
比較器１６７は、ＳＡＰａ／６４の剰余（Ｒｅｓ）を上側ゾーン設定用の上限値と比較するための比較器であり、この例では上限値（４４）との比較を行い、
（ｃ１） Ｒｅｓ＜４４
（ｃ２） Ｒｅｓ＝４４
（ｃ３） Ｒｅｓ＞４４
に対応する判定信号を補正回路１６８に出力する。
【００９１】
補正回路１６８は、上記第１乃至第３比較器１６５〜１６７の出力をもとに、第３のカウンタ１６３の出力である仮決定アドレス（ｊ）の補正値（＋１，０，−１）を出力する回路であり、下記の条件に応じて補正値を出力する。
【００９２】

ここで、Ｄｍ（ｔｉ）≧５１２に対応するゾーンは、上記（ａ２）及び（ａ３）の論理和（Ｄｍ（ｔｉ）＝５１２） （Ｄｍ（ｔｉ）＞５１２）である。また、０≦Ｒｅｓ＜２０に対応するゾーンは、上記（ｂ１）すなわち（Ｒｅｓ＜２０）である。さらに、上側ゾーン４４≦Ｒｅｓ＜６４は、（ｃ２）と（ｃ３）の論理和すなわち（Ｒｅｓ＝４４） （Ｒｅｓ＞４４）であり、また、無条件でアドレスを決定できる中間ゾーン２０≦Ｒｅｓ＜４４は、上記第２の比較器１６６の出力との組み合わせた（（Ｒｅｓ＝２０） （Ｒｅｓ＞２０）） （Ｒｅｓ＜４４）である。
【００９３】
ただし、実際の回路では”−１”に対応する補正値は補数（−１）の形に変換されて加算回路１６９で加算される。
【００９４】
加算回路１６９は、例えば４ｂｉｔのフルアダーで構成され、第３のカウンタ１６３からの仮決定アドレス（ｊ）と、上記補正回路１６８の出力である補正値（＋１，０，−１）とを加算する。この加算回路１６９は、”−１”に対応する補正値、すなわち補数（−１）が入力されたときはｊ＋（−１）を補数回路１７０に出力する。
【００９５】
補数回路１７０は、加算回路１６９から”−１”に対応する補正値、すなわち補数（−１）が入力されたときの加算出力（ｊ＋（−１）において、加算回路１６９の桁上信号信号（Ｃ４）が出力されなかったとき動作し、真数（ｊ−１）に変換して、決定アドレス（Ａｊ）の上位桁を出力する。
【００９６】
以上、本発明の具体的な実施の形態として、所望の分解能Ｒ＝１μｍを得るために、第１のスケールの波長λｍを所望の分解能Ｒ＝１μｍの１，０２４倍とし、位相変調信号のキャリア周波数ｆの１，０２４（Ｍ＝１，０２４）倍のクロックパルスを用いて内挿するとともに、第１のスケール１の波長λｍの１６倍区間（Ｎ＝１６）の絶対位置を検出するため、第１のスケール１の波長λｍと第２のスケール７の波長λａとの関係を１６×λｍ＝１７×λａなる２進系列の数値を設定した事例について説明した。
【００９７】
Ｎとして２進系列を選択すると、内挿処理等に用いるハードウエアが簡単になるばかりでなく、２進処理を基本とするＣＰＵを用いた絶対位置合成部６におけるλｍアドレスの特定におけるソフトウエア処置が簡単かつ高速に実現できる等のメリットがある。
【００９８】
また、上記実施の形態の説明においてはＮ×λｍ＝（Ｎ＋１）×λａとしたが、Ｎ×λｍ＝（Ｎ−１）×λａと設定できること、さらには、Ｎ±１＝２^ｎと選ぶことができること、さらには、所望の分解能Ｒ＝λｍ／Ｍを得るために、第１のスケール１の波長λｍ及び設計条件Ｍ、Ｎは本発明の主旨を逸脱しない範囲で任意に設定できること、また、２進系列ではなく、Ｍ，Ｎについて１０進系列の設計条件を設定し得ることは言うまでもない。
【００９９】
また、上記実施の形態において、第１の変位量検出部３から得られる位相変調信号ｅｐｍと第２の変位量検出部９から得られる位相変調信号ｅｐａとの位相差Δφの検出において、第２の位相比較部１０にて直接検出するように構成した。しかしながら、第１の位相比較部４におけるごとく、第２の位相比較部１０においても、位相変調信号ｅｐａと上記基準信号との位相比較により第２のスケール７の波長λａ内の絶対位置として検出し、該位相差をφａ（ｔｉ）として検出した後、第２のゲート回路１１及びパルスカウンタ６２を介してパルス数Ｄａ（ｔｉ）として検出し、絶対位置合成部６により演算処理ΔＤ＝Ｄａ（ｔｉ）−Ｄｍ（ｔｉ）として検出できることは言うまでもない。
【０１００】
さらに、本発明は、磁気式に制約されることなく、例えば光学方式のごとくスケールとヘッドとの相対移動に対応した２チャンネルの直交する正弦波信号が出力されるようなシステムにおいても、該検出された２相の正弦波信号を、キャリア周波数ｆの信号で直交変調した後加算することにより、位相変調信号を取り出すようにすれば同様に適用できることはいうまでもない。
【０１０１】
さらに、本発明においてはリニアエンコーダヘの適用について説明したが、繰り返し区間を円周長と一致させることにより回転量のアブソリュート検出にも適用可能である。
【０１０２】
【発明の効果】
以上のように、本発明によれば、第１のスケールの記録波長λｍに対応して得られるキャリア周波数ｆの位相変調信号をＭ倍の周波数を有するクロックパルスを用いることにより、波長λｍ内を分解能Ｒ＝λｍ／Ｍで読み出すことができる。すなわち、位相変調信号を用いた位置検出システムのため、該位相変調信号のキャリア周波数ｆに対し、クロックパルスの周波数Ｍ×ｆを高く、すなわち、Ｍを大きくするだけで容易に高分解能を実現することができる。また、設計条件Ｍ，Ｎはスケールの波長λｍとして２進系列の数値を選ぶことにより、ハードウエアが簡単になるのみならず、ＣＰＵを用いた絶対位置演算処理におけるソフトウエア処理が簡単になり、結果として高速な処理を実現できる。
【０１０３】
また、第１のスケールの波長λｍと第２のスケールの波長λａとを、例えば、Ｎ×λｍ＝（Ｎ±１）×λａなる関係を満足するように設定することにより、第１のスケールの波長λｍのＮ倍区間にわたってアブソリュートで検出することができる。
【０１０４】
また、第１のスケール及び第２のスケールから出力される位相変調信号の位相差に応じて第１のスケールのＮ倍区間におけるλｍアドレスの特定に際して、位相変調信号に含まれる内挿誤差によって生ずるλｍアドレス検出に係る誤動作を防ぐことができ、システムが許容できる範囲で設計値Ｎを大きくし、広い範囲での絶対位置検出を安定かつ高精度に行うことが可能となる。
【０１０５】
また、高分解能なアブソリュート検出が可能なため、例えば、差動トランス方式を多用していた用途にも使用でき、ＤＣドリフトの影響や、ウオームアップなしで直ちに測定できる等の効果が期待できる。
【０１０６】
本発明によれば、システムの構造が簡単になり、小型・低コストで絶対位置検出システムを構築することができる。
【図面の簡単な説明】
【図１】本発明に係るアブソリュートエンコーダの構成を示すブロック図である。
【図２】上記アブソリュートエンコーダにおける第１の変位量検出部の構成を示すブロック図である。
【図３】上記アブソリュートエンコーダにおける第１の位相比較部の構成を示すブロック図である。
【図４】上記第１の位相比較部の動作タイミングを説明するための図である。
【図５】アブソリュート計測区間において第１の変位量検出回路で検出された位相量φｍと、第２の変位量検出回路で検出された位相量φａとの関係を示す図である。
【図６】第１の変位量検出部で検出された位相量φｍと、φａとφｍとの位相差Δφ（＝φａ−φｍ）との関係を示す図である。
【図７】絶対位置合成部の構成例を示すブロック図である。
【図８】ＤＣ偏倚が乗じたときの第１のスケールの内挿誤差ΔＸの例を示す図である。
【図９】λｍアドレスＡｊの確定にかかる基本的な考え方を説明する図である。
【図１０】λｍアドレスＡｊの判定手順を示すフローチャートである。
【図１１】上記絶対位置合成部のハードウエア構成例を示すブロック図である。
【符号の説明】
１ 第１のスケール、２Ａ，２Ｂ ＭＲセンサ、２ 第１の検出ヘッド、３ 第１の変位量検出部、４ 第１の位相比較部、５ 第１のゲート回路、６ 演算部、１２ タイミング信号生成部、７ 第２のスケール、８ 第２の検出ヘッド、９ 第２の変位量検出部、１０ 第２の位相比較部、１１ 第２のゲート回路、３１，３２ 乗算器、３３ 加算増幅器、４１ 波形整形回路、４２，４３ 第１及び第２の同期微分回路、４４ ＪＫフリップフロップ、６１，６２ パルスカウンタ、６３ ＣＰＵ、６４ ＲＡＭ、１００ アブソリュートエンコーダ、１６１〜１６３ 第１乃至第３のカウンタ、１６４ カウンタ制御回路、１６５〜１６７ 第１乃至第３比較器、１６８ 補正回路、１６９ 加算回路、１７０ 補数回路[0001]
BACKGROUND OF THE INVENTION
The present invention is used for dimensional measurement in the industrial machinery field, for example, measurement of adhesion and parallelism of mold press dies, measurement and control of rolling amount in a roll rolling mill, and measurement of part dimensions in production / assembly factories, etc. It is related to the absolute encoder that has been used favorably.
[0002]
[Prior art]
A first modulation circuit that outputs a phase modulation signal whose phase repeatedly changes in response to a relative displacement between a first scale having a predetermined wavelength λm and a first detection head that detects a signal of the first scale. The phase repeatedly changes in response to the relative displacement between the second detecting head for detecting the second scale and the second scale having a wavelength λa different from the first scale and the second scale head for detecting the signal of the second scale. A second detection unit that outputs a phase modulation signal; and a phase comparison circuit that compares a phase difference between signals obtained from the first detection unit and the second detection unit. A signal whose phase changes corresponding to a signal having a wavelength sufficiently longer than the wavelengths of the first scale and the second scale is obtained, the first scale and the second scale, the first detection head, Relative position with the second detection head Japanese Patent Publication No. 50-23618 discloses a measuring device for detecting the above.
[0003]
In this measuring device, the phase modulation signal epm obtained from the first detection means and the phase modulation signal epa obtained from the second detection means can be expressed by the following equations.
[0004]
epm = Ep1 × Sin (2πft + 2πX / λm)
epa = Ep2 × Sin (2πft + 2πX / λa)
Further, when the relationship between the wavelengths λm and λa is selected as, for example, a relationship of N × λm = (N−1) × λa, the phases θm (= 2πX / λm) and θa (= 2πX / λa) of these signals The difference Δθ (= θm−θa) is a signal that repeats at a period N times the wavelength λm as shown in the following equation.
[0005]
Δθ = 2πX / (N × λm)
Therefore, the measuring device can detect the position in units of λm in the N × λm section by dividing the phase difference Δθ by a predetermined phase difference, that is, 2π / N.
[0006]
[Problems to be solved by the invention]
However, in the above measuring device, when an ideal signal cannot be obtained from each scale, for example, when the phase modulation signal is incomplete, a periodic error occurs in the wavelength λ, and these errors are It is also superimposed on the switching position in λm units. Therefore, when the phase difference Δθ is divided by 2π / N as described above, a deviation occurs due to the error, and as a result, an error of λm may occur.
[0007]
In order to avoid these errors, a method of directly detecting the inside of Nλm using the phase difference Δθ obtained from the above two scales can be considered, but in this method, a virtually long scale in which the phase difference Δθ is Nλm is considered. When the phase is 2π, that is, the signal periodically changes in phase, the clock frequency M × f M times the carrier frequency f is interpolated into the carrier frequency f to obtain high resolution. As the resolution λm / (M × N) increases the wavelength λm or N, it becomes more difficult to obtain a high resolution. In addition, there is a problem that detection accuracy deteriorates due to a change with time.
[0008]
Therefore, in view of the conventional problems as described above, the object of the present invention is to provide an absolute value over a section N times the wavelength of the scale due to the phase difference between the phase modulation signals output from two sets of scales having different wavelengths. In an absolute encoder configured to detect the above, it is an object of the present invention to provide a small encoder, a low-cost, high-impact, and high-resolution absolute encoder that prevents an erroneous detection of an adjacent section due to a detection error of the scale.
[0009]
[Means for Solving the Problems]
The present invention relates to a first scale having a scale of wavelength λm, a first detection head for detecting a signal of the first scale, and the relative relationship between the first scale and the first detection head. A first displacement amount detecting means configured to extract the displacement amount as a phase modulation signal having a carrier frequency f; a second scale having a scale having a wavelength λa different from the first scale; A second detection head for detecting a signal of a second scale, and a second displacement of the second scale and the second detection head is extracted as a phase modulation signal of the carrier frequency f. Detecting the phase difference between the displacement amount detection means, the phase modulation signal obtained from the first displacement amount detection means, and the phase modulation signal obtained from the second displacement amount detection means, and using the phase difference, First scale wavelength λm A carrier frequency obtained from the first displacement amount detection means in an absolute encoder configured to obtain a periodic signal repeated at an N-fold wavelength and to absolutely detect an N-fold section of the wavelength of the first scale. first phase comparison means for generating a pulse width modulation signal corresponding to the absolute position of the first detection head within the wavelength λm of the first scale by comparing the phase modulation signal of f with the reference signal of frequency f The pulse width modulation signal generated by the first phase comparison means is interpolated with a clock pulse M times the carrier frequency f to correspond to the absolute position of the first detection head within the wavelength λm of the first scale. A first gate circuit for converting to a pulse train of resolution R = λm / M, a phase modulation signal output from the first displacement amount detection means, and a second displacement amount detector; Second phase comparison means for generating a pulse width modulation signal corresponding to the phase difference of the phase modulation signal output from the signal, and the pulse width modulation signal generated by the second phase comparison means is M times the carrier frequency f The second gate circuit that interpolates the clock pulses of the above and converts them into a pulse train corresponding to the phase difference, and the output of the second gate circuit is counted, and the counted value is the number of pulses corresponding to one section of the wavelength λm Dividing by M / N, the address of the wavelength λm of the first scale is tentatively determined by the obtained quotient, and which of the segment pulses M / N that the remainder is divided into three zones belongs to After the determination, when belonging to the zone corresponding to the switching unit of the λm address, the comparison is made with a predetermined position within the wavelength λm of the first scale as a reference, and the tentatively determined λm address is corrected according to the comparison result. First The λm address in the N-times section of the wavelength λm of the scale is specified, and when the remainder belongs to the central zone, the tentatively determined λm address is unconditionally specified as the λm address. An absolute position synthesizing unit that synthesizes the absolute position within the wavelength λm of the scale and the identified λm address by counting the pulse train output from the first gate circuit, and having the wavelength λm of the first scale A feature is that detection is performed with a resolution R = λm / M over an N-fold interval.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0011]
An embodiment of the present invention described below uses a phase modulation signal output from two tracks having different wavelengths and uses a phase modulation signal to detect an absolute range longer than the recording wavelength of the track, for example, a special measurement system. This is an improvement of the measuring device disclosed in Japanese Patent Publication No. 50-23618. In the magnetic type, for example, the recording wavelength and the reproduction wavelength may differ depending on the method using a supersaturated core or the method using a magnetoresistive effect element (hereinafter referred to as MR sensor). The description will be made based on the wavelength to be reproduced using the MR sensor.
[0012]
FIG. 1 is a block diagram showing a configuration of an absolute encoder 100 according to the present invention.
[0013]
Here, the wavelength λm is 1,024 μm, and the interpolation number M is 1,024 (= 2). ¹⁰ ), And the extended count N is 16 (= 2) ⁴ ), The relationship between the wavelengths λm and λa is 16 × λm = (16 + 1) × λa = 17 × λa, so that 16 of λm (N = 2) ⁴ ) A specific example in which about 16 mm (more precisely, 1.024 × 16 = 16.384 mm) of the double section can be detected with a resolution R of 1 μm will be described.
[0014]
The absolute encoder 100 has a first scale 1 formed by recording a scale having a wavelength λm (= 1,024 μm) on a scale member (not shown), and is opposed to the first scale 1 and has a wavelength λm. On the other hand, a first detection head 2 composed of two-channel MR sensors 2A and 2B arranged with a 90 ° phase difference (λm / 4) is provided. The first detection head 2 has two systems of sine wave signals having a relative movement period of 2πx / λm (where x is a displacement amount) and having a phase difference of 90 ° due to relative movement with the first scale 1. Sin (2πx / λm) and Cos (2πx / λm) are output.
[0015]
These two-phase sine wave signals Sin (2πx / λm) and Cos (2πx / λm) are guided to the first displacement amount detection unit 3 having a configuration as shown in FIG. 2, for example.
[0016]
The first displacement detection unit 3 includes two-phase sinusoidal signals Sin (2πx / λm) and Cos (2πx) obtained by the two-channel MR sensors 2A and 2B constituting the first detection head 2. / Λm) is provided by the timing signal generator 12 to perform balanced modulation with the two-phase signals MODC and MODS of the carrier frequency f having a phase difference of 90 °, and balanced modulation by the multipliers 31 and 32 is performed. A summing amplifier 33 for adding the signals Sin (2πx / λm) × Cosωt, Cos (2πx / λm) Sinωt is provided, and a phase modulation signal ep as shown in the following equation (1) is added as an addition output by the summing amplifier 33. Output.
[0017]
epm = Ep1 × Sin (ωt + 2πx / λm) (1)
Where ω = 2πf, x = relative displacement
This phase modulation signal epm is guided to, for example, the first phase comparison unit 4 configured as shown in FIG.
[0018]
The first phase comparison unit 4 includes first and second synchronous differentiation circuits 42 and 43 and a JK flip-flop 44 to which a clock pulse having a frequency M × f given by the timing signal generation unit 12 is supplied. The differential output by the first synchronous differentiation circuit 42 to which the phase modulation signal epm is supplied from the one displacement amount detection unit 3 via the waveform shaping circuit 41 is supplied to the K input terminal of the JK flip-flop 44. By supplying the differential output from the second synchronous differentiating circuit 43 to which the reference signal MODS is supplied to the J input terminal of the JK flip-flop 44, within the wavelength λm every sampling period T (= 1 / f). The pulse width modulation signal PWSm corresponding to the absolute position is output from the JK flip-flop 44.
[0019]
Here, as shown in FIG. 4, the operation timing of the first phase comparison unit 4 is set by the phase modulation signal epm output from the first displacement amount detection unit 3 at the sampling time ti, and the reference signal The phase amount φm (ti) corresponding to the absolute position x (ti) within the wavelength λm at the time ti of the pulse width modulation signal PWSm reset by the MODS can be expressed as the following equation (2).
[0020]
φm (ti) = 2π × x (ti) / λm (2)
The pulse width modulation signal PWSm obtained by the first phase comparison unit 4 is M (= 1,024 = 2) of the carrier frequency f given by the timing signal generation unit 12. ¹⁰ ) Is input to the first gate circuit 5 together with the double clock pulse M × f.
[0021]
Here, the pulse width modulation signal PWSm having the phase amount φm (ti) is a signal whose pulse width changes according to the displacement x, and the pulse width when the maximum phase amount 2π, that is, the maximum displacement amount λm is reached. Is equal to the sampling period T (= 1 / f), the first gate circuit 5 uses the M × f clock frequency to change the phase amount φm (ti) to the resolution R of 1 / M, that is, the displacement x (Ti) can be detected as a pulse train SAPm having a resolution of 1 μm (R = λm / M = 1,024 / 1,024), and the pulse train SAPm converted by the first gate circuit 5 is supplied to the absolute position synthesizer 6. Entered.
[0022]
The absolute encoder 100 includes a second scale 7 formed by recording a scale having a wavelength λa (= 963.8 μm) in parallel with the first scale 1 on a scale member (not shown), and the second scale 7. A second detection head 8 composed of a two-channel MR sensor facing the scale 7 and arranged with a 90 ° phase difference (λa / 4) with respect to the wavelength λa is provided. The second detection head 8 is formed integrally with the first scale detection head 2 and is relatively moved with respect to the second scale 7 by a relative movement period of 2πx / λa and about 90 °. Two systems of sinusoidal signals 2πx / λa having a phase difference (where x is a displacement amount), and two systems of sinusoidal signals Sin (2πx / λa) and Cos (2πx / λa) having a phase difference of 90 ° are output. .
[0023]
The two sine wave signals Sin (2πx / λa) and Cos (2πx / λa) obtained by the second detection head 8 are the second displacement having the same configuration as the first displacement amount detection unit 3. Guided to the quantity detector 9.
[0024]
The second displacement amount detector 9 outputs a phase modulation signal epa whose phase changes by 2π for each displacement amount λa as shown in the following equation (3).
[0025]
epa = Ep2 × Sin (ωt + 2πx / λa) (3)
Where ω = 2πf, x = relative displacement
This phase modulation signal epi is compared in phase with the phase modulation signal epm output from the first displacement amount detection unit 3 in the second phase comparison unit 10 having the same configuration as the first phase comparison unit 4. . The second phase comparison unit 10 is a pulse corresponding to the phase difference between the phase modulation signal epa output from the second displacement amount detection unit 9 and the phase modulation signal epm output from the first displacement amount detection unit 3. The width modulation signal PWS2 is output.
[0026]
As is clear from the above equation (2), the phase difference φa (ti) of the phase modulation signal can be expressed by the following equation (4).
[0027]
φa (ti) = 2π × x (ti) / λa (4)
Therefore, the phase difference Δφ (= φa (ti) −φm (ti) is
Δφ = φa (ti) −φm (ti)
= 2π × x (ti) (1 / λa−1 / λm) (5)
Here, since the wavelength λm of the first scale 1 and the wavelength λa of the second scale 7 are selected to have a relationship of 16λm = 17λa, Δφ (ti) is
Δφ = 2π × x (ti) / 16λm
= 2π × x (ti) / 17λa (5) ′
This is a repetitive signal that coincides when the position reaches 16 times (N = 16) the wavelength λm of the first scale.
[0028]
FIG. 5 shows the relationship between the phase amount φm detected by the first displacement detector 3 and the phase amount φa detected by the second displacement detector 9 in the absolute measurement section.
[0029]
FIG. 6 shows the phase difference Δφ between the phase amount φm detected by the first displacement amount detection unit 3 and the φa and φm with respect to an arbitrary position x within the 16-fold section of the wavelength λm of the first scale. This shows the relationship with (= φa−φm). As shown in FIG. 6, the phase amount φm is 2π for each period of λm, and Δφ is 2π / 16 for each period of λm.
[0030]
Therefore, the phase difference Δφ is divided by a phase amount corresponding to one period of λm (hereinafter referred to as a section phase amount) 2π / 16, and the absolute position of λm unit where x is located, that is, a λm address within 16λm. Aj can be detected.
[0031]
Here, the phase difference Δφ is guided to the second gate circuit 11 having the same configuration as the first gate circuit 5 together with the clock pulse M × f M times the carrier frequency f, and corresponds to the phase difference Δφ. Converted to the pulse train SAPa.
[0032]
Therefore, the section phase amount 2π / 16 is equivalent to the section pulse number M / 16, and by dividing the pulse train SAPa by the section pulse number M / 16, the absolute position of λm unit where x is located as the quotient. That is, the λm address Aj within 16λm can be detected.
[0033]
Table 1 below shows the relationship between Δφ and λm address Aj when the displacement amount x is changed from 0 to 16λm and the number of pulses ΔD corresponding to Δφ when 16λm = 17λa. It is shown.
[0034]
[Table 1]

[0035]
The absolute position synthesizer 6 specifies the λm address Aj using the above relationship, and calculates the absolute position of the 16λm section with a resolution R of 1 μm using the pulse train SAPm with a resolution of 1 μm generated based on the φm. Generate. For example, it can be realized by software processing using a microcomputer (CPU) 63 having a counter function (timer) as shown in FIG.
[0036]
Here, the basic principle concerning the detection of the λm address Aj in the absolute position synthesis unit 6 will be described.
[0037]
The absolute position synthesizer 6 includes a pulse counter 61 that counts the pulse train SAPm with 1 μm resolution output from the first gate circuit 5 and a pulse counter 62 that counts the pulse train SAPa output from the second gate circuit 11. As a trigger signal for fetching the measured values of the pulse counters 61 and 62 into the CPU 63, a reference signal MODS as a set input of the pulse width modulation signals PWSm and PWSa is provided as an interrupt terminal from the timing signal generator 12 to the CPU 63. Have been supplied.
[0038]
When the reference signal MODS corresponding to the reset timing of the phase amount φm (ti) shown in the above equation (2) is input at the sampling time ti, the CPU 63 starts an interrupt operation and the first time measured by the pulse counter 61 is measured. The data Dm (ti) corresponding to the absolute position within the wavelength λm of the scale 1 and the measured value ΔD (ti) of the pulse train SAPm corresponding to the phase difference Δφ of the two phase modulation signals measured by the pulse counter 62 are The data is taken into the CPU 63 and stored in a predetermined memory area in the RAM 64.
[0039]
Next, the CPU 63 stores the difference ΔD of these count values corresponding to the phase difference Δφ in a predetermined area in the RAM 64, and divides the difference pulse number M / 16, and uses the λm address Aj as the quotient. Then, the obtained Aj is multiplied by λm, and the absolute value Dm (ti) in λm at timing ti is added to generate an absolute position with a resolution of 1 μm over the entire 16λm section.
[0040]
The absolute position generated in this way is stored in a predetermined memory area in the RAM 64 and is output to the outside as measurement data, for example.
[0041]
By the way, the operation of the absolute position synthesizer 6 is described in an ideal state. In an actual system, the imperfection of the detected signal, for example, the DC superimposed on each of the detection heads 2 and 8 is used. In some cases, an error may occur in the determination of the λm address Aj due to an influence of an interpolation error caused by an output level imbalance or the like.
[0042]
Therefore, a method for generating a λm address without malfunction which is applied in the present invention will be described.
[0043]
First, the interpolation error that occurs when the phase modulation signal deviates from the ideal state will be described.
[0044]
The phase modulation signals shown in the above equations (1) and (2) are theoretical equations based on the premise that an ideal signal can be obtained from a two-channel detection head.
[0045]
However, in an actual system, a deviation from a complete phase modulation signal as shown in Equations (1) and (2) occurs due to DC and output level imbalance superimposed on each detection head, resulting in interpolation. An error is generated.
[0046]
Here, as a cause of the interpolation error, it is assumed that the DC component is superimposed and the output level is unbalanced as described above, and the balanced modulation signal obtained from the CH1 detection head and the CH2 detection head in the track of wavelength λ is expressed as a general formula. Assuming that e1 and e2 respectively, the balanced modulation signals e1 and e2 are
e1 = {A + (1 + a) × Sin (2πx / λ)} × Cosωt (6)
e2 = {B + (1 + b) × Cos (2πx / λ)} × Sinωt (7)
However,
a: CH1 amplitude deviation, b: CH2 amplitude deviation
A: DC superimposition of CH1, B: DC superimposition of CH2
If 2πx / λ = X and ωt = T, then equations (6) and (7) are
e1 = {A + (1 + a) × SinX} × CosT (6) ′
e2 = {B + (1 + b) × CosX} × SinT (7) ′
It can be expressed as.
[0047]
Here, for simplicity of explanation, if the phase modulation signal when there is a deviation only in DC is assumed to be epm (D), a = b = 0 in the equations (6) ′ and (7) ′. And added, and can be expressed as follows.
[0048]

However,
α = tan ^-1 (A / B)
θ = tan ^-1 {(A + SinX) / (B + CosX)} (9)
Here, {} in the expression (8) represents the envelope of the phase modulation signal epm (D), and the amplitude whose phase is delayed by α from the reference position of X with respect to the reference amplitude 1 is √ (A ² + B ² It can be seen that this is a sinusoidal signal having a first-order component with respect to X, with the ripples of
[0049]
In addition, θ in equation (9) represents the amount of displacement, so the theoretical value when there is no error {θ = tan ^-1 Subtracting from (SinX / CosX)} represents an error when the phase modulation signal deviates from ideal.
[0050]
Now, if an interpolation error within one wavelength ranging from 0 to 2π with respect to X is ΔX, the interpolation error ΔX is
ΔX = tan ^-1 {(A + SinX) / (B + CosX)}
-Tan ^-1 (SinX / CosX) (10)
And where
α = {(A + SinX) / (B + CosX)},
β = SinX / CosX
If you
ΔX = tan ^-1 (Α-β) / (1-α × β)
Therefore,
ΔX = -tan ^-1 {(B * CosX-A * SinX) / (1 + A * SinX + BXCos *)}
It becomes. Then, considering that (A × SinX + B × CosX) is sufficiently smaller than 1, an approximate expression of ΔX is obtained.
ΔX = -tan ^-1 (B x CosX-A x SinX)
= -Tan ^-1 {√ (A ² + B ² ) × Sin (X + γ)} (11)
It becomes. However,
γ = −tan ^-1 (A / B)
It is.
[0051]
Here, for simplicity, the case of A = B is organized.
ΔX = -tan ^-1 {√2 × Sin (X−π / 4)} (12)
It becomes.
[0052]
In other words, the interpolation error ΔX is a signal that changes in a sinusoidal shape having a component of the same period with respect to one period of X, and the magnitude of the signal varies depending on the magnitudes of DC superposition amounts A and B. I understand that.
[0053]
As shown in FIG. 5, the switching unit of the λm address Aj is a position corresponding to an integral multiple of the wavelength λm of the first scale 1. Since it corresponds to a position that is an integral multiple of 1/16, the interpolation error of the wavelength λa of the second scale 7 is superimposed on Δφ detected by the λm address switching unit, resulting in the influence of the interpolation error. In some cases, a reverse phenomenon of the phase difference Δφ may occur.
[0054]
Therefore, based on the relationship shown in Table 1 above, simply finding the quotient for the detected Δφ with respect to the section phase amount φZ (= 2π / 16) may cause a malfunction in the detection of the input m address Aj. become.
[0055]
FIG. 8 is a plot of the interpolation error ΔX expressed by the above equation (11) over the wavelength λa of the second scale 7 over one period of X, that is, the section of x = λa. The interpolation error Ie at each of the positions is superimposed corresponding to the switching position of the λm address Aj. Table 2 below shows the correspondence relationship.
[0056]
[Table 2]

[0057]
Next, the configuration and operation of the actual system applied in the present invention, that is, the absolute position synthesizer 6 that can correctly detect the λm address Aj even when an interpolation error occurs will be described.
[0058]
First, a basic concept for determining the λm address Aj will be described with reference to FIG.
[0059]
(1) The phase difference Δφ detected at the switching unit of λm address Aj, that is, both ends of λm, varies by the phase amount φie (a) corresponding to the interpolation error Ie (a) of the second scale 7. . Therefore, there is a possibility that the λm address Aj that should be detected as j is actually detected before or after that, that is, as j−1 or j + 1.
[0060]
(2) However, with respect to the region having the possibility of erroneous detection, interpolation is further performed in a region on the inner side by the phase amount φie (m) corresponding to the interpolation error Ie (m) in the first scale 1. There is an area where the λm address Aj can be uniquely determined without being affected by the error.
[0061]
(3) Further, also in (1) above, the position within the wavelength λm to which the phase φm detected in the first scale 1 belongs is, for example, the left side (x ≦ λm) with respect to the median value of λm. ) Or the right side (x> λm) is added and a correction based on the determination result corrects the λm address Aj.
[0062]
That is, in the switching unit of the λm address Aj, the determination region of the λm address Aj is provided with hysteresis, and in the hysteresis region, the determination condition based on the position of the first scale 1 is added to thereby influence the interpolation error. Λm address Aj can be detected without malfunction.
[0063]
Next, the setting of hysteresis and other determination conditions to be given to the switching unit of λm address Aj in the present invention will be described by applying specific numerical values.
[0064]
As described above, the phase amount φ is detected as the pulse number ΔD, and the section phase amount φZ (= 2π / 16) corresponds to the section pulse number ND (= 64).
[0065]
Since the wavelengths of the first scale 1 and the second scale 7 are substantially equal, assuming that the interpolation error assumed in the system is substantially equal and the amplitude (PP) is Ie, this corresponds to the interpolation error. The phase amount φie and the pulse number Die can be expressed as follows.
[0066]
φie = 2π × (Ie / λm) (10)
Die = M × Δφi / 2π = 1,024 × (Ie / λm) (11)
That is, in the switching unit of the λm address Aj, the pulse number ΔD may vary by Die / 2.
[0067]
Here, the interpolation error (Ie / λm) with respect to the wavelength λ is usually about 2%, and the Die at that time is about 20 pulses from the equation (11). In the switching unit of the λm address Aj, the second It can be considered that a variation of ± 10 pulses occurs with respect to the number of interval pulses M / 16 (= 64) due to the interpolation error of the scale 7.
[0068]
Furthermore, if the number of pulses Die due to the influence of the interpolation error in the first scale 1 is also 20 pulses, an area within ± 20 pulses with respect to the section pulse number ND (= 64) to which this value is added, that is, In the section where the pulse number ΔD is 20 or more (= 0 + 20) to less than 44 (= 64-20), the area where the λm address Aj can be uniquely determined without being affected by the interpolation error (hereinafter referred to as unconditional determination area). It is.
[0069]
On the outside of the unconditional discrimination region, that is, in the lower region where ΔD is 0 or more and less than 20, and the upper region where ΔD is 44 or more and less than 64, the phase amount φm detected by the first scale 1 is λm In other words, a condition for discriminating the magnitude based on the intermediate value of 512, that is, the 512 pulse (1,024 / 2) position is added, and the λm address Aj temporarily determined according to the determination result may be corrected.
[0070]
Hereinafter, the procedure for determining the λm address Aj in the present invention will be described according to the processing flow shown in FIG.
[0071]
First, in the first step S1, when the reference signal MODS is input at the sampling time ti, the CPU 63 starts an interrupt operation, and the count value Dm (ti) of the first pulse counter 61 and the second pulse counter are counted. The count value ΔD (ti) of 62 is fetched and stored in a predetermined memory area of the RAM 64.
[0072]
In the next step S2, the CPU 63 divides ΔD by the number of section pulses 64, and stores the quotient j as a λm address candidate and the remainder Res as data for λm address determination in a predetermined memory area of the RAM 64.
[0073]
In the next step S3, the CPU 63 classifies into three areas according to the value of the remainder Res, and determines the λm address Aj by the next determination process.
[0074]
That is, when 0 ≦ Res <20 (step S41), it is determined whether or not Dm (ti) exceeds the median value 512 (step S51).
[0075]
If the determination result in step S51 is “Yes”, that is, Dm (ti) ≧ 512, 1 is subtracted from the quotient j calculated in step S2, and this value is set as the λm address Aj (step S61). If the determination result is “No”, that is, Dm (ti) <512, Aj detected in step S2 is directly used as the λm address Aj (step S62).
[0076]
When 20 ≦ Res <44 (step S42), the quotient j detected in step S2 is directly used as the λm address Aj (step S62).
[0077]
Further, when 44 ≦ Res <64 (step S43), it is determined whether or not Dm (ti) is smaller than the median value 512.
[0078]
If the determination result in step S53 is “Yes”, that is, Dm (ti) <512, 1 is added to the quotient j calculated in step S2, and this value is set as the λm address Aj (step S63). If the determination result is “No”, that is, Dm (ti) ≧ 512, Aj detected in step S2 is directly used as the λm address Aj (step S62).
[0079]
In the next step S7, after determining the λm address Aj by the above procedure, the CPU 63 multiplies the λm address Aj by the wavelength λm, and then adds it to the above Dm (ti) to obtain the absolute position X in the 16λm section at time ti. (Ti) is generated.
[0080]
Thereafter, the same procedure (S1 to S7) is repeated for each sampling time, and the absolute position in the 16λm section is obtained. Further, the generated absolute position X (ti) can be used as necessary, for example, as a display or output to an external system as measurement data.
[0081]
The absolute position synthesizer 6 is realized by software processing using a microcomputer (CPU) 63, but may be configured by hardware as shown in FIG.
[0082]
That is, the absolute position synthesizer 6 shown in FIG. 11 includes a first counter 161 that counts a pulse train SAPm with a resolution of 1 μm that is output from the first gate circuit 5 and a pulse train that is output from the second gate circuit 11. A second counter 162 for counting SAPa and a counter control circuit 164 to which the reference signal MODS is supplied from the timing signal generator 12 are provided.
[0083]
When M = 1,024, the first counter 161 is a 1,024-ary (10-bit) counter that counts the pulse train SAPm corresponding to the position within the wavelength λm of the first scale 1, and the count value of the counter The output (Dm (ti)) of the latch circuit is supplied to the first comparator 165 and is output as a lower digit (10 bits) of the combined absolute position.
[0084]
The first comparator 165 is a comparator that compares a predetermined position within the wavelength λm, in this example, a predetermined position within the wavelength λm.
[0085]
In this example, compared to the median (512)
(A1) Dm (ti) <512
(A2) Dm (ti) = 512
(A3) Dm (ti)> 512
Is output to the correction circuit 168.
[0086]
The second counter 162 counts a pulse string SAPa equal to the phase difference between the phase modulation signals output from the first scale 1 and the second scale 7 when M = 1,024. It comprises a counter and a 6-bit latch circuit that latches the count value of the counter, and supplies the carry signal (Ca2) of the above-mentioned hexadecimal counter to the third counter 163, and outputs the output (Res) of the latch circuit to the second And supplied to the third comparators 166 and 167.
[0087]
The third counter 163 is a counter with a latch output function for counting the quotient of SAPa / 64 (hexadecimal when M = 1,024), and the carry signal (Ca2) of the second counter 162 is received. A hexadecimal (4-bit) counter for counting and a 4-bit latch circuit for latching the count value of the counter are provided, and the output of the latch circuit is supplied to one input terminal of the adder circuit 169 as a temporary decision address (j).
[0088]
The counter control circuit 164 initializes (resets) the latch signal for transferring the counter count value to the latch circuit from the MODS signal inputted every sampling period T (= 1 / f) and the counter count value. A reset signal to be generated is generated, and this reset signal is supplied to the first to third counters 161 to 163.
[0089]
The comparator 166 is a comparator for comparing the remainder (Res) with the lower limit value for setting the lower zone, and in this example, compares with the lower limit value (20).
(B1) Res <20
(B2) Res = 20
(B3) Res> 20
Is output to the correction circuit 168.
[0090]
The comparator 167 is a comparator for comparing the remainder (Res) of SAPa / 64 with the upper limit value for setting the upper zone. In this example, the comparator 167 compares the upper limit value (44),
(C1) Res <44
(C2) Res = 44
(C3) Res> 44
Is output to the correction circuit 168.
[0091]
Based on the outputs of the first to third comparators 165 to 167, the correction circuit 168 calculates the correction value (+1, 0, −1) of the temporary decision address (j) that is the output of the third counter 163. The output circuit outputs a correction value according to the following conditions.
[0092]

Here, the zone corresponding to Dm (ti) ≧ 512 is the logical sum (Dm (ti) = 512) (Dm (ti)> 512) of the above (a2) and (a3). The zone corresponding to 0 ≦ Res <20 is the above (b1), that is, (Res <20). Further, the upper zone 44 ≦ Res <64 is a logical sum of (c2) and (c3), that is, (Res = 44) (Res> 44), and the intermediate zone 20 ≦ Res <that can determine the address unconditionally. 44 is a combination with the output of the second comparator 166 ((Res = 20) (Res> 20)) (Res <44).
[0093]
However, in the actual circuit, the correction value corresponding to “−1” is converted into a complement (−1) form and added by the adder circuit 169.
[0094]
The adder circuit 169 is configured by, for example, a 4-bit full adder, and adds the provisional decision address (j) from the third counter 163 and the correction value (+1, 0, −1) that is the output of the correction circuit 168. . The addition circuit 169 outputs j + (− 1) to the complement circuit 170 when the correction value corresponding to “−1”, that is, the complement (−1) is input.
[0095]
The complement circuit 170 receives the correction signal corresponding to “−1” from the adder circuit 169, that is, the addition signal (j + (− 1)) when the complement (−1) is input, It operates when C4) is not output, converts to a true number (j-1), and outputs the upper digit of the decision address (Aj).
[0096]
As described above, as a specific embodiment of the present invention, in order to obtain a desired resolution R = 1 μm, the wavelength λm of the first scale is set to 1,024 times the desired resolution R = 1 μm, and the carrier of the phase modulation signal is obtained. In order to interpolate using a clock pulse of 1,024 (M = 1,024) times the frequency f, and to detect the absolute position of the 16th section (N = 16) of the wavelength λm of the first scale 1, The example in which the numerical value of the binary series of 16 × λm = 17 × λa is set as the relationship between the wavelength λm of the first scale 1 and the wavelength λa of the second scale 7 has been described.
[0097]
Selecting a binary sequence as N not only simplifies the hardware used for interpolation processing, etc., but also software measures in specifying the λm address in the absolute position synthesis unit 6 using a CPU based on binary processing. Has the advantage that it can be realized easily and at high speed.
[0098]
In the description of the above embodiment, N × λm = (N + 1) × λa, but it can be set as N × λm = (N−1) × λa, and N ± 1 = 2. ⁿ Furthermore, in order to obtain a desired resolution R = λm / M, the wavelength λm of the first scale 1 and the design conditions M and N can be arbitrarily set within the scope of the present invention. Of course, it is possible to set design conditions for decimal sequences for M and N instead of binary sequences.
[0099]
In the above embodiment, in the detection of the phase difference Δφ between the phase modulation signal epm obtained from the first displacement amount detection unit 3 and the phase modulation signal epa obtained from the second displacement amount detection unit 9, The phase comparator 10 is configured to detect directly. However, as in the first phase comparison unit 4, the second phase comparison unit 10 also detects the absolute position within the wavelength λa of the second scale 7 by phase comparison between the phase modulation signal epa and the reference signal. The phase difference is detected as φa (ti), and then detected as the pulse number Da (ti) via the second gate circuit 11 and the pulse counter 62, and the absolute position synthesis unit 6 performs the arithmetic processing ΔD = Da (ti Needless to say, it can be detected as -Dm (ti).
[0100]
Furthermore, the present invention is not limited to the magnetic type, and the detection is also performed in a system in which two channels of orthogonal sine wave signals corresponding to the relative movement of the scale and the head are output, for example, as in the optical method. Needless to say, the two-phase sine wave signals are quadrature modulated with the signal of the carrier frequency f and then added to obtain a phase modulation signal.
[0101]
Furthermore, in the present invention, the application to the linear encoder has been described, but the present invention can also be applied to absolute detection of the rotation amount by making the repeated section coincide with the circumferential length.
[0102]
【The invention's effect】
As described above, according to the present invention, the phase modulation signal of the carrier frequency f obtained corresponding to the recording wavelength λm of the first scale is used in the wavelength λm by using the clock pulse having M times the frequency. Data can be read with a resolution R = λm / M. That is, since the position detection system uses the phase modulation signal, the clock pulse frequency M × f is set higher than the carrier frequency f of the phase modulation signal, that is, high resolution can be easily realized simply by increasing M. be able to. Design conditions M and N not only simplify the hardware by selecting a numerical value in the binary series as the wavelength λm of the scale, but also simplify the software processing in the absolute position calculation processing using the CPU. As a result, high-speed processing can be realized.
[0103]
Further, by setting the wavelength λm of the first scale and the wavelength λa of the second scale so as to satisfy the relationship of N × λm = (N ± 1) × λa, for example, It is possible to detect with absolute over the N times section of wavelength λm.
[0104]
In addition, when specifying the λm address in the N-times section of the first scale according to the phase difference between the phase modulation signals output from the first scale and the second scale, it is caused by an interpolation error included in the phase modulation signal. It is possible to prevent malfunction related to the detection of the λm address, and to increase the design value N within the allowable range of the system, and to detect the absolute position in a wide range stably and with high accuracy.
[0105]
In addition, since high-resolution absolute detection is possible, it can be used, for example, in applications where a differential transformer method is frequently used, and effects such as the effect of DC drift and immediate measurement without warm-up can be expected.
[0106]
According to the present invention, the structure of the system is simplified, and an absolute position detection system can be constructed with a small size and low cost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an absolute encoder according to the present invention.
FIG. 2 is a block diagram showing a configuration of a first displacement amount detection unit in the absolute encoder.
FIG. 3 is a block diagram showing a configuration of a first phase comparison unit in the absolute encoder.
FIG. 4 is a diagram for explaining an operation timing of the first phase comparison unit;
FIG. 5 is a diagram illustrating a relationship between a phase amount φm detected by a first displacement amount detection circuit and a phase amount φa detected by a second displacement amount detection circuit in an absolute measurement section.
6 is a diagram showing a relationship between a phase amount φm detected by a first displacement amount detection unit and a phase difference Δφ (= φa−φm) between φa and φm. FIG.
FIG. 7 is a block diagram illustrating a configuration example of an absolute position synthesis unit.
FIG. 8 is a diagram illustrating an example of an interpolation error ΔX of the first scale when the DC bias is multiplied.
FIG. 9 is a diagram for explaining a basic concept relating to determination of a λm address Aj.
FIG. 10 is a flowchart showing a procedure for determining a λm address Aj.
FIG. 11 is a block diagram illustrating a hardware configuration example of the absolute position synthesis unit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1st scale, 2A, 2B MR sensor, 2 1st detection head, 3rd 1st displacement amount detection part, 4th 1st phase comparison part, 5 1st gate circuit, 6 calculating part, 12 timing signal Generator, 7 second scale, 8 second detection head, 9 second displacement detection unit, 10 second phase comparison unit, 11 second gate circuit, 31, 32 multiplier, 33 summing amplifier, 41 waveform shaping circuit, 42, 43 first and second synchronous differentiation circuit, 44 JK flip-flop, 61, 62 pulse counter, 63 CPU, 64 RAM, 100 absolute encoder, 161-163 first to third counters, 164 counter control circuit, 165 to 167 first to third comparators, 168 correction circuit, 169 adder circuit, 170 complement circuit

Claims (3)

A first scale having a scale of wavelength λm, a first detection head for detecting a signal of the first scale, and a relative displacement amount of the first scale and the first detection head as a carrier A first displacement amount detecting means configured to be extracted as a phase modulation signal having a frequency f; a second scale having a scale having a wavelength λa different from that of the first scale; and a signal of the second scale. And a second displacement amount detecting means configured to extract a relative displacement amount between the second detection head for detecting the second scale and the second detection head as a phase modulation signal of the carrier frequency f. And detecting the phase difference between the phase modulation signal obtained from the first displacement amount detection means and the phase modulation signal obtained from the second displacement amount detection means, and using the phase difference, the first scale is detected. Wavelength λm N times wavelength To obtain a periodic signal that repeats, in absolute encoder configured to detect the first scale N times the interval of the wavelength of the absolute,
A pulse corresponding to the absolute position of the first detection head within the wavelength λm of the first scale by comparing the phase of the phase modulation signal of the carrier frequency f obtained from the first displacement amount detection means with the reference signal of the frequency f. First phase comparison means for generating a width modulation signal;
A resolution corresponding to the absolute position of the first detection head within the wavelength λm of the first scale by interpolating a clock pulse M times the carrier frequency f into the pulse width modulation signal generated by the first phase comparison means. A first gate circuit for converting into a pulse train of R = λm / M;
Second phase comparison means for generating a pulse width modulation signal corresponding to the phase difference between the phase modulation signal output from the first displacement amount detection means and the phase modulation signal output from the second displacement amount detection means; ,
A second gate circuit for interpolating a clock pulse M times the carrier frequency f into the pulse width modulation signal generated by the second phase comparison means, and converting it to a pulse train corresponding to the phase difference;
The output of the second gate circuit is counted, the counted value is divided by the number of pulses M / N corresponding to one section of the wavelength λm (hereinafter referred to as the number of section pulses), and the first scale is obtained by the obtained quotient. Address of wavelength λm (hereinafter referred to as λm address) is tentatively determined, and it is determined which of the number of section pulses M / N divided into three zones belongs to, and corresponds to the switching unit of λm address When the data belongs to a zone to be compared, a predetermined position within the wavelength λm of the first scale is compared as a reference, and the λm address temporarily corrected according to the comparison result is corrected to N times the wavelength λm of the first scale. The λm address in the section is specified, and when the remainder belongs to the central zone, the tentatively determined λm address is unconditionally specified as the λm address and is output from the first gate circuit. The Provided that the absolute position of the pulse train by counting the first scale wavelength lambda] m, the absolute position combining means for combining the lambda] m address specified above,
An absolute encoder configured to detect at a resolution R = λm / M over a section N times the wavelength λm of the first scale. The wavelength λm of the first scale and the wavelength λa of the second scale are set to N × λm = (N ± 1) × λa (where n is a positive integer and N = 2 ⁿ or N ± 1 = 2 ⁿ ). The absolute encoder according to claim 1, wherein the absolute encoder is configured to be selected. By selecting the wavelength λm of the first scale as M × R = λm (where m is a positive integer and M = 2 ^m ) with respect to the desired resolution R, M (= 2 ^m ) times the carrier frequency f 2. The absolute encoder according to claim 1, wherein an absolute position within the wavelength λm of the first scale is detected with a resolution R = λm / M using the clock pulse of 1.

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