JP4725130B2 - Distributed shared memory device and memory access method - Google Patents

Description

  The present invention relates to a distributed shared memory device and a memory access method in a system having a plurality of nodes each having one or more processors and a main storage device.

  Conventionally, a system having a plurality of nodes each having one or more processors and a main storage device has been proposed.

  In such a system, the main memory of each node is stacked to form the main memory space of the device, or the main memory space of each node is interleaved to form the main memory space.

  Either one of these two memory access methods is not superior, and the memory access method has to be selected according to the processing executed on the system.

Here, a distributed shared memory device comprising a plurality of nodes having one or more processors and a main storage device, and having a inter-node interleave control unit, which performs interleaving between the main storage devices of each node In this distributed shared memory device, a power-of-two node having the same main storage capacity is grouped, the address ranges of these groups are stacked to form a main storage space, and an inter-node interleave control unit In a system composed of a plurality of nodes having one or more processors and a main memory device, a predetermined register is provided in the system and a unit of interleaving between nodes can be selected from a plurality of candidates. Even when the processor accesses the same address range, it accesses the main memory of multiple nodes. Technology which makes it possible to distribute the scan has been proposed (e.g., see Patent Document 1).
JP 2003-21689A

  However, the conventional example described above has the following problems.

  Determining which method is appropriate for a given process requires specialized knowledge of software and hardware, and in some cases, detailed information about the software may not be disclosed. It was very difficult to make this judgment.

  Further, since the memory access method is fixed, the user has to develop software in accordance with the memory access method.

  Furthermore, even if the memory access method can be changed, it is difficult to determine which method is suitable.

  Therefore, an object of the present invention is to provide a distributed shared memory device and a memory access method that can automatically select an optimal memory access method without being conscious of the user side.

According to the first aspect of the present invention, in the distributed shared memory device, the memory access latency is calculated by measuring the time required for memory access, and the memory access occurrence source and destination are checked to determine the local memory latency. A latency measuring unit comprising: a means for separately calculating a remote memory latency and a means for predicting a latency at the time of interleaving; a means for measuring and recording the number of memory access requests via the system controller; and a memory An access frequency measurement unit comprising means for separately calculating a local memory access frequency and a remote memory access frequency by checking an access source and a destination, and a main memory address range of each node is stacked and stacked. a stack configuration is a configuration that forms a storage space, each node And means for switching a is inter-node interleaving arrangement configured to form the main storage space performs interleaving between de main storage, based on the data latency measurement unit and the access frequency measurement unit, the average latency time of the stack structure A distributed shared memory device comprising: a system control device comprising: means for calculating a predicted average latency in an interleave configuration.

  The invention according to claim 2 is suitable for the processing executed on the system in the distributed shared memory device according to claim 1 by comparing the average latency in the stack configuration and the predicted average latency in the interleave configuration. The apparatus further includes means for determining a memory access method.

  The invention according to claim 3 is the distributed shared memory device according to claim 2, further comprising means for automatically changing the memory access system based on the determination of the means for determining the memory access system.

The invention according to claim 4 is a memory access method in a distributed shared memory device, wherein the latency measuring unit measures the time required for the memory access to calculate the memory access latency, and the occurrence of the memory access A step of separately calculating the local memory latency and the remote memory latency by checking the source and destination, and a step of predicting the latency at the time of interleaving, and the access frequency measurement unit passes through the system controller A system control device comprising: a step of measuring and recording the number of memory access requests; and a step of separately calculating a local memory access frequency and a remote memory access frequency by checking a memory access generation source and a destination but, address Ren of the main memory of each node A step of switching the inter-node interleaving arrangement is configured to form a main memory space subjected to interleaving between main storage of the stack configuration and each node is configured to form a main memory space stacked, latency measurement unit and the access A memory access method comprising: calculating an average latency in a stack configuration and a predicted average latency in an interleave configuration based on data of a frequency measurement unit.

  According to a fifth aspect of the present invention, in the memory access method according to the fourth aspect, the memory suitable for processing executed on the system is compared by comparing the average latency in the stack configuration and the predicted average latency in the interleave configuration. The method further includes a step of determining an access method.

The invention described in claim 6 is the memory access method according to claim 5, further comprising a step of automatically changing the memory access system based on the determination of the step of determining the memory access system.

  According to the distributed shared memory device and the memory access method of the present invention, the optimum memory access method can be automatically selected without being conscious of the user side.

  Next, an embodiment of the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 1, a distributed shared memory device according to the present embodiment is shown.

  In FIG. 1, this distributed shared memory device is composed of eight nodes 101-108.

  The internal configuration of the node will be described below using the node 101.

  The system control device 116 is connected to the system bus 109 to communicate with other nodes.

  One or a plurality of processors are mounted in the node. In this configuration example, four processors 111 to 114 are mounted.

  These processors are connected to the system controller 116 via a processor bus 115. A main storage device 117 is mounted on the node and is connected to the system control device 116.

  The system controller 116 includes an inter-node interleave control unit 121 used when an interleaving method is used as a memory access method, and a latency measurement unit 122 that records the time taken from issuing a memory access request to receiving data. In addition, an access frequency measurement unit 123 that records the number of accesses to the main storage device 117 of the own node and the number of accesses to the main storage device of another node is mounted.

  Next, the operation of the system controller 116 in FIG. 1 will be described with reference to the flowchart shown in FIG.

  In FIG. 1, the inter-node interleave control unit 121 is present in the system control device 116. However, in the initial setting, the setting of this control unit is off, and the main storage space is assumed to have a stack configuration.

  First, when a memory access request is generated from the processors 111 to 114 (step S1), the request reaches the system control device 116 via the processor bus 115.

  Here, the system controller 116 is the main storage device 117 of the local node (hereinafter referred to as “local”) or the main storage device of another node (hereinafter referred to as “remote”). It is determined whether or not there is (step S2).

  If the destination is the local main storage device 117, data is requested from the local main storage device 116 (step S3).

  At the same time as the data request is made, the local counter of the latency measuring unit 122 is started (step S4).

  Thereafter, when the data in the local main storage device 117 arrives at the system control device 116 as a response to the data request (step S5), the local counter of the latency measurement unit 122 started first is stopped (step S6).

  As a result, the counter has advanced by the time (latency) required for the current memory access. Further, the local counter of the access frequency measurement unit 123 is incremented by 1 to record the number of memory accesses (step S7).

  The same procedure is followed when the destination of the memory access request is remote (steps S3a to S7a).

  The above procedure is repeated, and when it is considered that a sufficient time has passed to judge the characteristics of the processing being executed on the system (step S8), the latency is calculated and compared. The local latency can be calculated by dividing the numerical value of the local counter of the latency measuring unit 122 by the numerical value of the local counter of the access frequency measuring unit 123 (step S9).

  Similarly, the remote latency is calculated (step S10).

  Furthermore, the average latency is calculated by dividing the total of the local and remote counter values of the latency measurement unit of all nodes by the total of the local and remote counter values of the access frequency measurement unit of all nodes. It can be obtained (step S11).

  Although latency is obtained in this way, depending on the characteristics of the processing executed on the system, memory access may be concentrated on a specific node when the main storage space is configured as a stack. In this case, access concentrates on a specific circuit and processing is delayed, so that memory access latency increases and processing performance deteriorates. On the other hand, when the main storage space is configured in an interleaved manner, memory access is distributed to all nodes, so there is no concentration of access as in the stack configuration, and the latency is independent of the characteristics of the processing being executed in the system. It becomes constant, and the numerical value can be predicted in advance. The interleave configuration latency thus predicted in advance is compared with the above-described calculated stack configuration average latency (step S12), and superiority or inferiority is determined (step S13).

  As a result, when it can be estimated that the interleaved configuration can reduce the latency and improve the processing performance, the interleaved configuration is changed to the interleaved configuration using the inter-node interleave control unit in each node (step S14).

  According to the above embodiment, since a suitable memory access method is determined on the system side, it is not necessary to optimize for the distributed shared memory method on the software side.

  In addition, since the comparison is made quantitatively based on the latency, the accuracy of determining the appropriateness of the memory access method is high.

  In addition, since various types of latency data are collected, it can be used to optimize the software for the distributed shared memory system.

  Each of the above-described embodiments is a preferred embodiment of the present invention, and various modifications can be made without departing from the scope of the present invention. For example, processing for realizing the functions of the present system may be performed by causing each unit or the like to read and execute a program for realizing the functions of the system control device 116 in the above embodiment. Further, the program is transmitted to another computer system by a transmission wave via a CD-ROM or a magneto-optical disk that is a computer-readable recording medium, or via the Internet or a telephone line that is a transmission medium. Also good.

1 is a schematic configuration diagram of a distributed shared memory device according to an embodiment of the present invention. It is a flowchart which shows the processing operation of the system control apparatus in embodiment of this invention.

Explanation of symbols

101-108 node 116 system control device 109 system bus 111-114 processor 115 processor bus 116 system control device 117 main storage device 121 interleave control unit between nodes 122 latency measurement unit 123 access frequency measurement unit

Claims (6)

In a distributed shared memory device,
Means for calculating memory access latency by measuring the time required for memory access;
Means for separately calculating the local memory latency and the remote memory latency by checking the source and destination of the memory access;
Means for predicting latency at the time of interleaving, and a latency measuring unit comprising:
Means for measuring and recording the number of memory access requests via the system controller;
Means for separately calculating the local memory access frequency and the remote memory access frequency by checking the source and destination of the memory access, and an access frequency measuring unit comprising:
Stack configuration that forms the main storage space by stacking the address ranges of the main storage of each node, and inter-node interleave configuration that forms the main storage space by interleaving between the main storage devices of each node Means for switching;
A system controller comprising: means for calculating an average latency in a stack configuration and a predicted average latency in an interleave configuration based on data of the latency measurement unit and the access frequency measurement unit; Distributed shared memory device.   2. The apparatus according to claim 1, further comprising means for determining a memory access method suitable for processing executed on the system by comparing the average latency in the stack configuration and the predicted average latency in the interleave configuration. Distributed shared memory device.   3. The distributed shared memory device according to claim 2, further comprising means for automatically changing the memory access system based on the determination of the means for determining the memory access system. A memory access method in a distributed shared memory device, comprising:
A step of calculating a memory access latency by measuring a time required for the memory access by the latency measuring unit; and
Calculating local memory latency and remote memory latency separately by checking the source and destination of memory access; and
Predicting latency during interleaving configuration, and
An access frequency measurement unit measuring and recording the number of memory access requests via the system control device;
Calculating the local memory access frequency and the remote memory access frequency separately by checking the source and destination of the memory access, and
A node in which the system controller stacks the main memory address range of each node to form a main memory space, and a node that interleaves between the main memory devices of each node to form a main memory space Switching between interleave configurations,
A memory access method comprising: calculating an average latency in a stack configuration and a predicted average latency in an interleave configuration based on data of the latency measurement unit and the access frequency measurement unit.   5. The method according to claim 4, further comprising a step of determining a memory access method suitable for processing executed on the system by comparing an average latency in a stack configuration and a predicted average latency in an interleave configuration. Memory access method. 6. The memory access method according to claim 5, further comprising a step of automatically changing the memory access system based on the determination of the step of determining the memory access system.

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