JP4721295B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device that reduces power consumption in a standby mode.

  25A to 25C show a conventional semiconductor integrated circuit device that reduces power consumption in the standby mode.

  In the semiconductor integrated circuit device 10X of FIG. 25A (see Non-Patent Document 1), the PMOS transistor 12 is connected between the power supply line of the potential VDD and the circuit block 11, and the gate of the PMOS transistor 12 is standbyd from the outside. A signal STBY is supplied. In the case where the circuit block 11 is a CMOS circuit, no current flows ideally when the clock signal CLK is turned off during standby, but the threshold voltage of the transistor is set low in order to increase the operation speed. A leak current flows through the block 11. In order to prevent this leakage current, the standby signal STBY is activated and the PMOS transistor 12 is turned off during standby.

  When the circuit block 11 includes a circuit that needs to retain stored contents even during standby, such as a memory, as shown in FIG. 25B, the power supply potential VDD is set lower than during normal operation during standby. In this case, the clock signal CLK is turned off or its frequency is lowered.

When the standby signal STBY is not supplied in order to reduce the number of external terminals, the switch element 13 is connected to an external power supply line of the semiconductor integrated circuit device 10Z as shown in FIG. Is turned off.
IEEE ISSCC 96 PAPER FA 10.4 Figure. 2

  However, in general, the circuit block 11 includes a circuit capable of turning off the power supply during standby, and thus wasteful power is consumed in the case of FIG. In the case of FIG. 25C, a circuit that maintains the state during standby cannot be incorporated in the circuit block 11.

  In view of such problems, the object of the present invention is to provide an operation mode having the same configuration without externally supplying a mode signal indicating whether or not it is in a standby state and irrespective of the value of the power supply potential in the standby state. An object of the present invention is to provide a semiconductor integrated circuit device capable of reducing power consumption using a detection circuit.

  Another object of the present invention is to supply power only to a circuit that needs to maintain or operate a state at the time of standby without supplying a mode signal indicating whether or not the device is in a standby state. An object of the present invention is to provide a semiconductor integrated circuit device capable of further reducing power consumption.

In one embodiment of the present invention, a power supply line;
A switch circuit connected to the power supply line;
A first circuit block connected to the power supply line via the switch circuit;
The amount of change of the potential of the power supply line in a predetermined period is detected, and if the amount of change is less than a negative predetermined value, the switch circuit is turned off, and if the amount of change exceeds a positive predetermined value, the switch circuit And an operation mode detection circuit for turning on.

  According to this configuration, there is no need to supply an operation mode signal indicating a standby state to the semiconductor integrated circuit device, so that the number of external terminals is reduced.

  Furthermore, since the amount of change in the power supply potential in a predetermined period is detected and compared with a predetermined value of positive and negative, it is determined whether or not the standby state has been entered. Regardless, an operation mode detection circuit having the same configuration can be used.

  In another aspect of the present invention, the semiconductor device further includes a second circuit block connected to the power supply line.

  According to this configuration, since the power supply potential of the second circuit block is lowered during standby and unnecessary power supply to the first circuit block is stopped, the internal storage state of the second circuit block is maintained or The necessary operation can be ensured and the power consumption of the semiconductor integrated circuit device can be reduced.

  Other objects, configurations and effects of the present invention will become apparent from the following description.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic block diagram showing a semiconductor integrated circuit device 10 according to a first embodiment of the present invention.

  This circuit includes a circuit block 11A that needs to maintain or operate a state during standby, and a circuit block 11B that can be turned off during standby. For example, the circuit block 11A is a sequential circuit or a key scan circuit, and the circuit block 11B is a combinational circuit. A power supply line of potential VDD is directly connected to the circuit block 11A, and this power supply line is connected to the circuit block 11B via the switch circuit 13.

  When the signal indicating the operation mode is not supplied from the outside to the semiconductor integrated circuit device 10 and the clock signal CLK supplied from the outside is turned off by the clock on / off detection circuit 20 as the operation mode detection circuit, the standby mode is set. It is determined that The clock on / off detection circuit 20 supplies this determination result to the control input terminal of the switch circuit 13 as an enable signal ENBL, and controls the switch circuit 13 on / off.

  FIG. 2 is a flowchart showing the control operation of the clock on / off detection circuit 20 for the switch circuit 13 of FIG.

  When the clock signal CLK transitions from on to off (S1), the enable signal ENBL is deactivated to turn off the switch circuit 13, thereby stopping the power supply to the circuit block 11B (S2). When the clock signal CLK transitions from off to on (S3), the enable signal ENBL is activated to turn on the switch circuit 13, thereby supplying power to the circuit block 11B (S4). When the clock signal CLK is kept on or off, the enable signal ENBL is not changed and the state of the switch circuit 13 is maintained (S5).

  FIG. 3 is a circuit diagram showing a more detailed configuration of the semiconductor integrated circuit device 10.

  In the clock on / off detection circuit 20, the clock signal CLK is supplied to one end of the current path of the transfer gate 21, and the other end of this current path is connected to the output end of the clock on / off detection circuit 20 via the inverters 22 and 23. Has been. The input end and the output end of the inverter 22 are connected to the output end and the input end of the tri-state inverter 24, respectively, and the inverters 22 and 24 constitute a flip-flop 25. Each of the transfer gate 21 and the inverter 24 includes a control input terminal to which a pair of complementary signals are supplied, and a clock signal CLKD and a signal obtained by inverting the CLKD by the inverter 26 are supplied thereto. The clock signal CLKD is generated by the chopping / delay circuit 30 based on the clock signal CLK.

  FIG. 4A is a logic circuit diagram showing a configuration example of the chopping / delay circuit 30. FIG. 4B is a time chart showing the operation of this circuit 30.

  In the chopping / delay circuit 30, the clock signal CLK is supplied to one input terminal of the AND gate 31, and the clock signal * CLK1 obtained by delaying the clock signal CLK by the inverting delay circuit 32 by the time td1 is supplied to the other input terminal. Is done. The delay time td1 is shorter than the pulse width PW of the clock signal CLK. The inverting delay circuit 32 includes an odd number of inverters connected in cascade.

  When the clock signal CLK transitions from the low level to the high level, the clock signal * CLK1 is delayed by the time td1 and transitions from the high level to the low level. As a result, the output CLK2 of the AND gate 31 becomes a rising detection pulse of the clock signal CLK, and its pulse width is equal to the delay time td1 of the inverting delay circuit 32.

  The clock signal CLK2 becomes the clock signal CLKD through the delay circuit 33 in which an even number of inverters are cascade-connected. The delay time td2 of the delay circuit 33 is determined so as to be longer by Δt than one cycle T of the clock signal CLK and satisfy Δt + td1 <PW.

  FIG. 5 is a time chart showing the operation of the circuit of FIG.

  While the clock signal CLKD is at a high level, the transfer gate 21 is on, the output of the inverter 24 is in a high impedance state, the flip-flop 25 functions as a simple inverter, and the enable signal ENBL has the same logic as the clock signal CLK. .

  When the clock signal CLKD transitions to a low level, the transfer gate 21 is turned off, the inverter 24 operates normally, and the flip-flop 25 functions to hold the state of the clock signal CLK immediately before that. Thus, the enable signal ENBL becomes a signal that maintains the level of the clock signal CLK at the time of falling of the clock signal CLKD until the next rising of the clock signal CLKD.

  Therefore, when the clock signal CLK is turned off, the enable signal ENBL transits to a low level at the rising edge of the clock signal CLKD, and the clock signal CLKD rises after the time T + Δt has elapsed after the clock signal CLK is turned on to be at a high level. Transition to.

  The power supply potential VDD is supplied to one input terminal of the AND gate 13A as the switch circuit, and the enable signal ENBL is supplied to the other input terminal as the control input terminal. When the enable signal ENBL is at a low level, that is, when the clock signal CLK is off, the output VDDm of the AND gate 13A becomes 0 V, and the power supply to the circuit block 11B is stopped. When the enable signal ENBL becomes high level, the power supply potential VDDm becomes equal to VDD, and the power supply voltage is supplied to the circuit block 11B.

  According to the semiconductor integrated circuit device 10 of the first embodiment, since it is not necessary to supply an operation mode signal indicating a standby state to the semiconductor integrated circuit device 10, the number of external terminals is reduced, and only the circuit block 11B is in a standby state. Since the power supply is stopped, the internal storage state of the circuit block 11A can be maintained or a necessary operation can be ensured, and the power consumption of the semiconductor integrated circuit device 10 can be reduced.

  FIG. 6 is a schematic circuit diagram showing a semiconductor integrated circuit device 10A according to the second embodiment of the present invention.

  Since no power supply voltage is supplied to the circuit block 11B during standby, the output signal is invalid. However, when the circuit block 11B is turned off, the output of the circuit block 11B is in a floating state. When the output of the circuit block 11B is supplied to another operating CMOS circuit, and its input gradually decreases in the vicinity of the threshold potential, a relatively large leak current continues to flow.

  Therefore, a signal to be output from the circuit block 11B to the external terminal of the semiconductor integrated circuit device 10A is supplied to one input terminal of an AND gate 40 as a mask circuit, and an enable signal ENBL is supplied to the other input terminal. The output OUT of the gate 40 is supplied to the external terminal. The other configuration of the semiconductor integrated circuit device 10A is the same as that of FIG.

  FIG. 7 is a time chart showing the operation of the circuit of FIG.

  When the clock signal CLK is turned off, the power supply potential VDDm transits to 0V, and the output of the circuit block 11B enters a floating state. However, since the enable signal ENBL is at a low level, the output of the AND gate 40 is fixed at a low level, thereby preventing the occurrence of a leak current as described above.

  In the circuit of FIG. 3, when the standby state is entered when the clock signal CLK is at a high level, the enable signal ENBL is maintained at a high level, so the power supply potential VDDm cannot be set to 0V.

  FIG. 8 is a schematic block diagram showing a semiconductor integrated circuit device 10B according to the third embodiment of the present invention that solves this problem.

  In the clock on / off detection circuit 20A, the clock signal CLK is supplied to the input terminal of the transfer gate 21 through the chopping circuit 34 as the clock signal CLKC.

  FIG. 9A shows a configuration example of the chopping circuit 34. FIG. 9B is a time chart illustrating the operation of the circuit in FIG.

  The chopping circuit 34 includes a delay circuit 35 in which an odd number of inverters are cascade-connected to generate a signal * CLK3 obtained by delay-inverting the clock signal CLK, and an AND gate 36 to which the clock signals CLK and * CLK3 are supplied. The clock signal CLKC is taken out from the output terminal of the AND gate 36. The clock signal CLKC has the same rising edge as that of the clock signal CLK, and the pulse width is equal to the delay time td3 of the delay circuit 35.

  FIG. 10 is a time chart showing the operation of the circuit of FIG.

  According to the third embodiment, as shown in FIG. 10, when the clock signal CLK is stopped and enters a standby state, even if CLK is stopped at a high level, the pulse width of the clock signal CLKC is Since it becomes equal to the delay time td3, the clock signal CLKC becomes low level in the standby state. As a result, the enable signal ENBL is maintained at a low level, and power supply to the circuit block 11B is stopped.

  FIG. 11 is a schematic block diagram showing a semiconductor integrated circuit device 10C according to the third embodiment of the present invention.

  This semiconductor integrated circuit device 10C adds an AND gate 40 to the semiconductor integrated circuit device 10B of FIG. 8 as in the second embodiment, and fixes the output of the AND gate 40 at a low level during standby. Leakage current is prevented.

  FIG. 12 is a time chart showing the operation of the circuit of FIG.

  FIG. 13 is a schematic block diagram showing a semiconductor integrated circuit device 10D according to the fifth embodiment of the present invention.

  In this device, similarly to the semiconductor integrated circuit device 10 of FIG. 1, an operation mode signal indicating a standby state is not supplied from the outside to the semiconductor integrated circuit device 10D. The difference from the semiconductor integrated circuit device 10 is that the power supply potential VDD becomes a potential VDDL lower than the normal potential VDDN in the standby state, and the clock signal CLK operates in the standby state. The frequency of the clock signal CLK in the standby state is the same as or lower than that in the normal state. The power supply potential VDDL is a potential sufficient for the circuit block 11 to maintain its storage state or to operate as necessary during standby.

  The power supply potential VDD and the clock signal CLK are supplied to the VDD change detection circuit 20B as the operation mode detection circuit.

  FIG. 14 is a flowchart showing a control operation of the VDD change detection circuit 20B for the switch circuit 13 of FIG.

  The VDD change detection circuit 20B periodically detects the amount of change in the power supply potential VDD and performs the following operation. That is, assuming that ΔV is a positive constant value, if the amount of change becomes smaller than −ΔV (S11), the enable signal ENBL is deactivated and the switch circuit 13 is turned off (S12), and the amount of change is larger than ΔV. If this is the case (S13), the enable signal ENBL is activated and the switch circuit 13 is turned on (S14). If none of these is true, the enable signal ENBL does not change and the state of the switch circuit 13 is maintained (S15).

  FIG. 15 is a circuit diagram showing a more detailed configuration of the semiconductor integrated circuit device 10D.

  The VDD change detection circuit 20B includes a sample and hold circuit 50 that periodically samples and holds the power supply potential VDD. The sample hold circuit 50 includes a transfer gate 51 having one end of the current path connected to the power supply potential VDD, and a capacitor 52 connected between the other end of the current path of the transfer gate 51 and the ground potential. The control input terminal of the transfer gate 51 is supplied with the clock signal CLKB. While the clock signal CLKB is at a high level, the transfer gate 51 is turned on and the power supply potential VDD is sampled by the capacitor 52, and the clock signal CLKB is at a low level. The power supply potential VDD at the time of transition is held in the capacitor 52 as the reference potential Vref.

  The reference potential Vref is supplied to the inverting input terminal of the comparator 53 and the non-inverting input terminal of the comparator 54. The level shift circuit 55 supplies a potential obtained by reducing the power supply potential VDD by ΔV to the non-inverting input terminal of the comparator 53, and the level shift circuit 56 provides a potential obtained by increasing the power supply potential VDD by ΔV by the inverting input of the comparator 54. Supply to the end. A clock signal CLKA is supplied to the control input terminals of the comparators 53 and 54 as an output enable signal. Both the comparators 53 and 54 output a comparison result when the clock signal CLKA is at a high level, and output a low level when the clock signal CLKA is at a low level.

  The clock signal CLKA is a signal obtained by dividing the clock signal CLK by N by the N divider 57, and the clock signal CLKB is a signal obtained by delaying the clock signal CLKA by the buffer gate 58.

  The outputs Vdn and Vup of the comparators 53 and 54 are supplied to the reset input terminal R and the set input terminal S of the RS flip-flop 59, respectively. The output Q of the RS flip-flop 59 is supplied to one input terminal of the AND gate 13A as the enable signal ENBL.

  FIG. 16 is a time chart showing the operation of the semiconductor integrated circuit device 10D of FIG.

  The power supply potential VDD is sampled by the pulse of the clock signal CLKB, and the power supply potential VDD at the time of falling of the clock signal CLKB is held in the capacitor 52 as the reference potential Vref. Next, the comparison result of the comparators 53 and 54 becomes valid by the pulse of the clock signal CLKA.

  If the absolute value of the change amount of the power supply potential VDD in the period from the falling edge of the clock signal CLKB to the next clock signal CLKA is smaller than ΔV, the outputs Vdn and Vup of the comparators 53 and 54 are at a low level. The output of the RS flip-flop 59 does not change. When the amount of decrease of the power supply potential VDD during this period exceeds ΔV, the output Vdn of the comparator 53 becomes high level, the RS flip-flop 59 is reset, the enable signal ENBL becomes low level, and the output VDDm of the AND gate 13A. Becomes 0V. When the increase amount of the power supply potential VDD during this period exceeds ΔV, the output Vup of the comparator 53 becomes high level, the RS flip-flop 59 is set, the enable signal ENBL becomes high level, and the output VDDm of the AND gate 13A. Becomes equal to the power supply potential VDD.

  According to the semiconductor integrated circuit device 10D of the fifth embodiment, since there is no need to supply an operation mode signal indicating a standby state to the semiconductor integrated circuit device 10D, the number of external terminals is reduced, and the circuit block 11A of the circuit block 11A is in a standby state. Since the power supply potential is lowered and unnecessary power supply to the circuit block 11B is stopped, the internal storage state of the circuit block 11A is maintained or a necessary operation is ensured, and the power consumption of the semiconductor integrated circuit device 10D is reduced. can do.

  Further, since it is determined whether or not the standby state has been entered by periodically detecting the amount of change in the power supply potential VDD and comparing it with a reference value, the same regardless of the value of the power supply potential VDDL in the standby state. The VDD change detection circuit 20B having the configuration can be used.

  FIG. 17 is a schematic circuit diagram showing a semiconductor integrated circuit device 10E according to the sixth embodiment of the present invention.

  In this device 10E, the leakage current is reduced by adding an AND gate 40 to the semiconductor integrated circuit device 10D of FIG. 15 and fixing the output of the AND gate 40 to a low level during standby, as in the second embodiment. It is preventing.

  In the circuit of FIG. 15, the power supply potential VDD fluctuates due to power supply noise or the like while the power supply potential VDD is maintained at the normal potential VDDN or the low potential VDDL, and this fluctuation amount exceeds a predetermined value in one cycle of the clock signal CLKA. Then, the RS flip-flop 59 is reset or set, and a malfunction occurs in which the power supply to the circuit block 11B is stopped in the normal state or the power supply to the circuit block 11B is started in the standby state.

  FIG. 18 is a schematic circuit diagram showing a semiconductor integrated circuit device 10F according to the seventh embodiment of the present invention that solves this problem.

  In the VDD change detection circuit 20C, an M cycle matching circuit 60 is connected between the output terminal of the comparator 53A and the reset input terminal R of the RS flip-flop 59, and the output terminal of the comparator 54A and the set input terminal S of the RS flip-flop 59. A K cycle matching circuit 61 is connected between the two. A clock signal CLKA is supplied to the M cycle matching circuit 60 and the K cycle matching circuit 61.

  The comparator 53A is the same as the comparator 53 in that it outputs a comparison result while the clock signal CLKA is at a high level, but holds and outputs this comparison result while the clock signal CLKA is at a low level next time. This is different from the comparator 53 in that respect. Similarly to the comparator 53A, the comparator 54A has a comparison result holding function.

  FIG. 19 shows a configuration example of the M cycle matching circuit 60.

  The M period coincidence circuit 60 includes a shift register and an AND gate 65. In the shift register, buffer gates 66 are provided at the data input terminals of (M−1) D flip-flops 62, 63,. , 67,..., 68 are connected in cascade, and the signal CLKA is supplied to the clock input terminals of the D flip-flops 62, 63,. All bit outputs Vdn1, Vdn2,..., Vdn (M−1) of the shift register and the input Vdn0 of the shift register are supplied to the input terminal of the AND gate 65.

  FIG. 20 is a time chart showing the operation of the circuit of FIG. 19 when the power supply potential VDD drops.

  When the input Vdn0 of the M period matching circuit 60 is maintained at a high level over the M periods of the clock signal CLKA, the output Vdn of the AND gate 65 becomes a high level, and the RS flip-flop 59 in FIG. 18 is reset. When the input Vup0 of the K cycle matching circuit 61 is maintained at a high level over the K cycle of the clock signal CLKA, the output Vup of the AND gate 65 becomes a high level, and the RS flip-flop 59 of FIG. 18 is set.

  The values of M and K are determined so as not to cause the above-described malfunction according to the period of the clock signal CLKA and the level of power supply noise, and may be M = K.

Table 1 below shows the logical operations of the M cycle matching circuit 60, the K cycle matching circuit 61, and the RS flip-flop 59 when M = 4 and K = 3.

  In Table 1, “1” indicates a high level and “0” indicates a low level. In Table 1, the state of the power supply potential VDD with respect to the cycle of the clock signal CLKA changes as follows.

1 to 4 cycles: normal potential VDDN maintenance 5 to 10 cycles: potential drop 11 to 14 cycles: low potential VDDL maintenance 15 to 20 cycles: potential rise 21 cycles to: normal potential VDDN maintenance Signal Vdn is all signals VdnO to Vdn3 The signal Vup becomes a high level in 8 to 10 cycles that become a high level, and the signal Vup becomes a high level in 17 to 20 cycles in which all the signals VupO to Vup2 become a high level. These signals Vdn and Vup are respectively supplied to the reset input terminal R and the set input terminal S of the RS flip-flop 59, the enable signal ENBL becomes low level in 8 to 16 cycles, and the power supply to the circuit block 11B is stopped. The

  FIG. 21 is a schematic circuit diagram showing a semiconductor integrated circuit device 10G according to the eighth embodiment of the present invention.

  In this device semiconductor integrated circuit device 10G, by adding an AND gate 40 to the semiconductor integrated circuit device 10F of FIG. 18 in the same manner as in the second embodiment, and fixing the output of the AND gate 40 to a low level during standby, The leakage current is prevented.

  In the circuit of FIG. 18, malfunction of on / off control of the power supply voltage VDDm can be prevented in a period in which the power supply potential VDD is maintained at the normal potential VDDN or the low potential VDDL. However, during the fall from the normal potential VDDN to the low potential VDDL or the rise from the low potential VDDL to the normal potential VDDN, the signal Vdn0 or Vup0 is an error value even for one cycle in the M cycle or K cycle, respectively, due to power supply noise or the like. Then, the on / off control of the power supply voltage VDDm malfunctions.

  FIG. 22 is a schematic circuit diagram showing a semiconductor integrated circuit device 10H according to the ninth embodiment of the present invention that solves this problem.

  The VDD change detection circuit 20D includes a (M−m) period matching circuit 70 and a (K−k) period matching circuit 71 instead of the M period matching circuit 60 and the K period matching circuit 61 in FIG. The (M−m) period coincidence circuit 70 sets the output Vdn to a high level when the input VdnO is at a high level in (M−m) periods or more during the M periods of the clock signal CLKA. Therefore, the RS flip-flop 59 is not erroneously set even if the signal VdnO becomes low level in the M period or less during the M period of the clock signal CLKA due to power supply noise or the like. Similarly, the (K−k) period coincidence circuit 71 sets the output Vup to a high level when the input VupO is at a high level in (M−k) periods or more during the M periods of the clock signal CLKA.

  FIG. 23 shows a configuration example of the (M−m) period matching circuit 70.

  The (M−m) period matching circuit 70 includes a shift register and a “1” number comparison circuit 75, in which (M−m) D flip-flops 72, 73,. Inverters 76, 77,..., 78 are connected to the data input terminals, respectively, and are connected in cascade, and the signal CLKA is supplied to the clock input terminals of the D flip-flops 72, 73,. All input bits Vdn1, Vdn2,..., Vd (M−1) of the shift register and the input Vdn0 of the shift register are supplied to the input terminal of the “1” number comparison circuit 75.

  The '1' number comparison circuit 75 sets the output Vdn to a high level when (M−k) or more of M inputs are at a high level, and sets the output Vdn to a low level in other cases.

Table 2 below shows the truth values of the “1” number comparison circuit 75 when M = 4 and m = 1.

  The '1' number comparison circuit 75 can be configured based on such a truth table. The values of M, m, K, and k (M> m, K> k) are determined so as not to cause the malfunction according to the period of the clock signal CLKA and the level of power supply noise, and M = K. Also good.

The following Table 3 shows the logic of the (M−m) period coincidence circuit 70, the (K−k) period coincidence circuit 71, and the RS flip-flop 59 when M = 4, m = 1, K = 3, and k = 1. The operation is shown.

  In Table 3, the state of the power supply potential VDD with respect to the cycle of the clock signal CLKA changes as follows.

1 to 4 cycles: normal potential VDDN maintenance 5 to 10 cycles: potential drop 11 to 14 cycles: low potential VDDL maintenance 15 to 20 cycles: potential rise 21 cycles to: normal potential VDDN maintenance Furthermore, power supply noise is mixed to supply power potential VDD fluctuates and the following malfunction occurs.

  In the second cycle, the signal VdnO becomes an error value (high level) due to negative power supply noise, and in the third cycle, the signal VupO becomes an error value (high level) due to potential recovery. In the seventh cycle, the signals VdnO and VupO become error values (low level and high level, respectively) due to positive power supply noise. In the twelfth cycle, the signal VupO becomes an error value (high level) due to power supply noise in the positive direction, and in the thirteenth cycle, the signal VdnO becomes an error value (high level) due to potential recovery. In the 17th cycle, the signals VdnO and VupO become error values (high level and low level, respectively) due to power noise in the negative direction.

  According to Table 3, the enable signal ENBL maintains the low level during the period in which the power supply potential VDD is the low potential VDDL, although the low level transition point of the enable signal ENBL is delayed and becomes the eighth cycle due to the mixing of the power supply noise. It turns out that it is normal.

  FIG. 24 is a schematic circuit diagram showing a semiconductor integrated circuit device 10I according to the tenth embodiment of the present invention.

  In this device semiconductor integrated circuit device 10I, an AND gate 40 is added to the semiconductor integrated circuit device 10H of FIG. 22 in the same manner as in the second embodiment, and the output of the AND gate 40 is fixed to a low level during standby. The leakage current is prevented.

  Note that the present invention includes various other modifications.

  For example, a configuration in which the comparator 53 in FIG. 15 compares the power supply potential VDD with the potential obtained by increasing the reference potential Vref by ΔV by the level shift circuit may be used. Similarly, the comparator 54 may be configured to compare the potential obtained by reducing the reference potential Vref by ΔV by the level shift circuit with the power supply potential VDD. The same applies to the comparators 53A and 54A. Instead of the comparators 53 and 54, comparators 53A and 54A each having a comparison result holding function may be used.

  The switch circuit may be a CMOS inverter.

  As is clear from the above description, the present invention includes the following supplementary notes.

(Supplementary note 1) In a semiconductor integrated circuit device having an operation mode in which the first clock signal is in a standby state while it is off,
A first circuit block connected to the power supply line;
A switch circuit;
A second circuit block to which the power supply line is connected via the switch circuit;
An operation mode detection circuit that detects on / off of the first clock signal and turns off the switch circuit while detecting the off;
A semiconductor integrated circuit device comprising: (1)
(Appendix 2) The operation mode detection circuit is
In response to the leading edge of the pulse of the first clock signal, a pulse having a narrower width than the pulse is included in the pulse period of the first clock signal when the first clock signal is on. A second clock generation circuit for generating a second clock signal delayed by one clock cycle or more,
A flip-flop that latches the on / off state of the first clock signal in response to a pulse of the second clock signal;
The semiconductor integrated circuit device according to appendix 1, wherein the switch circuit is on / off controlled by an output of the flip-flop. (2)
(Supplementary Note 3) The operation mode detection circuit further includes:
A signal line for supplying the first clock signal is coupled to the first end of the current path, the second end of the current path is connected to the input end of the flip-flop; A transfer gate for supplying the second clock signal to the control input terminal and turning on the current path in a pulse period of the second clock signal; (3)
The semiconductor integrated circuit device as set forth in appendix 2, wherein:

(Supplementary Note 4) The operation mode detection circuit further includes:
A third clock generation circuit that is inserted into the signal line and generates a pulse having a predetermined width in response to a leading edge of the pulse of the first clock signal;
The semiconductor integrated circuit device according to appendix 3, characterized by comprising: (4)
(Additional remark 5) It has further a mask circuit which fixes the signal output from this 2nd circuit block to a predetermined level, while the output of this flip-flop shows the OFF state of this 1st clock signal, It is characterized by the above-mentioned. The semiconductor integrated circuit device according to any one of appendices 2 to 4.

  (Appendix 6) The switch circuit is a logic gate that outputs the potential of the power supply line while the output of the flip-flop indicates the ON state of the first clock signal. 6. The semiconductor integrated circuit device according to any one of 5 above.

(Supplementary note 7) In a semiconductor integrated circuit device having an operation mode in which the power supply line is in a standby state while the potential of the power supply line is a potential within a predetermined range lower than that during normal operation
A first circuit block connected to the power supply line;
A switch circuit;
A second circuit block to which the power supply line is connected via the switch circuit;
The amount of change in one period of the potential of the power supply line is detected at a predetermined cycle, and the switch circuit is turned off when the change exceeds a negative predetermined value, and the switch circuit is turned off when the change exceeds a positive predetermined value. An operation mode detection circuit for turning on,
A semiconductor integrated circuit device comprising: (5)
(Appendix 8) The operation mode detection circuit is
A sample-and-hold circuit that samples and holds the potential of the power supply line in response to a pulse of a sampling signal that is a pulse train of the predetermined cycle;
The potential Vref held in the sample and hold circuit is compared with the potential VDD of the power supply line, and in response to a pulse of a comparison signal having a phase different from that of the sampling signal in a pulse train having the same cycle as the sampling signal, the potential A window comparator that activates the first signal if the difference between VDD and the potential Vref is less than the negative predetermined value, and activates the second signal if the difference is greater than the positive predetermined value;
A flip-flop that enters a first state in response to the activation of the first signal and enters a second state in response to the activation of the second signal;
8. The semiconductor integrated circuit device according to appendix 7, wherein the switch circuit is on / off controlled by the output of the flip-flop. (6)
(Supplementary Note 9) The operation mode detection circuit is
A sample-and-hold circuit that samples and holds the potential of the power supply line in response to a pulse of a sampling signal that is a pulse train of the predetermined cycle;
The potential Vref held in the sample and hold circuit is compared with the potential VDD of the power supply line, and in response to a pulse of a comparison signal having a phase different from that of the sampling signal in a pulse train having the same cycle as the sampling signal, the potential A window comparator that activates the first signal if the difference between VDD and the potential Vref is less than the negative predetermined value, and activates the second signal if the difference is greater than the positive predetermined value;
An M period coincidence circuit that activates the third signal when the first signal is active continuously for M periods (M ≧ 2);
A K period matching circuit that activates the fourth signal when the comparison signal is continuously active for K periods (K ≧ 2) and the second signal is active;
A flip-flop that enters a first state in response to the activity of the third signal and enters a second state in response to the activity of the fourth signal;
8. The semiconductor integrated circuit device according to appendix 7, wherein the switch circuit is on / off controlled by the output of the flip-flop. (7)
(Supplementary Note 10) The operation mode detection circuit includes:
A sample-and-hold circuit that samples and holds the potential of the power supply line in response to a pulse of a sampling signal that is a pulse train of the predetermined cycle;
The potential Vref held in the sample and hold circuit is compared with the potential VDD of the power supply line, and in response to a pulse of a comparison signal having a phase different from that of the sampling signal in a pulse train having the same cycle as the sampling signal, the potential A window comparator that activates the first signal if the difference between VDD and the potential Vref is less than the negative predetermined value, and activates the second signal if the difference is greater than the positive predetermined value;
During the M period (M ≧ 2) of the comparison signal, if the first signal is active for (M−m) periods (m <M) or more, the third signal is activated (M−m). Circuit,
During the K period (K ≧ 2) of the comparison signal, if the second signal is active for (K−k) periods (k <K) or more, the fourth signal is activated (K−k). Circuit,
A flip-flop that enters a first state in response to the activity of the third signal and enters a second state in response to the activity of the fourth signal;
The semiconductor integrated circuit device according to appendix 7, wherein the switch circuit is on / off controlled by the output of the flip-flop. (8)
(Supplementary Note 11) A frequency divider that divides the first clock signal by N to generate the comparison signal;
A delay circuit that delays the comparison signal to generate the sampling signal;
The semiconductor integrated circuit device according to any one of appendices 8 to 10, further comprising: (9)
(Additional remark 12) It further has a mask circuit which fixes the signal supplied from the second circuit block to the first circuit block at a predetermined level while the output of the flip-flop indicates the first state. The semiconductor integrated circuit device according to any one of appendices 2 to 4 and 8 to 11. (10)
(Supplementary note 13) Any one of Supplementary notes 8 to 12, wherein the switch circuit is a logic gate that outputs the potential of the power supply line while the output of the flip-flop indicates the second state. The semiconductor integrated circuit device according to one.

1 is a schematic block diagram illustrating a semiconductor integrated circuit device according to a first embodiment of the present invention. 2 is a flowchart showing a control operation of a clock on / off detection circuit 20 for a switch circuit 13 in FIG. FIG. 2 is a circuit diagram showing a more detailed configuration of the semiconductor integrated circuit device of FIG. 1. (A) is a logic circuit diagram showing a configuration example of the chopping / delay circuit 30 in FIG. 3, and (B) is a time chart showing the operation of this circuit. 4 is a time chart showing the operation of the circuit of FIG. 3. It is a schematic circuit diagram which shows the semiconductor integrated circuit device of Example 2 of this invention. 7 is a time chart showing the operation of the circuit of FIG. 6. It is a schematic block diagram which shows the semiconductor integrated circuit device of Example 3 of this invention. (A) is a logic circuit diagram showing a configuration example of the chopping circuit 34 in FIG. 8, and (B) is a time chart showing the operation of this circuit. It is a time chart which shows operation | movement of the circuit of FIG. It is a schematic block diagram which shows the semiconductor integrated circuit device of Example 3 of this invention. 12 is a time chart showing the operation of the circuit of FIG. It is a schematic block diagram which shows the semiconductor integrated circuit device of Example 5 of this invention. 14 is a flowchart showing a control operation of the VDD change detection circuit 20A for the AND gate 13A in FIG. FIG. 14 is a circuit diagram showing a more detailed configuration of the semiconductor integrated circuit device of FIG. 13. 16 is a time chart showing an operation of the semiconductor integrated circuit device of FIG. It is a schematic circuit diagram which shows the semiconductor integrated circuit device of Example 6 of this invention. It is a schematic circuit diagram which shows the semiconductor integrated circuit device of Example 7 of this invention. It is a figure which shows the structural example of the M period coincidence circuit 60 in FIG. 20 is a time chart showing the operation of the circuit of FIG. 19 when the power supply potential VDD is dropping. It is a schematic circuit diagram which shows the semiconductor integrated circuit device of Example 8 of this invention. It is a schematic circuit diagram which shows the semiconductor integrated circuit device of Example 9 of this invention. FIG. 23 is a diagram illustrating a configuration example of a (M−m) period matching circuit 70 in FIG. 22. It is a schematic circuit diagram which shows the semiconductor integrated circuit device of Example 10 of this invention. (A)-(C) are schematic block diagrams which show the conventional semiconductor integrated circuit device which reduces power consumption at the time of standby mode.

Explanation of symbols

10, 10A to 10I, 10X to 10Z Semiconductor integrated circuit device 11, 11A, 11B Circuit block 12 PMOS transistor 13 Switch circuit 13A, 31, 36, 40 AND gate 20, 20A Clock on / off detection circuit 20B-20D VDD change detection Circuit 21, 51 Transfer gate 22-24, 26 Inverter 25 Flip-flop 30 Chopping / delay circuit 32, 35 Inversion delay circuit 33 Delay circuit 34 Chopping circuit 50 Sample hold circuit 52 Capacitor 53, 54, 53A, 54A Comparator 55, 56 level Shift circuit 57 N frequency divider 58 Buffer gate 59 RS flip-flop 60 M period coincidence circuit 61 K period coincidence circuit 62-64, 72-74 D flip-flop 65 AND gate 66- 8, 76 to 78 Buffer gate 70 (Mm) Period coincidence circuit 71 (Kk) Period coincidence circuit 75 '1' Number comparison circuit ENBL Enable signal CLK, CLK1, * CLK1, CLK2, * CLK3, CLKA to CLKD Clock signal Vref Reference potential VDDN Normal potential VDDL Low potential

Claims (8)

A power supply line;
A switch circuit connected to the power supply line;
A first circuit block connected to the power supply line via the switch circuit;
The amount of change of the potential of the power supply line in a predetermined period is detected, and if the amount of change is less than a negative predetermined value, the switch circuit is turned off, and if the amount of change exceeds a positive predetermined value, the switch circuit An operation mode detection circuit for turning on,
A semiconductor integrated circuit device comprising:   The semiconductor integrated circuit device according to claim 1, further comprising a second circuit block connected to the power supply line. The operation mode detection circuit includes:
A sample-and-hold circuit that samples and holds the potential of the power supply line in response to a pulse of a sampling signal that is a pulse train of the predetermined cycle;
The potential Vref held in the sample and hold circuit is compared with the potential VDD of the power supply line, and in response to a pulse of a comparison signal having a phase different from that of the sampling signal in a pulse train having the same cycle as the sampling signal, the potential A window comparator that activates the first signal if the difference between VDD and the potential Vref is less than the negative predetermined value, and activates the second signal if the difference is greater than the positive predetermined value;
A flip-flop that enters a first state in response to the activation of the first signal and enters a second state in response to the activation of the second signal;
2. The semiconductor integrated circuit device according to claim 1, wherein the switch circuit is on / off controlled by an output of the flip-flop. The operation mode detection circuit includes:
A sample-and-hold circuit that samples and holds the potential of the power supply line in response to a pulse of a sampling signal that is a pulse train of the predetermined cycle;
The potential Vref held in the sample and hold circuit is compared with the potential VDD of the power supply line, and in response to a pulse of a comparison signal having a phase different from that of the sampling signal in a pulse train having the same cycle as the sampling signal, the potential A window comparator that activates the first signal if the difference between VDD and the potential Vref is less than the negative predetermined value, and activates the second signal if the difference is greater than the positive predetermined value;
An M period coincidence circuit that activates the third signal when the first signal is active continuously for M periods (M ≧ 2);
A K period matching circuit that activates the fourth signal when the comparison signal is continuously active for K periods (K ≧ 2) and the second signal is active;
A flip-flop that enters a first state in response to the activity of the third signal and enters a second state in response to the activity of the fourth signal;
2. The semiconductor integrated circuit device according to claim 1, wherein the switch circuit is on / off controlled by an output of the flip-flop. The operation mode detection circuit includes:
A sample-and-hold circuit that samples and holds the potential of the power supply line in response to a pulse of a sampling signal that is a pulse train of the predetermined cycle;
The potential Vref held in the sample and hold circuit is compared with the potential VDD of the power supply line, and in response to a pulse of a comparison signal having a phase different from that of the sampling signal in a pulse train having the same cycle as the sampling signal, the potential A window comparator that activates the first signal if the difference between VDD and the potential Vref is less than the negative predetermined value, and activates the second signal if the difference is greater than the positive predetermined value;
During the M period (M ≧ 2) of the comparison signal, if the first signal is active for (M−m) periods (m <M) or more, the third signal is activated (M−m). Circuit,
During the K period (K ≧ 2) of the comparison signal, if the second signal is active for (K−k) periods (k <K) or more, the fourth signal is activated (K−k). Circuit,
A flip-flop that enters a first state in response to the activity of the third signal and enters a second state in response to the activity of the fourth signal;
2. The semiconductor integrated circuit device according to claim 1, wherein the switch circuit is on / off controlled by an output of the flip-flop. A frequency divider for dividing the first clock signal by N to generate the comparison signal;
A delay circuit that delays the comparison signal to generate the sampling signal;
The semiconductor integrated circuit device according to claim 3, further comprising:   2. A mask circuit for fixing a signal supplied from the first circuit block to the second circuit block at a predetermined level while the output of the flip-flop indicates the first state. 7. The semiconductor integrated circuit device according to any one of 3 to 6. The operation mode detection circuit includes:
A capacitor that maintains the potential of the power supply line at one of its electrodes at a first timing;
A level shift circuit for generating a first potential obtained by lowering the potential of the power supply line by the negative predetermined value;
A comparator for comparing the maintained potential with the first potential at a second timing later than the first timing;
The semiconductor integrated circuit device according to claim 1, comprising: