JP4720600B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4720600B2
JP4720600B2 JP2006120033A JP2006120033A JP4720600B2 JP 4720600 B2 JP4720600 B2 JP 4720600B2 JP 2006120033 A JP2006120033 A JP 2006120033A JP 2006120033 A JP2006120033 A JP 2006120033A JP 4720600 B2 JP4720600 B2 JP 4720600B2
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electrode
semiconductor device
lead electrode
chip
semiconductor chip
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JP2007294627A (en
JP2007294627A5 (en
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真二 平光
康二 佐々木
聡 松吉
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は半導体装置に係り、例えば交流を直流に変換することを目的とする車載用に好適な半導体装置に関する。 The present invention relates to a semiconductor device, relates to a semiconductor device suitable vehicle for the purpose of converting such as alternating current to direct current.

本装置は、自動車の交流発電機に搭載され、交流出力を直流出力に変換する整流機能を有した車載用半導体装置である。図１０に、従来の半導体装置の断面図を示す。図１０において、１は半導体チップ、２は半導体チップ１とリード電極３とを接合する接合部材、３は接合部材との接合用にリードより大きな径となっているリード電極ヘッダ部３ａを有するリード電極、４は半導体チップ１と緩衝板１０を接合する接合部材、６は緩衝板１０とケース電極７を接合する接合部材、７はケース電極、９は半導体チップ１の表面を保護する絶縁部材、１０は半導体チップ１とケース電極７の線膨張係数差を緩和するための緩衝板である。本半導体装置では、内蔵された半導体チップ１が通電により発熱するため、その熱の放熱経路を確保する必要がある。本構造においては、半導体チップ１から接合部材２，リード電極３の順で熱を運び、その先へ熱を逃がす経路と、半導体チップ１から接合部材４，緩衝板１０，接合部材６，ケース電極７の順で熱を運び、その先へ逃がす経路とがある（例えば特許文献１，２参照）。   This device is a vehicle-mounted semiconductor device that is mounted on an AC generator of an automobile and has a rectifying function for converting AC output to DC output. FIG. 10 shows a cross-sectional view of a conventional semiconductor device. In FIG. 10, 1 is a semiconductor chip, 2 is a bonding member for bonding the semiconductor chip 1 and the lead electrode 3, and 3 is a lead having a lead electrode header portion 3a having a larger diameter than the lead for bonding to the bonding member. Electrode 4, 4 is a joining member that joins the semiconductor chip 1 and the buffer plate 10, 6 is a joining member that joins the buffer plate 10 and the case electrode 7, 7 is a case electrode, 9 is an insulating member that protects the surface of the semiconductor chip 1, Reference numeral 10 denotes a buffer plate for reducing a difference in linear expansion coefficient between the semiconductor chip 1 and the case electrode 7. In this semiconductor device, since the built-in semiconductor chip 1 generates heat when energized, it is necessary to secure a heat dissipation path for the heat. In this structure, a path through which heat is transferred in order from the semiconductor chip 1 to the bonding member 2 and the lead electrode 3, and the heat is released from the semiconductor chip 1, the bonding member 4, the buffer plate 10, the bonding member 6, and the case electrode from the semiconductor chip 1. There is a path for carrying heat in the order of 7 and letting it go away (see, for example, Patent Documents 1 and 2).

特開２００２−３５９３２８号公報（図１）JP 2002-359328 A (FIG. 1) 特開２００２−４３４８０号公報（図１）JP 2002-43480 A (FIG. 1)

本半導体装置は、内蔵された半導体チップ１が通電により発熱する上、自動車のエンジンルームに搭載されるため、車両に搭載された他の電装品での発熱の影響を極めて受けやすい。本半導体装置がこのような熱負荷を繰返し受けると、本半導体装置を構成する部材の線膨張係数差に起因する熱ひずみが接合部材２，４，６に加わり、この接合部材２，４，６の端部よりき裂が発生，進展し、最終的には機能停止に至る。   Since this semiconductor device generates heat when energized and is mounted in the engine room of an automobile, it is extremely susceptible to heat generated by other electrical components mounted on the vehicle. When the present semiconductor device is repeatedly subjected to such a thermal load, thermal strain resulting from a difference in linear expansion coefficient between members constituting the semiconductor device is applied to the joining members 2, 4, 6. Cracks are generated and propagated from the end of the steel, and eventually stop functioning.

近年、自動車の電装化は急激な勢いで進行しており、車載電装品の増加，車載用発電機の容量増加により、本半導体装置への熱負荷の増大は不可避である。このため、本半導体装置の放熱性の向上，長期信頼性の向上が急務となってきている。これまでに、半導体チップ１の上下のリード電極３や緩衝板１０，ケース電極７を大きくし、半導体装置の熱容量を大きくすることで、放熱性を向上させる技術が提案されている。しかし、半導体チップ１の上下の部材を大きくすることは、その部材の剛性を大きくすることにもつながるため、結果的には、半導体チップ１との線膨張係数差に起因する熱ひずみが大きくなり、長期信頼性は低下してしまうことになる。   In recent years, the electrification of automobiles has been proceeding at a rapid pace, and due to the increase in in-vehicle electrical components and the increase in the capacity of in-vehicle generators, an increase in the thermal load on the semiconductor device is inevitable. For this reason, improvement in heat dissipation and long-term reliability of the semiconductor device have become urgent. Up to now, a technique for improving heat dissipation has been proposed by increasing the upper and lower lead electrodes 3, the buffer plate 10, and the case electrode 7 of the semiconductor chip 1 and increasing the heat capacity of the semiconductor device. However, increasing the upper and lower members of the semiconductor chip 1 also increases the rigidity of the members. As a result, the thermal strain due to the difference in linear expansion coefficient from the semiconductor chip 1 increases. Long-term reliability will be reduced.

特許文献２では、電極の周りに線膨張係数の小さい拘束材を配置することで、電極の線膨張を抑えている。しかし、特許文献２に記載の発明は、パワー回路用の半導体装置であり、整流用の半導体装置とは構造が異なり、整流用の半導体に拘束材を用いるのに適した形態が開示されていない。   In Patent Document 2, the linear expansion of the electrode is suppressed by disposing a restraining material having a small linear expansion coefficient around the electrode. However, the invention described in Patent Document 2 is a semiconductor device for a power circuit, has a different structure from the semiconductor device for rectification, and does not disclose a form suitable for using a restraining material for the semiconductor for rectification. .

上記の課題を解決するために、本発明では半導体チップと、ヘッダ部を有し、リード部に接続されるリード電極と、前記半導体チップと前記ヘッダ部を接合する第一の接合部材と、前記半導体チップの前記リード電極の反対側に電気的に連絡されるケース電極とを備え、前記ヘッダ部の周囲に、前記ヘッダ部よりも線膨張係数の小さい拘束材を配置し、前記拘束材の下端は、前記リード電極の下端よりも上になるように配置することを特徴とする。In order to solve the above problems, in the present invention, a semiconductor chip, a lead electrode having a header portion and connected to a lead portion, a first joining member for joining the semiconductor chip and the header portion, A case electrode electrically connected to the opposite side of the lead electrode of the semiconductor chip, a restraining material having a smaller linear expansion coefficient than the header portion is disposed around the header portion, and a lower end of the restraining material Is arranged to be above the lower end of the lead electrode.


本発明は、車載用半導体装置において、リード電極ヘッダ部およびチップ下電極の周囲に、電極よりも線膨張係数が小さい材質の拘束材を備え、リード電極およびチップ下電極の大きさによらず、第一および第二の接合部材の熱ひずみを低減でき、高い放熱性と高い長期信頼性の両方を確保される半導体装置である。   The present invention provides a vehicle-mounted semiconductor device including a restraint material made of a material having a smaller linear expansion coefficient than the electrode around the lead electrode header and the chip lower electrode, regardless of the size of the lead electrode and the chip lower electrode. This is a semiconductor device that can reduce the thermal strain of the first and second joining members and ensure both high heat dissipation and high long-term reliability.

本発明によれば、リード電極およびチップ下電極の周囲に電極よりも線膨張係数が小さい材質の拘束材を配置することで、半導体チップとリード電極ヘッダ部またはチップ下電極間の接合部材の熱ひずみを低減することができる。 According to the present invention, by disposing the restraint material of the material linear expansion coefficient than the electrode around the rie de electrostatic Gokuo by beauty Ji-up under electrodes is small, the semiconductor chip and the rie de electrode header parts or can reduce the thermal distortion of the joint member of the Chi-up under electrostatic machining gap.

以下、本発明の実施形態を図を用いて説明する。   Embodiments of the present invention will be described below with reference to the drawings.

本発明の第１の実施形態を、図１を用いて説明する。図１に示す半導体装置は、半導体チップ１と、鍔部３ｂ付きのリード電極ヘッダ部３ａを有し、リード部（図示せず）に接続されるリード電極３と、ケース電極７と、半導体チップ１とケース電極７の間に配置される鍔部５ａを有するチップ下電極５と、半導体チップ１とリード電極ヘッダ部３ａを接合する第一の接合部材２（はんだ）と、半導体チップ１とチップ下電極５を接合する第二の接合部材４（はんだ）と、チップ下電極５とケース電極７を接合する第三の接合部材６（はんだ）と、リード電極ヘッダ部３ａおよびチップ下電極５の周囲に配置される拘束材８と、を有している。   A first embodiment of the present invention will be described with reference to FIG. The semiconductor device shown in FIG. 1 includes a semiconductor chip 1, a lead electrode header portion 3a with a flange portion 3b, a lead electrode 3 connected to a lead portion (not shown), a case electrode 7, and a semiconductor chip. A chip lower electrode 5 having a flange portion 5a disposed between 1 and the case electrode 7, a first bonding member 2 (solder) for bonding the semiconductor chip 1 and the lead electrode header portion 3a, and the semiconductor chip 1 and the chip The second bonding member 4 (solder) for bonding the lower electrode 5, the third bonding member 6 (solder) for bonding the chip lower electrode 5 and the case electrode 7, the lead electrode header portion 3 a and the chip lower electrode 5. And a restraint member 8 disposed around.

半導体チップ１は、半導体装置の機能に用いられる整流機能を有している。リード電極ヘッダ部３ａおよびチップ下電極５の径は、半導体チップ１の径と同じないしは＋５％以下のものであり，リード電極鍔部３ｂおよびチップ下電極鍔部５ａは、接合部材２，４よりも厚さが３倍以下のものである。拘束材８は、径方向の厚さをリード電極ヘッダ部３ａおよびチップ下電極５の径の１５％以上とし、鉛直（径方向に対して垂直）方向の厚さを１.２mm 以下とし、さらに線膨張係数を３〜１０×１０-6／℃とすることで、リード電極ヘッダ部３ａおよびチップ下電極５の熱変形を拘束し、半導体チップ１とリード電極ヘッダ部３ａおよびチップ下電極５間の接合部材２，４の熱ひずみを低減した構造の例を示したものである。 The semiconductor chip 1 has a rectifying function used for the function of the semiconductor device. The diameters of the lead electrode header portion 3 a and the chip lower electrode 5 are the same as those of the semiconductor chip 1 or + 5% or less. The lead electrode flange portion 3 b and the chip lower electrode flange portion 5 a are formed by the joining members 2 and 4. The thickness is 3 times or less. The restraint member 8 has a radial thickness of 15% or more of the diameter of the lead electrode header portion 3a and the chip lower electrode 5, a vertical (perpendicular to the radial direction) thickness of 1.2 mm or less, and By setting the linear expansion coefficient to 3 to 10 × 10 −6 / ° C., the thermal deformation of the lead electrode header portion 3 a and the chip lower electrode 5 is constrained, and between the semiconductor chip 1, the lead electrode header portion 3 a and the chip lower electrode 5. The example of the structure which reduced the heat distortion of the joining members 2 and 4 of this is shown.

まず、リード電極ヘッダ部３ａおよびチップ下電極５の周囲に、電極３，５よりも線膨張係数の小さい拘束材８を配置する効果について説明する。   First, the effect of disposing the constraining material 8 having a smaller linear expansion coefficient than the electrodes 3 and 5 around the lead electrode header portion 3a and the chip lower electrode 5 will be described.

図６〜図９は、半導体チップ１，リード電極ヘッダ部３ａ，チップ下電極５，接合部材２，４，６が全て円板形かつ拘束材８が円筒形の解析モデルを用い、周囲の温度を３０℃→２００℃→３０℃に変化させた場合の熱応力解析において、リード電極ヘッダ部３ａおよびチップ下電極５の径・拘束材８における径方向および鉛直（径方向に対して垂直）方向の厚さ・リード電極鍔部３ｂおよびチップ下電極鍔部５ａの厚さと、接合部材２，４に発生する最大相当塑性ひずみの関係を整理した図である。●は、リード電極ヘッダ部３ａおよびチップ下電極５が、鍔部３ｂ，５ａを有している場合、△は、鍔部３ｂ，５ａを有していない場合の結果である。また、拘束材８がない場合の最大相当塑性ひずみは、18.9％（グラフ内の横線）である。   6 to 9 show an analysis model in which the semiconductor chip 1, the lead electrode header portion 3 a, the chip lower electrode 5, the joining members 2, 4, and 6 are all disk-shaped and the restraint material 8 is cylindrical, and the ambient temperature In the thermal stress analysis when the temperature is changed from 30 ° C. → 200 ° C. → 30 ° C., the radial direction and the vertical direction (perpendicular to the radial direction) in the diameter / constraint 8 of the lead electrode header portion 3a and the lower chip electrode 5 FIG. 6 is a diagram in which the relationship between the thickness of the lead electrode flange 3b and the tip lower electrode flange 5a and the maximum equivalent plastic strain generated in the joining members 2 and 4 is arranged. ● indicates the results when the lead electrode header portion 3a and the chip lower electrode 5 have the flange portions 3b and 5a, and Δ indicates the result when the flange portions 3b and 5a are not included. Further, the maximum equivalent plastic strain in the absence of the restraint material 8 is 18.9% (horizontal line in the graph).

拘束材８がない場合に対し，拘束材８がある場合は、リード電極ヘッダ部３ａおよびチップ下電極５の径・拘束材８における径方向および鉛直（径方向に対して垂直）方向の厚さ・リード電極鍔部３ｂおよびチップ下電極鍔部５ａの厚さを調整することで、接合部材２，４に発生する最大相当塑性ひずみを最大で１０.５％ まで、つまり拘束材８の無い場合の６割程度に低減できることが確認できる。このときのリード電極ヘッダ部３ａの電極径は、半導体チップ１の径の１００％であり、電極径が１００〜１０５％の範囲では、おおよそ拘束材８による塑性ひずみ低減の効果がみられる。また、図７より、拘束材８の径方向の厚さは、電極径の１５％以上であると塑性ひずみ低減の効果があり、図８より、拘束材８の鉛直方向（軸方向）の厚さは１.２mm 以下であり、図９より、接合部材２，４の厚さの３倍以下が望ましいことがわかる。拘束材８の材料は、線膨張係数が３〜１０×
１０-6／℃ 程度の金属が望ましく、例えば、モリブデン（４.９×１０-6／℃），タングステン（４.５×１０-6／℃），鉄−ニッケル合金（インバー：２.８×１０-6／℃）等が適用できる。 In contrast to the case where there is no restraining material 8, when there is the restraining material 8, the diameter of the lead electrode header portion 3 a and the chip lower electrode 5 and the thickness in the radial direction and vertical direction (perpendicular to the radial direction) of the restraining material 8・ By adjusting the thickness of the lead electrode flange 3b and the chip lower electrode flange 5a, the maximum equivalent plastic strain generated in the joining members 2 and 4 is up to 10.5%, that is, when there is no restraint 8 It can be confirmed that it can be reduced to about 60%. The electrode diameter of the lead electrode header portion 3a at this time is 100% of the diameter of the semiconductor chip 1, and when the electrode diameter is in the range of 100 to 105%, the effect of reducing plastic strain by the restraint material 8 is observed. From FIG. 7, the radial thickness of the restraint 8 is 15% or more of the electrode diameter, which has the effect of reducing plastic strain. From FIG. 8, the thickness of the restraint 8 in the vertical direction (axial direction). The thickness is 1.2 mm or less, and it can be seen from FIG. 9 that the thickness of the joining members 2 and 4 is preferably 3 times or less. The material of the restraint material 8 has a linear expansion coefficient of 3 to 10 ×.
A metal of about 10 −6 / ° C. is desirable, for example, molybdenum (4.9 × 10 −6 / ° C.), tungsten (4.5 × 10 −6 / ° C.), iron-nickel alloy (invar: 2.8 × 10 −6 / ° C.) can be applied.

また、一方のみの線膨張を抑えると半導体チップ１に反りが発生するので、半導体チップの上下のリード電極ヘッダ部３ａおよびチップ下電極５の両方に拘束材８を設けるとよい。この場合において、リード電極ヘッダ部３ａ及びチップ下電極５の半導体チップ側
(リード電極ヘッダ部３ａの高さ方向で半分から下側及びチップ下電極５の半分から上側)の形状及び材料，拘束材８の形状及び材料を略同一とすると、半導体チップ１の上下の線膨張がほぼ等しくなる。つまり、リード電極ヘッダ部３ａおよびチップ下電極５の周囲に、電極３，５よりも線膨張係数の小さい拘束材８を配置することで、局所的に電極の熱変形を拘束し、接合部材２，４に発生する熱ひずみを低減できることになる。 Further, if only one of the linear expansions is suppressed, the semiconductor chip 1 is warped. Therefore, it is preferable to provide the restraining material 8 on both the upper and lower lead electrode header portions 3a and the lower chip electrode 5 of the semiconductor chip. In this case, the lead electrode header portion 3a and the chip lower electrode 5 on the semiconductor chip side
If the shape and material of the lead electrode header 3a in the height direction from the lower half and the upper side of the chip lower electrode 5 are substantially the same, and the shape and material of the restraint material 8 are substantially the same, the upper and lower lines of the semiconductor chip 1 Expansion is almost equal. That is, by disposing the restraining material 8 having a smaller linear expansion coefficient than the electrodes 3 and 5 around the lead electrode header portion 3a and the lower chip electrode 5, the thermal deformation of the electrode is locally restrained, and the joining member 2 , 4 can be reduced.

次に、リード電極ヘッダ部３ａおよびチップ下電極５が、各々における半導体チップ１側の端部に鍔部３ｂ，５ａを有する効果について説明する。   Next, the effect of the lead electrode header portion 3a and the chip lower electrode 5 having the flange portions 3b and 5a at the end portions on the semiconductor chip 1 side in each will be described.

図１１（ａ）（ｂ）に常温時及び高温時のリード電極を示す。図１１における点線３ｃは常温時のリード電極３、実線３ｄは高温時のリード電極３を示す。常温時には、略円筒状であったリード電極ヘッダ部３ａは、高温になると熱膨張するが、線膨張係数の小さい拘束材８が周囲に存在すると、拘束材８によりリード電極ヘッダ部３ａの膨張が抑えられる。しかし、図１１（ａ）に示すように、高さ方向において拘束材８をリード電極ヘッダ部３ａの全体に配置していない場合には、リード電極ヘッダ部３ａの半導体チップ１側の底面にひずみが生じ、半導体チップ１へのひずみへも影響する。これは、拘束材８の位置が偏っているために発生するものであり、特にリード電極ヘッダ部３ａの下端と拘束材８の下端が同じ高さであるときに大きくなる。一方で、図１１（ｂ）に示すように、リード電極ヘッダ部３ａの下端を拘束材８の下端よりも下に配置した場合には、リード電極ヘッダ部３ａの線膨張のアンバランスが低減して底面のひずみが低減される。そのため、上記解析モデルでは、鍔部３ｂ，５ａを有しているものが有していないものに比べて相当塑性ひずみが小さくなる電極径の範囲がある。鍔部３ｂ，５ａを有している方がひずみが小さくなる領域は、電極径が半導体チップ１の径よりも大きい場合なので、電極径を大きくして放熱性を向上させる場合等に適している。なお、上記解析モデルでは半導体チップ１は円形のものとしたが、半導体チップ１が四角形，六角形等の円形で無い場合には、半導体チップ１の径は、図心と図心から最も遠い箇所（例えば四角形の頂点）との距離が該当する。   FIGS. 11A and 11B show lead electrodes at normal temperature and high temperature. In FIG. 11, a dotted line 3c indicates the lead electrode 3 at normal temperature, and a solid line 3d indicates the lead electrode 3 at high temperature. At normal temperature, the lead electrode header portion 3a, which is substantially cylindrical, expands thermally when the temperature rises. However, if the restraint material 8 having a small linear expansion coefficient is present in the vicinity, the lead electrode header portion 3a is expanded by the restraint material 8. It can be suppressed. However, as shown in FIG. 11A, when the restraining material 8 is not disposed in the entire lead electrode header portion 3a in the height direction, the bottom surface of the lead electrode header portion 3a on the semiconductor chip 1 side is distorted. This affects the strain on the semiconductor chip 1. This occurs because the position of the restraint material 8 is biased, and is particularly large when the lower end of the lead electrode header portion 3a and the lower end of the restraint material 8 are the same height. On the other hand, as shown in FIG. 11B, when the lower end of the lead electrode header portion 3a is disposed below the lower end of the restraint member 8, the unbalance of the linear expansion of the lead electrode header portion 3a is reduced. This reduces the distortion at the bottom. Therefore, in the analysis model, there is an electrode diameter range in which the equivalent plastic strain is smaller than that having the flanges 3b and 5a. The region where the strain is reduced when the flanges 3b and 5a are provided is suitable for the case where the electrode diameter is larger than the diameter of the semiconductor chip 1 and the heat dissipation is improved by increasing the electrode diameter. . In the above analysis model, the semiconductor chip 1 is circular. However, when the semiconductor chip 1 is not circular, such as a square or a hexagon, the diameter of the semiconductor chip 1 is the farthest from the centroid and the centroid ( For example, the distance to the vertex of a rectangle corresponds.

本半導体装置においては、高放熱性を確保するためには、半導体装置自体の熱容量が大きい方が好ましい。そのため、リード電極ヘッダ部３ａおよびチップ下電極５の径は、できるだけ大きい方が好ましいことになる。図５において、リード電極ヘッダ部３ａおよびチップ下電極５の径を大きくした場合、リード電極ヘッダ部３ａおよびチップ下電極５が鍔部３ｂ，５ａを有している構造の方が、有していない構造に比べ、接合部材２，４に発生する熱ひずみを低減できることが確認できる。また、鍔部３ｂ，５ａを介して熱が伝わり、放熱性が向上する効果も期待できる。   In the present semiconductor device, in order to ensure high heat dissipation, it is preferable that the heat capacity of the semiconductor device itself is large. Therefore, it is preferable that the diameters of the lead electrode header portion 3a and the chip lower electrode 5 are as large as possible. In FIG. 5, when the diameters of the lead electrode header portion 3a and the chip lower electrode 5 are increased, the structure in which the lead electrode header portion 3a and the chip lower electrode 5 have the flange portions 3b and 5a has. It can be confirmed that the thermal strain generated in the joining members 2 and 4 can be reduced as compared with the structure without the structure. Further, heat is transmitted through the flange portions 3b and 5a, and an effect of improving heat dissipation can be expected.

以上により、高い放熱性と高い長期信頼性の両方を確保した半導体装置を提供できる。   As described above, a semiconductor device that secures both high heat dissipation and high long-term reliability can be provided.

また、拘束材８の備え付け方法について、ここで言及しておく。拘束材８は、半導体装置の組立工程よりも以前に、リード電極ヘッダ部３ａおよびチップ下電極５に対し、焼き嵌めによりセットされることとする。そうすることで，リード電極ヘッダ部３ａおよびチップ下電極５と拘束材８を一体として扱えるため、既存の半導体装置の組立工程に影響を及ぼすことがない。また、拘束材８は、鍔部３ｂ，５ａに接して設けることにより、拘束材８の位置決めが容易になる。なお、本実施例では、チップ下電極５とケース電極７とは別部材となっているが、一つの部材として、チップ下電極５兼ケース電極７に拘束材８を取り付けてもよい。   Further, a method for installing the restraint material 8 will be mentioned here. The restraint material 8 is set to the lead electrode header portion 3a and the chip lower electrode 5 by shrink fitting before the assembly process of the semiconductor device. By doing so, the lead electrode header portion 3a, the chip lower electrode 5 and the restraint material 8 can be handled as a unit, so that the assembly process of the existing semiconductor device is not affected. Moreover, positioning of the restraint material 8 becomes easy by providing the restraint material 8 in contact with the flange portions 3b and 5a. In this embodiment, the chip lower electrode 5 and the case electrode 7 are separate members, but the restraining material 8 may be attached to the chip lower electrode 5 and case electrode 7 as one member.

本発明の第２の実施形態を、図２を用いて説明する。図２は、半導体チップ１と、鍔部３ｂ付きのリード電極ヘッダ部３ａを有し、リード部に接続されるリード電極３と、ケース電極７と、半導体チップ１とケース電極７の間に配置される鍔部５ａを有するチップ下電極５と、半導体チップ１とリード電極ヘッダ部３ａを接合する第一の接合部材２，１０，１２と、半導体チップ１とチップ下電極５を接合する第二の接合部材４，１１，１３と、チップ下電極５とケース電極７を接合する第三の接合部材６（はんだ）と、リード電極ヘッダ部３ａおよびチップ下電極５の周囲に配置される拘束材８と、を有した半導体装置において、半導体チップ１とリード電極ヘッダ部３ａとの間の第一の接合部材２，１０，１２に、はんだ２，１２の熱ひずみを低減するための緩衝板１０を有し、さらに、半導体チップ１とチップ下電極５との間の第二の接合部材４，１１，１３に、はんだ４，１３の熱ひずみを低減するための緩衝板１１と、を有することで、半導体チップ１上下の接合部材２，４の長期信頼性を確保した構造の例を示したものである。本実施例は、拘束材８による接合部材２，４の熱ひずみ低減効果のみでは、製品の要求寿命に対して不十分な場合に有効である。   A second embodiment of the present invention will be described with reference to FIG. FIG. 2 shows a semiconductor chip 1, a lead electrode header portion 3 a with a flange 3 b, a lead electrode 3 connected to the lead portion, a case electrode 7, and a semiconductor chip 1 and a case electrode 7. Chip lower electrode 5 having flange 5a to be formed, first joining members 2, 10, 12 for joining semiconductor chip 1 and lead electrode header part 3a, and second for joining semiconductor chip 1 and chip lower electrode 5 Bonding members 4, 11, 13, a third bonding member 6 (solder) for bonding the chip lower electrode 5 and the case electrode 7, and a restraining material disposed around the lead electrode header 3 a and the chip lower electrode 5. 8 to the first bonding members 2, 10, 12 between the semiconductor chip 1 and the lead electrode header portion 3 a, the buffer plate 10 for reducing the thermal strain of the solder 2, 12. And even half Since the second bonding members 4, 11, 13 between the body chip 1 and the chip lower electrode 5 have buffer plates 11 for reducing the thermal strain of the solder 4, 13, the upper and lower sides of the semiconductor chip 1 The example of the structure which ensured the long-term reliability of these joining members 2 and 4 is shown. This embodiment is effective when the thermal strain reduction effect of the joining members 2 and 4 by the restraint material 8 is insufficient for the required life of the product.

本願発明の第３の実施形態を、図３を用いて説明する。本実施形態では、第１の実施形態とは、リード電極ヘッダ部３ａの径が異なり、他の部分は同一である。第１の実施形態では、リード電極３の径は、半導体チップ１の径とほぼ同一またはやや大きい程度であるが、本実施形態のリード電極３の径は、半導体チップ１の径よりも小さく、鍔部３ｂ，
５ａの径は、半導体チップ１の径よりも大きくなっている。 A third embodiment of the present invention will be described with reference to FIG. In this embodiment, the diameter of the lead electrode header portion 3a is different from that of the first embodiment, and the other portions are the same. In the first embodiment, the diameter of the lead electrode 3 is approximately the same as or slightly larger than the diameter of the semiconductor chip 1, but the diameter of the lead electrode 3 of the present embodiment is smaller than the diameter of the semiconductor chip 1, Buttocks 3b,
The diameter of 5a is larger than the diameter of the semiconductor chip 1.

この効果を説明する。リード電極ヘッダ部３ａの厚さが薄いと、線膨張によって生じる応力が小さいので、拘束材８がリード電極３の線膨張による膨張を抑え易い。しかし、リード電極３の径を小さくすると、電極の面積が減少して熱伝導度と電気伝導度が低下する。そこで、リード電極ヘッダ部３ａよりも厚さが薄い鍔部３ｂ，５ａの径を半導体チップ１の径よりも大きくすることで、電気伝導度及び熱伝導度の低下を抑えることができる。拘束材８を、電気伝導度と熱伝導度が比較的良い金属製とした場合には、拘束材８経由で電気伝導や熱伝導が起きるので、これらの低下は小さく抑えることができる。   This effect will be described. When the lead electrode header portion 3a is thin, the stress generated by the linear expansion is small, so that the restraint material 8 can easily suppress the expansion of the lead electrode 3 due to the linear expansion. However, when the diameter of the lead electrode 3 is reduced, the area of the electrode is reduced and the thermal conductivity and the electrical conductivity are lowered. Therefore, by making the diameters of the flange portions 3b and 5a thinner than the lead electrode header portion 3a larger than the diameter of the semiconductor chip 1, it is possible to suppress a decrease in electrical conductivity and thermal conductivity. When the restraint material 8 is made of a metal having relatively good electrical conductivity and thermal conductivity, electric conduction and heat conduction occur via the restraint material 8, so that these reductions can be suppressed small.

本発明の第４の実施形態を、図４を用いて説明する。図４は、半導体チップ１と、リード電極ヘッダ部３ａを有し、リード部に接続されるリード電極３と、ケース電極７と、半導体チップ１とケース電極７の間に配置されるチップ下電極５と、半導体チップ１とリード電極ヘッダ部３ａを接合する第一の接合部材２（はんだ）と、半導体チップ１とチップ下電極５を接合する第二の接合部材４（はんだ）と、チップ下電極５とケース電極７を接合する第三の接合部材６（はんだ）と、リード電極ヘッダ部３ａおよびチップ下電極５の周囲に配置される拘束材８と、を有した半導体装置であり、リード電極３およびチップ下電極５の形状を簡素にすることで、放熱性，長期信頼性に加え、加工コストの低減を図った構造の例を示したものである。本実施例は、リード電極３およびチップ下電極５における鍔部３ｂ，５ａの効果に対し、リード電極３およびチップ下電極５の加工コストが高い場合に有効である。   A fourth embodiment of the present invention will be described with reference to FIG. 4 shows a semiconductor chip 1, a lead electrode header portion 3a, a lead electrode 3 connected to the lead portion, a case electrode 7, and a chip lower electrode disposed between the semiconductor chip 1 and the case electrode 7. 5, a first bonding member 2 (solder) for bonding the semiconductor chip 1 and the lead electrode header portion 3a, a second bonding member 4 (solder) for bonding the semiconductor chip 1 and the lower chip electrode 5, and the chip A semiconductor device having a third joining member 6 (solder) for joining the electrode 5 and the case electrode 7, and a restraining member 8 disposed around the lead electrode header portion 3 a and the chip lower electrode 5, An example of a structure in which the shape of the electrode 3 and the lower electrode 5 of the chip is simplified to reduce the processing cost in addition to the heat radiation property and long-term reliability is shown. The present embodiment is effective when the processing cost of the lead electrode 3 and the lower chip electrode 5 is high compared to the effect of the flanges 3b and 5a on the lead electrode 3 and the lower chip electrode 5.

本発明の第５の実施形態を、図５を用いて説明する。図５は、半導体チップ１と、リード電極ヘッダ部３ａを有し、リード部に接続されるリード電極３と、ケース電極７と、前記半導体チップ１と前記ケース電極７の間に配置されるチップ下電極５と、半導体チップ１とリード電極ヘッダ部３ａを接合する第一の接合部材２，１０，１２と、半導体チップ１とチップ下電極５を接合する第二の接合部材４，１１，１３と、チップ下電極５とケース電極７を接合する第三の接合部材６（はんだ）と、リード電極ヘッダ部３ａおよびチップ下電極５の周囲に配置される拘束材８と、を有した半導体装置において、半導体チップ１とリード電極ヘッダ部３ａとの間の第一の接合部材２，１０，１２に、はんだ２，１２の熱ひずみを低減するための緩衝板１０を有し、さらに、半導体チップ１とチップ下電極５との間の第二の接合部材４，１１，１３に、はんだ４，１３の熱ひずみを低減するための緩衝板
１１を有することで、半導体チップ１上下の接合部材２，４の長期信頼性を確保した上、リード電極３およびチップ下電極５の形状を簡素にすることで、加工コストの低減を図った構造の例を示したものである。本実施例は、拘束材８による接合部材２，４の熱ひずみ低減効果が、製品の要求寿命に対して不十分かつ、リード電極３およびチップ下電極５の加工コストが高い場合に有効である。 A fifth embodiment of the present invention will be described with reference to FIG. FIG. 5 shows a semiconductor chip 1, a lead electrode header portion 3 a, a lead electrode 3 connected to the lead portion, a case electrode 7, and a chip disposed between the semiconductor chip 1 and the case electrode 7. The lower electrode 5, the first bonding members 2, 10, 12 for bonding the semiconductor chip 1 and the lead electrode header portion 3a, and the second bonding members 4, 11, 13 for bonding the semiconductor chip 1 and the chip lower electrode 5 And a third joining member 6 (solder) for joining the chip lower electrode 5 and the case electrode 7, and a restraining material 8 disposed around the lead electrode header portion 3 a and the chip lower electrode 5. 1, the first joining members 2, 10, 12 between the semiconductor chip 1 and the lead electrode header 3 a have a buffer plate 10 for reducing the thermal strain of the solder 2, 12, and further, the semiconductor chip 1 and below the chip By having the buffer plate 11 for reducing the thermal strain of the solder 4, 13 on the second bonding members 4, 11, 13 between the pole 5, the long-term bonding members 2, 4 above and below the semiconductor chip 1 The example of the structure which reduced the processing cost by ensuring the reliability and simplifying the shapes of the lead electrode 3 and the chip lower electrode 5 is shown. The present embodiment is effective when the thermal strain reduction effect of the joining members 2 and 4 by the restraint material 8 is insufficient for the required life of the product and the processing cost of the lead electrode 3 and the under-chip electrode 5 is high. .

本発明の第１実施形態を示す半導体装置の断面図である。It is sectional drawing of the semiconductor device which shows 1st Embodiment of this invention. 本発明の第２実施形態を示す半導体装置の断面図である。It is sectional drawing of the semiconductor device which shows 2nd Embodiment of this invention. 本発明の第３実施形態を示す半導体装置の断面図である。It is sectional drawing of the semiconductor device which shows 3rd Embodiment of this invention. 本発明の第４実施形態を示す半導体装置の断面図である。It is sectional drawing of the semiconductor device which shows 4th Embodiment of this invention. 本発明の第５実施形態を示す半導体装置の断面図である。It is sectional drawing of the semiconductor device which shows 5th Embodiment of this invention. 半導体チップ１の径に対する、リード電極ヘッダ部３ａおよびチップ下電極５の径の比と、接合部材２，４に発生する最大相当塑性ひずみの関係を説明する図である。FIG. 3 is a diagram for explaining the relationship between the ratio of the diameter of the lead electrode header portion 3a and the lower chip electrode 5 to the diameter of the semiconductor chip 1 and the maximum equivalent plastic strain generated in the joining members 2 and 4; リード電極ヘッダ部３ａおよびチップ下電極５の径に対する、拘束材８の径方向の厚さの比と、接合部材２，４に発生する最大相当塑性ひずみの関係を説明する図である。It is a figure explaining the relationship of the ratio of the thickness of the radial direction of the restraint material 8 with respect to the diameter of the lead electrode header part 3a and the chip | tip lower electrode 5, and the largest equivalent plastic strain which generate | occur | produces in the joining members 2 and 4. 拘束材８における鉛直（径方向に対して垂直）方向の厚さと、接合部材２，４に発生する最大相当塑性ひずみの関係を説明する図である。FIG. 6 is a diagram for explaining a relationship between a thickness in a vertical direction (perpendicular to a radial direction) of the restraint member 8 and a maximum equivalent plastic strain generated in the joining members 2 and 4. 接合部材２，４の厚さに対する、リード電極鍔部３ｂおよびチップ下電極鍔部５ａの厚さの比と、接合部材２，４に発生する最大相当塑性ひずみの関係を説明する図である。FIG. 6 is a diagram for explaining the relationship between the ratio of the thickness of the lead electrode flange 3b and the chip lower electrode flange 5a to the thickness of the bonding members 2 and 4 and the maximum equivalent plastic strain generated in the bonding members 2 and 4; 従来の半導体装置を示す図である。It is a figure which shows the conventional semiconductor device. 常温時と熱膨張時のリード電極３を示す。The lead electrode 3 at the time of normal temperature and thermal expansion is shown.

符号の説明Explanation of symbols

１…半導体チップ（Ｓｉ）、２，４，６，１２，１３…接合部材（Ｐｂ−Ｓｎ系高温はんだ）、３…リード電極（Ｃｕ）、３ａ…リード電極ヘッダ部（Ｃｕ）、３ｂ…リード電極鍔部（Ｃｕ）、５…チップ下電極（Ｃｕ）、５ａ…チップ下電極鍔部（Ｃｕ）、７…ケース電極（Ｃｕ）、８…拘束材（Ｍｏ）、９…絶縁部材（シリコーンゴム）、１０，１１…緩衝板（ＣＩＣ）。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip (Si), 2, 4, 6, 12, 13 ... Joining member (Pb-Sn high temperature solder), 3 ... Lead electrode (Cu), 3a ... Lead electrode header part (Cu), 3b ... Lead Electrode flange (Cu), 5 ... Chip lower electrode (Cu), 5a ... Chip lower electrode flange (Cu), 7 ... Case electrode (Cu), 8 ... Restraint material (Mo), 9 ... Insulating member (silicone rubber) ) 10, 11 ... Buffer plate (CIC).

Claims (10)

半導体チップと、ヘッダ部を有し、リード部に接続されるリード電極と、前記半導体チップと前記ヘッダ部を接合する第一の接合部材と、前記半導体チップの前記リード電極の反対側に電気的に連絡されるケース電極とを備え、
前記ヘッダ部の周囲に、前記ヘッダ部よりも線膨張係数の小さい拘束材を配置し、前記拘束材の下端は、前記リード電極の下端よりも上になるように配置することを特徴とする半導体装置。 A semiconductor chip, a lead electrode having a header portion, connected to the lead portion, a first joining member for joining the semiconductor chip and the header portion, and an electrical side opposite to the lead electrode of the semiconductor chip And a case electrode to be contacted,
A restraint material having a smaller linear expansion coefficient than the header portion is disposed around the header portion, and a lower end of the restraint material is disposed so as to be higher than a lower end of the lead electrode. apparatus. 請求項１に記載の半導体装置において、
前記リード電極は、下面を共有する鍔部をその周囲に有し、前記拘束材は、前記鍔部に接して前記鍔部の上側に配置されていることを特徴とする半導体装置。 The semiconductor device according to claim 1 ,
2. The semiconductor device according to claim 1, wherein the lead electrode has a flange part sharing the lower surface in the periphery thereof, and the restraining material is disposed on the upper side of the flange part in contact with the flange part. 請求項１に記載の半導体装置において、
前記リード電極は、第一の領域と、前記第一の領域の前記半導体チップ側に位置し、径が前記第一の領域の径よりも大きい第二の領域を有し、前記拘束材は、前記第一の領域の周囲に、前記第二の領域の上面に接して設けられていることを特徴とする半導体装置。 The semiconductor device according to claim 1 ,
The lead electrode has a first region and a second region located on the semiconductor chip side of the first region and having a diameter larger than the diameter of the first region. A semiconductor device is provided around the first region and in contact with the upper surface of the second region. 請求項１に記載の半導体装置において、
前記リード電極または前記リード電極の第一の領域の径は、前記半導体チップの径の１〜１.０５倍であることを特徴とする半導体装置。 The semiconductor device according to claim 1 ,
The diameter of the lead electrode or the first region of the lead electrode is 1 to 1.05 times the diameter of the semiconductor chip. 請求項１乃至３のいずれかに記載の半導体装置において、
前記拘束材は、径方向の厚さが、前記リード電極または前記リード電極の第一の領域の径の１５％以上であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 3 ,
The restraint member has a radial thickness of 15% or more of the diameter of the lead electrode or the first region of the lead electrode. 請求項１乃至３のいずれかに記載の半導体装置において、
前記拘束材は、軸方向の厚さが、前記リード電極のヘッダ部の厚さよりも薄いことを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 3 ,
The semiconductor device according to claim 1, wherein the restraining material has a thickness in an axial direction smaller than a thickness of a header portion of the lead electrode. 請求項１乃至６のいずれかに記載の半導体装置において、
前記半導体チップと前記ケース電極の間に設けられたチップ下電極と、前記ケース電極と前記チップ下電極とを接合する第三の接合部材とを備え、前記チップ下電極の周囲に、前記チップ下電極よりも線膨張係数が小さい拘束材を備えたことを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 6,
A chip lower electrode provided between the semiconductor chip and the case electrode; and a third bonding member for bonding the case electrode and the chip lower electrode; A semiconductor device comprising a constraining material having a smaller linear expansion coefficient than an electrode. 請求項７に記載の半導体装置において、
前記リード電極の前記半導体チップ側及びその周囲の拘束材と、前記チップ下電極の半導体チップ側及びその周囲の拘束材は、同一の材料及び形状であることを特徴とする半導体装置。 The semiconductor device according to claim 7 ,
And the semiconductor chip side and the restraining material surrounding the lead electrode, restraint material of the semiconductor chip side and around the tip lower electrode, a semiconductor device which is a same material and shape. 請求項１乃至８のいずれかに記載の半導体装置において、
前記拘束材は、金属製であることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 8,
The semiconductor device, wherein the restraining material is made of metal. 請求項１乃至９のいずれかに記載の半導体装置において、
前記拘束材は、モリブデン，タングステン，鉄−ニッケル合金のいずれかを主原料とすることを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 9,
The restraint material is made of any one of molybdenum, tungsten, and iron-nickel alloy as a main material.
JP2006120033A 2006-04-25 2006-04-25 Semiconductor device Expired - Fee Related JP4720600B2 (en)

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JP2004363225A (en) * 2003-06-03 2004-12-24 Nissan Motor Co Ltd Stacked semiconductor device
JP2005072351A (en) * 2003-08-26 2005-03-17 Nissan Motor Co Ltd Semiconductor device and manufacturing method thereof
JP2005340267A (en) * 2004-05-24 2005-12-08 Hitachi Ltd Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591165A (en) * 1978-12-28 1980-07-10 Fujitsu Ltd Microwave ic

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5591165U (en) * 1978-12-19 1980-06-24
JP2004363225A (en) * 2003-06-03 2004-12-24 Nissan Motor Co Ltd Stacked semiconductor device
JP2005072351A (en) * 2003-08-26 2005-03-17 Nissan Motor Co Ltd Semiconductor device and manufacturing method thereof
JP2005340267A (en) * 2004-05-24 2005-12-08 Hitachi Ltd Semiconductor device

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