JP4701949B2 - Phase information generating apparatus, phase information generating method, transmitter and receiver - Google Patents

Description

  The present invention relates to a phase information generating apparatus, a phase information generating method, a transmitter, and a receiver that are suitable for application to an optical communication system or the like.

  Specifically, the present invention obtains the phase information for generating the phase modulation signal based on the next level stage of the n-value multilevel signal, the current phase and the previous phase, and the current phase. By determining the next phase so that the phase difference becomes a value corresponding to the next level step of the n + 1 value multi-level signal whose level step changes every clock, the n-value multi-level signal is converted into noise. The present invention relates to a phase information generating apparatus and the like that can transmit without requiring a complicated synchronization circuit with little influence.

  With the development of society, the amount of communication continues to increase. Accordingly, there is an increasing demand for a higher communication speed, that is, an increase in bandwidth in a single communication path. There are various obstacles for realizing high speed.

  For example, an obstacle for realizing high speed is S / N. In optical communications, the amount of signal is determined by the capabilities of the light emitting device and eye safety, and does not depend on the bandwidth. However, the noise power is directly proportional to the band. In other words, when the bandwidth is increased 10 times from 10 Gbps to 100 Gbps, if the signal output remains 1 mW in consideration of eye safety, the noise component will have 10 times the energy, and the S / N will be degraded by 10 dB. Will end up. In addition, when the modulation method is such that the signal component extends to the low range, as in normal NRZ (non-return-to-zero) modulation, it is difficult to cut the low range by applying a band limit, resulting in large noise. S / N becomes worse.

  Further, for example, a failure for realizing high speed is synchronization. For accurate signal transmission, a clock must be sent to synchronize the information bits, but this way of sending is a problem. There are two methods that are often used at present.

  One is called an external clock, and provides a dedicated line for the clock in addition to the data line. This enables accurate clock transmission, but requires an extra clock line. Also, when the number of data lines increases, a difference in arrival time, called bit skew, occurs due to variations in responsiveness of transmission / reception devices, variations in transmission line length, etc. Not suitable for high-speed transmission.

  The other is called an internal clock, which performs modulation such as 4B / 5B, 8B / 10B, etc. on the data so that the same data does not continue and reliably transmits the clock component. This method is used for PCI-Express, Gigabit Ethernet (GbE), etc., to extend the distance. Ethernet is a registered trademark.

  However, since a clock component is inserted, redundancy is required, and in the case of 4B / 5B and 8B / 10B, 1.25 times as much data as the original data must be sent. Further, a PLL (Phase-Locked Loop) circuit is required for each line for clock extraction. In a high-speed communication path exceeding 10 Gbps, it is very difficult to implement this PLL circuit.

  Patent Document 1 describes a technique for obtaining a ternary signal whose amplitude level always changes every clock based on binary signals of 0 and 1. Here, in addition to a low level signal and a high level signal corresponding to 0 and 1, respectively, a third level signal different from these is set. The level signal is applied.

  Thus, according to the ternary signal whose amplitude level always changes every clock, it is not necessary to provide a dedicated line for the clock as in the case of an external clock, and the arrival time of the multilevel signal and the clock becomes a problem. There is no need to use an expensive clock recovery circuit such as a PLL circuit as in the case of an internal clock. For example, a clock recovery circuit can be configured with an inexpensive differentiation circuit, and further, as in 4B / 5B and 8B / 10B. It is not necessary to add 25% redundancy to generate the clock component.

  Note that, in amplitude modulation and phase modulation, generally, S / N is better in phase modulation than in FM radio, as in FM radio. In the field of coherent optical communication, it is known that even with π / 2 phase modulation, there are fewer misidentifications than 0 and 1 amplitude modulation (see Non-Patent Document 1, for example).

JP-A-55-10256 Kazuo Kikuchi, “Fundamentals of optical fiber communication”, Shosodo, May 8, 1997 (Chapter 7.4 “Code Error Rate in Coherent Systems”)

  In the technique described in Patent Document 1 described above, when 0 or 1 continues, the third level signal is applied to the even-numbered one. Therefore, in a multi-level modulation device that obtains a ternary signal based on a binary signal, whether the clock before the binary signal is 0 or 1 and whether it is an odd or even number of 0 and 1 It is necessary to remember whether it is. Therefore, although not described in Patent Document 1, it seems that the circuit configuration of the multi-level modulation device is complicated. Note that this Patent Document 1 does not mention anything about the phase modulation signal, and therefore does not completely disclose how to control the modulation phase in relation to the ternary signal based on the binary signal. Not.

  An object of the present invention is to make it possible to transmit an n-value multilevel signal with little influence of noise and without requiring a complicated synchronization circuit.

The concept of this invention is
Based on an n-value multilevel signal having n (n is an integer greater than or equal to 2) level steps, it corresponds to an n + 1 value multilevel signal having n + 1 level steps whose level steps change every clock. A phase information generator for generating phase information when generating a phase modulation signal,
Based on the next level stage of the n-value multilevel signal, the current phase and the previous phase, the phase difference from the current phase becomes a value corresponding to the next level stage of the n + 1-value multilevel signal. Thus, the phase information generating apparatus includes a phase information generating unit that determines the next phase and generates information on the next phase.

The concept of the present invention is
Corresponds to n + 1 value multilevel signal with n + 1 level steps generated based on n value multilevel signal having n level steps (n is an integer of 2 or more). And the phase of the predetermined clock position is modulated so that the phase difference from the previous clock phase becomes a value corresponding to the level step of the predetermined clock position of the n + 1 value multilevel signal. A phase detector for obtaining the n + 1-valued multilevel signal from:
And a decoder for generating an n-value multilevel signal having the n level steps based on the n + 1-value multilevel signal obtained by the phase detector.

  In the present invention, phase information for generating a phase modulation signal is generated based on an n-value multilevel signal having n (n is an integer of 2 or more) level steps. That is, the phase modulation signal in this case relates to an n-value multilevel signal. The phase modulation signal corresponds to an n + 1 value multilevel signal having n + 1 level steps whose level steps change every clock. Eventually, this phase modulation signal is the same as that obtained by converting an n-value multi-value signal into an n + 1-value multi-value signal and phase-converting the converted n + 1-value multi-value signal.

The width of the n-level multi-level signal in the level stage and the width of the n + 1-level multi-level signal in the level stage may be the same or different. For example, an n-value multilevel signal is a 2 ^m- value (m is an integer equal to or greater than 1) multi-value signal and is composed of m-bit data, and an n + 1-value multivalue signal is 2 ^m + 1-value. It is a multi-level signal and is composed of m + 1 bit data. The m-bit data can be obtained, for example, by extracting input serial data every m bits.

  For example, the level stage of a predetermined clock position of an n + 1-valued multilevel signal is set to a level level of a predetermined clock position of an n-valued multilevel signal as a first level stage, and is 1 from a predetermined clock position of an n + 1-valued multilevel signal. When the level stage before the clock is set as the second level stage, the first level stage is the same as the second level stage when the first level stage is smaller than the second level stage. Alternatively, when it is greater than the second level step, it is set to a level step that is one greater than the first level step. As a result, the multi-level signal of (n + 1) value changes in level level every clock.

  In the present invention, based on the next level stage of the n-value multilevel signal, the current phase and the previous phase, the phase difference from the current phase corresponds to the next level stage of the n + 1-value multilevel signal. The next phase is determined to be a value. By determining the next phase in this way, a phase-modulated signal corresponding directly to the n + 1-value multivalue signal is obtained from the n-value multivalue signal without converting it into an n + 1 value multivalue signal. Phase information is obtained.

  For example, the phase information is converted into a control voltage for controlling the modulation phase in the phase modulator for obtaining the phase modulation signal. In this case, when there are a plurality of phases whose phase difference from the current phase is a value corresponding to the next level step of the n + 1-valued multilevel signal, there is little change in the control voltage, or the value of the control voltage is The smaller phase is set as the next phase. This makes it possible to increase the operation speed and suppress power consumption.

  In the transmitter, for example, a signal having a continuous phase output from a signal source is phase-modulated by a phase modulator, whereby a transmission phase modulation signal is obtained. In this case, when the signal source is a light source, the phase modulation signal is an optical signal. The phase information described above is used as phase information for controlling the modulation phase in this phase modulator. As a result, it is possible to transmit a phase modulation signal corresponding to an n + 1-value multilevel signal whose level level changes every clock according to the n-value multilevel signal.

  In the receiver that receives the phase modulation signal transmitted in this way, an n + 1 value multilevel signal is obtained from the received phase modulation signal by the phase detector. For example, when the phase modulation signal is an optical signal, homodyne detection is performed. The n + 1-value multilevel signal is converted into an n-value multilevel signal by a decoder.

For example, an n + 1 value multi-value signal is a 2 ^m +1 value multi-value signal and is composed of m + 1 bit data, and an n-value multi-value signal is a 2 ^m value multi-value signal, and m Composed of bit data. The m-bit data is converted into output serial data, for example.

  In the decoder, as described above, the level stage at the predetermined clock position of the n + 1 value multilevel signal is set to the first level stage at the predetermined clock position level of the n value multilevel signal, and the n + 1 value multilevel signal is output. When the level stage one clock before the predetermined clock position is set as the second level stage, the first level stage is defined as the first level stage when the first level stage is smaller than the second level stage. If the level level is equal to or larger than the second level level and one level level higher than the first level level, for example, the following values (1) and (2) A multilevel signal is obtained.

  (1) The first level stage, which is the current level stage of the n + 1 value multilevel signal, is compared with the second level stage, which is the level stage one clock before the n level multilevel signal. When an n + 1 multilevel signal is composed of m + 1 bit data and an n value multilevel signal is composed of m bit data, the first value that is the current value of the m + 1 bit data and the m bit The second value which is a value one clock before the data is compared.

  Then, based on the comparison result between the first level stage and the second level stage, the current level stage of the n-value multilevel signal is determined. Here, when the first level stage is larger than the second level stage, the level stage one smaller than the first level stage is set as the current level stage of the n-value multilevel signal. When the first level stage is the same as the second level stage or smaller than the second level stage, the first level stage is set as the current level stage of the n-value multilevel signal.

  When the n + 1 value multilevel signal is composed of m + 1 bit data and the n value multilevel signal is composed of m bit data, m is determined based on the comparison result between the first value and the second value. The current value of the bit data is determined. Here, when the first value is larger than the second value, 1 is subtracted from the first value to obtain the current value of the m-bit data. When the first value is the same as the second value or smaller than the second value, the first value is directly used as the current value of the m-bit data.

  (2) The n + 1-valued multilevel signal is compared with the first to n-1th threshold values among the first to nth threshold values that are sequentially increased to identify n + 1 level stages. As a result, m-bit data related to the (n + 1) -value multilevel signal is obtained. Further, the n + 1 value multilevel signal is compared with the nth threshold value. When the n + 1 value multilevel signal is equal to or higher than the nth threshold value, the first level is obtained. When is less than the nth threshold value, a control signal having a second level is obtained.

  The first value that is the current value of the m-bit data related to the above-described n + 1 value multi-value signal and the second value that is the value one clock before the m-bit data constituting the n-value multi-value signal Are compared. Then, based on the comparison result between the first value and the second value and the control signal, the current value of the m-bit data constituting the n-value multi-value signal is determined. Here, when the first value is larger than the second value and the control signal is at the second level, 1-bit is subtracted from the first value, and m-bit data constituting an n-value multilevel signal. The current value of. When the first value is greater than the second value and the control signal is at the first level, or when the first value is the same as the second value or less than the second value, the first value The current value is the current value of m-bit data constituting an n-value multilevel signal.

  In the process (2), the maximum level stage of the n + 1-valued multilevel signal and the next level stage are handled together, and the number of bits required for the process can be set to m bits instead of m + 1 bits. One bit can be saved.

  Thus, based on the n-level multilevel signal, it is possible to generate phase information when generating the phase modulation signal corresponding to the n + 1-level multilevel signal whose level level changes every clock. Therefore, using this phase information, an n-value multilevel signal is converted into an n + 1-value multilevel signal, and a phase-modulated signal equivalent to a phase-modulated version of the converted n + 1-value multilevel signal is obtained. The transmitter can transmit this phase modulated signal. The receiver that has received the phase modulation signal obtains an n + 1 value multilevel signal whose level level changes every clock from the phase modulation signal, and further processes the n + 1 value multilevel signal to obtain an n value. Multi-level signals can be obtained.

  In this case, since the signal is transmitted in the form of a phase modulation signal, the receiver can obtain an n + 1 value phase modulation signal with less noise. In addition, the n + 1-value multilevel signal changes in level level every clock, and an n-value multilevel signal can be generated without requiring a complicated synchronization circuit.

  According to the present invention, when obtaining phase information for generating a phase-modulated signal, the position of the current phase is determined based on the next level stage, the current phase, and the previous phase of the n-value multilevel signal. The next phase is determined so that the phase difference becomes a value corresponding to the next level step of the n + 1 value multi-level signal whose level step changes every clock. It is less affected and can be transmitted without the need for a complicated synchronization circuit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, the transmitter 100 will be described. FIG. 1 shows the configuration of the transmitter 100. The transmitter 100 includes a light source 101, a phase modulator 102, an optical fiber 103, and a signal phase converter 104. The light source 101 outputs an optical signal (continuous light) Sop having a continuous phase. As this optical signal Sop, for example, one having a wavelength of 1.5 μm, 1.3 μm, 800 nm or the like can be used.

  The phase modulator 102 performs phase modulation on the optical signal Sop from the light source 101 to obtain a phase modulation signal Spm to be transmitted through the optical fiber 103. The phase modulator 102 is configured using a conventionally known nonlinear optical crystal such as lithium niobate (LN). In this case, when the control voltage Vct corresponding to the phase information from the signal phase converter 104 is applied to the nonlinear optical crystal, the refractive index of the nonlinear optical crystal changes, and the phase at the emission time of the nonlinear optical crystal is changed. Becomes a phase corresponding to the phase information, and the phase modulation signal Spm can be obtained.

  The signal phase converter 104 is based on the input serial data Din input to the data input terminal 105 and the clock CL synchronized with each bit of the input serial data Din input to the clock input terminal 106 described above. Phase information for controlling the modulation phase at 102 is generated, and this phase information is converted into a control voltage Vct and output.

  FIG. 2 shows a detailed configuration of the signal phase converter 104.

  The signal phase converter 104 has a shift register 141 and a 1 / m frequency divider 142. The shift register 141 constitutes a data converter, sequentially shifts the input serial data Din input to the input terminal 105 with the clock CL, and outputs m-bit (m is an integer of 1 or more) data. In this case, when m is 1, m-bit data is serial data like the input serial data Din, and when m is 2 or more, m-bit data is parallel data. The 1 / m frequency divider 142 divides the clock CL input to the clock input terminal 106 by 1 / m, and acquires the clock CLm corresponding to each m bits of the input serial data Din.

The signal phase converter 104 includes a latch circuit 143, a code generator 144, and a latch circuit 145 that constitute a phase information generation unit. The phase information generation unit converts m-bit data M constituting an n-value multi-value signal into m + 1-bit data A constituting an n + 1-value multi-value signal whose value changes every clock. Phase information Ipm is generated to obtain a phase modulation signal similar to that obtained when the data A is phase modulated. Note that n = 2 ^m .

  Here, the conversion from the data M to the data A is performed as follows.

  For example, when m = 1, processing for obtaining the next value At + 1 of the data of m + 1 bits (2 bits) is performed according to the conversion map (encoding) shown in FIG. In FIG. 3, V-, V0, and V + indicate m + 1 bit data values, 0 and 1 indicate m bit data values, and "pre" indicates the current value At of m + 1 bit data. ing.

  In the case of At = V−, when Mt + 1 = 0, At + 1 = V0, and when Mt + 1 = 1, At + 1 = V +. When At = V0, At + 1 = V− when Mt + 1 = 0, At + 1 = V + when Mt + 1 = 1. Further, when At = V +, At + 1 = V− when Mt + 1 = 0, At + 1 = V0 when Mt + 1 = 1.

  Further, for example, when m = 2, processing for obtaining the next value At + 1 of the data of m + 1 bits (3 bits) is performed according to the conversion map (encoding) shown in FIG. In FIG. 4, V-2, V-1, V0, V1, and V2 indicate m + 1 bit data values, 0, 1, 2, and 3 indicate m bit data values, and "pre" indicates m + 1. The current value At of the bit data is shown.

  When At = V-2, At + 1 = V-1 when Mt + 1 = 0, At + 1 = V0 when Mt + 1 = 1, and Mt + 1 = 2. In this case, At + 1 = V1, and when Mt + 1 = 3, At + 1 = V2. Further, when At = V-1, when Mt + 1 = 0, At + 1 = V-2, when Mt + 1 = 1, At + 1 = V0, and Mt + 1 = 2. When At, At + 1 = V1, and when Mt + 1 = 3, At + 1 = V2. When At = V0, At + 1 = V-2 when Mt + 1 = 0, At + 1 = V-1 when Mt + 1 = 1, and Mt + 1 = 2. When At, At + 1 = V1, and when Mt + 1 = 3, At + 1 = V2. Further, when At = V1, when Mt + 1 = 0, At + 1 = V-2, when Mt + 1 = 1, At + 1 = V-1, and Mt + 1 = 2. When At, At + 1 = V0. When Mt + 1 = 3, At + 1 = V2. Further, when At = V2, At + 1 = V-2 when Mt + 1 = 0, At + 1 = V-1 when Mt + 1 = 1, and Mt + 1 = 2. When At, At + 1 = V0. When Mt + 1 = 3, At + 1 = V1.

  Further, a phase transition is required on the transmitter side so that the output of the phase detector can perform the above-described data A transition on the receiver side. Here, on the receiver side, for example, a phase detector 202 shown in FIG. 5 is used as a phase demodulator that demodulates the phase modulation signal and obtains M + 1 bit data. The phase detector 202 converts the phase difference into a voltage value by homodyne detection.

  That is, the phase modulation signal Spm is branched by the beam splitter 221 into two optical paths (arms). One optical signal Spm 1 is reflected by the mirror 222 and enters the beam splitter 223. The other optical signal Spm2 is sequentially reflected by the mirrors 224, 225, and 226, is delayed by one clock time, and enters the beam splitter 223.

  In this beam splitter 223, the wave of the optical signal Spm1 interferes with the wave of the optical signal Spm2 delayed by one clock time. In FIG. 5, the beam splitters 221 and 223 represent the side shifted by π phase due to reflection as a black dot. Here, when the branching ratio in the beam splitters 221 and 223 is 50:50, the complex amplitude of the optical signals Spm1 and Spm2 is a, and the phase difference is θ, the output IA of the photodetector 227 is (1). The output IB of the photodetector 228 is expressed by equation (2), and the output of the subtractor 229, that is, the output V (IA-IB) of the phase detector 202 is expressed by equation (3). Is done.

  Thus, the output V of the phase detector 202 has a relationship of V∝cos θ with respect to the phase difference θ. Therefore, for example, when m = 1, in order to output the above three values V-, V0, and V +, as shown in FIG. 6, 0 degrees, 90 degrees (π / 2), and 180 degrees It is sufficient to prepare four types of phase differences of (π) and −90 degrees (−π / 2).

  Here, a 2-bit code as shown in FIGS. 7A and 7B is assigned to each phase value. This is introduced in order to make the coding for generating the phase difference easy to understand. The Hamming distance of this code (a different number of 0 and 1 at each bit position) is an integral multiple of 90 degrees when four types of phases are output. Here, “00” is assigned to 0 degrees, “01” is assigned to 90 degrees, “11” is assigned to 180 degrees, and “10” is assigned to −90 degrees.

  Further, for example, when m = 2, in order to output the above five values V-2, V-1, V0, V1, and V2, as shown in FIG. 8, 0 degrees and 45 degrees (π / 4), 90 degrees (π / 2), 135 degrees (3π / 4), 180 degrees (π), -45 degrees (-π / 4), -90 degrees (-π / 2), -135 degrees (- It is sufficient to prepare a phase difference of 3π / 4).

  Here, a 4-bit code as shown in FIGS. 9A and 9B is assigned to each phase value. The Hamming distance of this code (a different number of 0 and 1 at each bit position) is an integral multiple of 45 degrees when eight types of phases are output. Here, “0000” at 0 degrees, “0001” at 45 degrees, “0011” at 90 degrees, “0111” at 135 degrees, “1111” at 180 degrees, −45 "1000" is assigned to the degree, "1100" is assigned to -90 degrees, and "1110" is assigned to -135 degrees.

  Generally, when n types (n is a multiple of 2) of phases are output, the number of bits of this code is n / 2, and the Hamming distance of this code is 180 / n degrees.

  As described above, the phase information generation unit including the latch circuit 143, the code generator 144, and the latch circuit 145 is for obtaining a phase modulation signal corresponding to the m + 1 bit data A obtained by converting the m bit data M. Phase information Ipm is generated. Here, the phase information generating unit generates the phase information Ipm directly from the m-bit data M without converting the m-bit data M into the m + 1-bit data A.

  The latch circuit 143 latches the m-bit data obtained by the shift register 141 with the clock CLm obtained by the 1 / m frequency divider 142 and acquires the m-bit data M. The m-bit data M is composed of m-bit data obtained by dividing the input serial data Din into m bits.

  The latch circuit 145 latches the code CDa indicating the phase output from the code generator 144 based on the clock CLm obtained by the 1 / m frequency divider 142. In this case, when the code CDa generated by the code generator 144 indicates the current phase, the output code CDb of the latch circuit 145 indicates the phase one clock before.

  The code generator 144 is composed of, for example, a ROM table, and is based on the m-bit data M output from the latch circuit 143, the generated code CDa of the code generator 144, and the output code CDb of the latch circuit 145. In synchronization with the clock CLm obtained by the frequency divider 142, a new code is generated as the code CDa. That is, the code generator 144 generates a code CDa indicating the next phase based on the next value of the m-bit data M, the current phase and the previous phase.

  The code table of FIG. 10 shows the relationship between the next phase generated by the code generator 144 and the next value of the m-bit data M, the current phase and the previous phase when m = 1. Show. In this code table, the first column corresponds to the previous phase, the second column corresponds to the current phase, and the fifth or seventh column depending on whether the next value of the data M is 1 or 0 The next phase is generated. The items required in this code table are columns 1, 2, 5, and 7. However, in the code table, the phase detection output (reception voltage) of the receiver at that time is shown in columns 3, 4 and 6 for easy understanding.

  In the code table of FIG. 10, for example, a case where the previous phase is “00” and the current phase is “00” is considered. Since the reception voltage at this time is V +, when the next value of the data M is 1, 0, the reception voltage must be V0, V-, respectively (see FIG. 3). The output of V0 is given by a phase difference of 90 degrees or -90 degrees (see FIG. 6). Therefore, when the next value of the data M is 1, the next phase is “00”, so that when the Hamming distance is 1, the next phase is “01” or “10”. Further, the output of V− is given by a phase difference of 180 degrees (see FIG. 6). Therefore, when the next value of the data M is 0, the next phase is “00”, so that the Hamming distance is “11” because the current phase is “00”. The same applies to the following cases.

  11 and 12 show the case where m = 2, and the next phase generated by the code generator 144, the next value of the m-bit data M, the current phase, and the previous phase. The relationship with the phase is shown. In this code table, the first column corresponds to the previous phase, the second column corresponds to the current phase, and depending on whether the next value of the data M is 00, 01, 10 or 11, the fifth column , The next phase of the seventh, ninth or eleventh column is generated. The items required in this code table are columns 1, 2, 5, 7, 9, and 11. However, in the code table, the phase detection output (reception voltage) of the receiver at that time is shown in columns 3, 4, 6, 8, and 10 for easy understanding.

  In the code tables of FIG. 11 and FIG. 12, for example, the case where the previous phase is “0000” and the current phase is “0000” is considered. Since the reception voltage at this time is V2, when the next value of the data M is 00, 01, 10, and 11, the reception voltage must be V-2, V-1, V0, and V1, respectively. (See FIG. 4).

  The output of V-2 is 180 degrees from the current phase (see FIG. 8). Therefore, when the next value of the data M is 00, the next phase is “0000”, so that the Hamming distance is “1111” when the Hamming distance is 4. The output of V-1 is given by a phase difference of 135 degrees or -135 degrees (see FIG. 8). Therefore, when the next value of the data M is 01, the next phase is “0000”, so that the Hamming distance is 3 and becomes “0111” or “1110”.

  The output of V0 is given by a phase difference of 90 degrees or -90 degrees (see FIG. 8). Therefore, when the next value of the data M is 10, the next phase is “0000”, so that when the Hamming distance is 2, the next phase is “0011” or “1100”. Also, the output of V1 is given by a phase difference of 45 degrees or -45 degrees (see FIG. 8). Therefore, when the next value of the data M is 11, the next phase is “0000”, so that the hamming distance is 1 and becomes “0001” or “1000”.

  The same applies to the following cases.

As described above, when m = 1, the four phases are represented by 2-bit codes, and when m = 2, the eight phases are represented by 4-bit codes. In general, when m-bit data M is handled, it means that 2 ^{(m + 1)} types of phases are represented by 2 ^m- bit codes. This is because the Hamming distance is used for easy understanding. However, if it is redundant and there is a code transition table, it can be compressed to m + 1 bits. For example, FIG. 13 shows an example of transition between a 4-bit code and a 3-bit compressed code when m = 2.

  Further, the code table in the case of m = 1 and the code table in the case of m = 2 show all cases where transition is possible as the next phase. However, considering the high-speed operation in the phase modulator 102, it is better that the difference between the current phase and the next phase is small. In this case, the amount of change in the control voltage Vct described above can be reduced.

  For example, consider the transition from the current phase “00” to the next phases “01” and “10” in the code table for m = 1 shown in FIG. A code / voltage converter 146, which will be described later, controls 0, Va, Vb, and Vc, respectively, as shown in FIG. 14, corresponding to the codes “00”, “01”, “11”, and “10”. Output as voltage Vct. In this case, in response to the code “10” corresponding to −90 degrees (−π / 2), the control voltage Vc for actually setting the phase to 270 degrees (3π / 2) is output. This is because the control voltage Vct is required to be changed in a positive voltage range in order to simplify the circuit configuration. Therefore, when transitioning from the current phase “00” to the next phase “01” or “10”, it is desirable to transition to “01” in which the amount of change in the control voltage Vct is small.

  There is also a request to reduce average power. For example, consider the transition from the current phase “11” to the next phases “01” and “10” in the code table for m = 1 shown in FIG. In this case, the amount of change in the control voltage Vct is the same, but the magnitude of the control voltage Vct itself is smaller in the phase “01” than in the phase “10”. Therefore, when transitioning from the current phase “11” to the next phase “01” or “10”, it is desirable to transition to “01” in which the control voltage Vct is small and the average power is small. It will be.

  In FIG. 15, as described above, when there are a plurality of options, the one having the smaller change amount of the control voltage Vct is selected, and when the change amount of the control voltage Vct is the same, the control voltage Vct is small. An improved code table obtained by selecting one is shown. Note that improvements to the code tables of FIGS. 11 and 12 when m = 2 can be similarly performed. By using such an improved code table, it is possible to reduce the amount of change in the control voltage Vct, speed up the operation, and suppress power consumption.

  Returning to FIG. 2, the signal phase converter 104 has a code / voltage converter 146 constituting a control voltage converter. The code / voltage converter 146 controls the phase information Ipm based on the phase information Ipm, which is the output code CDb of the latch circuit 145, to control the modulation phase in the phase modulator 102 (see FIG. 1). Convert to Vct. For example, when m = 1, as shown in FIG. 14, the codes “00”, “01”, “11”, and “10” constituting the phase information Ipm are set to voltages 0, Va, Vb, and Vc, respectively. Converted. For example, when m = 2, as shown in FIG. 16, the codes “0000”, “0001”, “0011”, “0111”, “1111”, “1110”, “1100” constituting the phase information Ipm. , “1000” are converted to voltages 0, Va ′, Va, Vb ′, Vb, Vc ′, Vc, and Vd ′, respectively.

  Next, the operation of the signal phase converter 104 shown in FIG. 2 will be described.

  The input serial data Din is input to the data input terminal 105, and the clock CL synchronized with each bit of the input serial data Din is input to the clock input terminal 106. The input serial data Din and the clock CL are supplied to the shift register 141. In the shift register 141, the input serial data Din is sequentially shifted by the clock CL, and data of m bits (m is an integer of 1 or more) is output. The m-bit data is supplied to the latch circuit 143.

  The clock CL input to the clock input terminal 106 is supplied to the 1 / m frequency divider 142. The 1 / m frequency divider 142 divides the clock CL by 1 / m to obtain a clock CLm corresponding to each m bits of the input serial data Din. The clock CLm is supplied to the latch circuits 143 and 145, the code generator 144 and the code / voltage converter 146.

  In the latch circuit 143, m-bit data supplied from the shift register 141 is latched by the clock CLm, and consists of m-bit data obtained by dividing the input serial data Din into m bits. M is obtained. The m-bit data M is input to the code generator 144.

  The code CDa generated by the code generator 144 is supplied to the latch circuit 145 and latched by the clock CLm. In this case, when the code CDa indicates the current phase, the code CDb latched and output by the latch circuit 145 indicates the phase one clock before. The code CDa generated by the code generator 144 and the code CDb output from the latch circuit 145 are input to the code generator 144.

  The code generator 144 generates a new code as the code CDa in synchronization with the clock CLm based on the m-bit data M and the codes CDa and CDb. That is, the code generator 144 generates a code CDa indicating the next phase based on the next value of the m-bit data M, the current phase and the previous phase.

  The code CDb output from the latch circuit 145 is supplied to the code / voltage converter 146 as phase information Ipm generated by the phase information generator. This phase information Ipm is phase information Ipm for obtaining a phase modulation signal corresponding to m + 1 bit data A whose value changes every clock after converting m bit data M. In the code / voltage converter 146, the phase information Ipm is converted into a control voltage Vct for controlling the modulation phase in the phase modulator 102 (see FIG. 1).

FIG. 17 shows the transition of the current value Mt of the m-bit data M, the current value At of the m + 1-bit data A, the phase (code) constituting the phase information Ipm, and the control voltage Vct when m = 1. An example is shown. Note that the value A0 of the data A at t = 0 is 2 ^m = 2. FIG. 18 shows the current value Mt of the m-bit data M, the current value At of the m + 1-bit data A, the phase (code) constituting the phase information Ipm, and the control voltage Vct when m = 2. An example of the transition is shown. Note that the value A0 of the data A at t = 0 is 2 ^m = 4. Although detailed description is omitted, even when m = 3 or more, when m = 1, phase information Ipm corresponding to m + 1 bit data A is generated and corresponding to m = 2 as in the case of m = 2. The control voltage Vct thus obtained is obtained.

  Next, the operation of the transmitter 100 shown in FIG. 1 will be described.

  The optical signal Sop output from the light source 101 is incident on the phase modulator 102. Further, the input serial data Din is supplied from the data input terminal 105 to the signal phase converter 104 and the clock CL synchronized with each bit of the input serial data Din is input from the clock input terminal 106.

  In this signal phase converter 104, m-bit data M obtained by dividing the input serial data Din into m bits is converted, and a phase modulation signal corresponding to m + 1 bit data A whose value changes every clock. Is obtained, and a control voltage Vct obtained by further converting the phase information Ipm is obtained. The control voltage Vct is supplied to the phase modulator 102 as a modulation phase control signal.

  In the phase modulator 102, the optical signal Sop is phase-modulated based on the control voltage Vct. The phase modulation signal Spm output from the phase modulator 102 is transmitted to the receiving side through the optical fiber 103.

  As described above, in the transmitter 100 shown in FIG. 1, the m-bit data M constituting the n-value multi-value signal is constituted by the n + 1-value multi-value signal whose value (level stage) changes every clock. The data is converted into m + 1 bit data A and transmitted. Therefore, m-bit data M can be obtained without requiring a complicated synchronization circuit on the receiving side. In this case, it is not necessary to provide a dedicated line for the clock as in the external clock, the arrival time between the multi-level signal and the clock is not a problem, and an expensive clock such as a PLL circuit is required as in the internal clock. There is no need to use a regenerative circuit. For example, a clock regenerative circuit can be configured with an inexpensive differentiation circuit, and 25% redundancy is required to generate a clock component such as 4B / 5B and 8B / 10B. Nor.

  Further, the transmitter 100 shown in FIG. 1 transmits m + 1 bit data A with phase modulation, and the receiving side receives m + 1 bit data A whose level level changes every clock from the phase modulation signal. Therefore, m-bit data M can be obtained well.

  In the transmitter 100 shown in FIG. 1, the signal phase converter 104 determines the phase difference from the current phase based on the next value (level stage) of the m-bit data M, the current phase, and the previous phase. The next phase is determined so that becomes a value corresponding to the next value (level stage) of the data A of m + 1 bits. That is, the phase information Ipm for obtaining the phase modulation signal corresponding to the m + 1 bit data A is obtained directly from the m bit data M without converting it to the m + 1 bit data A. The signal phase converter 104 can be realized with a simple configuration.

  Next, the receiver 200 as an embodiment will be described. FIG. 19 shows the configuration of the receiver 200.

  The receiver 200 includes an optical fiber 201, a phase detector 202, a decoder 203, a clock regenerator 204, and an m multiplier 205.

The phase detector 202 obtains an n + 1 value (2 ^m +1 value) multilevel signal V from the phase modulation signal Spm sent from the transmitter 100 via the optical fiber 201 described above. The phase modulator 202 is configured, for example, as shown in FIG. 5 described above, and is an n + 1-valued multi-value whose level level changes every clock from the phase modulation signal Spm, which is an optical signal, by homodyne detection. A signal V is obtained.

The decoder 203 generates m-bit data M constituting an n-value (2 ^m- value) multi-value signal based on the n + 1-value multi-value signal V obtained by the phase detector 202, and relates to the data M Output serial data Dout is output to the data output terminal 206.

  The clock regenerator 204 regenerates the clock CLm from the m + 1 value multilevel signal obtained by the phase detector 202. As described above, since the level of the data A is always changed every clock as described above, the clock regenerator 204 can be configured by an inexpensive differentiation circuit, for example.

  The m multiplier 205 multiplies the clock CLm reproduced by the clock regenerator 204 by m, acquires the clock CL synchronized with the output serial data Dout, and outputs the clock CL to the clock output terminal 207.

  Note that the clock CLm obtained by the clock regenerator 204 and the clock CL obtained by the m multiplier 205 are respectively supplied to the decoder 203 and used for decoding processing.

  FIG. 20 shows a detailed configuration of the decoder 203.

The decoder 203 has an A / D converter 231. The A / D converter 231 detects a level step in each clock of the n + 1 value (2 ^m +1 value) multilevel signal V, and converts it into m + 1 bit data indicating the level step. That is, the A / D converter 231 samples a signal in each clock of the n + 1 value multilevel signal V with the clock CLm, and converts the signal in each clock into n + 1 level steps in the n + 1 value multilevel signal. Compared with the first to nth threshold values that are sequentially increased for identification, the above-described m + 1-bit data is obtained.

  The decoder 203 includes a latch circuit 232, a subtracter 233, a latch circuit 234, and a comparator 235 that constitute multilevel demodulation means. This multi-level demodulating means obtains m-bit data M constituting an n-value multi-value signal based on m + 1-bit data A constituting an n + 1-value multi-value signal. The m-bit data M corresponds to the m-bit data M output from the latch circuit 143 (see FIG. 2) of the signal phase converter 104 described above.

  The latch circuit 232 latches the m + 1-bit data obtained by the A / D converter 231 based on the clock CLm reproduced by the clock regenerator 204 (see FIG. 19), and m + 1 that forms an n + 1-value multi-value signal. Bit data A is acquired. The latch circuit 234 latches the m-bit data M obtained by the subtracter 233 based on the clock CLm.

  The comparator 235 constitutes a data value comparison means (level stage comparison means). The current value At of the m + 1 bit data A latched by the latch circuit 232 is set as the first value, and the latch circuit 234 A value Mt-1 one clock before the latched m-bit data M is set as a second value, and the first value and the second value are compared. In this case, as described above, the m + 1 bit data A constitutes an n + 1 value multilevel signal, and the m bit data M constitutes an n value multilevel signal. Comparing with the value of 2 means that the first level stage which is the current level stage of the n + 1-valued multi-level signal and the second level stage which is the level stage one clock before the n-valued multi-level signal. Is equivalent to.

  The comparator 235 further outputs 0 or 1 data based on the comparison result between the first value and the second value. In this case, when the first value is larger than the second value (At> Mt−1), the comparator 235 outputs 1 data, and the first value is the same as the second value or the second value. When smaller than the value (At ≦ Mt−1), 0 data is output.

  The subtractor 233 constitutes a calculation means (level stage determination means), and is a 0 or 1 output from the comparator 235 based on the current value At of the m + 1 bit data A latched by the latch circuit 232. The data is subtracted to obtain the current value Mt of m-bit data. In this case, when 0 data is output from the comparator 235, the current value At of the m + 1 bit data A becomes the current value Mt of the m bit data M as it is.

  The multilevel demodulating means including the latch circuit 232, the subtractor 233, the latch circuit 234, and the comparator 235 described above has m bits (1 bit) according to the conversion map (decode) shown in FIG. 3 when m = 1. The current value Mt of the data is obtained. That is, when At = 10, Mt = 1. When At = 01, Mt = Mt-1. Further, when At = 00, Mt = 0.

  Further, the multilevel demodulating means including the latch circuit 232, the subtracter 233, the latch circuit 234, and the comparator 235 described above has m bits (2) according to the conversion map (decode) shown in FIG. 4 when m = 2. The current value Mt of the bit) data is obtained. That is, when At = 100, Mt = 3. When At = 011, Mt = 3 when Mt-1 = 3, and Mt = 2 otherwise. When At = 010, Mt = 1 is set when Mt-1 = 0 or 1, and Mt = 2 is set otherwise. When At = 001, Mt = 0 if Mt-1 = 0, and Mt = 1 otherwise. When At = 000, Mt = 0.

  Returning to FIG. 20, the decoder 203 has a shift register 236. The shift register 236 sequentially shifts each bit data constituting the m-bit data latched by the latch circuit 234 with the clock CLm with the clock CL obtained by the m multiplier 205 (see FIG. 19), and outputs serial data Dout. The output serial data Dout is output to the data output terminal 206.

  The operation of the decoder 203 shown in FIG. 20 will be described.

  The n + 1-value multilevel signal V from the phase detector 202 (see FIG. 19) is supplied to the A / D converter 231. The A / D converter 231 detects the level level of the n + 1-valued multilevel signal V in each clock and converts it to m + 1 bit data indicating the level level. The m + 1 bit data is supplied to the latch circuit 232.

  In the latch circuit 232, the m + 1 bit data supplied from the A / D converter 231 is latched by the clock CLm, and the m + 1 bit data A constituting the n + 1 value multilevel signal is obtained.

  The latch circuit 234 is supplied with m-bit data M obtained by the subtracter 233. In the latch circuit 234, m-bit data M is latched by the clock CLm. The m-bit data M latched by the latch circuit 234 is supplied to the comparator 235.

  In the comparator 235, the first value which is the current value At of the m + 1 bit data A latched by the latch circuit 232, and the value one clock before the m bit data M latched by the latch circuit 234. A second value that is Mt-1 is compared. The comparator 235 outputs 0 or 1 data based on the comparison result between the first value and the second value. That is, when the first value is larger than the second value (At> Mt−1), 1 data is output, and when the first value is equal to or smaller than the second value (At ≦ Mt−1), 0 data is output. In this way, 0 or 1 data output from the comparator 235 is supplied to the subtractor 233.

  In the subtracter 233, 0 or 1 data output from the comparator 235 is subtracted from the current value At of the m + 1 bit data A latched by the latch circuit 234 to obtain the current value of the m bit data. Mt. In this case, when 0 data is output from the comparator 235, the current value At of the m + 1 bit data A is used as it is as the current value Mt of the m bit data M.

  In this case, when the first value is larger than the second value (At> Mt−1), since the data of 1 is output from the comparator 235, 1 is subtracted from the first value and m-bit data It becomes the current value Mt of M. When the first value is the same as the second value or smaller than the second value (At ≦ Mt−1), 0 data is output from the comparator 235, so that the first value is directly m bits. Is the current value Mt of the data M.

  As a result, in the multilevel demodulating means comprising the latch circuit 232, the subtractor 233, the latch circuit 234, and the comparator 235, the n-level multilevel signal is based on the m + 1 bit data A constituting the n + 1-level multilevel signal. Is obtained. The m-bit data M corresponds to the m-bit data M output from the latch circuit 143 (see FIG. 2) of the signal phase converter 100.

FIG. 21 shows the transition of the current value At of the m + 1-bit data A and the current value Mt of the m-bit data M when m = 1. In the comparator 235, 2 ^m −1 = 1 is used as the value Mt at t = 0, that is, M0. As is clear from FIG. 21 and FIG. 17 described above, the m-bit data M obtained by the multilevel demodulation means of the decoder 203 is the m-bit data output from the latch circuit 143 of the signal phase converter 104 described above. It can be seen that it matches the data M.

FIG. 22 shows the transition of the current value At of the m + 1 bit data A and the current value Mt of the m bit data M in the case of m = 2. In the comparator 235, 2 ^m -1 = 3 is used as the value Mt at t = 0, that is, M0. As is apparent from FIG. 22 and FIG. 18 described above, the m-bit data M obtained by the multilevel demodulating means of the decoder 203 is the m-bit data output from the latch circuit 143 of the signal phase converter 104 described above. It can be seen that it matches M.

  Although detailed description is omitted, even when m is 3 or more, when m = 1, as in the case of m = 2, m-bit data M is obtained from m + 1-bit data A. The m-bit data M coincides with the m-bit data M output from the latch circuit 143 of the signal phase converter 104 described above.

  The m-bit data M constituting the n-value multilevel signal output from the latch circuit 234 is supplied to the shift register 236. In the shift register 236, each bit data constituting m-bit data latched by the latch circuit 234 with the clock CLm is sequentially shifted with the clock CL, and output serial data Dout is obtained. The output serial data Dout corresponds to the input serial data Din input to the data input terminal 105 (see FIG. 1) of the transmitter 100. The output serial data Dout is output to the output terminal 206.

  Next, the operation of the receiver 200 shown in FIG. 19 will be described.

The phase modulation signal Spm sent from the transmitter 100 via the optical fiber 201 is incident on the phase detector 202. In this phase detector 202, an n + 1 value (2 ^m +1 value) multilevel signal V whose level level changes every clock is obtained from the phase modulation signal, which is an optical signal, by homodyne detection. The n + 1-value multilevel signal V is supplied to the decoder 203.

  The phase detector 202 regenerates the clock CLm from the m + 1 bit data A obtained by the phase detector 202. This clock CLm is supplied to the decoder 203 and also to the m multiplier 205. The m multiplier 205 multiplies the clock CLm by m to obtain the clock CL. This clock CL is supplied to the decoder 203 and also output to the output terminal 207.

In the decoder 203, the clocks CLm and CL are used for the n + 1-valued multilevel signal V acquired by the phase detector 202, and the decoding process is performed. The decoder 203 generates m-bit data M constituting an n-value (2 ^m value) multi-value signal based on the n + 1 value (2 ^m +1 value) multi-value signal V. The output serial data Dout is output to the data output terminal 206.

  As described above, in the multilevel demodulating means of the decoder 203 shown in FIG. 20, the m-bit data constituting the n-level multilevel signal output from the multilevel demodulating means is the phase of the receiver 200 of FIG. When the phase modulation signal Spm incident on the detector 202 is the phase modulation signal Spm emitted from the phase modulator 102 of the transmitter 100 of FIG. 1, the latch circuit 143 of the signal phase converter 104 shown in FIG. This is the same as the latched m-bit data. Accordingly, the receiver 200 shown in FIG. 19 can favorably demodulate the phase modulation signal Spm emitted from the phase modulator 102 of the transmitter 100 shown in FIG. 1 to the optical fiber 103.

  Further, in the receiver 200 shown in FIG. 19, the n + 1-value multilevel signal V output from the phase detector 202 always changes in level level every clock. It can be configured with a differential circuit.

  In the receiver 200 shown in FIG. 19, the decoder 203A shown in FIG. 23 can be used instead of the decoder 203 (see FIG. 20). In FIG. 23, parts corresponding to those in FIG. 20 are denoted by the same reference numerals, and detailed description thereof is omitted.

The decoder 203A has an A / D converter 231A instead of the A / D converter 231 of the decoder 203 in FIG. The A / D converter 231A detects a level step in each clock of the n + 1 value multilevel signal V output from the phase detector 202 (see FIG. 19), and converts it into m-bit data indicating the level step. To do. In this case, the A / D converter 231A treats the maximum level stage of the n + 1-value multilevel signal together with the next level stage, and treats the m-bit data value corresponding to the maximum level stage as the original value. It is not a value (2 ^m ), but a value (2 ^m −1) smaller by 1 than that.

That is, the A / D converter 231A samples the signal in each clock of the n + 1-value multilevel signal V with the clock CLm reproduced by the clock regenerator 204 (see FIG. 19), and the signal in each clock is The first to n-1th thresholds among the sequentially increasing first to nth thresholds for identifying n + 1 level stages in the n + 1 value (2 ^m +1 value) multilevel signal And the above-described m-bit data is acquired. For this reason, the A / D converter 231A constitutes a data acquisition unit.

  Further, the A / D converter 231A compares the n + 1-value multilevel signal V with the above-described nth threshold value, and when the n + 1 value multilevel signal is equal to or greater than the nth threshold value, 0 ( The control signal CS becomes 1 (second level) when the n + 1-value multilevel signal is less than the nth threshold value. In this case, the control signal CS is 0 when the n + 1-value multilevel signal is in the maximum level stage, and 1 otherwise. For this reason, the A / D converter 231A constitutes a control signal acquisition unit.

Further, the decoder 203A has a latch circuit 232A instead of the latch circuit 232 of the decoder 203 in FIG. The latch circuit 232A latches the m-bit data obtained by the A / D converter 231A based on the clock CLm, and obtains the m-bit data A ′ related to the n + 1-value multilevel signal. The m-bit data A ′ is obtained by changing the 2 ^m value portion of the m + 1 bit data A output from the latch circuit 232 of the decoder 203 in FIG. 20 to a value of 2 ^m −1. Although the latch circuit 232 of the decoder 203 in FIG. 20 needs to have an m + 1 bit configuration, the latch circuit 232A can have an m bit configuration. Accordingly, the subtractor 233 and the comparator 235 can also have an m-bit configuration in the decoder 203A shown in FIG.

  The decoder 203 </ b> A has a latch circuit 237 and an AND circuit 238. The latch circuit 237 latches the control signal CS obtained by the A / D converter 231A based on the clock CLm. In this case, the value of the control signal CS latched by the latch circuit 237 corresponds to the current value A′t of the m-bit data A ′ related to the multi-value signal of n + 1 value latched by the latch circuit 232A. Will be.

When the current value A′t of the data A ′ latched by the latch circuit 232A corresponds to the maximum level of the n + 1 value multi-level signal, as described above, the original value (2 ^m ) The value is smaller by 1 (2 ^m −1). In this case, the value of the control signal CS latched by the latch circuit 237 is always 0.

  The AND circuit 238 takes the logical product of the control signal CS latched by the latch circuit 237 and the 0 or 1 data output from the comparator 235, and supplies the output signal to the subtractor 233 from the latch circuit 232A. Is supplied as a signal to be subtracted from the current value A't of the m-bit data A '.

  The rest of the decoder 203A shown in FIG. 23 is configured in the same manner as the decoder 203 shown in FIG.

  The operation of the decoder 203A shown in FIG. 23 will be described.

The n + 1-value multilevel signal V from the phase detector 202 (see FIG. 19) is supplied to the A / D converter 231A. In this A / D converter 231A, the level stage in each clock of the n + 1 value multi-level signal is detected and converted into m-bit data indicating the level stage. In this case, the maximum level stage of the n + 1 value multi-level signal is treated as the next level stage, and the m-bit data value corresponding to the maximum level stage is the original value (2 ^m ). Instead, it is set to a value (2 ^m −1) smaller by 1 than that. This m-bit data is supplied to an m-bit latch circuit 232A.

In the latch circuit 232A, the m-bit data supplied from the A / D converter 231A is latched by the clock CLm, and the m-bit data A ′ related to the n + 1-value multilevel signal is obtained. The m-bit data A ′ is obtained by changing the 2 ^m value portion of the m + 1 bit data A to a value of 2 ^m −1.

  In the A / D converter 231A, the n + 1 value multilevel signal V is compared with the above-described nth threshold value, and becomes 0 when the n + 1 value multilevel signal is greater than or equal to the nth threshold value. A control signal CS that becomes 1 when the n + 1-value multilevel signal is less than the nth threshold value is obtained. In this case, the control signal CS is 0 when the n + 1-value multilevel signal V is in the maximum level stage, and 1 otherwise. The control signal CS is supplied to the latch circuit 237.

  In the latch circuit 237, the control signal CS obtained by the A / D converter 231A is latched based on the clock CLm. In this case, the value of the control signal CS latched by the latch circuit 237 corresponds to the current value A′t of the m-bit data A ′ related to the multi-value signal of n + 1 value latched by the latch circuit 232A. Will be. The control signal CS latched by the latch circuit 237 is supplied to the AND circuit 238.

  The latch circuit 234 is supplied with m-bit data M that is obtained by the subtracter 233 and forms an n-value multi-value signal. In the latch circuit 234, m-bit data M is latched by the clock CLm. The m-bit data M latched by the latch circuit 234 is supplied to the comparator 235.

  In the comparator 235, the first value which is the current value A′t of the m-bit data A ′ related to the n + 1-valued multilevel signal latched by the latch circuit 232 A, and the latch circuit 234 latches the first value. The second value which is the value Mt-1 one clock before the m-bit data M constituting the n-value multilevel signal is compared.

  The comparator 235 outputs 0 or 1 data based on the comparison result between the first value and the second value. That is, when the first value is larger than the second value (A't> Mt-1), 1 data is output, and the first value is the same as the second value or smaller than the second value. (A't≤Mt-1), 0 data is output. In this manner, 0 or 1 data output from the comparator 235 is supplied to the AND circuit 238.

  In the subtracter 233, the output value of the AND circuit 238 is subtracted from the current value A't of the m-bit data A 'latched by the latch circuit 232A, and the current value Mt of the m-bit data M is obtained. Is done.

  In this case, when the first value is larger than the second value (A′t> Mt−1) and the control signal CS latched by the latch circuit 237 is 1, the output signal of the AND circuit 238 is 1 Thus, 1 is subtracted from the current value A′t of the m-bit data A ′ to obtain the current value Mt of the m-bit data M. On the other hand, in other cases, that is, when the first value is larger than the second value (A′t> Mt−1) and the control signal CS latched by the latch circuit 237 is 0, When the value is equal to or smaller than the second value (A′t ≦ Mt−1), the output signal of the AND circuit 238 becomes 0, and the current value A′t of the m-bit data A ′ is The current value Mt of the m-bit data M is used as it is.

Thus, even if the first value is larger than the second value, the latch circuit 237 is used when the current value A′t of the data A ′ corresponds to the maximum level of the n + 1-value multilevel signal. Since the value of the control signal CS latched in step S is always 0, the value A't is used as it is as the current value Mt of the m-bit data M. As described above, when the current value A′t of the data A ′ corresponds to the maximum level of the n + 1-value multilevel signal, the value A′t is already the original value (2 ^m This is because it is a value (2 ^m -1) smaller by 1 than.

  As described above, in the multilevel demodulating means including the latch circuit 232A, the subtractor 233, the latch circuit 234, and the comparator 235, based on the m-bit data A ′ related to the n + 1 level multilevel signal, the n level multilevel The m-bit data M constituting the signal is obtained. The m-bit data M corresponds to the m-bit data M output from the latch circuit 143 (see FIG. 2) of the signal phase converter 104.

FIG. 24 shows the transition of the current value A′t of the m-bit data A ′, the current value Mt of the m-bit data M, and the value of the control signal CS when m = 1. In the comparator 235, 2 ^m −1 = 1 is used as the value Mt at t = 0, that is, M0. Further, in the current value A′t of the data A ′, the portion marked with “*” indicates the portion corresponding to the maximum level of the n + 1 value (2 ^m +1 value) multilevel signal, is a moiety which has a value (2 ^m) from only one less (2 ^m -1). The same applies to FIG. 24 below. As is apparent from FIG. 24 and FIG. 17 described above, the m-bit data M obtained by the multi-level demodulation means of the decoder 203A is the m-bit data output from the latch circuit 143 of the signal phase converter 104 described above. It can be seen that it matches the data M.

FIG. 25 shows the transition of the current value A′t of the m-bit data A ′, the current value Mt of the m-bit data M, and the value of the control signal CS when m = 2. In the comparator 235, 2 ^m -1 = 3 is used as the value Mt at t = 0, that is, M0. As apparent from FIG. 25 and FIG. 18, m-bit data M obtained by the multilevel demodulation means of the decoder 203A is m-bit data output from the latch circuit 143 of the signal phase converter 104 described above. It can be seen that it matches M.

  Although detailed description is omitted, even when m is 3 or more, when m = 1, as in the case of m = 2, m-bit data M is obtained from m-bit data A ′. The m-bit data M coincides with the m-bit data M output from the latch circuit 143 of the signal phase converter 104 described above.

  Similarly to the decoder 203 shown in FIG. 20, the m-bit data M constituting the n-valued multi-level signal output from the latch circuit 234 is supplied to the shift register 236 and converted into serial data for output. Output serial data Dout is output to the terminal 206.

  As described above, the decoder 203A shown in FIG. 23 can obtain the same operational effects as the decoder 203 shown in FIG.

  Further, in the decoder 203A shown in FIG. 23, the A / D converter 231A treats the maximum level stage of the n + 1-value multilevel signal and the next level stage together so that the n + 1-value multilevel signal is processed. M to obtain m-bit data, obtain a control signal CS for identifying that the n + 1-value multilevel signal is in the maximum level stage, and use them to construct an n-value multilevel signal m The bit data M is obtained, and the number of bits necessary for the demodulation processing is not m + 1 bits but m bits, and there is an advantage that one bit can be saved.

  That is, in the decoder 203A illustrated in FIG. 23, an m-bit configuration can be used as the latch circuit 232A, the subtracter 233, the comparator 235, and the like, and the circuit scale can be reduced.

  In the above-described embodiment, the n-value multi-value signal is composed of m-bit data, the n + 1-value multi-value signal is composed of m + 1-bit data, and each level step of the n-value multi-value signal. The width and the width of each level step of the n + 1 value multilevel signal are the same, but those having different widths are also conceivable.

In the above-described embodiment, the n-level multi-level signal has n = 2 ^m level steps, and the n + 1-level multi-level signal has n + 1 = 2 ^m +1 level steps. However, the present invention can be similarly applied when n is other than 2 ^m (m = 1, 2,...).

  In the above-described embodiment, the transmitter 100 and the receiver 200 handle optical signals. However, the present invention is a communication system that performs transmission / reception by phase-modulating a multilevel signal in the form of a voltage signal. Can be applied similarly.

  The present invention is capable of satisfactorily transmitting / receiving n-valued multilevel signals without being affected by noise and without requiring a complicated synchronization circuit. For example, an optical communication system for transmitting / receiving n-valued multilevel signals, etc. Applicable to.

It is a block diagram which shows the structure of the transmitter as embodiment. It is a block diagram which shows the structure of a signal phase converter. It is a figure which shows the conversion map (m = 1) of the encoding from the m bit data which comprises an n value multi-value signal to the m + 1 bit data which comprises an n + 1 value multi value signal, and its decoding. It is a figure which shows the conversion map (m = 2) of the encoding from the m bit data which comprises an n value multi-value signal to the m + 1 bit data which comprises an n + 1 value multi value signal, and its decoding. It is a figure which shows the structure of a phase detector. It is a figure which shows four types of phase differences for outputting 3 levels in a phase detector. It is a figure for demonstrating a response | compatibility with four types of phases and a code | cord | chord. It is a figure which shows eight types of phase differences for outputting 5 levels in a phase detector. It is a figure for demonstrating a response | compatibility with 8 types of phases and codes | symbols. It is a figure which shows the code table in the case of 3 values in a code generator. It is a figure which shows the code table (1/2) in the case of 5 values in a code generator. It is a figure which shows the code table (2/2) in the case of 5 values in a code generator. It is a figure which shows an example of the transition between a 4-bit code | cord | chord in the case of m = 2 and a 3-bit compression code. It is a figure which shows the relationship (M = 1) of a phase and control voltage Vct. It is a figure which shows the improved code table in the case of 3 values in a code generator. It is a figure which shows the relationship (M = 2) of a phase and control voltage Vct. The current value Mt of the m-bit data M in the encoding (m = 1) from the m-bit data M constituting the n-value multi-value signal to the m + 1-bit data A constituting the n + 1-value multi-value signal, It is a figure which shows an example of transition of present value At of m + 1 bit data A, phase (code) which constitutes phase information Ipm, and control voltage Vct. The current value Mt of the m-bit data M in the encoding (m = 2) from the m-bit data M constituting the n-value multi-value signal to the m + 1-bit data A constituting the n + 1-value multi-value signal, It is a figure which shows an example of transition of the present value At of m + 1 bit data A, the phase (code | cord) which comprises the phase information Ipm, and control voltage Vct. It is a block diagram which shows the structure of the receiver as embodiment. It is a block diagram which shows the structure of a decoder. Current value At of data A and data M in decoding (m = 1) from m + 1 bit data A constituting an n + 1 value multivalue signal to m bit data M constituting an n value multivalue signal It is a figure which shows an example of transition of the present value Mt. Current value At of data A and data M in decoding (m = 2) from m + 1 bit data A constituting an n + 1 value multivalue signal to m bit data M constituting an n value multivalue signal It is a figure which shows an example of transition of the present value Mt. It is a block diagram which shows the other structure of a decoder. the current value A′t of the data A ′ in the decoding (m = 1) of the m-bit data A ′ relating to the n + 1-valued multivalued signal into the m-bit data M constituting the n-valued multivalued signal; It is a figure which shows an example of transition of the present value Mt of data M. the current value A′t of the data A ′ in the decoding (m = 2) of the m-bit data A ′ relating to the n + 1-valued multivalued signal into the m-bit data M constituting the n-valued multivalued signal; It is a figure which shows an example of transition of the present value Mt of data M.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Transmitter, 101 ... Light source, 102 ... Phase modulator, 103 ... Optical fiber, 104 ... Signal phase converter, 105 ... Data input terminal, 106 ... Clock Input terminal 141 shift register 142 1 / m frequency divider 143 145 latch circuit 144 code generator 146 code / voltage converter 200 ..Receiver, 201 ... optical fiber, 202 ... phase detector, 203, 203A ... decoder, 204 ... clock regenerator, 205 ... m multiplier, 206 ... data output Terminal, 207... Clock output terminal, 231, 231 A, A / D converter, 232, 232 A, 234, 237, latch circuit, 233, subtractor, 235, comparator, 236.・ ・Shift register, 238 ... and circuit

Claims (20)

Based on an n-value multilevel signal having n (n is an integer greater than or equal to 2) level steps, it corresponds to an n + 1 value multilevel signal having n + 1 level steps whose level steps change every clock. A phase information generator for generating phase information when generating a phase modulation signal,
Based on the next level stage of the n-value multilevel signal, the current phase and the previous phase, the phase difference from the current phase becomes a value corresponding to the next level stage of the n + 1-value multilevel signal. A phase information generation device comprising: a phase information generation unit that determines a next phase and generates information on the next phase. The level stage of the predetermined clock position of the n + 1 value multilevel signal is as follows:
The level stage at the predetermined clock position of the n-value multilevel signal is defined as a first level stage, and the level stage one clock before the predetermined clock position of the n + 1-value multilevel signal is defined as a second level stage. When
When the first level stage is smaller than the second level stage, the first level stage is set, and when the first level stage is the same as the second level stage or larger than the second level stage. The phase information generating device according to claim 1, wherein the phase level is one level level higher than the first level level. A control voltage conversion unit that converts the phase information generated by the phase information generation unit into a control voltage for controlling a modulation phase in a phase modulator for obtaining the phase modulation signal;
The phase information generator is
When there are a plurality of phases in which the phase difference from the current phase is a value corresponding to the next level step of the n + 1-valued multilevel signal, the change in the control voltage is small or the value of the control voltage The phase information generating device according to claim 1, wherein a phase in which becomes smaller is a next phase. Based on an n-value multilevel signal having n (n is an integer greater than or equal to 2) level steps, it corresponds to an n + 1 value multilevel signal having n + 1 level steps whose level steps change every clock. A phase information generation method for generating phase information when generating a phase modulation signal,
Based on the next level stage of the n-value multilevel signal, the current phase and the previous phase, the phase difference from the current phase becomes a value corresponding to the next level stage of the n + 1-value multilevel signal. A phase information generation method characterized by determining the next phase and generating information on the next phase. A signal source that outputs a signal having a continuous phase;
A phase modulator that phase-modulates a signal output from the signal source to obtain a transmission phase-modulated signal;
A phase information generator for generating phase information for controlling the modulation phase in the phase modulator,
The phase information generator is
Based on the next level stage of the n-value multilevel signal having n level stages (n is an integer of 2 or more), the current phase, and the previous phase, the phase difference from the current phase is changed every clock. The next phase is determined so as to be a value corresponding to the next level step of the n + 1 value multi-level signal having n + 1 level steps whose level step changes to the next phase information, and generating information on the next phase. Features transmitter. Based on m-bit data constituting a 2 ^m- value multi-value signal (m is an integer of 1 or more), m + 1-bit data constituting a 2 ^m + 1-value multi-value signal whose value changes every clock. A phase information generator for generating phase information when generating a corresponding phase modulation signal,
Based on the next value of the m-bit data, the current phase and the previous phase, the next phase is set so that the phase difference from the current phase becomes a value corresponding to the next value of the m + 1-bit data. A phase information generation device comprising: a phase information generation unit that determines and generates information of the next phase. The phase information generating apparatus according to claim 6, further comprising a data conversion unit that converts input serial data into the m-bit data. The value of the predetermined clock position of the m + 1 bit data is
When the value of the predetermined clock position of the m-bit data is a first value and the value one clock before the predetermined clock position of the m + 1-bit data is a second value,
When the first value is smaller than the second value, the first value is used. When the first value is the same as the second value or larger than the second value, the first value is used. The phase information generating apparatus according to claim 6, wherein the phase information generating apparatus is one larger value. Based on m-bit data constituting a 2 ^m- value multi-value signal (m is an integer of 1 or more), m + 1-bit data constituting a 2 ^m + 1-value multi-value signal whose value changes every clock. A phase information generation method for generating phase information when generating a corresponding phase modulation signal,
Based on the next value of the m-bit data, the current phase and the previous phase, the next phase is set so that the phase difference from the current phase becomes a value corresponding to the next value of the m + 1-bit data. Determining and generating information of the next phase. A signal source that outputs a signal having a continuous phase;
A phase modulator that obtains a transmission phase modulation signal by phase-modulating an optical signal output from the signal source;
A phase information generator for generating phase information for controlling the modulation phase in the phase modulator,
The phase information generator is
2 Based on the next value, the current phase, and the previous phase of the m-bit data constituting the multi-value signal of ^m value (m is an integer of 1 or more), the phase difference from the current phase is changed every clock. The next phase is determined so as to be a value corresponding to the next value of the m + 1 bit data constituting the 2 ^m +1 value multi-value signal whose value changes to the value, and information on the next phase is generated. Features transmitter. An n + 1-value multilevel signal having n + 1 level steps, which is generated based on an n-value multilevel signal having n (n is an integer of 2 or more) level steps and whose level step changes every clock. Correspondingly, the phase of the predetermined clock position is modulated so that the phase difference from the phase one clock before becomes a value corresponding to the level step of the predetermined clock position of the n + 1 value multilevel signal. A phase detector that obtains the n + 1-value multilevel signal from the signal;
And a decoder that generates an n-value multilevel signal having the n level steps based on the n + 1-value multilevel signal obtained by the phase detector. The phase modulation signal is an optical signal,
The receiver according to claim 11, wherein the phase detector performs homodyne detection to obtain the n + 1-value multilevel signal from the phase modulation signal. The level stage of the predetermined clock position of the n + 1 value multilevel signal is as follows:
The level stage at the predetermined clock position of the n-value multilevel signal is defined as a first level stage, and the level stage one clock before the predetermined clock position of the n + 1-value multilevel signal is defined as a second level stage. When
When the first level stage is smaller than the second level stage, the first level stage is set, and when the first level stage is the same as the second level stage or larger than the second level stage. The receiver according to claim 11, wherein the level stage is one level higher than the first level stage. The decoder
Level level comparing means for comparing a first level level which is a current level level of the n + 1 level multilevel signal and a second level level which is a level level one clock before the n level multilevel signal; ,
Based on the comparison result of the level stage comparison means, when the first level stage is larger than the second level stage, a level stage that is one smaller than the first level stage is set to the current value of the n-value multilevel signal. When the first level stage is the same as the second level stage or smaller than the second level stage, the first level stage is set as the current level stage of the n-value multilevel signal. The receiver according to claim 13, further comprising a level stage determination unit. The decoder
The n + 1-valued multilevel signal is compared with first to n-1th thresholds among first to nth thresholds that are sequentially increased to identify the n + 1 level stages. Data acquisition means for obtaining m-bit (m is an integer of 1 or more) data;
The n + 1 value multilevel signal is compared with the nth threshold value. When the n + 1 value multilevel signal is equal to or higher than the nth threshold value, the first level is obtained. Control signal acquisition means for obtaining a control signal that is at a second level when the signal is less than the nth threshold;
A first value, which is a current value of m-bit data acquired by the data acquisition means, and a second value, which is a value one clock before the m-bit data constituting the n-value multilevel signal; Data value comparison means for comparing
Based on the comparison result of the data value comparison means and the control signal obtained by the control signal acquisition means, when the first value is larger than the second value and the control signal is at the second level, 1 is subtracted from the first value to obtain the current value of the m-bit data constituting the n-value multi-value signal, the first value is greater than the second value, and the control signal Is the first level, or when the first value is the same as the second value or smaller than the second value, the first value is used as it is to form the n-value multilevel signal. The receiver according to claim 13, further comprising a calculation unit that sets a current value of the m-bit data. M + 1 bits forming a 2 ^m +1 value multi-value signal generated based on m-bit data constituting a 2 ^m value (m is an integer of 1 or more) multi-level signal and changing in level level every clock. Receiving phase modulation, in which the phase of the predetermined clock position is modulated so that the phase difference from the phase one clock earlier is a value corresponding to the value of the predetermined clock position of the m + 1 bit data. A phase detector that obtains the 2 ^m +1 multi-value signal from the signal;
And a decoder that generates m-bit data constituting the 2 ^m -value multi-value signal based on the 2 ^m +1 value multi-value signal obtained by the phase detector. . The phase modulation signal is an optical signal,
The receiver according to claim 16, wherein the phase detector performs homodyne detection to obtain the 2 ^m +1 value multilevel signal from the phase modulation signal. The value of the predetermined clock position of the m + 1 bit data is
When the value of the predetermined clock position of the m-bit data is a first value and the value one clock before the predetermined clock position of the m + 1-bit data is a second value,
When the first value is smaller than the second value, the first value is used. When the first value is the same as the second value or larger than the second value, the first value is used. The receiver according to claim 16, wherein the value is one larger. The decoder
Data value comparison means for comparing a first value that is a current value of the m + 1 bit data and a second value that is a value one clock before the m bit data;
Based on the comparison result of the data value comparison means, when the first value is larger than the second value, 1 is subtracted from the first value to obtain the current value of the m-bit data, and the first value 19. An arithmetic means for using the first value as it is as the current value of the m-bit data when the value of is equal to or smaller than the second value. As described in the receiver. The optical receiver according to claim 16, further comprising data conversion means for converting the m-bit data obtained by the decoder into output serial data.

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