JP4701490B2 - Solid-state imaging device and solid-state imaging device driving method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device in which photoelectric conversion elements are two-dimensionally arranged, for example, a CCD solid-state imaging device and a driving unit thereof, and a driving method of the solid-state imaging device.
[0002]
[Prior art]
In recent years, digital still cameras have been rapidly spreading.
The digital still camera includes automatic control devices such as auto focus (AF), auto white balance (AWB), and automatic exposure (AE).
In automatic control by these devices, processing is performed using an output signal obtained from an image sensor.
[0003]
In addition, the digital still camera employs a frame readout operation in driving the solid-state imaging device for the purpose of obtaining a high-resolution still image.
[0004]
FIG. 6 shows this conventional frame reading operation. 6A shows a schematic diagram of the signal charge transfer operation, FIG. 6B shows a vertical simultaneous timing chart, and FIG. 6C shows a horizontal synchronization timing chart.
[0005]
This frame readout operation alternately reads out the odd-numbered signal charges and even-numbered signal charges for each field in order to obtain a high-resolution still image, and is independent without adding the signal charges of each pixel. To be transferred.
[0006]
The odd-numbered lines (1, 3, 5, 7, 9) are supplied with the first-phase vertical transfer clock V1 via the first-phase transfer electrodes (not shown), and the even-numbered lines (2, 4, 4, 9). 6, 8) is supplied with a third-phase vertical transfer clock V3 via a third-phase transfer electrode (not shown).
Thereby, the signal charge of the sensor part 51 of each line is read to the vertical transfer register 52 through the read gate part.
[0007]
Although not shown, a second-phase transfer electrode to which a second-phase vertical transfer clock V2 is supplied is provided between the odd-phase first-phase transfer electrode and the even-line third-phase transfer electrode. The fourth phase transfer electrode to which the fourth phase vertical transfer clock V4 is supplied is arranged, and the first phase, the second phase, the third phase, and the fourth phase are directed toward the lower horizontal transfer register 53 in the figure. Transfer electrodes are arranged in order.
[0008]
The signal charges read to the vertical transfer register 52 are vertically transferred by applying vertical transfer clocks V1, V2, V3, and V4 shown in FIG. 6C during horizontal blanking HBLK.
The actual horizontal blanking period HBLK is slightly longer than the period shown in the horizontal synchronization timing chart of FIG. 6C, that is, the period in which signal charges are transferred by the vertical transfer register 52 (vertical transfer period). It becomes a period.
Here, for the sake of simplicity, the following description will be made assuming that the period in which signal charges are transferred by the vertical transfer register 52 = the horizontal blanking period HBLK.
[0009]
Then, a frame reading operation is performed as follows.
First, as shown in FIG. 6B, when the first-phase vertical transfer clock V1 becomes a high level, the signal charges of the sensor units 51 in the odd-numbered lines (first field) are read out to the vertical transfer register 52. As shown in 6C, the vertical transfer clocks V1, V2, V3, and V4 of the respective phases are supplied, whereby the signal charges of the sensor unit 51 of the first line 1 are vertically transferred to the horizontal transfer register 53.
In this state, the horizontal blanking period HBLK ends, the signal charge of the sensor unit 51 of the first line 1 is horizontally transferred, and sequentially output through the charge-voltage conversion unit 54.
[0010]
Thereafter, the vertical transfer in the horizontal blanking period HBLK and the horizontal transfer in the horizontal transfer register 53 are repeated, and the signal charges of all the pixels in the odd line, that is, the first field are output without being added halfway.
[0011]
Subsequently, as shown in FIG. 6B, the signal charge of the sensor unit 51 of the even line (second field) is read out to the vertical transfer register 52 when the third-phase vertical transfer clock V <b> 3 becomes a high level. The subsequent operation is the same as in the case of odd lines (first field).
In this way, signal charges of all the pixels in the odd line (first field) and the even line (second field) are output.
[0012]
[Problems to be solved by the invention]
However, when performing the above-described various automatic controls, it is not preferable to use the same operation mode (frame reading operation) as that for a still image because the response speed of the various automatic control devices becomes slow.
In particular, when a solid-state imaging device with a large number of pixels is used, there is a problem that the response speed becomes slower.
[0013]
Also, when monitoring an image taken with a liquid crystal monitor or the like, use of the same operation mode as that for a still image is not preferable because the frame rate becomes slow and a smooth moving image cannot be obtained.
[0014]
Therefore, as one method for increasing the frame rate, the number of lines of the imaging signal to be output by applying a read voltage to each read gate of a predetermined repeating unit, reading only the charges of the pixels of some lines to the vertical transfer register, and outputting them. The operation for obtaining a higher-speed imaging signal, that is, the line thinning-out operation is performed.
[0015]
In addition, there is an increasing demand for multi-function digital still cameras, and an increasing number of products are equipped with a plurality of operation modes in order to cope with various subject conditions.
[0016]
FIG. 7 shows the above-described line thinning operation. FIG. 7A shows a schematic diagram of a signal charge transfer operation, FIG. 7B shows a vertical simultaneous timing chart, and FIG. 7C shows a horizontal synchronization timing chart.
[0017]
In the case of FIG. 7, the 2 / 8-line thinning operation mode for outputting 2 lines out of 8 lines is set.
In this thinning-out operation mode, there is an empty packet that does not contain signal charge behind the packet that contains signal charge. Therefore, it is necessary to mix these two packets in the horizontal transfer register and eliminate the no-signal period. is there.
Therefore, vertical transfer for two lines is performed within the horizontal blanking period to mix packets containing signal charges and empty packets.
[0018]
Specifically, the first-phase transfer clock V1 and transfer electrode, and the third-phase transfer clock V3 and transfer electrode are used for reading signal charges (V1A and V3A), respectively, and for reading signal charges. It is divided into those not used (V1B and V3B).
Then, the vertical transfer clocks V1A and V3A for reading are supplied to the fifth line 8 and the eighth line 8 out of two lines in eight lines, in FIG. Configured to do. The fifth line 5 is made up of red R and green G, and the eighth line 8 is made up of green G and blue B. The signals are output with the same color balance of R, G and B as the pixels of all the 8 lines from these 2 lines 5 and 8. can get.
At this time, the signal charges of the pixels on the other lines shaded are not read out.
[0019]
Then, the line thinning operation is performed as follows.
First, as shown in FIG. 7B, when the first-phase vertical transfer clock V1A and the third-phase vertical transfer clock V3A for reading are at a high level, the sensor units 51 of the fifth line 5 and the eighth line 8 are used. Are transferred to the vertical transfer register 52.
Here, since the signal charges of the pixels on the other lines are not read out, an empty packet is generated in the vertical transfer register 52. In FIG. 7, each set of the fourth line 4 and the fifth line 5 and the eighth line 8 and the ninth line 9 is a packet including a signal charge. In addition, an empty packet is generated in each set of the second line 2 and the third line 3 and the sixth line 6 and the seventh line 7.
[0020]
Thereafter, in the horizontal blanking period HBLK, vertical transfer clocks V1A / V1B, V2, V3A / V3B, and V4 for each phase are supplied as shown in FIG. Is made.
As a result, the signal charge of the sensor unit 51 on the fifth line 5 is vertically transferred to the horizontal transfer register 53. Then, the signal charges of the sensor unit 51 in the fifth line 5 are mixed with the empty packets in the set of the second line 2 and the third line 3.
Further, the signal charges of the sensor unit 51 on the eighth line 8 are vertically transferred to the fourth line 4 and the fifth line 5.
In this state, the horizontal blanking period HBLK ends, a horizontal transfer clock (not shown) is supplied, and the signal charges of the sensor unit 51 of the fifth line 5 transferred to the horizontal transfer register 53 are sequentially output.
[0021]
Thereafter, the vertical transfer during the horizontal blanking period HBLK and the horizontal transfer in the horizontal transfer register 53 are repeated, and the signal charges of all the pixels on the selected line are output without being added halfway.
[0022]
Here, when the horizontal synchronization timing chart shown in FIG. 7C is compared with the horizontal synchronization timing chart shown in FIG. 6C, the lengths of the horizontal blanking periods HBLK for performing vertical transfer in the two operation modes are equal.
In FIG. 6C, when the length of the overlap period of the vertical transfer clock for performing transfer for one line is x, in FIG. 7C, the overlap period of the vertical transfer clock for performing vertical transfer for two lines. The length of x is x / 2.
[0023]
Further, in the case of an image sensor with a larger number of pixels, it is conceivable to perform a thinning operation of 4/16 lines by line thinning + horizontal transfer register 2 line addition as shown in FIG. FIG. 8A shows a schematic diagram of the signal charge transfer operation, FIG. 8B shows a vertical simultaneous timing chart, and FIG. 8C shows a horizontal synchronization timing chart.
In this operation mode, two lines including signal charges and two lines having no signal are mixed and output in the horizontal transfer register, so that vertical transfer for four lines is performed within the horizontal blanking period.
[0024]
Specifically, as in the operation of FIG. 7, the first-phase transfer clock V1 and the transfer electrode, and the third-phase transfer clock V3 and the transfer electrode are used for reading signal charges (V1A and V3A) and those not used for reading signal charges (V1B and V3B).
Then, 4 lines out of 16 lines, in FIG. 8, vertical transfer clocks for reading with respect to the first line 1, the fifth line 5, the 10th line 10 and the 14th line 14 among the first line 16 to the 16th line 16. V1A and V3A are supplied to perform reading. The first line 1 and the fifth line 5 are made up of red R and green G, the tenth line 10 and the fourteenth line 14 are made up of green G and blue B, and these four lines 1, 5, 10, 14 to all 16 lines. A signal is obtained with the same color balance of R, G, and B as the pixel.
[0025]
Then, line thinning + horizontal transfer register 2-line addition operation is performed as follows.
First, as shown in FIG. 8B, when the first-phase vertical transfer clock V1A and the third-phase vertical transfer clock V3A for reading are at a high level, the sensor units of the four lines 1, 5, 10, and 14 described above. 51 signal charges are read to the vertical transfer register 52.
Thereafter, in the horizontal blanking period HBLK, vertical transfer clocks V1A / V1B, V2, V3A / V3B, and V4 for each phase are supplied as shown in FIG. Is made. As a result, the signal charges of the sensor unit 51 of the first line 1 and the signal charges of the sensor unit 51 of the fifth line 5 are both transferred vertically to the horizontal transfer register 53, and the signal charges of the two lines 1 and 5 are transferred horizontally. It is added in the register 53.
In this state, the horizontal blanking period HBLK ends, and the signal charges of the sensor units 51 of the first line 1 and the fifth line 5 transferred to the horizontal transfer register 53 are horizontally transferred and sequentially output.
Thereafter, the vertical transfer during the horizontal blanking period HBLK and the horizontal transfer in the horizontal transfer register 53 are repeated, and the signal charges of all the pixels on the selected line are added two lines at a time and output.
[0026]
In this case as well, as in the case of FIG. 7C, the length of the horizontal blanking period HBLK in which vertical transfer is performed is equal to that in the case of frame reading in FIG. 6C.
6C, when the length of the overlap period of the vertical transfer clock for transferring one line in FIG. 6C is x, in FIG. 8C, the overlap period of the vertical transfer clock for performing vertical transfer of four lines. Will be x / 4.
[0027]
As described above, in the operation mode shown in FIG. 8, since the overlap period of the vertical transfer clock is shortened to ¼ that in the frame read operation, a propagation delay is likely to occur in the vertical transfer clock.
As a result, the waveform becomes dull at a position far from the input terminal of the transfer clock, and there is a problem that the transfer efficiency of the vertical register is deteriorated and the amount of charge handled is reduced.
[0028]
In order to solve the above-described problem, in the present invention, the frame rate is high and handled by preventing the deterioration of the waveform of the transfer clock even in a mode of operation different from normal, such as thinning-out operation. The present invention provides a solid-state imaging device and a solid-state imaging device driving method capable of performing efficient transfer with a sufficient amount of charge.
[0029]
[Means for Solving the Problems]
The solid-state imaging device of the present invention includes a plurality of two-dimensionally arranged photoelectric conversion elements, a gate unit that reads signal charges photoelectrically converted by the plurality of photoelectric conversion elements, and a signal charge read by the gate unit. A plurality of vertical transfer registers for transferring in the vertical direction; a horizontal transfer register for transferring signal charges transferred from the plurality of vertical transfer registers in the horizontal direction; and a drive means for driving the vertical transfer registers and the horizontal transfer registers. And A horizontal synchronization period is composed of a horizontal blanking period including a period in which signal charges are transferred by the vertical transfer register and a period in which signal charges are transferred by the horizontal transfer register, The driving means is a period in which signal charges are transferred by the vertical transfer register according to the number of vertical transfer stages of the vertical transfer register performed during the horizontal blanking period. And the length of Length of horizontal blanking period and horizontal synchronization period And make them both longer or shorter Is.
[0030]
According to the above-described configuration of the solid-state imaging device of the present invention, the driving unit is configured to transfer a signal charge by the vertical transfer register (vertical transfer period) according to the number of vertical transfer stages of the vertical transfer register performed during the horizontal blanking period. ) And the length of Length of horizontal blanking period and horizontal synchronization period To make it longer or shorter Therefore, when performing an operation with a large number of vertical transfer stages, the period (vertical transfer period) in which signal charges are vertically transferred is relatively longer or shorter than an operation with a small number of vertical transfer stages. Is possible.
[0031]
The solid-state imaging device driving method of the present invention includes a plurality of two-dimensionally arranged photoelectric conversion elements, a gate portion that reads signal charges photoelectrically converted by the plurality of photoelectric conversion elements, and a signal charge read by the gate portion. When driving a solid-state imaging device having a plurality of vertical transfer registers that transfer signals vertically and a horizontal transfer register that horizontally transfers signal charges transferred from the plurality of vertical transfer registers, during a horizontal blanking period Has multiple operation modes with different number of vertical transfer stages, A horizontal synchronization period is composed of a horizontal blanking period including a period in which signal charges are transferred by the vertical transfer register and a period in which signal charges are transferred by the horizontal transfer register, Period in which signal charge is transferred by vertical transfer register according to multiple operation modes And the length of Length of horizontal blanking period and horizontal synchronization period And make them both longer or shorter Is.
[0032]
According to the above-described method of the present invention, a period in which signal charges are transferred by the vertical transfer register according to a plurality of operation modes in which the number of stages of vertical transfer performed during the horizontal blanking period is different (vertical transfer period). And the length of Length of horizontal blanking period and horizontal synchronization period To make it longer or shorter As a result, in an operation mode with a large number of vertical transfer stages, it is possible to lengthen or shorten a period (vertical transfer period) in which signal charges are vertically transferred relative to an operation mode with a small number of vertical transfer stages. .
[0033]
DETAILED DESCRIPTION OF THE INVENTION
The present invention relates to a plurality of photoelectric conversion elements arranged two-dimensionally, a gate section for reading out signal charges photoelectrically converted by the plurality of photoelectric conversion elements, and a signal charge read out by the gate section in the vertical direction. A plurality of vertical transfer registers, a horizontal transfer register that horizontally transfers signal charges transferred from the plurality of vertical transfer registers, and a drive unit that drives the vertical transfer register and the horizontal transfer register. A horizontal synchronization period is composed of a horizontal blanking period including a period in which signal charges are transferred by the vertical transfer register and a period in which signal charges are transferred by the horizontal transfer register, The driving means is a period in which signal charges are transferred by the vertical transfer register according to the number of vertical transfer stages of the vertical transfer register performed during the horizontal blanking period. And the length of Length of horizontal blanking period and horizontal synchronization period And make them both longer or shorter It is a solid-state imaging device.
[0034]
The present invention relates to a plurality of two-dimensionally arranged photoelectric conversion elements, a gate portion that reads signal charges photoelectrically converted by the plurality of photoelectric conversion elements, and a plurality of signal charges that are read by the gate portions in the vertical direction. Of vertical transfer performed during a horizontal blanking period when driving a solid-state imaging device having a vertical transfer register and a horizontal transfer register that horizontally transfers signal charges transferred from a plurality of vertical transfer registers Has multiple operating modes, A horizontal synchronization period is composed of a horizontal blanking period including a period in which signal charges are transferred by the vertical transfer register and a period in which signal charges are transferred by the horizontal transfer register, Period in which signal charge is transferred by vertical transfer register according to multiple operation modes And the length of Length of horizontal blanking period and horizontal synchronization period And make them both longer or shorter It is a drive method of a solid-state image sensor.
[0035]
First, a schematic configuration diagram of a solid-state imaging device to which the present invention is applied is shown in FIG.
The solid-state imaging device 20 includes a plurality of sensor units 23 that are two-dimensionally arranged as photoelectric conversion elements that perform photoelectric conversion, and a readout gate unit 24 that reads signal charges photoelectrically converted by the plurality of sensor units 23. The imaging area 22 of the CCD solid-state imaging device 21 is configured to have a plurality of vertical transfer registers 25 arranged for each of the sensor units 23 columns.
A horizontal transfer register 26 that transfers the signal charges transferred from the vertical transfer register 25 in the horizontal direction is provided at the lower part of the imaging region 22 in the drawing connected to the end of the vertical transfer register 25. A charge-voltage converter 27 is connected to the subsequent stage of the horizontal transfer register 26.
[0036]
The vertical transfer register 25 includes a four-phase vertical transfer clock, that is, a first-phase vertical transfer clock φV1A or φV1B, a second-phase vertical transfer clock φV2, a third-phase vertical transfer clock φV3A or φV3B, and a fourth-phase vertical transfer. The clock φV4 is applied to perform four-phase driving.
The horizontal transfer register 26 is configured to perform two-phase driving by applying two horizontal transfer clocks φH1 and φH2.
These vertical transfer clocks φV1A, φV1B, φV2, φV3A, φV3B, φV4 and horizontal transfer clocks φH1 and φH2 are supplied from a timing generation circuit 28 provided outside the CCD solid-state imaging device 21 to a vertical transfer register 25 and a horizontal transfer register 26, respectively. Is input.
[0037]
Next, embodiments of the present invention will be described.
In this embodiment, the solid-state imaging device 20 shown in FIG. 2 performs line thinning + horizontal register 2-line addition operation as a high-speed operation mode.
[0038]
First, when shooting a still image that requires high resolution, an operation mode for performing a field readout operation is set as shown in FIG. 3A shows a schematic diagram of the signal charge transfer operation, FIG. 3B shows a vertical simultaneous timing chart, and FIG. 3C shows a horizontal synchronization timing chart.
That is, in FIG. 3, the field readout operation shown in FIG. 6 is performed by the solid-state imaging device 20 having the configuration of FIG.
[0039]
As shown in FIG. 3A, the odd-numbered lines (1, 3, 5, 7, 9) are supplied with a first-phase vertical transfer clock V1 via a first-phase transfer electrode (not shown). A third-phase vertical transfer clock V3 is supplied to the even lines (2, 4, 6, 8) via a third-phase transfer electrode (not shown).
Thereby, the signal charge of the sensor part 23 of each line is read to the vertical transfer register 25 through the read gate part.
The signal charges read to the vertical transfer register 25 are vertically transferred by applying vertical transfer clocks V1, V2, V3, and V4 shown in FIG. 3C during horizontal blanking HBLK.
[0040]
The actual horizontal blanking period HBLK is slightly longer than the period shown in the horizontal synchronization timing chart of FIG. 3C, that is, the period in which signal charges are transferred by the vertical transfer register 25 (vertical transfer period). It becomes a period.
Here, for the sake of simplicity, the following description will be made assuming that the period in which signal charges are transferred by the vertical transfer register 25 = the horizontal blanking period HBLK.
[0041]
Then, the frame reading operation is performed as follows.
First, as shown in FIG. 3B, when the first-phase vertical transfer clock V1 becomes a high level, the signal charges of the sensor units 23 in the odd lines (first field) are read out to the vertical transfer register 25.
Thereafter, as shown in FIG. 3C, the vertical transfer clocks V1, V2, V3, and V4 of the respective phases are supplied, so that the signal charges of the sensor units 23 in the odd-numbered lines are perpendicular to the line one lower (2 pixels lower). The signal charges of the sensor unit 23 on the first line 1 are transferred vertically to the horizontal transfer register 26.
In this state, the horizontal blanking period HBLK ends, and although not shown, horizontal transfer clocks (φH1, φH2) are supplied, and the signal charges of the sensor unit 23 of the first line 1 transferred to the horizontal transfer register 26 are charged − The signals are sequentially output via the voltage converter 27.
[0042]
Thereafter, the vertical transfer during the horizontal blanking period HBLK and the horizontal transfer in the horizontal transfer register 26 are repeated, and the signal charges of all the pixels in the odd line, that is, the first field are output without being added halfway.
[0043]
Subsequently, as shown in FIG. 3B, the signal charge of the sensor unit 23 in the even line (second field) is read out to the vertical transfer register 25 when the third-phase vertical transfer clock V <b> 3 becomes a high level. The subsequent operation is the same as in the case of odd lines (first field).
In this way, signal charges of all the pixels in the odd line (first field) and the even line (second field) are output.
[0044]
In the operation mode of FIG. 3, vertical transfer for one line is performed during the horizontal blanking period HBLK. Further, the length of the overlap period of the vertical transfer clock is x as in FIG.
[0045]
In the present embodiment, as shown in FIG. Frame rate In the required operation mode, line thinning + two-line addition in the horizontal transfer register is performed.
This line thinning + horizontal transfer register 2-line addition operation is the same as the operation of FIG. 8 described above.
[0046]
Specifically, as in the operation of FIG. 8, the first-phase transfer clock V1 and the transfer electrode, and the third-phase transfer clock V3 and the transfer electrode are used for reading signal charges (V1A and V3A) and those not used for reading signal charges (V1B and V3B).
Then, 4 lines out of 16 lines and 4 lines 1, 5, 10, and 14 similar to those in FIG. 8 are selected.
[0047]
Then, line thinning + horizontal transfer register 2-line addition operation is performed as follows.
First, as shown in FIG. 1B, when the first-phase vertical transfer clock V1A and the third-phase vertical transfer clock V3A for reading are at a high level, the sensor units of the four lines 1, 5, 10, and 14 described above. 23 signal charges are read out to the vertical transfer register 25.
Thereafter, in the horizontal blanking period HBLK, as shown in FIG. 1C, vertical transfer clocks V1A / V1B, V2, V3A / V3B, and V4 of each phase are supplied, thereby vertical transfer of 4 lines (8 pixels). Is made. As a result, the signal charge of the sensor unit 23 of the first line 1 and the signal charge of the sensor unit 23 of the fifth line 5 are both transferred vertically to the horizontal transfer register 26, and the signal charges of the two lines 1 and 5 are transferred horizontally. Add in register 26.
In this state, the horizontal blanking period HBLK ends, and although not shown, a horizontal transfer clock is supplied and the signal charges of the sensor units 23 of the first line 1 and the fifth line 5 transferred to the horizontal transfer register 26 are sequentially output. Is done.
[0048]
The signal charge of the sensor unit 23 on the tenth line 10 and the signal charge of the sensor unit 23 on the fourteenth line 14 are both vertically transferred to the horizontal transfer register 26 in the next (second read-out) horizontal blanking period HBLK. Thus, the signal charges of these two lines 10 and 14 are added in the horizontal transfer register 26.
Thereafter, the vertical transfer during the horizontal blanking period HBLK and the horizontal transfer in the horizontal transfer register 26 are repeated, and the signal charges of all the pixels of the selected line are added two lines at a time and output.
[0049]
In this embodiment, in particular, the length of the horizontal blanking period HBLK is set to the field reading operation mode requiring high resolution shown in FIG. 3 and the line thinning + horizontal transfer register 2 line addition operation mode shown in FIG. Therefore, the lengths are different.
That is, as shown in FIG. 1C, the horizontal blanking period HBLK for performing vertical transfer for four lines is expanded to be longer than the horizontal blanking period HBLK of the frame reading operation of FIG. Thereby, the overlap period y of the vertical transfer clock is set to y> x / 4.
[0050]
Therefore, in this case, the vertical transfer clock overlap period y can be made longer than the vertical transfer clock overlap period x / 4 in the case of FIG. The transfer period can be lengthened and the vertical transfer can be slowed down.
[0051]
According to the above-described embodiment, the horizontal blanking period HBLK in the line thinning + horizontal transfer register two-line addition operation mode is set longer than the horizontal blanking period HBLK in the frame reading operation mode. The vertical transfer clock overlap period y in the mode of line thinning for performing vertical transfer for four lines during the ranking period HBLK + two-line addition operation in the horizontal transfer register is made longer than the period x / 4 in the case of FIG. be able to.
[0052]
Accordingly, the vertical transfer period can be lengthened and the vertical transfer can be performed at a low speed, so that the propagation delay of the vertical transfer clock hardly occurs, and the waveform does not become dull even at a position far from the input terminal of the clock.
Accordingly, a vertical transfer clock having a required waveform is applied, and deterioration of transfer efficiency of the vertical transfer register 25 and reduction in the amount of charge handled by the vertical transfer register 25 can be prevented.
That is, it is possible to achieve both a high frame rate and a sufficient amount of charge handled by the vertical transfer register 25 even in an operation mode in which the number of lines vertically transferred during the horizontal blanking period HBLK is large and high-speed transfer is performed. .
[0053]
Next, another embodiment of the present invention will be described.
In this embodiment, the horizontal blanking period is extended in the operation mode in which the two-line addition operation in the horizontal transfer register is performed.
[0054]
4 and 5 show the 2-line addition operation in the horizontal transfer register of this embodiment.
4 shows a schematic diagram of the signal charge transfer operation, FIG. 5A shows a vertical simultaneous timing chart, and FIG. 5B shows a horizontal synchronization timing chart.
[0055]
As shown in FIG. 4, the arrangement of the vertical transfer clocks V1A, V1B, V3A, and V3B applied to the lines 1 to 16 is the same as that in FIG.
However, as shown in FIGS. 5A and 5B, the same waveform is applied to both the first phase vertical transfer clocks V1A and V1B without distinguishing them, and the third phase vertical transfer clocks V3A and V3B are not distinguished from each other. Are applied with the same waveform. That is, the vertical transfer clock has the same four types of waveforms as those in the frame reading operation of FIG.
[0056]
Then, the two-line addition operation in the horizontal transfer register is performed as follows.
First, as shown in FIG. 5A, when the first-phase vertical transfer clocks V1A and V1B are at a high level, the signal charges of the sensor units 23 on the odd lines (red R and green G pixels) as the first field are vertical. Read to transfer register 25.
Thereafter, as shown in FIG. 5B, vertical transfer clocks V1A / V1B, V2, V3A / V3B, and V4 for each phase are supplied, whereby vertical transfer for two lines (four pixels) is performed, and the first line 1 Both the signal charges of the sensor unit 23 and the signal charges of the sensor unit 23 of the third line 3 are vertically transferred to the horizontal transfer register 26. As a result, the signal charges of the two lines of the first line 1 and the third line 3 are added in the horizontal transfer register 26.
In this state, the horizontal blanking period HBLK ends, and although not shown, a horizontal transfer clock is supplied, and the signal charges of the sensor units 23 of the first line 1 and the third line 3 transferred to the horizontal transfer register 26 are added. The charged charges are sequentially output through the charge-voltage converter 27.
[0057]
Thereafter, the vertical transfer in the horizontal blanking period HBLK and the horizontal transfer in the horizontal transfer register 26 are repeated, and the signal charges of all the pixels in the odd lines, that is, the first field are added by two lines in the horizontal transfer register 26. Is output.
[0058]
Subsequently, as shown in FIG. 5A, when the third-phase vertical transfer clocks V3A and V3B are at a high level, the signal charges of the sensor unit 23 of the even lines (green G and blue B pixels) as the second field are changed. Read to the vertical transfer register 25. The subsequent operation is the same as in the case of odd lines (first field).
In this way, the signal charges of all the pixels of the odd lines (first field) and even lines (second field) are added and output by two lines in the horizontal transfer register 26, respectively.
[0059]
When comparing FIG. 5A and FIG. 3B, the intervals at which the first-phase and third-phase vertical transfer clocks are at high levels and the number of vertical transfer clocks between them are expressed in the same way. The shape of the timing chart is schematically shown, and it does not indicate that both vertical transfer clocks are actually equal.
[0060]
In this operation mode, adding two lines of signals doubles the saturation signal amount and doubles the sensitivity, and the number of vertical lines is halved to eight out of 16 lines. The output period is shortened and the frame rate is doubled.
[0061]
In the conventional configuration, the horizontal blanking period HBLK in this operation mode is also equal in length to the horizontal blanking period HBLK in the frame read operation. Therefore, the overlap period of the vertical transfer clock in this two-line addition operation mode is as shown in FIG. Similar to the thinning-out operation, it was necessary to shorten the length to x / 2.
For this reason, the amount of charge handled by the vertical transfer register is reduced due to the propagation delay of the vertical transfer clock, and there is a problem that it is impossible to secure a double saturation signal amount.
[0062]
On the other hand, in the present embodiment, as shown in FIG. 5A, the horizontal blanking period HBLK is enlarged to be twice as long as the horizontal blanking period HBLK of the frame reading operation of FIG.
As a result, the length of the overlap period of the vertical transfer clock is the same x as in the frame read operation of FIG.
[0063]
According to the above-described embodiment, since the length of the overlap period of the vertical transfer clock is ensured to be equal to that in the frame reading operation of FIG. 3, the vertical transfer clock is propagated by high-speed driving. It is possible to prevent a delay from occurring, and it is possible to prevent deterioration in transfer efficiency of the vertical transfer register and reduction in the amount of charge handled.
Therefore, the two-line addition operation in the horizontal transfer register can double not only the sensitivity and frame rate but also the saturation signal amount, and the number of output lines is halved. Dynamic range imaging can be realized.
[0064]
In the present embodiment, the length of the horizontal blanking period HBLK is twice that of the frame reading operation of FIG. 3, and the length of the overlap period of the vertical transfer clock is set to x which is the same as that of the frame reading operation of FIG. However, the enlargement ratio of the horizontal blanking period is not limited to twice, and it is considered as required in consideration of the characteristics (frame rate, sensitivity, dynamic range, etc.) required in the 2-line addition operation. What is necessary is just to expand to a magnification.
[0065]
Even when the horizontal blanking period is expanded depending on the operation mode as in the above-described embodiments, particularly in the case of an image sensor with multiple pixels, the total number of clocks in the horizontal synchronization period = the total number of horizontal pixels + the horizontal blanking. Since it is the number of clocks in the period and the number of clocks in the horizontal blanking period << the total number of horizontal pixels, it does not lead to an extreme increase in the frame rate.
[0066]
For example, assuming that the horizontal blanking period HBLK is about 10% of the horizontal synchronization period H in the prior art, the horizontal blanking period HBLK can be increased to twice that of the conventional horizontal blanking period HBLK as shown in FIGS. H is only about 10% longer.
The length of the frame is the product of the horizontal synchronization period H and the number of times, and if the number of output lines (number of lines to be selected) and the number of lines to be added are the same (that is, the operation is the same), the horizontal synchronization period H Are the same, and the length of the frame is proportional to the length of the horizontal synchronization period H.
Therefore, even if the horizontal blanking period HBLK is doubled, the frame length only increases by about 10%, so the degradation of the frame rate (the number of frames handled within a unit time) is small. No noticeable difference appears.
[0067]
When the number of stages to be vertically transferred is increased during the horizontal blanking period HBLK, for example, when the thinning operation or the addition operation is performed as described above, the horizontal blanking period HBLK necessary for outputting all the selected pixels. In addition, since the number of horizontal synchronization periods H is reduced, the frame length is shortened, and as a result, the frame rate can be increased.
Since the deterioration of the frame rate when the horizontal blanking period HBLK is lengthened is small, the frame rate increased by increasing the number of stages for vertical transfer in this way can be substantially maintained.
[0068]
In the operation mode in which priority is given to the frame rate, it is conceivable to reduce the horizontal blanking period HBLK to the minimum necessary level (that is, to reduce the vertical transfer period to the minimum necessary) on the basis of other operation modes.
In this case, the horizontal blanking period HBLK is relatively shortened and the horizontal synchronization period H is also shortened as compared with the other operation modes, so that the frame rate can be further increased.
[0069]
Therefore, according to the present invention, it is possible to optimize the horizontal blanking period for each operation mode and achieve both a sufficient amount of charge handled by the vertical transfer register and a high frame rate.
[0070]
In each of the above-described embodiments, the present invention is applied to a frame readout type CCD solid-state imaging device. However, the present invention is not limited to the frame readout type, and an all-pixel readout type CCD solid-state imaging device or other types of solid-state imaging. It is also possible to apply to an element.
[0071]
Further, the number of operation modes is not limited to two or three, and the present invention can be similarly applied to a solid-state imaging device having four or more operation modes.
In the present invention, in at least one of the plurality of operation modes, the length of the vertical transfer period is different from that of the other operation modes. For this purpose, for example, the length of the horizontal blanking period is set to be different from the length of the horizontal blanking period in other operation modes.
[0072]
The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.
[0073]
【The invention's effect】
According to the above-described present invention, in an image sensor having a plurality of operation modes, in at least one operation mode, the length of the vertical transfer register, that is, the length of the vertical transfer period is set to the vertical length of the other operation modes. By setting the length different from the transfer period, the length of the vertical transfer period can be optimized for each operation mode.
[0074]
For example, when the vertical transfer period is lengthened, the vertical transfer can be performed at a low speed, so that the propagation delay of the vertical transfer clock hardly occurs, and the waveform does not become dull even at a position far from the input terminal of the clock.
As a result, a vertical transfer clock having a required waveform is applied, and deterioration in transfer efficiency of the vertical transfer register and reduction in the amount of charge handled by the vertical transfer register can be prevented.
Since the rate of increase in the frame length due to the length of the vertical transfer period is small and the deterioration of the frame rate is small, for example, a high frame rate can be maintained.
Therefore, even in an operation mode in which the number of stages of vertical transfer during the horizontal blanking period is large and high-speed transfer is performed, it is possible to achieve both a high frame rate and a sufficient amount of charge handled by the vertical transfer register.
[Brief description of the drawings]
FIGS. 1A to 1C are diagrams illustrating a line thinning + horizontal transfer register 2-line addition operation according to an embodiment of the present invention.
FIG. 2 is a schematic configuration diagram of an embodiment of a solid-state imaging device to which the present invention is applied.
FIGS. 3A to 3C are diagrams illustrating a frame reading operation in the solid-state imaging device of FIG.
FIG. 4 is a diagram illustrating a 2-line addition operation in a horizontal transfer register according to another embodiment of the present invention.
FIGS. 5A and 5B are diagrams illustrating a 2-line addition operation in a horizontal transfer register according to another embodiment of the present invention. FIGS.
FIGS. 6A to 6C are diagrams illustrating a frame reading operation in a conventional solid-state imaging device. FIGS.
FIGS. 7A to 7C are diagrams illustrating line thinning operations in a conventional solid-state imaging device. FIGS.
FIGS. 8A to 8C are diagrams for explaining line thinning + horizontal transfer register 2-line addition operation in a conventional solid-state imaging device; FIGS.
[Explanation of symbols]
20 solid-state imaging device, 21 CCD solid-state imaging device, 22 imaging area, 23 sensor unit, 24 readout gate unit, 25 vertical transfer register, 26 horizontal transfer register, 27 charge-voltage conversion unit, 28 timing generation circuit, φV1A, φV1B, φV2, φV3A, φV3B, φV4 Vertical transfer clock, φH1, φH2
Horizontal transfer clock

Claims (2)

A plurality of two-dimensionally arranged photoelectric conversion elements;
A gate portion for reading signal charges photoelectrically converted by the plurality of photoelectric conversion elements;
A plurality of vertical transfer registers that transfer the signal charges read by the gate unit in the vertical direction;
A horizontal transfer register for horizontally transferring the signal charges transferred from the plurality of vertical transfer registers;
Driving means for driving the vertical transfer register and the horizontal transfer register;
A horizontal blanking period including a period in which signal charges are transferred by the vertical transfer register and a period in which signal charges are transferred by the horizontal transfer register constitutes a horizontal synchronization period.
Said drive means, the number of stages of the vertical transfer of the vertical transfer register is performed during the horizontal blanking period, the length of the period during which the signal charge by the vertical transfer register is transferred, the horizontal blanking period and the horizontal synchronization period A solid-state imaging device that increases or decreases the length of both . A plurality of two-dimensionally arranged photoelectric conversion elements;
A gate portion for reading signal charges photoelectrically converted by the plurality of photoelectric conversion elements;
A plurality of vertical transfer registers that transfer the signal charges read by the gate unit in the vertical direction;
In a method for driving a solid-state imaging device having a horizontal transfer register that horizontally transfers signal charges transferred from the plurality of vertical transfer registers,
Multiple operation modes with different number of vertical transfer stages performed during the horizontal blanking period
A horizontal blanking period including a period in which signal charges are transferred by the vertical transfer register and a period in which signal charges are transferred by the horizontal transfer register constitutes a horizontal synchronization period.
In response to the plurality of operation modes, the length of the period during which the signal charge by the vertical transfer register is transferred, a length of the horizontal blanking period and the horizontal synchronization period, both lengthening or shortening A method for driving a solid-state imaging device.

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