JP4700914B2 - Active matrix electroluminescence display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an electroluminescence display device, and more particularly to an electroluminescence display device that is not limited to using a light-emitting diode made of a semiconducting conjugated polymer or other organic semiconductor material. The invention also relates to a method of manufacturing such a device.

  Such active matrix electroluminescent display devices are known and the display device has an array of pixels present on a circuit board, each pixel being an electroluminescent element, typically made of an organic semiconductor material. Have. The electroluminescent element is connected to a circuit configuration on the substrate, for example, a matrix address circuit configuration having address (row) lines and signal (column) lines and a drive circuit configuration having supply lines. These lines are generally constituted by thin film conductor layers in the substrate. The circuit board also includes an address element and a drive element (typically a thin film transistor, hereinafter referred to as “TFT”) for each pixel.

  In many such arrays, a physical barrier of insulating material exists between adjacent pixels in at least one direction of the array. Examples of such barriers include British Patent Application Publication No. 2347017, International Publication No. 1-99 / 43031, European Patent Application Publication No. 0895219, European Patent Application Publication No. 1095568 and European Patent Application Publication No. No. 1102317, which is hereby incorporated by reference in its entirety.

  Such barriers are used in part, for example, by the terms “wall”, “partition”, “bank”, “rib”, “separator” or “dam”. As understood from the cited literature, it plays several roles. They can be used in manufacturing to define electroluminescent layers and / or electrode layers of individual pixels and / or columns of pixels. In this way, for example, the barrier can be spin coated for monochromatic display or imprinted for red, green and blue pixels of color display. Avoid pixel overflow. Barriers in the manufactured devices can provide a well-defined optical separation of the pixels. The barrier also supports or consists of a conductive material (such as the upper electrode material of the electroluminescent element) as an auxiliary wiring for reducing the electrical resistance of the common upper electrode of the electroluminescent element (and hence the voltage drop). It is possible.

  An active matrix electroluminescent display device having a switched current mirror pixel circuit can achieve very good image quality. Such a display device is disclosed in US Patent Application Publication No. 2001/0052606, and the description of the invention is partially substituted by using the content of the document. This requires a display column addressed by a weak current in the display line time. For large display devices with large column capacitances, this means that the time constant for addressing the pixel to the correct current level is large. High resolution for display makes the situation more difficult by shortening the line time.

  It is an object of the present invention to identify certain features of an active matrix electroluminescent display device in a manner compatible with the basic device structure, its layout and electronics to reduce such problems associated with signal lines (column conductors). To develop, adapt and / or extend.

  According to a feature of the invention, the physical barrier between the pixels is formed using an electrically conductive material (typically metal), i.e. at least part of the signal lines (column conductors) at a higher level than the circuit board. Used to prepare. In this way, the column capacitance problem moves from within the scope of the circuit board (these problems are strictly limited by the layout of the circuit configuration) to a fairly free environment of pixel barriers on the board. This transition facilitates the reduction of the column capacitance and hence the time constant for addressing the pixel to the correct current level. The conductive barrier material is connected to the matrix address circuitry in the circuit board and is also insulated on at least the side of the barrier adjacent to the electroluminescent element.

  In accordance with the present invention, considerable versatility is possible. Various structural features can be employed for the pixel barrier. Thus, the pixel barrier can be based on a conductive material or an insulating material, and can have an insulating coating and / or a conductive coating. Preferably, an inter-capacitance guard line is provided at least between the signal line of the barrier and the circuit configuration of the circuit board. A voltage buffer can be connected between the signal line and the guard line in order to keep the voltage between them approximately zero.

  In accordance with another aspect of the present invention, an advantageous method of manufacturing an active matrix electroluminescent display device or the like is provided.

  Various advantageous features and combinations of features according to the present invention are set forth in the accompanying claims. These and other features will become apparent in the embodiments of the present invention described below by way of example with reference to the accompanying drawings.

  It should be noted that all the figures are schematic diagrams. The relevant dimensions and proportions of the components in these figures are shown by increasing or decreasing the size for convenience and clarity in drawing. In general, the same reference numbers are used to represent corresponding or similar features in modified and different embodiments.

Embodiment of FIGS. 1-3 The active matrix electroluminescent display device of the embodiment of FIGS. 1-3 has an array of pixels 200 on a circuit board 100 having a matrix address circuit configuration. A physical barrier 210 is between at least some adjacent pixels in at least one direction of the array. At least some of these barriers 210 are constructed using a conductive barrier material 240 that is used as at least some signal lines (column conductors) in accordance with the present invention. Except for the use of the barrier 210 according to the present invention and this particular configuration, the display device can be constructed using known device and circuit techniques, as in the background reference above. .

  The matrix address circuit configuration has a transverse set of address (row) lines 150 and signal (column) lines 160, respectively, as shown in FIG. An address element T2 (typically a thin film transistor, hereinafter referred to as “TFT”) is incorporated at the intersection of each of these address (row) lines 150 and signal (column) lines 160. It should be understood that FIG. 1 shows one particular pixel circuit configuration as an example. Other pixel circuit configurations are known for active matrix electroluminescent display devices. It should be readily understood that the present invention can be applied to pixel barriers in such devices regardless of the specific pixel circuit configuration of the device.

  As shown in FIG. 1, each pixel 200 is a current-driven electroluminescence element 25 (21, 22, 23), and typically includes a light emitting diode (LED) made of an organic semiconductor material. The LED 25 is connected in series with a drive element T1 (typically a TFT) between the two voltage supply lines 140 and 230 of the array. These two supply lines are typically a power supply line 140 (having a voltage Vdd) and a ground line 230 (also referred to as a “return line”). The light emission from the LED 25 is controlled by the current through the LED 25 so as to be changed by each drive TFT T1.

Each row of pixels is addressed sequentially in a frame period by a selection signal applied to the associated row conductor 150 (and hence the gate of the row pixel address TFT T2).
This signal turns on address TFT T2 and therefore loads the row of pixels with the respective data signal from column conductor 160. These data signals are applied to the gates of the individual drive TFTs T1 of the respective pixels. In order to maintain the conduction state obtained as a result of the driving TFT T1, this data signal is maintained at the gate 5 by a holding capacitor Ch coupled between the gate 5 and the driving lines 140, 240. In this way, the drive current flowing through the LED 25 of each pixel 200 is controlled by the TFT T1 based on the drive signal applied during the previous address period and stored as a voltage in the associated capacitor Ch. In the specific example of FIG. 1, T1 is shown as a P-channel TFT and T2 is shown as an N-channel TFT.

  This circuit configuration can be configured using known thin film technology. The substrate 100 can have an insulating glass substrate 10 on which an insulating surface buffer layer 11 of silicon oxide is deposited, for example. The thin film circuit configuration is formed on the insulating surface buffer layer 11 by a known method.

  FIG. 3 shows a specific example of the TFT T2, in which an active semiconductor layer 1 (typically polysilicon), a gate dielectric layer 2 (typically silicon oxide), a gate electrode 5 ( Metal electrodes 3 and 4 (typically aluminum or polysilicon) and in contact with the doping source and drain regions of the semiconductor layer 1 through windows (vias) in the overlying insulating layers 2 and 8 Shows a specific example of TFT T2 each having aluminum.

  Depending on the specific TFT (eg, T1, T2 or other TFT of the circuit board) and its circuit function, the extension of the electrodes 3, 4 and 5 can be, for example, the electrodes T1, T2, Ch and the LED 25 and / or An interconnect between conductive lines 140, 150 and 160 is formed. FIG. 3 shows a partial extension 160 a of a small area of the electrode 4 of T 2 as a connection to the signal line 160. The line extension of the gate electrode 5 at T 2 constitutes an address (row) line 150. The line extension of the electrode 4 of T1 (not shown in FIG. 3) can constitute a power supply line 140.

  The storage capacitor Ch can be formed as a thin film structure inside the circuit board 100 by a known method.

  The LED 25 is typically composed of a light emitting organic semiconductor material 22 between the lower electrode 21 and the upper electrode 23. In a preferred specific embodiment, a semiconducting conjugated polymer can be used for the electroluminescent material 22. For an LED that transmits light 250 through the substrate, the lower electrode 21 can be an anode made of ITO (Indium Tin Oxide), and the upper electrode 23 is made of, for example, calcium and aluminum. It can be a cathode. FIG. 3 shows an LED in which the lower electrode is formed as a thin film on the circuit board 100. The next doped organic semiconductor material 22 is in contact with the thin film electrode layer 21 of the window portion 12a in the planar insulating layer 12 (eg, silicon nitride) extending over the thin film structure of the substrate 100.

As in known devices, the device of FIGS. 1-4 according to the present invention has a physical barrier 210 between at least some adjacent pixels in at least one direction of the array. These barriers 210 also use the terms “wall”, “partition”, “bank”, “rib”, “separator” or “dam”, for example. Depending on the specific device embodiment and its manufacturing method, they are used in a known manner. For example,
• While adjusting the semiconducting polymer layer 22, the polymer solution overflows between the respective regions of the individual pixels 200 and / or the columns of the pixels 200 and is separated.
Other electroluminescent layers 22 or semiconducting polymers for individual pixels 200 and / or columns of pixels (or individual electrodes for the pixels, eg self-underlying individual layers of the upper electrode 23 It provides self-patterning capability to the substrate surface in a limited range (even separation).
It acts as a spacer for the mask over the substrate surface at least during the deposition of the organic semiconductor material 22 and / or electrode material.
When the light 250 is emitted through the top, it constitutes an opaque barrier 210 (instead of or in conjunction with the bottom substrate 100) for a well-defined optical separation of the pixels 200 in the array.

  Whatever the specific use in these known schemes, at least some of the insulating portions of the physical barrier 210 in embodiments of the present invention are used and configured in a particular manner. Therefore, the pixel barrier 210 of FIG. 3 provides at least a portion of the signal lines (column conductors) at a higher level than the circuit board 100, thus reducing the column capacitance, metal 240 (or other electrical conductivity). Material 240).

  This conductive barrier material 240 is insulated on its side adjacent to the LED 25 and connected to the main electrode 4 of the address TFT at its extension 160a. As shown in FIG. 3, this connection of the conductive barrier material 240 to the TFT T2 is made at individual connection windows 12b in the intermediate insulating layer 12 in each pixel along the column. In this way, the conductive barrier material 240 can provide the signal line 160 over most of their distance adjacent to the pixel.

This specific configuration and use of the barrier 210 for the signal line 160 according to the present invention allows for the reduction of the prior art column capacity shown in FIG. Thus, FIG. 2 shows the capacitance understood by the signal (column) line at each individual pixel in a typical prior art arrangement. In such a known arrangement, the signal (column) line 160X, for example, the line extension 160X of the electrode 4 of the TFT is formed in the entire circuit board 100. The barrier 210X is simply made of an insulating material (for example, an insulating polymer). Parasitic capacitances (C _D and C _SN ) exist across the dielectrics 12 and 210X between the thin film column line 160X and the upper electrode 23 of the LED (typically the cathode in the polymer LED 25). . Thin column line 160X, between each power supply line 140 and an address (row) line 150, (typically silicon nitride) dielectric 8 across, resulting a large parasitic capacitance _{C P} and _{C A} . As a result of the large column capacitance, the time constant for addressing individual pixels in the array of devices to the correct current level is unacceptably large for large display devices.

The present invention is configured with a pixel barrier 210 with a metal 240 (or other electrically conductive material 240) in the pixel region as a signal line (column conductor) 160, ie, at a higher level than the circuit board 100. This avoids this problem. Therefore, as can be seen from FIG. 3, the upper planarizing insulating layer 12 of the circuit board 100 is now located between the signal line 160 and the thin film line 150 and 5, 150 of the circuit board 100 where the barrier is formed. Inserted as an additional dielectric. Therefore, a large parasitic capacitance _{C P,} and _{C A} is greatly reduced.

  FIG. 3 illustrates a specific example in which the pixel barrier 210 is an electrically conductive material 240, 240x, preferably composed of a very low resistance metal (eg, aluminum, copper, nickel or silver). An embodiment is shown. Thus, these barriers 210 in FIG. 3 are a bulk or core of conductive material having an insulating coating 40 (eg, silicon oxide or silicon nitride) on the top and sides of the barrier. Have FIG. 3 shows, as an example, the upper electrode 23 of the pixel LED 25 adjacent to the insulating coating 40. Thus, the electrodes 23 can have a striped geometric configuration in a layout that traverses the pixel array. Also, if a sufficiently thick insulator is used for the insulating coating 40, the pixel array can have a common electrode 23 that extends at the pixel barrier 210.

4 and 5 Selective Column Line Barrier Embodiment FIG. 4 illustrates an improved embodiment where the barrier 210 is based on an insulating material 244. In this case, the via 244b is etched and formed through the insulating material 244 toward the circuit elements 4 and 5 in the circuit board 100. Metal coating 240 provides a conductive barrier material that extends on top of insulating barrier 210 and via 244b.

  The metal coating 240 of the barrier 210 can be formed simultaneously with the main portion 23a of the upper electrode 23 of the LED 25 in a self-alignment manner. Therefore, as shown in FIG. 4, the metal layer can be exposed at the same time because of the electrode 23 and the metal coating 240 separated by the effect of the protruding shadow mask on the side of the barrier 210. . This is one effective process embodiment for column line barriers 210, 240 in accordance with the present invention. FIGS. 11-13 illustrate other process embodiments for metal-based column line barriers 210,240.

  FIGS. 4 and 5 illustrate both guard line features that may also be advantageously included in embodiments of the present invention. In this embodiment, the thin film conductor layer 9 (which can be formed simultaneously with the TFT electrode regions 3, 4, and 160 a) extends as an intercapacitor guard line below the conductive barrier material 240 of the signal line 160. Therefore, this guard line 9 exists as a shield between the circuit configuration of the substrate 100 and the column line 160 over most of its distance. FIG. 6 shows the capacitance understood here by the column line 160 over each individual pixel. In particular, a very small column capacitance can be achieved when the arrangement of FIG. 6 is used with the advantageous buffer circuit features as shown in FIG.

In embodiments of the specific embodiments of the guard line 6 of FIG. 6 and 7, each of the capacitance C _P and C _A of the power lines 140 and row lines 150, as in Figure 2 the guard line 9 (prior art (Not across the column line 160) (crossing the dielectric 8). Further, each of capacitance _{C SN} and _{C D} of the dielectric 12 and 244 is formed between the guard line 9 and column line 160 in the embodiment of FIG.

  Here, a very small column capacity can be achieved using the buffer circuit configuration of FIG. In this case, the voltage buffer 600 is connected between the column line 160 and the guard line 9. The basic circuit of FIG. 7 is of a known type, except that it includes a barrier configuration of buffer 600, guard line 9 and column line 160. Thus, reference numeral 620 may represent a known type of current mirror pixel circuit, such as disclosed in, for example, US Patent Application Publication No. 2001/0052606. The signal is supplied to column line 160 by, for example, a column driver 610 of a known current sink type. The column driver 610 and the voltage buffer 600 can be implemented externally in an IC (integrated circuit) connected to the circuit board 100. Also, they can be integrated and integrated in the circuit board 100 using polysilicon TFT technology.

The voltage buffer 600 takes the signal voltage at the output of the column driver 610 as an input and buffers it on the guard line 9. As a result, the voltage between the column line 160 and the guard line 9 becomes 0 or substantially 0. Therefore, no charge is accumulated in the column-guard capacitors CD and CSN, and all current is drawn from the pixel circuit 620. . This allows for fast operation. The voltage buffer, guard line 9, it is necessary to vary the capacitance C _P and C _A between the respective power lines 140 and address lines 150, a small output impedance of buffer 600 this change is achieved faster Make it possible.

8 and 9 Embodiment of the Multiconductor Barrier The embodiment of FIG . 8 is similar to the embodiment of FIG. 3 in that the barrier 210 has a metal core 240x with an insulative coating 40a. However, the embodiment of FIG. 8 further has a metal coating 240y present on the insulating coating 40a across the sides and top of the core 240x.

  The structure of FIG. 8 is more versatile than the structure of FIG. That allows the metal core 240x and the metal coating 240y to be used for different purposes. Thus, for example, the metal core 240x provides a column (signal) line 160 as in FIG. 3 and can therefore be connected to the electrode 4 of the TFT T2. The metal coating 240y can function as a coaxial shield for signals in the core line 240x. The metal coating 240y can be connected to a part of the guard line 9b in the substrate 100 and / or to other circuit elements of other TFTs, for example. Also, the metal coating 240y can be provided on the column (signal) line 160, and the metal core 240x can constitute a part of the guard line 9a.

  Instead of shielding the column (signal) line 160, this multi-conductor structure 240x, 240y of the barrier 210 is intended for different purposes, such as overlapping two lines, such as 140 and 150, or constituting additional components. Therefore, it can be used anywhere in the device. The metal coating 240y can be localized at specific locations along the barrier 210 where specific connections or components are required, such as, for example, individual pixels or subpixels.

  Of particular importance is the embodiment in which the multiconductor structures 240x, 240y of FIG. 8 are designed to constitute a capacitor having a capacitor dielectric 40a. Therefore, the separation distance portion and / or the insulation distance portion of the metal core 240x, the insulating coating 40a, and the metal coating 240y can be configured together with a capacitor connected between the substrate circuit elements 4, 5 and the like. is there. Such a capacitor may be, for example, each respective pixel connected between a supply line 140 (main electrode line 4 of TFT T1) and a gate line 5 of TFT T2 (and main electrode line 3 of TFT T1). It is possible to be an individual storage capacitor Ch for 200.

  FIG. 9 shows a suitable pixel layout for integrating multi-conductor barrier configurations 240x, 240y, etc. as the sustaining capacitor Ch for each pixel region 200. FIG. In this case, the multi-conductor barrier configuration 240x, 240y has an insulating barrier distance that extends across the barriers 210 (240, 160) that make up the row.

  Also, the lateral barrier layout of FIG. 9 can be adapted with each barrier 210 and 210c having a single metal conductor 240 (without metal coating 240y) as in FIG. 3 or FIG. Is possible. In this case, the conductive barrier material 240 of the lateral barrier 210c may be connected to the gate line 5, 150 of the TFT T2 in order to back up the distance of the address (row) line 150 and / or to replace it. Is possible. The line barrier has a cross-sectional area in which the line resistance of the row line is at least twice (possibly even an order of magnitude) larger than the area of the conductive layer typically provided on the circuit board 100 of the TFT gate line 5 (150). Due to the material 240, it can be significantly reduced in this way. Furthermore, the gate line 5 (150) is typically doped polysilicon, and the conductive barrier material 240 is typically a metal having a fairly high conductivity.

Process Embodiments of FIGS. 10-12 Other than comprising using a barrier 210 with an interconnect material 240 for the signal line 160, an active matrix electroluminescent display device according to the present invention is described, for example, in the background described above. Can be constructed using known device technology and circuit technology.

FIGS. 11-12 illustrate the novel process steps in a specific manufacturing embodiment. The thin film circuit board 100 with the upper planar insulating layer 12 (eg, silicon nitride) is manufactured by known methods. Connection windows (eg, vias 12a, 12b, 12x, etc.) are opened in the upper planar insulating layer 12 in a known manner, for example, by photolithography masking and etching. However, in order to fabricate the device according to the present invention, these via patterns are used to connect the metal electrode 4, the gate electrode 5, the address line 150, etc. for bottom connection to the conductive barrier material 240, 240x, 240y, etc. Extending vias 12b, 12x are provided. The resulting structure is shown in FIG. At this stage, the barrier 210 is
Regardless of whether it has a metal core as in FIGS. 3 and 8 or is based on an insulating material as in FIG.

  The formation of the barrier 210 mainly composed of an insulating material has been described above with reference to FIG. Suitable process steps for a barrier having a metal core will be described below with reference to FIGS.

  In this case, the electrically conductive material for the barrier 210 is deposited on the insulating layer 12 at least in the vias 12a, 12b, 12x and the like. The preferred distance and layout pattern for the barrier 210 can be obtained by using known masking techniques. FIG. 11 illustrates an embodiment in which at least a bulk of a conductive barrier material (eg, copper, nickel or silver) is deposited by a plating method. In this case, for example, a thin seed layer 240a made of, for example, copper, nickel, or silver is deposited covering the insulating layer 12 and the vias 12a, 12b, 12x, etc., and the barrier layout pattern is formed using a photolithography mask. Then, a bulk 240 of conductive barrier material is formed by plating to a preferred film thickness. The resulting structure is shown in FIG.

  An insulating material (eg, silicon oxide or silicon nitride) is then deposited for the insulating coating 40 using CVD (Chemical Vapor Deposition). This deposited material is left on the side and top surfaces of the conductive barrier material by patterning using known photolithographic masking and etching techniques, as shown in FIG.

  After this, production is continued in a known manner to form the LED 25. Thus, for example, the conjugated polymer material 22 can be printed using inkjet or spin coated for the pixel 200. The barriers 240, 40 with the insulating coating 40 can be used in a known manner to prevent polymer overflow from the pixel area between the physical barriers 240, 40. The upper electrode material 23 is then deposited.

Improved Process Embodiment of FIG. 13 This embodiment uses an anodization process (instead of deposition) to provide an insulating coating on at least the sides of the barrier 210 adjacent to the pixel region. Typically, the conductive barrier material 240 can comprise aluminum. Known photolithography masking and etching techniques can be used to define the preferred distance and layout pattern of the deposited aluminum. FIG. 17 shows an etchant mask limited by photolithography held on top of an aluminum barrier pattern 240.

  An anodized insulating coating of aluminum oxide is then formed on at least the sides of the aluminum barrier material 240 using known anodizing techniques. Therefore, no additional mask is required for this coating 40 to define the layout.

  As shown in FIG. 17, the mask 44 can be held during this anodization in the region where it is desired to form and protect the non-insulating upper connection region 240t. In this case, the coating by anodic oxidation is formed only on the side of the aluminum barrier pattern 240. The mask 44 can be removed prior to this anodization from areas where anodization coating is required on both the top and sides of the aluminum barrier pattern 240. Also, a mask 44 made of an insulating polymer or, for example, silicon oxide or silicon nitride, is held in this region where insulation is desired above the barrier 210 (240, 40) in the device being manufactured. It is possible.

  In the above embodiment, the conductive barrier material 240 is a thick opaque metal, such as aluminum, copper, nickel or silver. However, other conductive materials 240 are used, such as metal silicides or (although not advantageous) degenerately doped polysilicon that can be surface oxidized to form the insulating coating 40. It is possible. If a transparent barrier 210 is required, ITO can be used for the conductive barrier material 240.

  Those skilled in the art will appreciate from reading the present disclosure that various other improvements are possible. Such various improvements may have other equivalent features that are already well known in the art and can be used in addition to or in place of the features described above. Is possible.

  The claims were formulated in the application of the present invention to specific feature combinations, regardless of whether the present invention relates to the same invention as previously claimed in any claim, and Regardless of whether or not all or any of the technical problems similar to those improved by the present invention are improved, the disclosed scope of the present invention also covers any novel features, clearly or implicitly above. It should be understood that any novel combination of features disclosed, or any generalization of features, may be possessed.

  The Applicant therefore makes new proposals for any such features and / or combinations of such features during the procedure of the application of the invention or of any further application derived from the invention. Let us know that claims can be formulated.

FIG. 4 is a circuit diagram for four pixel regions of an active matrix electroluminescent display device that can include a conductive barrier material for signal lines according to the present invention. It is typical sectional drawing which shows the parasitic capacitance in the pixel area | region of the display apparatus of a prior art type. 1 is a cross-sectional view of a portion of a circuit board and a pixel array of one embodiment of an active matrix electroluminescent display device illustrating an example of a conductive barrier configuration for signal lines according to the present invention. FIG. 6 is a cross-sectional view of a portion of an apparatus having another example of a conductive barrier configuration using a metal coating for a signal line in accordance with the present invention. FIG. 5 is a plan view of a conductive layer pattern layout of the circuit board of the apparatus of FIG. 4 having guard lines in a specific embodiment of the apparatus according to the present invention. FIG. 6 is a cross-sectional view similar to the cross-sectional view of FIG. 2 showing the parasitic capacitance in the pixel region of the display device of FIGS. 4 and 5 according to the present invention. 7 is a circuit diagram of a voltage buffer configuration for a guard line in an embodiment of a device such as the embodiment of FIGS. FIG. 4 is a cross-sectional view of a conductive barrier configuration similar to the conductive barrier configuration of FIG. 3 with guard lines in the metal coating for an improved embodiment according to the present invention. FIG. 6 is a plan view illustrating an example of layout features for a specific embodiment of an apparatus according to the present invention having a lateral conductive barrier. FIG. 4 is a cross-sectional view of a portion of the apparatus as in FIG. 3 at a stage of manufacture using a specific embodiment according to the present invention. FIG. 4 is a cross-sectional view of a portion of the apparatus as in FIG. 3 at a stage of manufacture using a specific embodiment according to the present invention. FIG. 4 is a cross-sectional view of a portion of the apparatus as in FIG. 3 at a stage of manufacture using a specific embodiment according to the present invention. FIG. 13 is a cross-sectional view of a portion of the device at the stage of FIG. 12 showing an improvement in the insulator of the conductive barrier material in accordance with the present invention.

Claims (15)

An active matrix electroluminescent display device having a circuit board, wherein an array of pixels exists with at least a portion of a plurality of adjacent pixels in at least one direction of the array with a physical barrier:
Each pixel has an electroluminescent element;
Said circuit board comprises a matrix address circuit comprising pixels addressed via lateral address lines and signal lines;
The physical barrier includes at least a part of the signal line at a height higher than that of the circuit board, and is connected to the matrix address circuit of the circuit board through a contact window in an intermediate insulating layer on the circuit board. A conductive material that has been
The conductive barrier material is insulated on at least a side of the physical barrier adjacent to the electroluminescent element;
A conductor layer in the circuit board extends below the conductive barrier material of the signal line as an inter-capacitance guard line between the signal line and the matrix address circuit of the circuit board;
Active matrix electroluminescence display device. The active matrix electroluminescent display device according to claim 1,
The conductive barrier material, via individual contact windows for each pixel along the signal line is connected to the matrix addressing circuitry of the circuit board, an active matrix electroluminescent display device. An active matrix electroluminescent display device according to claim 1, the voltage buffer is connected between the guard lines and the signal lines, the active matrix electroluminescent display device. 4. The active matrix electroluminescent display device according to claim 1, wherein the physical barrier comprises the conductive barrier material of the signal line and through each circuit element in the substrate. 5. An active matrix electroluminescent display device having a metal coating connected to the pixel. An active matrix electroluminescent display device according to claim 4,
The physical barrier is mainly composed of an insulating material through which a via extends for connection with an electrode connection for the matrix address circuit in the contact window of the intermediate insulating layer, and the metal coating includes the physical coating barriers in the vias through the and extends to the top of the physical barrier, an active matrix electroluminescent display device. An active matrix electroluminescent display device according to claim 4,
An active matrix electroluminescent display device having an insulating coating on at least a side of the metal coating as an insulator adjacent to the electroluminescent element. The active matrix electroluminescent display device according to any one of claims 1 to 3, wherein the physical barrier comprises a metal core comprising the conductive barrier material of the signal line, the metal core comprising: An active matrix electroluminescence display device, which is connected to the pixel via each circuit element on the substrate and has an insulating coating on at least a side portion of the substrate. The active matrix electroluminescence display device according to claim 7,
An active matrix electroluminescent display device , wherein a metal coating is on the insulating coating on the sides and top of the metal core. 9. The active matrix electroluminescent display device according to claim 1, wherein an additional barrier extends parallel to the lateral address line and is insulated by the conductive barrier material of the signal line. An additional conductive barrier material, wherein the additional conductive barrier material is connected to a portion of the lateral address line in the substrate through a contact window so as to reduce a voltage drop along the lateral address line. It is the active matrix electroluminescent display device. An active matrix electroluminescent display device according to any one of claims 1 to 9, wherein the electroluminescent element is a light emitting diode of organic semiconductor material, an active matrix electroluminescent display device. A method for manufacturing an active matrix electroluminescent display device according to claim 1, comprising:
(A) opening a contact window in the intermediate insulating layer in the circuit board to expose electrode connections for the matrix address circuit in the circuit board;
(B) forming the physical barrier on the circuit board having an insulator on at least a side of the physical barrier adjacent to a pixel region; and (c) in the pixel region between the physical barriers Providing an electroluminescent element;
An active matrix electroluminescent display device having
Conductive material is deposited as part of the physical barrier to provide at least a portion of the signal line at a height higher than the circuit board, the conductive material passing through the contact window of the intermediate insulating layer. Connected to the electrode connection for the matrix address circuit;
A manufacturing method of an active matrix electroluminescence display device. 12. The method of manufacturing an active matrix electroluminescent display device according to claim 11, wherein the step (b) includes a step of forming the physical barrier mainly composed of the conductive material, and the conductive barrier. at least side insulation coating is deposited in the manufacturing method of the active matrix electroluminescent display device materials. A manufacturing method of an active matrix electroluminescent display device according to claim 12, at least the bulk is deposited by a plating method, a manufacturing method of an active matrix electroluminescent display of the conductive barrier material. 13. The method of manufacturing an active matrix electroluminescent display device according to claim 12, wherein the conductive barrier material includes aluminum, and the insulating coating is formed on at least a side portion of the aluminum barrier material by an anodic oxidation method. It is the manufacturing method of the active matrix electroluminescent display device. 12. The method of manufacturing an active matrix electroluminescent display device according to claim 11, wherein the step (b) is performed for connection with the electrode connection for the matrix address circuit in a contact window of the intermediate insulating layer. Forming a physical barrier based on an insulating material through which a via extends, the electrically conductive material of the signal line extending to the via passing through the physical barrier and the A method of manufacturing an active matrix electroluminescent display device , deposited as a conductive coating on top of a physical barrier.

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