JP4698944B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a method for designing a semiconductor integrated circuit and a semiconductor device, and more particularly to a technology effective when applied to a technology for calculating and measuring the influence of crosstalk between wirings in the design of a semiconductor device.

  In recent years, the aspect ratio (aspect ratio) l / d of the wiring cross section has been increased as shown in FIG. 25 in order to suppress an increase in wiring resistance as the device becomes finer and the wiring width becomes smaller. As a result, the ratio of capacitance between the same-layer wirings is increasing, and it is becoming more susceptible to crosstalk noise. A circuit for reducing such crosstalk noise is disclosed in Patent Document 1 and the like.

  One of the problems with crosstalk noise is delay variation due to crosstalk noise. The delay variation due to the crosstalk noise will be described with reference to FIG. The delay variation due to the crosstalk noise is caused by the inter-wiring capacitance existing between the damage side wiring VIC and the harming side wiring AGG as shown in FIG. 26A when the signal propagating through the harming side wiring AGG undergoes a state transition. This occurs because of the movement of the charge through the power supply, which affects the state transition of the victim wiring VIC. More specifically, for example, when the signal propagating through the victim side wiring VIC makes a state transition from Low to High as shown in FIG. 26B, the signal propagating through the victim side wiring AGG is shown in FIG. When the state transitions from High to Low as in (), before the signal propagating through the damage side wiring VIC exceeds the logical threshold, the charge on the damage side wiring VIC is transferred to the harm side wiring AGG via the inter-line capacitance. Since it is pulled out and the potential of the damage side wiring VIC falls to the low side as shown in FIG.

  Another problem is malfunction due to crosstalk noise. The malfunction due to the crosstalk noise will be described with reference to FIG. The malfunction due to the crosstalk noise is similar to the delay variation due to the crosstalk noise described above. When the signal propagating through the harming side wiring AGG undergoes a state transition, the capacitance existing between the damage side wiring VIC and the harming side wiring AGG is reduced. This occurs because of the movement of the charge through the power supply, which affects the state transition of the victim wiring VIC. More specifically, for example, when the signal propagating through the damage side wiring VIC is in a high state as shown in FIG. 27B, the signal propagating through the harm side wiring AGG is as shown in FIG. When the state transitions from High to Low, the charge of the damage side wiring VIC is extracted to the harm side wiring AGG via the inter-wire capacitance, and the potential of the damage side wiring VIC is changed to the Low side as shown in FIG. The signal propagating through the damaged wiring VIC exceeds the logic threshold value on the Low side. As a result, as shown in FIG. 27E, a Low signal appears at the output VICa of the next-stage gate of the victim wiring VIC, causing a malfunction.

  For example, as a technique studied by the present inventors, the following technique can be considered as a method for calculating the delay fluctuation amount due to the crosstalk noise in designing a semiconductor device.

  (A) A method of categorizing wiring net information into several cases and adding a crosstalk delay fluctuation value (crosstalk margin) set for each category.

  (B) Since there is no method for accurately obtaining the amount of delay fluctuation due to crosstalk noise, a method of pointing out a highly dangerous wiring from the parallel wiring length or the inter-wiring capacitance value, and performing a targeted circuit simulation from the capacitance extraction result.

  Further, as a method for determining the risk of malfunction due to the crosstalk noise, the following techniques are conceivable.

(C) The crosstalk noise itself is not calculated. As shown in FIG. 28, if the inter-wiring capacitance is Cp and the damage-side wiring VIC is Cg, the crosstalk generated in the damage-side wiring VIC. The noise generation amount Vnoise is considered to be based on the following equation from the law of conservation of charge and Kirchhoff's law.
Vdd = Vp + Vnoise (Kirchhoff's law)
Cp · Vp = Cg · Vnoise (law of charge conservation)
If Ctotal (total capacity of damaged wiring) = Cp + Cg,
Vnoise = Cp · Vdd / Ctotal
However, the full amplitude during IC operation is Vdd of the power supply voltage, and the potential difference generated between the wirings is Vp.
(I) A method of determining that there is a risk of malfunction (NG) when the sum of the parallel wiring capacitance Cp exceeds the allowable wiring capacitance Cpmax.
(Ii) Considering that the parallel wiring length Lp corresponds to the inter-wiring capacitance Cp and the wiring net length Lnet corresponds to Ctotal, an allowable wiring length Lpmax is set for each net length of the wiring, and the parallel wiring length is expressed by the following equation: A method of determining that there is a risk of malfunction (NG) when the total sum of Lp exceeds the allowable wiring length Lpmax.

(D) A simple parallel wiring length check or parallel wiring capacity check as shown in (c) above is performed, and for those wirings that are likely to have a high degree of risk, a circuit is extracted after aiming extraction. A method of performing simulations to detect the risk of malfunctions.
JP-A-10-326870

  As described above, it is considered that crosstalk noise becomes a serious problem as miniaturization progresses, and it has become necessary to accurately measure the amount of delay variation due to crosstalk noise.

  However, a circuit system for actually measuring the amount of delay variation due to crosstalk noise has not been proposed. One method for measuring the crosstalk noise is to apply a probe to the wiring where the crosstalk noise is considered to occur and measure the signal waveform. The inventors of the present application have found that there is a problem that the circuit conditions change due to the generation of capacitance in between, the probe itself becomes a noise generation source, and the measurement cannot be performed accurately. It was issued.

  Accordingly, an object of the present invention is to provide a semiconductor integrated circuit for actually measuring the amount of delay variation due to crosstalk noise.

  Further, as a result of the study of the present inventor on the method of calculating the delay fluctuation amount due to the crosstalk noise as described above, the following has been clarified.

  That is, in the method (a), when the crosstalk margin is set to the maximum value of the delay fluctuation amount for each wiring category, the margin becomes an excessive margin, the chip area and power increase for the countermeasure against delay, and the delay fluctuation value When the average value is set, there may be a case where an under-pointing occurs and a timing violation in the actual chip may occur. Further, in the method (b), it is conceivable that the simulation time is increased by pointing out excessively dangerous wiring.

  Accordingly, another object of the present invention is to provide a semiconductor device design method capable of calculating a delay fluctuation amount due to crosstalk noise between wirings in a short time with high accuracy.

  Furthermore, the following has been clarified as a method for determining the risk of malfunction due to crosstalk noise as described above.

  That is, as the miniaturization progresses, the resistance of the wiring is increased, and the parallel position dependency of the wiring is increased. In addition, the influence of the driving force of the gate of the harming side wiring has increased.

  Therefore, in the method (c), it is considered that dangerous wiring is excessively checked when the criterion is set to the safe direction. In addition, when the determination criterion is set in an average case, the amount of noise may be estimated low, and there is a risk of malfunction.

  Further, in the method (d), it is conceivable that the simulation time increases by pointing out excessively dangerous wiring.

  Accordingly, another object of the present invention is to provide a semiconductor device design method capable of accurately determining the risk of malfunction due to crosstalk noise between wirings in a short time.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) A semiconductor integrated circuit according to the present invention supplies a ring oscillator in which a plurality of inverters are connected in series in an odd number of stages, a first wiring provided along a part of the wiring of the ring oscillator, and the first wiring. A pulse generation circuit for generating a first pulse, a first buffer connected between the first wiring and the pulse generation circuit, and a second wiring connected between the pulse generation circuit and the first buffer The distance between the first wiring and a part of the ring oscillator is shorter than the distance between the second wiring and a part of the ring oscillator.

  (2) The semiconductor integrated circuit according to (1) includes a third wiring provided along a part of the wiring of the ring oscillator, and a second buffer connected between the third wiring and the pulse generation circuit. The third wiring is thicker than the first wiring.

  (3) In the semiconductor integrated circuits of (1) and (2), the first pulse transitions between the first level and the second level, and the second pulse is retained from the period in which the first pulse is held at the first level. A first mode in which a period held at a level is long, and a second mode in which a period held in the second level is shorter than a period held in the first level, and the pulse generation circuit includes the first mode A mode setting circuit for switching between the first mode and the second mode is provided.

  (4) A semiconductor device design method according to the present invention includes a first step of extracting a wiring net list from layout data, and an equivalent amount of delay variation due to crosstalk between wirings for each wiring of the wiring net list. A second step of obtaining a capacity; and a third step of performing a delay calculation based on the wiring net list using the equivalent capacity.

  (5) The method for designing a semiconductor device according to (4) further includes a fourth step of performing a delay calculation based on the wiring netlist between the first step and the second step. In step 2, the equivalent capacitance is obtained based on the information obtained in the fourth step, and in the third step, the wiring netlist is corrected based on the equivalent capacitance and corrected. The delay calculation is performed based on the wiring net list.

  (6) In the semiconductor device design method of (4) and (5), the equivalent capacitance is set to zero when there is no overlapping portion of the timing windows between the parallel wirings in the second step. is there.

  (7) In the semiconductor device design methods of (4) and (5), the equivalent capacitance is obtained by multiplying the original wiring capacitance by a capacitance conversion coefficient.

  (8) In the method for designing a semiconductor device according to (7), the capacitance conversion coefficient depends on a rise / fall time of a signal propagating through the parallel wiring.

  (9) In the semiconductor device design method of (7), the capacitance conversion coefficient is corrected based on the measurement result of the evaluation circuit.

  (10) In the method for designing a semiconductor device according to (9), the evaluation circuit is the semiconductor integrated circuit according to (1) or (2).

  (11) A semiconductor device design method according to the present invention includes a first step of extracting a wiring net list from layout data, and a second step of determining the amount of crosstalk noise generated in a victim wiring by the operation of each parallel wiring. A third step of obtaining the amount of noise that the crosstalk noise generation amount attenuates due to the resistance and capacitance of the victim side wiring and reaches the next stage gate of the victim side wiring; A fourth step for obtaining the sum total and a fifth step for comparing the sum of the noise amounts and the allowable noise amount to determine the risk of malfunction due to crosstalk noise.

  (12) The semiconductor device design method according to (11) further includes a sixth step of performing a delay calculation based on the wiring netlist between the first step and the second step. In two steps, the crosstalk noise generation amount is obtained based on the information obtained in the sixth step.

  (13) In the method for designing a semiconductor device according to (11) and (12), in the second step, the crosstalk noise generation amount is obtained by using a capacitance between wirings and a capacitance against a substrate.

  (14) In the method for designing a semiconductor device according to (11) and (12), in the second step, the crosstalk noise generation amount is obtained in consideration of an effective wiring length of the damaged wiring.

  (15) In the method for designing a semiconductor device according to (14), the effective wiring length is obtained from wiring characteristics (wiring resistance, wiring capacity, etc.) of the damage side wiring and rise / fall times of the harming side wiring. Is.

  (16) In the method for designing a semiconductor device according to (11) and (12), in the second step, the charge extraction effect associated with driving the preceding gate of the damaged wiring and the input of the subsequent gate of the damaged wiring The crosstalk noise generation amount is obtained in consideration of the capacity.

  (17) In the method for designing a semiconductor device according to (11) and (12), in the fourth step, the total amount of the noise is obtained in consideration of overlapping of timing windows of the respective harming side wirings.

  (18) In the method for designing a semiconductor device according to (11) and (12), in the second step, the coefficient in the calculation formula used when obtaining the amount of generated crosstalk noise is the measurement result of the evaluation circuit. Is corrected based on the above.

  (19) In the method for designing a semiconductor device according to (18), the evaluation circuit causes a damage-side wiring to be measured, a first pre-stage gate that drives the damage-side wiring, and a signal propagated through the damage-side wiring. Is input, a flip-flop to which the output of the first post-stage gate is input data, an attack-side wiring parallel to the damage-side wiring, and a second pre-stage gate that drives the victim-side wiring; The polarity of signals input to the first pre-stage gate and the second pre-stage gate, the driving force of the first pre-stage gate and the second pre-stage gate, the damage side wiring and the harm side wiring The parallel position, the wiring width of the harming side wiring, the logic inversion voltage of the first rear stage gate, and the data fetch timing of the flip-flop are variously set as the design and measurement conditions of the evaluation circuit. It is to measure the evaluation circuit.

  (20) In the semiconductor device design method according to (19), the evaluation circuit includes a variable delay circuit connected between the input part of the second pre-stage gate and the clock input part of the flip-flop. is there.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) It is possible to accurately measure the amount of delay variation due to crosstalk noise.

  (2) The amount of delay variation due to crosstalk noise can be calculated with high accuracy.

  (3) The amount of delay variation due to crosstalk noise can be calculated in a short time.

  (4) The risk of malfunction due to crosstalk noise can be determined with high accuracy.

  (5) The risk of malfunction due to crosstalk noise can be determined in a short time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing a flow of a semiconductor device design method according to the first embodiment of the present invention.

  First, an example of a method for designing a semiconductor device according to the first embodiment will be described with reference to FIG. The method for designing a semiconductor device according to the present embodiment calculates a delay variation amount due to crosstalk noise in designing a semiconductor device such as an LSI, and feeds it back to the circuit design. .

  (1) Placement and wiring are performed based on the circuit diagram 10 and the cell library 11 (step S100), and layout data 12 is created.

  (2) Factors such as the resistance component (R) and the capacitance component (C) are extracted from the layout data in an inter-wiring capacitance extraction mode (a mode in which all capacitances are not assumed to be ground (GND)) (step S101). Then, the wiring RC netlist 13 is created. The wiring RC netlist 13 is created in the form of SPEF (Standard Parasitic Exchange Format) or the like.

  (3) Based on the wiring RC netlist 13 and the delay library 14, STA (Static Timing Analysis) is executed to perform delay calculation (step S102). STA creates a delay library in advance and comprehensively performs delay calculation based on table lookup, interpolation, and calculation formulas. In delay verification in large-scale circuits such as the entire chip, It is essential. As a result of the STA, a summary 15 including a timing window of each signal, a rise time / fall time trf, delay information, and the like is output. In this delay information, the amount of delay variation due to crosstalk noise is not yet taken into account.

  (4) Based on the node information in the wiring RC netlist 13 and the information obtained in the STA in step S102, the amount of delay variation due to crosstalk noise is represented by an equivalent capacitance difference ΔC, and the wiring RC Netlist capacity value conversion (net conversion) is performed (step S103). Details of the calculation formula used at this time and the capacity conversion coefficient (K) and capacity conversion constant (A, B) used for the calculation will be described later.

  The capacitance conversion constants (A, B) used for the calculation of the capacitance value conversion are obtained from the result of circuit simulation and the measurement result of the evaluation circuit. The circuit simulation is performed based on the circuit diagram 10 and the device parameter 16 (step S104). The evaluation circuit is manufactured and measured as an IC based on the layout data 12 (step S105). Further, the capacitance conversion constant (A, B) 17 is adjusted by the actual measurement value of the evaluation circuit. The evaluation circuit will be described later.

  (5) Based on the converted / corrected wiring RC netlist (SPEF) 18 and the delay library 14, STA is executed again to calculate the delay (step S106). As a result of the STA, a summary 19 including timing information of each signal, rise time / fall time trf, delay information, and the like is output. The delay information in this is a value that takes into account the amount of delay variation due to crosstalk noise.

  (6) The circuit diagram is corrected based on the information obtained in (5) (step S107).

  Next, details of a calculation formula used for the capacitance value conversion (step S103) in the procedure (4) will be described.

  First, the concept of the timing window used in the following description will be described with reference to FIGS. 2A to 2C are diagrams for explaining the concept of the timing window, where FIG. 2A is a circuit diagram, and FIGS. 2B and 2C are timing charts.

  In general, in an LSI internal circuit, as shown in FIG. 2A, data holding circuits s1, s2, s3,..., Sk,. A plurality of gates (gate group 20) exist between the paths 3,..., The paths k,..., And the path n, and the signal propagation time of each path differs depending on the number of gates, the wiring length, and the like. FIGS. 2B and 2C show such a state, and the state in which the signal reaches the target net 22 via each path and the state transitions from Low to High is shown in FIG. 2) FIG. 2 (c) shows a state transition from High to Low. The range of timing from the earliest to latest state transition timing is referred to as a state transition timing window of the net of interest.

  FIGS. 3A to 3E are diagrams showing the relationship between the timing window and the crosstalk noise. FIG. 3A shows a state where the damage side wiring VIC and the harming side wiring AGG are parallel, and FIGS. (E) shows the timing when the signals of the victim side wiring VIC and the victim side wiring AGG change state. As shown in FIG. 3A, when the damage side wiring VIC and the harm side wiring AGG are adjacent and parallel to each other, an inter-wiring capacitance exists in this region. Crosstalk noise is generated because the charge moves through the inter-wiring capacitance when the signal on the harming side wiring changes state. 3B to 3D, the timing windows of the victim side wiring VIC and the victim side wiring AGG are overlapped, but in FIG. 3E, the timing windows are not overlapped. In such a case, (b) to (d) are affected by crosstalk noise, but (e) is not affected by crosstalk noise.

  In the procedure (4), the capacitance value conversion is performed for each victim side wiring. At this time, if the timing windows of the victim side wiring and the victim side wiring do not overlap, the distance between the victim side wiring and the victim side wiring is not changed. Capacitance to substrate (ground). That is, the total capacity is unchanged. The timing window considers the rise time / fall time trf.

When the timing windows overlap, the inter-wiring capacitance value C is converted by the following formula to make it to the substrate (ground).
C ′ = C (1 + K) = C + ΔC
K = A {1-exp (−B · | trfv / trfa |)} Expression (1)
| X | indicates the absolute value of x.

  Where C ′ is the capacity after conversion, C is the capacity before conversion, K is a capacity conversion coefficient, ΔC is a capacity difference equivalent to the amount of delay variation due to crosstalk noise, A and B are capacity conversion constants, and trfv is damage The rising / falling time of the side wiring, trfa is the rising / falling time of the harming side wiring. The capacitance conversion constants A and B are values determined for each process technology generation, and are obtained by actually measuring an evaluation circuit described later. In the formula (1), the most characteristic point is that trfv / trfa is used. This is based on the fact that the inventors of the present application have found that the value of ΔC has a correlation with trfv / trfa. Therefore, the above formula (1) is an example, and if trfv / trfa is used, C ′ can be obtained even if the formula is different from the above formula (1). However, in this specification, in order to make the description easy to understand, the following description will be made using Expression (1).

  Here, the expression (1) is applied when the state transition on the harming side and the state transition on the damage side are in reverse phase (the harming side rise and damage side fall, or the harming side fall and damage side rise). This is because the delay fluctuation value becomes a positive value in the case where the state transition is in the opposite phase, which triggers the MAX delay violation. On the other hand, there may be a case in which a MIN delay violation is caused by a crosstalk delay variation in the same phase.

If you want to add
(I) Multiply equation (1) by the value of sgn (-trfv / trfa) ← (function that returns a sign).
(Ii) K = A · tanh (B ′ · trfv / trfa)
Even if trfv / trfa is negative, it may be modified so as to produce a reasonable value.

  Further, a calculation formula when there are a plurality of harming side wirings in parallel with the damage side wiring will be described. FIG. 4 is a diagram showing the parasitic capacitance of each wiring when the harming side wirings AGGa and AGGb are parallel to both sides of the damage side wiring VIC. In FIG. 4, the parallel wiring capacitance Cpa is between the damage side wiring VIC and the harming side wiring AGGa, and the parallel wiring capacitance Cpb is between the damage side wiring VIC and the harming side wiring AGGb, and between the damage side wiring VIC and the substrate. To the board capacitance Cg (capacitance between wirings other than parallel wiring + sum of the capacitances against the substrate), and the capacitance between substrates AGa and the substrate Cga (capacitance between wirings other than the parallel wiring + sum of the capacitances against the board) However, a substrate-to-substrate capacitance Cgb (capacitance between wires other than parallel wires + sum of substrate capacitance) exists between the harming-side wiring AGGb and the substrate.

  At this time, it is assumed that there is no timing window overlap between the damage side wiring VIC and the harm side wiring AGGa, and there is a timing window overlap between the damage side wiring VIC and the harm side wiring AGGb.

When the influence of the crosstalk noise is not taken into consideration, the parasitic capacitance Ctotal in the damaged wiring VIC is expressed by the following equation.
Ctotal = Cg + Cpa + Cpb
On the other hand, when the influence of crosstalk is taken into consideration, the parasitic capacitance Ctotal in the damaged wiring VIC is expressed by the following equation.
Ctotal = Cg + Cpa + Cpb (1 + K)
Furthermore, the calculation formula in the case where there are a plurality of harming side wirings parallel to the damage side wiring will be described in detail with reference to FIG. FIG. 5A is a diagram showing a state in which the harming side wirings AGGa and AGGb are arranged on both sides of the damage side wiring VIC. FIG. 5B is a diagram showing the harming side wirings AGGa and AGGb on both sides of the damage side wiring VIC. It is a figure which shows the parasitic capacitance and parasitic resistance of each wiring in the case of being parallel. In FIGS. 5A and 5B, inter-wiring capacitances Cpa1, Cpa2, and Cpa3 are provided in adjacent and parallel portions (nodes A, B, C, and D) between the damage-side wiring VIC and the harm-side wiring AGGa. , Cpa4 have inter-wiring capacitances Cpb1, Cpb2, and Cpb3 at portions (nodes A, B, and C) that are adjacent and parallel between the victim wiring VIC and the harming wiring AGGb. Further, at nodes A, B, C, and D of the damage side wiring VIC, there are anti-substrate capacitances Cg1, Cg2, Cg3, and Cg4 between the damage side wiring VIC and the substrate. The capacitance with respect to the substrate between the harming side wirings AGGa and AGGb and the substrate is omitted. In addition, wiring resistance is divided between the nodes of each wiring.

  At this time, it is assumed that there is no timing window overlap between the damage side wiring VIC and the harm side wiring AGGa, and there is a timing window overlap between the damage side wiring VIC and the harm side wiring AGGb.

When the influence of the crosstalk is not taken into consideration, the parasitic capacitance Ctotal at the node A of the damage side wiring VIC is expressed by the following equation.
Ctotal = Cg1 + Cpa1 + Cpb1
On the other hand, when the influence of crosstalk is taken into consideration, the parasitic capacitance Ctotal at each node of the victim wiring VIC is expressed by the following equation.
Node A: Ctotal = Cg1 + Cpa1 + Cpb1 (1 + Ka)
Node B: Ctotal = Cg2 + Cpa2 + Cpb2 (1 + Kb)
Node C: Ctotal = Cg3 + Cpa3 + Cpb3 (1 + Kc)
Node D: Ctotal = Cg4 + Cpa4
However, K is a capacitance conversion coefficient, and can be expressed by the following formula when expressed by the capacitance conversion constants A and B, the rise / fall time trfv at each node of the victim side wiring VIC, and the rise / fall time trfb of the victim side wiring AGGb. It becomes like this.
K = A {1-exp (−B · | trfv / trfb |)}
That is,
Ka = A {1-exp (-B · | (trfv @ node A) / (trfb @ node A) |)}
Here, trf information at each node is used in order to improve calculation accuracy, but trf at the parallel start position or trf immediately after the source gate may be substituted for convenience of the STA tool and calculation time. . In many cases, sufficient accuracy can be obtained with trf at the parallel start position.

  Therefore, according to the semiconductor device design method of the first embodiment, the capacitance value of the wiring RC netlist (SPEF), which is a general input file, based on the delay information that is the execution result of the commercially available STA tool. It is possible to include the delay fluctuation amount due to the crosstalk noise in the delay calculation simply by applying correction to. In addition, since the circuit simulator traces the actual operation of the circuit, it is virtually impossible to execute the circuit simulation on the entire chip, whereas it is executed only within the STA framework, that is, the STA tool is executed twice. Thus, the amount of delay variation due to crosstalk noise can be calculated, and an exhaustive check can be performed in a short time. Also, a very accurate delay value can be obtained as compared with a conventional method such as categorizing for each wiring type. As a result, delay violations that could not be pointed out by design in the past are reduced, excessive points are reduced, and delay verification time is reduced. And since the delay violation was seen as the yield at the time of selection, it contributes to the yield improvement. In addition, an increase in chip area and an increase in power consumption caused by rearrangement for over-pointing net countermeasures and cell optimization are improved, and design time is shortened. Therefore, the design TAT (Turn Around Time) is reduced, the chip area is reduced, the LSI can be increased in speed and power consumption, and the yield is improved.

  In the above embodiment, the case where the STA tool and the net conversion (capacitance value conversion) tool are separate programs has been described. However, the function of the net conversion tool may be directly incorporated in the STA tool.

  A method of directly incorporating the delay fluctuation amount due to crosstalk noise into the delay calculation of the STA tool will be described with reference to FIG. FIG. 6 is a block diagram showing a modification of the semiconductor device design method of the first embodiment. In FIG. 6, steps (3) and (4) of the above embodiment are omitted, and in step (5) of the above embodiment, the amount of delay variation due to crosstalk noise is directly incorporated in the delay calculation of the STA tool, and the STA (delay Calculation). That is, step S102 (STA) and step S103 (capacitance value conversion) are omitted, and in the STA of step S106, the delay fluctuation amount due to crosstalk noise is directly incorporated in the delay calculation of the STA tool.

  Hereinafter, a method for directly incorporating the delay fluctuation amount due to the crosstalk noise into the delay calculation of the STA tool will be specifically described.

  First, the basic concept of delay in the wiring RC netlist will be described. 7A and 7B are conceptual diagrams showing the delay of the CMOS inverter circuit in the capacitance mode, where FIG. 7A is a circuit diagram composed of the CMOS inverter and the load capacitance Cl, and FIG. 7B shows the relationship between the delay Tpd and the load capacitance C. FIG. 8A and 8B are conceptual diagrams showing the delay of the CMOS inverter circuit in the RC delay mode. FIG. 8A is a circuit diagram including the CMOS inverter, the load capacitor Cw, and the load resistor Rw, and FIG. 8B is the delay Tpd and the load capacitor C. It is a figure which shows the relationship.

When the wiring resistance is not taken into consideration in the capacitance mode as in the circuit of FIG. 7A, when the input of the CMOS inverter is changed from low to high to discharge the charge of the load capacitance Cl, the delay Tpd and the load capacitance The relationship with Cl is as shown in FIG. 5B, and the delay Tpd can be expressed by the following equation.
Tpd = tpd0 + Cl · Ron
Here, Ron is the on-resistance of the nMOS transistor.

On the other hand, in the RC delay mode considering the wiring resistance as in the circuit of FIG. 8A, the relationship between the delay Tpd and the load capacitance Cw is as shown in FIG. 8B, and the delay Tpd is expressed by the following equation. Can be represented.
Tpd = tpd0 + Cw · (Ron + k · Rw / 2)
However, k is an RC delay correction coefficient and is usually 1.

  FIG. 9 is a diagram showing the relationship between the distributed constant line and the RC delay. A case where the wiring model is compared with a lumped constant, a π-type model, a π2-type model, and a π-type ladder model is shown. As shown in FIG. 9, the time constants for the π-type model, π2-type model, and π-type ladder model are all Rw · Cw / 2, and this value matches the RC delay.

From the above, the delay Tpd for each gate is expressed by the following equation.
Tpd = tpd0 + Ron · Cw + k · Rw · Cw / 2
Similarly, the rise / fall time Trf is expressed by the following equation.
Trf (20-80%) = trf0 + 6 · Ron · Cw / 5 + k · Rw · Cw / 2
However, when Trf of the input signal is large, the above equation is deviated. This case can be solved by having a delay table for each Trf of the input signal or having a Trf correction term for the input signal.

FIG. 10 is a diagram illustrating an RC model of wiring. In FIG. 10, Rm represents the wiring resistance to the node of interest. In the case of the wiring as shown in FIG. 10, the capacitance difference ΔC equivalent to the delay fluctuation amount due to the crosstalk noise is expressed by the following equation.
ΔC = C · K
K = A {1-exp (−B · | trfv / trfa |)}
ΔC = C · {A (1-exp (−B · | trfv / trfa |))}
Therefore, the delay fluctuation amount Δtpd due to crosstalk noise is expressed by the following equation.
Δtpd = (Ron + k · Rm) · ΔC = (Ron + k · Rm) · C · {A (1-exp (−B · | trfv / trfa |))}
However, K is a capacity conversion coefficient, A and B are capacity conversion constants (one value for each technology, and this value is corrected from actual measurement), and Rm is a resistance value to the node of interest.

Therefore, the delay can be directly calculated by adding the above-mentioned delay fluctuation amount Δtpd to the original delay value. When there are multiple nodes in parallel, the calculation is performed as follows according to the wiring model shown in FIG.
ΔCn = K · Cn
However, this is applied only when the timing windows overlap. In FIG. 29, it is assumed that the timing windows overlap only at node m, node n-1, and node n.

  Here, Cn is a coupling capacitance of the node n (n = 1, 2, 3,...).

  In this case, the total delay variation ΔTPD is expressed by the following equation.

  Next, a method for obtaining the capacitance conversion constants A and B from the actual measurement result of the evaluation circuit will be described. If the delay fluctuation amount of each node of the wiring is Δtpdn, the total delay fluctuation amount ΔTPD of the wiring of interest can be expressed by the following equation.

In the above equation, k has been tuned by the wiring ring oscillator or circuit simulator, and the part of Σ (Ron + k · Rm) · Cn is a constant term determined from the netlist.
K = A {1-exp (−B · | trfvn / trfan |)}
Thus, the total delay variation ΔTPD is expressed by the following equation.
ΔTPD (n) = A · α (n) · {1-exp (−B · | trfv / trfa |)}
However, n is a net condition.

  Therefore, the equation of the total delay variation ΔTPD (n) is a simultaneous equation of only the variables A and B, and can be obtained from the measured data of the evaluation circuit.

  Next, an evaluation circuit for obtaining the capacitance conversion constants A and B by actual measurement will be described. FIG. 11 shows an example of a delay variation measuring circuit for measuring delay variation due to crosstalk noise. The delay variation measuring circuit according to the present embodiment includes the ring oscillator RO, parallel wiring for applying crosstalk noise to a part of the ring oscillator RO, a poisoning gate AG, a crosstalk application unit CTN including a damage gate VG, and a crosstalk noise as a damage gate VG. A timing control unit TC for inputting with a certain deviation from the transition timing of the signal, and a pulse generation circuit PGEN for generating a noise pulse AGS based on timing information received from the timing control unit and determining a damage / damage transition mode Is done.

  The distance between the wiring between the pulse generation circuit PGEN and the damage gate and the wiring of the ring oscillator RO is sufficiently separated from the wiring of the ring oscillator RO so that the crosstalk noise is applied only at the crosstalk application unit CTN. It is arranged at a position far from the position, that is, the distance between the parallel wiring and the ring oscillator wiring in the crosstalk application unit CTN.

  The ring oscillator RO has a configuration in which inverters INV are connected in odd-numbered stages in series. In FIG. 11, a two-stage inverter is shown as one buffer BUF. Further, a configuration in which a part of the output of the buffer BUF constituting the ring oscillator is input to the timing control unit TC as the timing information signal TIM, and the timing control unit TC selects one of the plurality of timing information signals TIM. It is said. With this configuration, it is possible to easily acquire timing information for applying crosstalk noise with a certain timing shift with respect to the state transition of the damage gate VG, and the circuit can be shared and the area can be shared. Can be reduced. Further, since the timing information signal TIM needs to be acquired either at the falling edge of the waveform or at the rising edge of the waveform, the timing information signal TIM is input to the timing control unit TC at every even stage of the inverter (every output of the buffer BUF). .

  FIG. 12 is a block diagram illustrating a configuration of the timing control unit TC. The timing control unit TC is configured to decode a control signal ENC input from the outside of the delay variation measuring circuit by a decoder DEC and select one of a plurality of timing information signals TIM by a selector SEL based on the decoding result. Yes. In the present embodiment, 32 timing information signals TIM are input, but it goes without saying that the number is not limited. Note that if the number of timing information signals TIM is increased, the timing range of pulses for applying crosstalk noise can be widened.

  FIG. 13 is a block diagram showing another configuration of the timing control unit TC. The timing control unit TC shown in FIG. 13 includes selectors SEL1 to SEL4 that select one from eight selectors SEL and a selector SEL5 that selects one from four. Normally, circuit design is performed using a logic synthesis tool or an automatic wiring tool using standard cells, but a selector for selecting one from 32 as shown in FIG. 12 is normally registered. There is no need to create a new one. However, by dividing the selector as shown in FIG. 13, a conventional selector registered as a standard cell can be used, and circuit design is facilitated.

  FIG. 14 is a block diagram showing a configuration of the pulse generation circuit PGEN. The pulse generation circuit PGEN is a damage-side mode setting circuit VEOR for determining whether to cause the influence-side pulse to be affected at the rise of the damage-side pulse or to be affected by the damage-side pulse at the fall. Harming pulse generation circuit APG that generates the pulse on the side, and the harming side mode that determines whether the pulse on the damage side is affected by raising the pulse on the harming side, or whether the pulse on the damage side is affected by falling It is composed of a setting circuit AEOR. Further, the harm pulse generation circuit APG is composed of one inverter, a delay circuit, and a NAND circuit, and the one-shot pulse (High period is shorter than the Low period) from the pulse output from the damage side mode setting circuit VEOR. Pulse). The aggressor-side mode setting circuit AEOR switches the mode of whether the one-shot pulse having a short High period is output with the High period being shortened or the Low period being shortened. It is done according to. By configuring in this way, (damage side: falling, offending side: falling), (damaging side: rising, offending side: falling), (damaging side: falling, offending side: rising), (damage Side: rising, harming side: rising) is possible, and it is possible to measure in all modes of damage harm considered in the actual operation of the circuit.

  FIG. 15 is an operation waveform diagram of this embodiment. 15A is a damage side pulse in the crosstalk application unit CTN, FIG. 15B is a damage side pulse of the crosstalk application unit CTN, and FIG. 15C is a waveform diagram of the output OUT of the ring oscillator. The broken line is a case where crosstalk noise is not taken into consideration, and the solid line is a waveform diagram when affected by the crosstalk noise. The victim side pulse is delayed by being affected by the victim side pulse in the crosstalk application unit CTN. In addition, since the ring oscillator is used in the present embodiment, the pulse having a delay caused by the crosstalk noise is fed back, reaches the crosstalk application unit CTN again, and is further influenced by the aggressor side pulse. There will be a delay. Therefore, the period of the output OUT of the ring oscillator is longer than that when the crosstalk noise is not taken into consideration.

  The amount of delay variation due to crosstalk noise is determined by assuming that the oscillation frequency of the ring oscillator RO when no crosstalk noise is applied is f0 and that the oscillation frequency of the ring oscillator RO when crosstalk noise is applied is f. The period is 1 / f0, 1 / f. Therefore, (1 / f0-1 / f) is the amount of delay variation due to crosstalk noise. That is, it is possible to measure accurately by measuring the output of the ring oscillator RO with an oscilloscope or the like.

  Here, in order to accurately measure the influence of the crosstalk noise, it is necessary to match the transition timing of the victim side pulse with the transition timing of the victim side pulse. In this embodiment, the timing information of the ring oscillator is used to generate the victim side pulse, that is, the transition timing of the victim side pulse and the victim side pulse after the delay fluctuation is used. The timing can be adjusted easily. Further, the harming side pulse is made a one-shot pulse by the pulse generation circuit PGEN shown in FIG. 14, and has a waveform that rises before the damage side pulse falls. By doing so, it is possible to prevent delay fluctuations from occurring only at the rising portion of the victim side pulse and to prevent delay fluctuations from occurring at the falling portion.

  In FIG. 15, since the transition direction of the victim side pulse and the transition direction of the victim side pulse are opposite, the delay value increases and the frequency decreases, but the transition direction of the victim side pulse and the transition of the victim side pulse If the directions are the same, the delay will decrease and the frequency will increase.

  FIG. 16 is a modification of the delay variation measuring circuit shown in FIG. As described above, in order to accurately measure the amount of delay variation due to crosstalk noise, it is necessary for the crosstalk application unit CTN to match the transition timing of the victim side pulse and the transition timing of the aggressor side pulse. However, since the harming side pulse is output from the crosstalk application unit CTN via the timing control unit TC and the pulse generation circuit PGEN, a delay occurs with respect to the damage side pulse propagating through the ring oscillator RO as it is. Depending on the size of the delay, if the timing information of the ring oscillator RO is used as it is, it may be difficult to match the timing of the victim side pulse and the victim side pulse in the crosstalk application unit CTN.

  In this embodiment, a timing adjustment circuit DADJ is provided to solve the above-described problem. That is, by providing timing information to the timing control unit TC via the timing adjustment circuit DADJ, the crosstalk application unit CTN can delay the transition timing of the harming side pulse with respect to the transition timing of the victim side pulse, It is possible to match the transition timing of the victim side pulse and the victim side pulse in the crosstalk application unit CTN.

  FIG. 17 shows another embodiment of the crosstalk application unit CTN. Compared with the crosstalk application unit CTN of FIGS. 11 and 16, four types of crosstalk application circuits AC0, AC1, AC2, and AC3 are provided. That is, on the basis of the crosstalk application circuit AC0, in the crosstalk application circuit AC1, the wiring for transmitting the harming side pulse is thicker than the wiring for transmitting the damage side pulse, and the crosstalk applying circuit AC2 The driving force of the buffer that outputs is larger than the driving force of the buffer that outputs the victim side pulse. Further, the crosstalk application circuit AC3 has a configuration in which the distance between the wiring for transmitting the harming side pulse and the wiring for transmitting the damage side pulse is one channel away. In this way, by providing several types of crosstalk application circuits in the crosstalk application unit CTN and selecting one of them according to the crosstalk application condition selection signals ASEL0 to ASEL3, one delay variation measuring circuit can be used. It is possible to measure the amount of delay variation due to crosstalk under various conditions that can occur in an actual circuit.

  In the crosstalk application unit of this embodiment, a variable delay circuit VDLY is provided in a path for transmitting the aggression side pulse to the crosstalk application circuits AC2 and AC3. In this variable delay circuit, when all combinations of a plurality of conditions, for example, the crosstalk application circuits AC0 to AC3 are selected by the crosstalk application condition selection signal, a damage side pulse is generated in the crosstalk application circuits AC0 and AC1. Minute delay is generated to adjust the timing of the victim side pulse and the victim side pulse. By having a variable delay circuit in this way, it is possible to measure by combining a plurality of circuit conditions.

(Embodiment 2)
FIG. 18 is a block diagram showing a flow of a semiconductor device design method according to the second embodiment of the present invention.

  First, an example of a method for designing a semiconductor device according to the second embodiment will be described with reference to FIG. The method for designing a semiconductor device according to the present embodiment is a method for determining the risk of malfunction due to crosstalk noise from a calculation formula in the design of a semiconductor device such as an LSI and feeding back to the circuit design. Will be implemented.

  (1) Placement and wiring are performed based on the circuit diagram 30 and the cell library 31 (step S200), and layout data 32 is created.

  (2) Factors such as a resistance component (R) and a capacitance component (C) are extracted from the layout data 32 (step S201), and a wiring RC netlist 33 is created. The wiring RC netlist 33 is created in a form such as SPEF.

  (3) Based on the wiring RC netlist 33 and the delay library 34, STA (Static Timing Analysis) is executed to perform delay calculation (step S202). As a result of the STA, a summary 35 including a timing window of each signal, a rise time / fall time trf, delay information, and the like is output.

  (4) A noise check is performed based on the node information of the wiring RC netlist (SPEF) 33 and the information obtained in the STA of (3) (step S202) (step S203). As a result of the noise check, a summary 37 is output as a result of determination of malfunction due to crosstalk noise, and wiring that has a risk of malfunction is pointed out. Details of the calculation formula used at this time and the coefficients (m, p, q) used for the calculation will be described later.

  Coefficients (m, p, q) used for calculation of determination of malfunction due to crosstalk noise are obtained from circuit simulation results and measured values of the evaluation circuit. The circuit simulation is performed based on the circuit diagram 30 and the device parameter 36 (step S204). The evaluation circuit is manufactured and measured as an IC based on the layout data 32 (step S205). Further, the evaluation circuit is measured, and the coefficient (m, p, q) is adjusted according to the result. A specific method for adjusting the coefficients (m, p, q) will also be described later.

  (5) The circuit diagram is corrected based on the information (summary 37) obtained in (4) (step S206).

Next, specific contents of the noise check (step S203) will be described. The noise that reaches the next gate on the victim side is estimated in the following four steps, and malfunction determination is performed.
(Step 1) Calculation of amount of noise generated at parallel position (Step 1.1) Considering capacitance shielding effect by wiring resistance (Wiring)
(Step 1.2) Consider capacitance shielding effect due to wiring resistance (next stage input capacitance)
(Step 1.3) Consideration of charge extraction effect by victim side source gate (Step 2) Consideration of noise propagation effect (attenuation) of crosstalk noise to sink gate (Step 3) Total noise calculation by consideration of damage timing (Step 4) Noise Comparison of total amount and determination reference voltage Each step will be specifically described below.

(Step 1) Calculation of Generated Noise at Parallel Position Vnoise = Vdd · Cp / Ctotal is used for calculating the generated noise. However, here, the three effects (step 1.1), (step 1.2), and (step 1.3) raised before are considered.

(Step 1.1) Capacitance shielding effect due to wiring resistance (wiring capacitance)
Capacitance shielding effect due to wiring resistance is explained with reference to FIG. 30. When a state transition occurs in the wiring (assuming charging), in the case of low resistance, at the same time in the vicinity of the transition point and the point far from the transition point. The same level of charge has been charged, but when the resistance is high, the wiring resistance is hindered at a point far from the transition point, and only a small amount is charged compared to the vicinity. This phenomenon takes into account the reduction of the total capacity of the victim wiring. The function indicating the capacity shielding effect can be variously changed as shown in FIG. 31. As an example, a case where (3) of FIG. 31 is used will be described below. In order to clarify the method of consideration, the resistance and capacity per unit length are assumed to be constant.

  FIG. 19 is a diagram showing the parallel positions of the victim side wiring and the victim side wiring when obtaining the amount of crosstalk noise generated in the semiconductor device design method of the second embodiment. In FIG. 19, VIC is the damage side wiring, AGG is the damage side wiring, Lp is the parallel wiring length, Ls is the non-parallel wiring length near the source gate (the previous gate of the wiring) of the damage side wiring, and Le is the sink of the damage side wiring. The non-parallel wiring length near the gate (the rear gate of the wiring), leff_s is the effective wiring length of the non-parallel portion near the source gate of the damage side wiring, and leff_e is the effective wiring length of the non-parallel portion near the sink gate of the damage side wiring is there. In the following expression, Cw is the damage side wiring capacity of the non-parallel portion per unit length, Cp is the wiring-to-wiring capacity per unit length, and Cg is the capacity against the board per unit length of the damage side of the parallel portion. , Cin is the sink gate input capacitance on the victim side, Ron is the on resistance of the source gate on the victim side, and Rw is the wiring resistance per unit length of the victim side wiring VIC. Here, the effective wiring length refers to a capacitance due to wiring resistance.

  First, the effective wiring lengths leff_s and leff_e of the non-parallel portion are obtained by the following equation.

  Here, trf is the rise / fall time (20% to 80%) on the harming side at the parallel start point, and m is an effective charge range coefficient due to trf. The above expression is an expression that takes into account the noise application effect by the harming side trf and the capacitance shielding effect by the wiring resistance.

  Next, Ctotal is obtained by the following equation.

  Where Leff_s = inf (2 · leff_s, Ls), Leff_e = inf (2 · leff_e, Le), Cp is the inter-wiring capacity per unit length, and Cg is the damage side substrate capacity per unit length of the parallel part. is there. Let Ctotal = Ctotal (1) be the basic type. The above equation is an equation considering the effective wiring length. Note that the return value of the inf function is the smallest value among the arguments.

  When the functions in FIG. 31 are (1), (2), and (3), the same case classification is necessary. When the function of FIG. 31 is (4), Leff_s = Ls and leff_e = Le.

(Step 1.2) Capacitance shielding effect due to wiring resistance (next-stage input capacitance)
As shown in FIG. 32, the shielding effect coefficient considered in (Step 1.1) is applied to the subsequent stage input capacitance.

  Next, the following conditional branch is performed on the basic type Ctotal (1).

When Le ≦ 2 · leff_e,
Ctotal (2) = Ctotal (1) + (1−Le / (2 · leff_e)) · Cin
When Le> 2 · leff_e,
Ctotal (2) = Ctotal (1)
When the functions in FIG. 31 are (1), (2), and (3), the case classification is necessary as described above. When the function of FIG. 31 is (4),
Ctotal (2) = Ctotal (1) + Cin · (1−tanh ² (Le / leff_e))
(Step 1.3) Consideration of Charge Extraction Effect by Damaged Source Gate This will be described with reference to FIG. If it is assumed that Vnoise noise is generated at the noise generation location, a potential difference is generated between the power source and the noise generation location. Therefore, the current i = Vnoise / () is obtained via the MOS (ON resistance Ron) and the resistance Rn to the noise generation location. Ron + Rn) flows (from Ohm's law). On the other hand, when Q = CV is differentiated with respect to time, i = C · dV / dt is established and deformed, and can be written as i · Δt = C · ΔV (i · Δt is the total amount of extracted charges). When Δt is a value q · trf proportional to the harming side trf,
Ctotal · Vnoise = Cp · Vdd−iΔt = Cp · Vdd−Vnoise / (Ron + Rn) · q · trf
Solving for Vnoise, the following equation is obtained.
Vnoise = Vdd · Cp / (Ctotal + q · trf / (Ron + Rn))
If the range where the charge extraction effect appears is defined as the case where the drive gate appears within the effective wiring length described above,
When Ls ≦ leff_s,
Ctotal (3) = q · trf / (p · Ron + Rn · Ls) + Ctotal (2)
When Ls> leff_s,
Ctotal (3) = Ctotal (2)
According to the conditional branch above,
Let Ctotal = Ctotal (1), Ctotal (2), and Ctotal (3).

  The noise generation amount is calculated as described above.

  Although described as a function of length for the sake of simplicity, since the netlist is extracted by RC, the conversion procedure to the function of RC will be described.

R · C is the dimension of time, Rw is the resistance per unit length, Cw is the capacity per unit length,
t = R · C, C = Cw · x, R = Rw · x
Therefore,
t = Rw · Cw · x ²
Differentiate and
d (R · C) = dt = 2 · Rw · Cw · dx
Therefore, for FIG. 31, f (x) / c: shielding function (c = Cw)
F (x) total capacity value is

  However, for the integration range,

  For function arguments:

And

(Step 2) Considering the effect of noise propagation (attenuation) of the crosstalk noise to the sink gate After obtaining the crosstalk noise generation amount Vnoise, the crosstalk noise generation amount Vnoise is attenuated by the wiring length of the victim wiring, and the sink gate The amount of noise Vsink that reaches (the next gate of the wiring) is obtained. Specifically, the noise attenuation amount is obtained from the parallel position Le and the damage side wiring type by the following equation, and the noise amount V sink reaching the sink gate is obtained.
Vsink = Vnoise · exp {−Rw · Le · (Cw · Le + b · Cin) / (a · trf)
Of these, a and b are tuning constants and may be 1 in many cases.

  Rw is the resistance per unit length, Le is the wiring length to the sink, and Cw is the capacitance per unit length.

  That is, Rw · Le is the total resistance until the sink after the parallel end, and Cw · Le + Cin is the total capacity until the sink after the parallel end. Thus, the length function is converted to the RC function.

(Step 3) Calculation of Total Noise by Considering Damage Timing After obtaining the noise amount Vsink, the total amount of noise Vsink reaching the sink gate from all the wirings parallel to the victim wiring is obtained while considering the damage timing. The damage timing consideration method will be described with reference to FIGS. In the malfunction due to the crosstalk, the operation of the harmful wiring is caused by a mechanism that generates a noise pulse in the damaged wiring. Therefore, it is necessary to follow a process of changing the timing window from the perpetrator side to the victim side. However, due to the nature of the delay calculation program, it is impossible to input trf in the middle of the net. Therefore, FIG. 34, (1) the state transition timing window between the target nets for the path on the victim side, and (2) the standard waveform (trf that the designer thinks is the largest in the IC being created) at the source gate on the victim side. Using the state transition timing window in the case of reaching the terminal FF and the state transition timing window in the case of reaching the terminal FF assuming that the standard waveform was input to the victim sink gate (3) As shown in the timing chart of FIG. 34, a noise state transition timing window at the terminal FF is acquired. Among these, those having a state transition timing window that overlaps with the data fetch timing window of the terminal FF (shown as NG section in the figure) become noise having potential to cause malfunction. As shown in FIG. 35, the noise having the possibility of causing such a malfunction is summed when the timing windows of the state transitions overlap, and the noise having the largest noise amount among the combinations is cross-talked to the net. Let it be the amount of noise (Vnoise_target net). As a result of dividing the amount of crosstalk noise of the target net by the allowable noise voltage Vmax of the input pin of the sink gate (kv = Vnoise_target net / Vmax), when the malfunction risk coefficient is greater than a certain value, for example, NG, To do.

  When it is determined as NG, rewiring is performed on the damage side wiring or the wiring parallel thereto. For example, a logic inversion voltage is used as the allowable noise voltage Vmax.

  Further, although the sum is taken for the noise with overlapping timing windows, the mean square is sufficient when the operating frequency of the IC is slow.

  When a circuit simulation is executed in order to perform a malfunction determination with high accuracy, it is virtually impossible to verify the entire chip in order to trace the actual operation of the circuit. According to the design method, since the amount of crosstalk noise is calculated within the framework of the STA tool and the malfunction is determined, a comprehensive check can be performed in a short time. Compared to the case where a malfunctioning net is detected only by checking the capacitance between wirings and the parallel wiring length check, the method according to the second embodiment for judging malfunctioning from the actual noise amount and timing window is more accurate in indicating the malfunctioning net. Is expensive. For this reason, there are three improvements: a reduction in malfunction nets that could not be pointed out in the conventional design, a reduction in excess indication nets, and a reduction in verification time. And since the malfunctioning net has influenced the yield at the time of selection, it can contribute to the yield improvement. Also, the design area can be shortened because there is no increase in chip area and power consumption caused by relocation and cell optimization that are originally unnecessary for countermeasures against excessive indications.

  In the above embodiment, the case where the STA tool and the noise check tool are separate programs has been described. However, the function of the noise check tool may be directly incorporated in the STA tool.

  A method for directly incorporating the noise check function into the STA tool will be described with reference to FIG. FIG. 20 is a block diagram showing a modification of the semiconductor device design method of the second embodiment. In FIG. 20, the procedures (3) and (4) of the above embodiment are performed together, that is, the delay calculation by the STA (step S202) and the noise check (step S203) are performed simultaneously, and the result is output as the summary 38. is doing.

  Next, a method for optimizing (tuning) the coefficients (m, p, q, Vmax, a, b) of the above-described calculation formula by actually measuring malfunctions due to crosstalk noise between the wirings using an evaluation circuit will be described.

  FIG. 21 is a block diagram illustrating a schematic configuration of an evaluation circuit for determining a malfunctioning condition due to crosstalk noise between wirings in the second embodiment. The evaluation circuit according to the second embodiment includes, for example, a damage side wiring VIC that is affected by crosstalk noise, a harming side wiring AGG0, AGG1, AGG2, and AGG3 that gives the influence of crosstalk noise to the damage side wiring VIC. A buffer BF1 in front of the VIC1, buffers BF2, BF3, BF4, BF5 in front of the victim side wiring, buffers BF6 in the rear side of the victim side wiring, buffers BF7, BF8, BF9, BF10 in the rear stage of the victim side wiring, flip-flop FF1, etc. The output of BF1 is connected to the victim side wiring VIC, the input of the buffer BF6 is connected to the victim side wiring VIC, the output of the buffer BF6 is input to the data input of the flip-flop FF1, and the outputs of the buffers BF2, BF3, BF4, BF5 Is the harm side wiring AGG0, AGG1, AGG2, A Is connected to the G3, the input of the buffer BF7, BF8, BF9, BF10 are connected to aggressor side wiring AGG0, AGG1, AGG2, AGG3.

  The evaluation circuit is manufactured and measured by changing the following four types of design and measurement conditions.

  (1) A combination of polarities of signals propagated through the harming side wirings AGG0, AGG1, AGG2, and AGG3 and the damage side wiring VIC. For example, each signal of the harming side wirings AGG0, AGG1, AGG2, and AGG3 rises or falls, and the signal of the damage side wiring VIC is High or Low.

  (2) Driving power of the harm side wirings AGG0, AGG1, AGG2, and AGG3 and the pre-stage buffers BF1, BF2, BF3, BF4, and BF5 of the damage side wiring VIC.

  (3) Parallel positions of the harming side wirings AGG0, AGG1, AGG2, AGG3 and the damage side wiring VIC. For example, parallel in the vicinity of the front stage or in the vicinity of the rear stage, the damage side wiring and the damage side wiring are adjacent or one channel (one wiring) is skipped, and the width of the parallel wiring is thin or thick. In FIG. 21, the harming side wirings AGG0 and AGG1 are parallel in the vicinity of the preceding stage, the harming side wirings AGG2 and AGG3 are parallel in the vicinity of the subsequent stage, the harming side wirings AGG0, AGG1 and AGG2 are adjacent to the damage side wiring VIC, and the harming side wiring AGG3 is one. The channel is skipped, and the wiring width of the harming side wiring AGG0 is thick.

  (4) Data fetch timing by the flip-flop FF1 (malfunction timing window).

  An evaluation circuit is manufactured and measured by changing the above four kinds of design / measurement conditions, and the coefficients (m, p, q, Vmax, a, b) of the calculation formula are optimized based on the results.

  Further, a circuit configuration example of the evaluation circuit shown in FIG. 21 will be described with reference to FIG.

  FIG. 22 is a block diagram showing a configuration of an evaluation circuit for determining a malfunction condition due to crosstalk noise between wirings. The evaluation circuit in the second embodiment includes, for example, the damage side wiring VIC, the harm side wirings AGG0, AGG1, AGG2, AGG3, buffers BF11, BF12, BF13, BF14, BF15, BF16, AND (AND) gates AN1, AN2, and so on. AN3, AN4, fall edge (falling) trigger type flip-flop FF1, variable delay (delay) circuit DL1 with variable delay time, XOR (exclusive OR) gate XO1, etc., signal VM is input to buffer BF11 The output of the buffer BF11 is connected to the victim wiring VIC, the terminal of the victim wiring VIC is input to the buffer BF12, the output of the buffer BF12 is input to the data input of the flip-flop FF1, and the flip-flop FF1 receives the signal RES as data. Output, AN Signals AS0, AS1, AS2, and AS3 are input to one input of the gates AN1, AN2, AN3, and AN4, respectively, and a signal ED is input to the other input of the AND gates AN1, AN2, AN3, and AN4. The signal ED is input to the circuit DL1, the output of the variable delay circuit DL1 is input to one input of the XOR gate XO1, the signal FE is input to the other input of the XOR gate XO1, and the output of the XOR gate XO1 is The signal is input to the clock input of the flip-flop FF1.

  The variable delay circuit DL1 adjusts the data fetch timing of the flip-flop FF1. The XOR gate XO1 converts the polarity of the signal ED into a fall because the flip-flop FF1 captures data at the fall timing of the clock input. The AND gates AN1, AN2, AN3, and AN4 select one of the harming side wirings AGG0, AGG1, AGG2, and AGG3 by signals AS0, AS1, AS2, and AS3 that select the harming side mode. The harming side wirings AGG0, AGG1, AGG2, and AGG3 are designed and manufactured under various conditions as described with reference to FIG. As a measurement method, for example, the signal VM is set to a high or low state, and any of the harming side wirings AGG0, AGG1, AGG2, and AGG3 is selected by the signals AS0, AS1, AS2, and AS3, and the signal ED is changed from high to low. Alternatively, state transition is performed from Low to High. Then, the variable delay circuit DL1 changes the data fetch timing by the flip-flop FF1, and measures the change (malfunction) of the signal RES. In this way, it is possible to measure the malfunction of the damage side wiring due to the crosstalk noise from the harm side wiring.

  Next, an example of optimization (tuning) of the coefficients (m, p, q, Vmax, a, b) of the calculation formula will be described with reference to FIG. In FIG. 23, the thickness of the line corresponds to the thickness of the wiring. In the evaluation circuit, when there is a difference in the timing window that can be acquired, feedback is performed to the coefficient in the calculation formula as follows.

  (Step 1) m (effective charge range coefficient by trf) is optimized by the net 03 and the net 04 which are not influenced by the victim side sink gate and source gate.

  (Step 2) When the difference is large between the net 01 and the net 02 (side closer to the victim source gate).

  (Step 2.1) When the difference is larger in the net 11 than in the net 01 (influence of the driving force on the damage side), p (charge extraction coefficient) is optimized.

  (Step 2.2) If the difference between the net 02 and the net 02 is larger than that of the net 01 (influence of the aggression side driving force), q (time coefficient related to charge extraction) and k (effective charge range coefficient by trf) are optimized. To do.

  (Step 3) When the difference is larger in the A pattern than in the C pattern (damage side wiring width), q (time coefficient related to charge extraction) and a and b (wiring propagation coefficient) are optimized.

  (Step 4) If it does not match, change Vmax (allowable voltage) and malfunction risk factor.

  Specifically, the effective charge range coefficient m by trf, the charge extraction coefficient p, the time coefficient q involved in charge extraction, and the allowable noise voltage Vmax are tuned according to the conditions shown in FIGS. FIG. 24 is a diagram illustrating a method for optimizing the coefficient and the allowable noise voltage.

  Therefore, by measuring the evaluation circuit according to the second embodiment, it is possible to correct the design condition and the library from the deviation of the delay variation due to the crosstalk noise that occurs according to the actual device performance. As a result, erroneous wiring due to crosstalk can be pointed out with high accuracy. And since malfunctioning wiring is seen as the yield at the time of selection, it contributes to the yield improvement.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the delay variation measuring circuit or the malfunction evaluation circuit may be manufactured as a TEG circuit on a scribe line, or may be manufactured in the same chip as the system LSI.

  The present invention relates to a method for designing a semiconductor integrated circuit and a semiconductor device, and more particularly to a method for designing a semiconductor integrated circuit and a semiconductor device for measuring and calculating the influence of crosstalk noise.

It is a block diagram which shows the flow of the design method of the semiconductor device which is Embodiment 1 of this invention. (A)-(c) is a figure for demonstrating the concept of a timing window, (a) is a circuit diagram, (b) and (c) are timing charts. (A)-(e) is a figure which shows the relationship between a timing window and crosstalk noise, (a) shows a mode that a damage side wiring and an injured side wiring are parallel, (b)-(e) The timing chart of the victim side wiring and the victim side wiring is shown. It is a figure which shows the parasitic capacitance of each wiring when the harming side wiring is parallel on both sides of the damage side wiring. (A) is a diagram showing a state where the victim side wiring is parallel to both sides of the victim side wiring, and (b) is a parasitic capacitance of each wiring when the victim side wiring is parallel to both sides of the victim side wiring. It is a figure which shows parasitic resistance. It is a block diagram which shows the modification of the design method of the semiconductor device of Embodiment 1 of this invention. (A), (b) is a conceptual diagram which shows the delay of a CMOS inverter circuit in a capacity | capacitance mode, (a) is a circuit diagram which consists of a CMOS inverter and load capacity, (b) is the relationship between a delay and load capacity. FIG. (A), (b) is a conceptual diagram which shows the delay of a CMOS inverter circuit in RC delay mode, (a) is a circuit diagram which consists of a CMOS inverter, load capacity, and load resistance, (b) is a delay and load. It is a figure which shows the relationship with a capacity | capacitance. It is a figure which shows the relationship between a distributed constant track | line and RC delay. It is a figure which shows the RC model of wiring. In Embodiment 1 of this invention, it is a block diagram which shows the 1st Example of a delay variation | change_quantity measuring circuit. It is a block diagram which shows the timing control part in FIG. FIG. 12 is a block diagram illustrating another embodiment of the timing controller unit in FIG. 11. It is a block diagram which shows the structure of the pulse generation circuit in FIG. It is a figure which shows the waveform of each point of the delay variation measuring circuit of FIG. In Embodiment 1 of this invention, it is a figure which shows the 2nd Example of a delay variation measuring circuit. In Embodiment 1 of this invention, it is a figure which shows the other Example of a crosstalk application part. It is a block diagram which shows the design method of the semiconductor device of Embodiment 2 of this invention. It is a figure which shows the parallel position of the damage side wiring at the time of calculating | requiring the amount of crosstalk noise generation | occurrence | production in the design method of the semiconductor device of Embodiment 2 of this invention. It is a block diagram which shows the modification of the design method of the semiconductor device of Embodiment 2 of this invention. In Embodiment 2 of this invention, it is a block diagram which shows schematic structure of the evaluation circuit for determining the conditions of the malfunctioning by the crosstalk noise between wiring. In Embodiment 2 of this invention, it is a block diagram which shows the structure of the evaluation circuit for determining the conditions of the malfunctioning by the crosstalk noise between wiring. In Embodiment 2 of this invention, it is a figure which shows the crosstalk evaluation method. In Embodiment 2 of this invention, it is a figure which shows the optimization method of a coefficient and an allowable noise voltage. It is the figure which compared the conventional wiring and the wiring which refined | miniaturized. It is the figure which showed the mechanism in which the delay fluctuation | variation by crosstalk noise generate | occur | produces. It is the figure which showed the mechanism in which the malfunction by crosstalk noise generate | occur | produces. It is a figure which shows the rough calculation model of crosstalk noise. It is a figure which shows the wiring model in the case of being parallel in multiple nodes. It is a figure which shows the effect of effective wiring length. It is a figure which shows the capacity | capacitance cutoff effect by wiring resistance. It is a figure which shows the capacity | capacitance effect of a damage side sink gate. It is a figure which shows the capacity | capacitance extraction effect by a damage side source gate. It is a figure which shows a timing window. It is a figure which shows the method of adding crosstalk noise.

Explanation of symbols

15, 19, 23, 35, 37, 38 Summary 10, 30 Circuit diagram 11, 31 Cell library 12, 32 Layout data 13, 33 Wiring RC netlist 14, 34 Delay library 16, 36 Device parameter 17 Capacitance conversion constant (A , B)
18 wiring RC netlist 20, 21 gate group 22 wiring of interest s1 to s3, sk,..., Sn data holding circuit RO ring oscillator TC timing control unit PGEN pulse generation circuit CTN crosstalk application unit TIM timing information signal ENC control signal VMOD damage Pulse mode setting signal AMOD Harmful pulse mode setting signal AGS Harmful side pulse VG Damaged gate AG Harmful gate VIC Damaged side wiring AGG, AGG0, AGG1, AGG2, AGG3, AGGa, AGGb Harmful side wiring BUF, BF1-BF16 Buffer INV Inverter VEOR Damaged Pulse mode setting circuit AEOR Harmful pulse mode setting circuit APG Harmful pulse generation circuit DADJ Timing adjustment circuit AC0 to AC3 Crosstalk application circuit AN1 to A 4 AND (AND) gate DL1 variable delay circuit (variable delay circuit)
XO1 XOR (Exclusive OR) Gate FF1 Flip-flop

Claims (3)

A ring oscillator in which a plurality of inverters are connected in an odd number of stages,
A first wiring provided along a part of the wiring of the ring oscillator;
A pulse generation circuit for generating a first pulse to be supplied to the first wiring;
A first buffer connected between the first wiring and the pulse generation circuit;
A second wiring connected between the pulse generation circuit and the first buffer;
A distance between the first wiring and a part of the ring oscillator is shorter than a distance between the second wiring and a part of the ring oscillator. The semiconductor integrated circuit according to claim 1,
A third wiring provided along a part of the wiring of the ring oscillator;
A second buffer connected between the third wiring and the pulse generation circuit;
The semiconductor integrated circuit according to claim 1, wherein the third wiring is thicker than the first wiring. The semiconductor integrated circuit according to claim 1 or 2,
The first pulse transits between a first level and a second level, and a first mode in which a period held at the second level is longer than a period held at the first level, and the first level And a second mode in which the period held at the second level is shorter than the period held at
The semiconductor integrated circuit, wherein the pulse generation circuit includes a mode setting circuit for switching between the first mode and the second mode.

Images