JP4692599B2 - Variable time division multiplex transmission system - Google Patents

Description

  The present invention relates generally to communication, and more particularly to a method and apparatus for communication in a system such as a circuit or apparatus having a daisy chain.

  2. Description of the Related Art Conventionally, in a circuit, apparatus, system, or the like, it is necessary to identify these devices in order to perform communication between devices such as various integrated circuit chips, units, and devices included therein. There are various methods for identifying such devices in the system. As a first method, there is a method of using a device-specific identifier as a device identifier or an address for communication in the system. The device-specific identifier is, for example, a number burned into the ROM at the time of manufacture in an integrated circuit chip. Standards that use such device-specific identifiers include the JTAG standard used in on-chip chip mounting tests and IIC (eg, Audio I / F (IIC)) used in many audio products. As a second method, there is a method of assigning addresses from the outside to devices such as branches and leaves. An example of using this method is the IEEE1394 standard. Further, as a third method, there is a method in which the device identifier, that is, the address is predetermined in a method. An example of this is the SCSI-2 standard. In this standard, a specific address is recommended in advance by the operating system for devices such as printers and displays.

  In the case of the first method using the device-specific identifier, particularly in the case of an integrated circuit chip, this unique identifier is unique to each device depending on the type of device manufacturer, device function, etc. A device identifier is assigned and written to the ROM in the device. Therefore, different device identifiers are given to devices manufactured by different manufacturers even if they are of the same device type. For this reason, it is not easy to simply replace a device used in a system such as an audio product with a device of the same device type but a different manufacturer. In order to perform such replacement, it is also necessary to replace the device identifier in the system of the device before replacement with the device identifier of the device after replacement. This includes software rewriting, ROM content rewriting, and the like. As another problem, when a plurality of devices of the same type are to be used in the system, devices to which the same device identifier is assigned cannot be used. It is also necessary to burn the device identifiers into the ROM so that one of them can be selected when the device is used. Furthermore, in a system that requires another device identifier instead of a unique device identifier, a new device identifier or address must be assigned to the device. Furthermore, since the device unique identifier includes a part for identifying the manufacturer, the device unique identifier is a very redundant number.

On the other hand, in the second method, since it is necessary to assign an address to the device from the outside, hardware and software for assigning the address are required.
In the third method, since an address used by a specific device is recommended in advance in an operating system or the like, there is a limitation on address allocation. There is also a limit to the number of devices that can be connected to the system.

  Therefore, an object of the present invention is to automatically assign an identifier for identifying a device number or an intra-system number in a number of devices in the system to a device in the system in communication in a system such as a circuit or apparatus. It is an object of the present invention to provide a communication method and apparatus that can be provided automatically.

  Another object of the present invention is to automatically assign an identifier for identifying the order in a predetermined order such as the allocation order of shareable resources to the devices in the system in the communication in the system as described above. It is an object to provide a communication method and apparatus that can be provided.

  Furthermore, another object of the present invention is to provide a variable time division multiplex communication method and apparatus using the above identifier in the above system.

  To achieve the above object, a communication system for performing communication between a plurality of devices in a system including a plurality of devices according to the present invention includes a bus connecting the plurality of devices to each other, and a daisy chain between the plurality of devices. And a daisy chain connection line connected by a chain.

  According to the present invention, the plurality of devices comprises a master device and a plurality of slave devices of at least one group, and in the communication system, between the master device and each of the plurality of slave devices. The bus connects the master device and each of the plurality of slave devices of the group, and the daisy chain connection line connects the plurality of slaves of the group. -Devices can be connected in a daisy chain.

  According to the present invention, the daisy chain connection line is connected to each device in the plurality of slave devices of the device in the plurality of slave devices or in a predetermined order in the system. It can be used to assign a device identifier for identifying the order.

Further, according to the present invention, the at least one group may be composed of a plurality of slave devices of a plurality of groups.
The daisy chain connection line can be used to assign a device identifier to the plurality of slave devices of the group. In this case, one daisy chain connection line may be provided for each of the plurality of groups of slave devices. At this time, the one group of slave devices connected to each of the plurality of daisy chain connection lines may have an identifier of the daisy chain connection line to which they are connected.

  The present invention further includes an apparatus for assigning a device identifier to the plurality of slave devices of one group, the device identifier assigning apparatus including a plurality of slave devices of the one group. Device identifier giving token generating means for sending a device identifier giving token toward the downstream of the daisy chain at a first time point provided in the most upstream device located in the uppermost stream of the daisy chain. The upstream device has a first device identifier, the device identifier grant token generating means, the storage device for storing the first device identifier provided in the most upstream device, and located downstream of the daisy chain Time measuring means provided in each downstream device, wherein the device identifier grant token is The time measuring means for measuring the time difference between the first time point and the second time point when received at the time point, and the device identifier determining means provided in each downstream device, based on the measured time difference Each of the downstream devices, and the storage means for storing the determined device identifier provided in each of the downstream devices. The plurality of devices may be identified by each device identifier different from the first device identifier of the upstream device and the first device identifier determined for each of the downstream devices.

  Also, according to the present invention, the bus can transmit information including both data and control signals between the master device and the plurality of slave devices.

  According to the present invention, the communication can be performed by time division multiplexing. In this case, the communication can be performed in at least two different transmission bands. At this time, the communication can be performed using continuous time slots. The different transmission bands can be realized by changing the number of time slots used in a predetermined time frame. The number of used time slots for each slave device may be variable. The number of use time slots can be set in advance. The number of use time slots may be 0 or an integer greater than or equal to 1. Further, according to the present invention, the daisy chain connection line includes a time slot allocation token for allocating a time slot to each of the plurality of slave devices of the one group, and the plurality of slaves of the one group. Can be used to communicate between devices. In this case, each of the plurality of slave devices of the group transmits the time slot allocation token among the plurality of slave devices of the group, and When using the time slot, the slave device starts using the time slot when receiving the time slot allocation token, uses the time slot by the number of used time slots, and uses the number of used time slots. When the use of the time slot is finished, the use of the time slot is terminated, and the time slot following the time slot used last among the time slots of the number of use time slots is changed to the one group. Of the plurality of slave devices connected to the daisy chain. To assign to a chair, it is possible to pass the time slot allocation token to the next slave device.

  According to the present invention, the bus can be a serial bus. In this case, communication via the serial bus is performed during a communication time frame, and the communication time frame can be made equal to one period of the first reference clock. In this case, communication via the serial bus can be performed in a common communication format for both data and control signals. The common communication format may include at least one command field at the time of initialization and at least one command field and at least one data channel field at the time of operation. The command field may include a device identifier. When the system includes multiple daisy chain connections, the command field may include a daisy chain number.

  Further, according to the present invention, a method for assigning device identifiers to a plurality of devices includes a step of connecting the plurality of devices in a daisy chain, and a most upstream device located at the most upstream of the daisy chain among the plurality of devices. To send a device identifier grant token at a first time point downstream of the daisy chain, wherein the most upstream device has a first device identifier, and the daisy chain Each downstream device receiving the device identifier grant token at a second time point, and each downstream device based on a time difference between the first time point and the second time point, Each downstream device determining its own device identifier, said device identifier being said first Each of the device identifiers different from the first device identifier determined for each of the downstream device and the first device identifier of the most upstream device, comprising: To identify the plurality of devices.

  According to the present invention, the first time point is determined by a first reference clock, and the time difference is generated by counting the number of second reference clocks from the first time point, thereby generating a count value. it can. Further, the device identifier can be determined based on the count value. Further, each of the devices may have storage means for storing the device identifier.

  According to the present invention, the plurality of devices can be the same type of device, and the same type of device can be either an input device or an output device.

  In addition, in a system including a master device and a plurality of slave devices according to the present invention, a method for the master device to identify the plurality of slave devices includes: The master device assigning device identifiers to the plurality of slave devices, and determining the device identifiers of the plurality of slave devices by executing the device identification assigning method described above. B. The master device identifying the plurality of slave devices by the device identifier given to the plurality of slave devices by the device identifier assigning method.

  According to the present invention, the master device can store the device identifier given to the plurality of slave devices by the device identifier assigning method in a storage unit provided in advance in the master device. Alternatively, the master device receives the device identifier given to the plurality of slave devices by the device identifier assigning method from the slave device, and stores the device identifier in storage means in the master device. it can.

  Further, according to the present invention, the plurality of slave devices can be composed of a plurality of groups of slave devices. In this case, the plurality of slave devices of the plurality of groups are respectively connected by the plurality of daisy chains, thereby assigning the device identifiers to the slave devices of each group, and the plurality of the plurality of groups connected to the plurality of daisy chains, respectively. A device group identifier is assigned to each group of slave devices, whereby each slave device of the plurality of groups of slave devices is combined with the device group identifier and the device identifier. Can be identified.

  According to the present invention, there is provided a data transmission method for transmitting data between a master device and a plurality of slave devices, wherein the master device uses the device identifier obtained by the device identification method described above. It is characterized by transmitting data between a plurality of slave devices.

  According to the present invention, an apparatus for assigning device identification to a plurality of devices includes a daisy chain connection line that connects the plurality of devices in a daisy chain, and an uppermost stream of the daisy chain among the plurality of devices. Device identifier grant token generating means for sending a device identifier grant token at a first time point provided downstream of the daisy chain provided in the most upstream device located, wherein the most upstream device receives the first device identifier. The device identifier giving token generating means; the storage means for storing the first device identifier provided in the most upstream device; and the time measuring means provided in each downstream device located downstream of the daisy chain. When the device identifier grant token is received at a second time point The time measuring means for measuring the time difference between the time point and the second time point, and the device identifier determining means provided in each downstream device, and based on the measured time difference, its own device of each downstream device The determination means for determining an identifier, and storage means for storing the determined device identifier provided in each downstream device, whereby the first device identifier of the most upstream device and the storage device The plurality of devices are identified by each device identifier different from the first device identifier determined for each of the downstream devices.

Furthermore, the present invention is a device, an input terminal for connecting to the upstream side of the daisy chain, an output terminal for connecting to the downstream side of the daisy chain,
There is provided a device comprising device identification providing means for assigning a device identifier to the device based on the position of the device in the daisy chain.

  According to the present invention, the device identification assigning means is a time measuring means, and the device identification grant token sent from the most upstream of the daisy chain at the first time point is received at the second time point. Said time measuring means for measuring a time difference between the first time point and the second time point; and a device identifier determining means for determining its own device identifier based on the measured time difference; Storage means for storing the determined device identifier.

  Further, in a system including a master device and a plurality of slave devices according to the present invention, a device identification system in which the master device identifies the plurality of slave devices includes the device identification granting device described above, Storage means provided in the master device for storing the device identifiers of the plurality of slave devices assigned by a device identification granting device, whereby the master device comprises the plurality of slave devices. A slave device is identified by the device identifier of the slave device stored in the master device.

  According to the present invention, the plurality of slave devices may comprise a plurality of groups of slave devices. In this case, the plurality of slave devices of the plurality of groups are respectively connected by the plurality of daisy chains, thereby assigning the device identifiers to the slave devices of each group, and the plurality of the plurality of groups connected to the plurality of daisy chains, respectively. A device group identifier is assigned to each group of slave devices, whereby each slave device of the plurality of groups of slave devices is combined with the device group identifier and the device identifier. Can be identified.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
Referring first to FIG. 1, there is shown a communication system A, which is an embodiment of a basic configuration incorporating the present invention. As shown in the figure, the system A includes one master device 1, a plurality of slave device groups 3-1 to 3-N (SDG1 to N), and each of these slave device groups. The bus 5 is connected to the device 1. Each slave device group comprises at least one, for example, a plurality of slave devices 30-1-1-1 to 30-1-N, or 30-2-1 to 30-2-N, as shown, for example. Yes. Each of these slave devices is connected to the bus 5. The communication system A further includes at least one daisy chain, for example, DC1 to DCN. Each daisy chain corresponds to each slave device group, and one daisy chain is associated with slave devices in one group. For example, in the slave device group 3-1, the daisy chain DC1 connects a plurality of slave devices in a daisy chain form by a daisy chain connection line 7-1. Daisy chain connection lines 7-2 to 7-N are provided in the other slave device groups.

  In the communication system A shown in FIG. 1, control signals and data such as commands between the master device 1 and each slave device 30 in each slave device group SDG 1 to N are sent via the bus 5. Is transmitted. This bus is a serial bus, but can also be constituted by a parallel bus. The identifier of the device used in this transmission is automatically given by each daisy chain DC1 to DCN provided in each slave device group 3-1 to 3-N. That is, the device identifier (device ID) of each of the slave devices 30-1-1-1 to 30-1-N in the slave device group SDG1 is daisy chained by the daisy chain DC1 or a resource allocation token (described later). Is provided by transmitting between the slave devices. When device IDs given to the slave devices 30-1-1-1 to 30-1-N by the daisy chain DC1 are known in advance at the time of system design, those device IDs are stored in advance in the memory of the master device 1. Can be. Note that when not known at the time of system design, the device IDs assigned to the slave devices may be held by the master device through communication between the master device and the slave device. In the configuration shown in FIG. 1, since there are a plurality of slave device groups, an identifier of the slave device group or an identifier of the daisy chain is required to distinguish the slave device among the device groups. . Such a slave device group identifier is stored in a ROM or RAM of a slave device provided in each slave device group, or is set at an external setting terminal (H is “1”, L is “2”). Can be set.

  The device ID given to each slave device as described above (may also include a slave device group identifier) is used as the number of the slave device in the communication system A, that is, the in-system number as described above. Or can be used as an order in a predetermined order, such as the order of allocation of sharable resources within the system.

  As for the operation of the communication system A, the present system can be operated by using variable time division multiplexing (VTDMCA), for example, as will be described later. For example, in variable time division multiplexing, communication is performed using a fixed communication format by providing a plurality of continuous time slots for each fixed communication time frame and assigning these time slots to each of a plurality of channels. The system can be operated to

  Next, with reference to FIG. 2, an audio multichip system B, which is one embodiment of the communication system A of the present invention shown in FIG. 1, will be described. This system B includes a digital signal processor (DSP) 1B as a master device, and N slave devices 30-1-1B, 30-1 in an input (IN) device group as slave devices. -2B... 30-1-NB (only two are shown) to the output (OUT) device group N slave devices 30-2-1B, 30-2-2B ... 30-2-NB (two Only shown). System B therefore comprises two slave device groups. Here, the IN device (device that receives input from the DSP) includes a digital-analog converter (DAC) and other devices, and the OUT device (device that supplies output to the DSP) includes analog-digital conversion. A device (ADC) or other device is included. As will be described later, an IN / OUT device such as a codec (CODEC) and a NO device without input / output as signal processing such as a PLL can also be included in the system. The system B includes a conductor 50B and a conductor 52B as a bus for mutually connecting the DSP 1B, the IN devices 30-1-1B to NB, and the OUT devices 30-2-1B to NB. That is, one connection line is provided for transmission from the master device to a plurality of slave devices, and one connection line is provided for transmission from the plurality of slave devices to the master device. Further, a conductor 60 for supplying a frame synchronization clock and a conductor 62 for supplying a port synchronization clock are provided. System B also daisy-chains DC1B for devices 30-1-1B through NB in the IN device group and devices 30-2-1B through NB in the OUT device group as daisy chains for the two slave device groups. Daisy chain DC2B. As will be described later, “1” is assigned to the IN device 30-1-1B and “2” is assigned to the IN device 30-1-2B as the device ID (device ID). Similarly, as the device ID, “1” is assigned to the OUT device 30-2-1B, and “2” is assigned to the OUT device 30-2-2B. In order to identify these two device groups, a slave device group identifier is further given by a method such as pre-baking in a ROM of a device belonging to each group. For example, “1” is assigned to the IN device group, “2” is assigned to the OUT device group, and the like.

  Specifically, the DSP 1B can use a commonly available digital signal processor, which uses a frame synchronization clock that defines a communication frame for transmission (FSX) and a communication frame for reception (FSR). A port for supplying, a port for supplying a transmission port synchronization clock (CLKX) and a reception port synchronization clock (CLKR), and a data transmission port for transmitting commands and data constituting the serial port of the DSP DX and a data reception port DR for receiving them. On the other hand, each of the IN device and the OUT device includes an LRCK port that receives a frame synchronization clock via a conductor 60, a BCK port that receives a port synchronization clock via a conductor 62, and data and commands from the DSP 1B via a conductor 50B. And an output port PDO for outputting a state and data to the DSP 1B through a conductor 52B. Further, these devices are provided with a daisy chain input port DCI and an output port DCO for assigning a device ID to each device. These ports are connected to either the daisy chain connection line 7-1B or 7-2B constituting the daisy chain. Note that the analog output terminal in the case of a DAC is not shown for an IN device, and the analog input terminal in the case of an ADC is not shown in the case of an OUT device, and transmits a digital signal. Only the lines to be shown are shown.

  Next, with reference to FIG. 3, a circuit for assigning a device ID (or device number) using a daisy chain will be described in detail. FIG. 3 shows only two devices of IN devices 30-1-1B and 30-1-2B in the system B of FIG. 2, but the same applies to other IN devices and OUT devices. . The IN device 30-1-1B is a circuit constituting a part of the daisy chain DC1B, and a device ID assignment circuit 70-1B for assigning a device ID to the device and a bus that is a resource that can be shared with the device A time slot allocation circuit 72-1B for allocating the usage order (in this example, a time slot in a specific order among a large number of continuous time slots in a communication frame) is provided. The inputs of these circuits are connected to a connection line 7-1BU1 on the upstream side of the daisy chain via a DCI port, and their outputs are connected to a connection line 7-1BD1 on the downstream side via a DCO port. The upstream connection line 7-1BU1 is connected to the reference voltage, and the downstream connection line 7-1BD1 is connected to the upstream connection line 7-1BU2 of the one downstream IN device 30-1-2B. Has been. Similarly, the IN device 30-1-2B includes the same ID assigning circuit 70-2B and the slot assignment circuit 72-2B, and the downstream connection line 7-1BD2 is further upstream of the next lower IN device. Connected to the connection line. Details of these circuits will be described later.

  Next, the overall operation of the audio multichip system B of FIG. 2 will be described with reference to FIG. FIG. 4 shows a format of variable time division multiplex communication (VTDMCA) used in this system. Specifically, LRCK, which is a frame synchronization clock, has a period 1 / fs that is the reciprocal of frequency fs that is the same as the sampling frequency of the audio signal. This is because the duty ratio is considerably smaller than 50% compared with the interface (Audio Serial Interface) used in the conventional audio product having a duty ratio of 50%. For example, “H” for two cycles of the clock BCK. "It is in the section. This is because the VTDMCA communication interface according to the present invention and the conventional communication interface can be distinguished from each other by the difference in duty ratio, thereby ensuring compatibility with the conventional method. Depending on the frequency of the port synchronization clock BCK, a large number of continuous time slots are defined during one period of the frame synchronization clock, thereby making it possible to cope with multiple channels. Thereby, time division multiplex communication is realized. FIG. 4 shows the input format of data and commands input to and output from the input port PDI of the IN device and OUT device and the output port PDO during initialization and operation during a communication frame having a large number of time slots. Shows the output format of data and commands output from. At initialization, the format of the input PDI is followed by a command field (CMD) followed by a number of extended command fields (EMD), as shown. Each field has 32 bits and has a length that can be accommodated within the period of the one time slot. The format of the output PDO from the IN device or the like has a continuous 8-bit status field (STF), and each status field includes status data stored in a register. Next, in operation, the format of the input PDI is a 32-bit command field (CMD) at the beginning, followed by an audio channel field (for each of a number of n channels ch1 to chn ( Ch1 to Ch (n)). The format of the output PDO includes an 8-bit status field (STF) at the head, followed by audio channel fields (Ch1 to Ch (m)) for each of the m channels. Since the number of input channels and output channels can be different, the number m and the number n of channels can be the same or different. That is, in operation, the IN device uses only the PDI format because it receives only input data, and the OUT device uses only the PDO format because it only sends out output data. As can be seen from the above, in the VTDMCA communication of the present invention, the serial bus is used in time division multiplexing.

  Next, the command field, extended command field, and audio channel field will be described with reference to FIG. Specifically, FIG. 5A shows the structure of the command field. The head DID field of this command is a field indicating whether or not the device ID determination sequence is executed. When this bit is “1”, the determination sequence is executed, and when it is “0”, the subsequent command is executed. To do. The EMD field is a field indicating whether or not the extended command field shown in FIG. 4 is subsequent. When this bit is “1”, it indicates that the next field is the extended command field, and “0”. Indicates that the next field is an audio channel field. The daisy chain select field (DCS) is a field indicating a slave device group. In the example shown in FIG. 2, 0 is assigned to the IN device and 1 is assigned to the OUT device. The “device ID” field is a device number given in the device ID determination sequence, and is used to identify the device. When the “device ID” field is “0x00”, no device is selected, and when it is “0x1F”, all devices are selected. This setting can be made at the same time (for example, DAC enable, mute on / off, etc.). The “register ID” field is a number assigned to each unique internal register of the IN device or the OUT device, and this number is used to identify the register. This field includes an R / W flag, and specifies writing or reading to the internal register. The “data” field includes data for a specified internal register of a specified device selected by the device ID and the register ID.

  Next, the extended command field shown in FIG. 5B will be described. This field has the same structure as the command field in FIG. 5A except that the MSB bit is not used (rvd). is doing. Note that only the extended command field can be selected after this field.

  FIG. 5C shows a status field (STF), which uses only 8 bits of bits 8 to 15 of 32 bits (illustrated as 8 bits in FIG. 4). This status field is used to read the status of the slave device stored in a register in the slave device and send it to the DSP 1B in response to a request in the command field or the extended command field.

  Finally, although not shown, the audio channel field is used for transmission of audio data. Each audio channel field is treated as audio data of the device selected in the command field preceding these fields. The audio format can be arbitrarily selected for each device.

  As can be seen from the format described above, the IN device and OUT device, which are the slave devices shown in FIGS. 2 and 3, are not shown, but are registers for selecting the audio channel occupied by each device. Is provided. For confirmation, it is preferable to provide a register for storing the device ID of each device. Further, as described above, the internal register of each device can be read from the internal register as well as setting control data in the internal register of each device. In the system of FIG. 2, a PDO port is used as a read port. However, the PDO port of all devices can be wired or connected by setting the PDO to a Hiz (high impedance, that is, open) output. Since the read / write timing of the register can be arbitrarily designed by those skilled in the art, the details thereof will be omitted.

  Next, the overall operation of the audio multichip system B shown in FIG. 2 will be described with reference to the flowchart of FIG. This flowchart shows control from the host controller (DSP in this example). First, in step 60, it is determined whether to use the VTDMCA communication mode. This determination is usually determined at the system design stage. If it is determined that the mode is not the VTDMCA mode, the conventional normal operation mode is used in step 61. In this conventional mode, Audio Serial Interface and Host Serial Interface are used. On the other hand, if it is determined that the VTDMCA mode is to be used, in step 62, the host controller performs initialization for using the VTDMCA mode. That is, the serial port of the DSP 1B is initialized, and the “H” section width of the frame synchronization clock LRCK, the number of BCK clocks, the data length, the frame length, and the like are set. Thereafter, in step 63, a VTDMCA mode determination sequence is generated. Also, by generating the initialization PDI input shown in FIG. 4 (the DID field of FIG. 5A is “1”), the device ID determination sequence is started, whereby the IN device and OUT device are started. A device ID is automatically assigned. Next, in step 64, if necessary, the device IDs of all IN devices and OUT devices are confirmed. This is performed by the DSP 1B reading the device ID stored in the internal register of each device. That is, using the PDI input, the DSP 1B sends a command for reading the internal register storing the device ID to each slave device, and in response to this, each slave device sends the read device ID to the DSP 1B. On the other hand, it is realized by sending using PDO output. The DSP 1B collates the received device ID of each slave device with the device ID of the slave device stored in advance in the DSP's own memory. Still further, in step 64, all slave devices are initialized by using the extended command field of the PDI data (shown in FIG. 5 (b)). In step 65 after the initialization is completed, the DSP 1B sends a PDI input to the IN device or receives a PDO output from the OUT device. For example, in operation, for a PDI input to an IN device, the DSP 1B sends a write or read command field to the first IN device (optionally selectable), followed by an audio signal. Send the channel field. The assignment of the audio channel field is determined in advance by initialization performed for all devices. If the command field at this time is read, the contents of the register specified by the command field are output from the PDO port to the status field. The command field for the OUT device is the same, only the audio channel field is changed to transmission of audio data.

Next, details of the operation of the system B described above will be described with reference to FIGS.
FIG. 7 shows the timings of the clocks LRCK and BCK for determining the VTDMCA mode generated by the DSP 1B in step 62 of FIG. As shown in the figure, the H (“1”) section of LRCK is set for two BCK clocks. Furthermore, in order to prevent malfunction, the IN device and the OUT device side determine the VTDMCA mode by detecting twice (in FIG. 7, the first time is shown as a pre VTDMCA frame and the second time is a VTDMCA frame). To work. The reason why the H (“1”) section of LRCK is set to two clocks of BCK is to distinguish the LRCK 50% duty of the Audio Serial Interface in the conventional operation mode as described above.

  Next, the timing of the device ID assignment sequence will be described with reference to FIG. This sequence is executed in step 63 of FIG. This device ID determination sequence is performed independently in each of the IN device group and the OUT device group, and a device ID grant token (DID token) is transmitted downstream from the most upstream of the daisy chain. In the following description, only the IN device will be described, but the same operation is performed for the OUT device group. Specifically, the DID token is formed by a reference voltage connected to the uppermost stream of the daisy chain. First, the PDI data input to the PDI port of FIG. 8 includes a command field in which the aforementioned DID field is set to “1” in order to start a device ID assignment sequence. The IN device that has received this command receives a high DID token at the DCI1 port at the most upstream IN device in the daisy chain, and therefore determines that device ID = 1 when the clock LRCK is high. Then, this DID token is transmitted to the downstream IN device. The downstream IN device determines its own device ID based on the number of BCK clocks counted until receiving this DID token (determined to be 1 in 2 clocks). As shown in FIG. 8, the next lowest IN device after the most upstream IN device (also called the head device) counts the BCK clock until DCI2 connected to DCO1 goes high, and count 4 is the device. ID = 2. The next lower IN device sets the count 6 to device ID = 3. That is, the device ID is determined using the second digit or more of the internal counter. As described above, by transmitting the DID token from the most upstream to the downstream in the daisy chain, the IN device can determine the device ID for execution. In summary, the DID field in the command field allows all slave devices to recognize the device ID determination sequence and send the DID tokens in sync with BCK in order from the first slave device to the DCI port. In the cycle in which “high” appears, each slave device recognizes by itself what number it is connected to, and outputs a DID token to the next device. By fixing the DCI port of the first device to “1”, device ID = 1 is recognized and becomes the starting point.

  By using this device ID determination method of the present invention, even if there are a plurality of devices of the same type in the same system, a master device such as a DSP can identify each. This method has an advantage that the number of devices that can be identified is not limited to the number of terminals of the master device that can be used, as compared to a method that simply identifies the device using the external terminals of the master device. In other words, by using the daisy chain of the present invention, such a conventional limitation is eliminated, and the number of slave devices can be increased without increasing the number of setting terminals of the master device.

  Next, with reference to FIG. 9, one detail of the device ID assigning circuit 70 shown in FIG. 3 for executing this device ID assigning sequence will be described. Since the other device ID assigning circuits are the same circuit, the circuit 70-2B will be described in detail. As shown in the figure, the device ID assigning circuit 70-2B receives a clock LRCK, a clock BCK, a device identifier (DID) assigning token input from the DCI port, a device ID determination sequence start command, and a system reset signal. Is configured to generate a DID grant token output to the DCO port as an input and as an output. The start command is a signal “1” in the DID field in the command field described with reference to FIG. The system reset signal is a signal that becomes high when the system reset is released. As shown in the figure, this circuit having these inputs and outputs is roughly divided into a device ID determination sequence start control unit 700, a time measurement unit 701, a device ID storage unit 702, a token discrimination circuit 703, and a DID assignment. A downstream token generation circuit 704, a head device (most upstream device) discrimination circuit 705, and a head token generation circuit 706 are configured. Specifically, the sequence start controller 700 includes a D-type flip-flop (F / F5) 7000, which has a D input, a CK input, a reset (RST) input, and a Q output, and the CK terminal is Receives clock LRCK via inverter 7002. This F / F5 generates a high Q output in response to the clock LRCK when the system reset signal is high and the start command is high. This high Q output outputs a signal indicating the period (equal to one frame period) from the start to the end of the decision sequence.

  On the other hand, the time measuring unit 701 includes a counter 7010, which includes a CLOCK terminal that receives the clock BCK and a RESET terminal connected to the Q output of F / F5. This counter is reset by the falling edge of the Q output of F / F2 received at the RESET terminal, and starts measuring the time from the start of the determination sequence by counting the clock BCK received after the start of the device ID determination sequence. As a result of the time measurement, a count value is generated at the output. The device ID storage unit 702 includes a +1 adder 7020 and a register 7022. The +1 adder 7020 is connected so that the input receives the counter output except the LSB of the counter 7010, and generates an output obtained by adding 1 to the counter output. As a result, two clocks of the clock BCK are counted as one device identifier. Register 7022 has a LATCH terminal for receiving a token input, and an input connected to the output of +1 adder 7020 in addition to a CLOCK terminal for receiving clock BCK. The register 7022 latches the adder output as a result of time measurement from the start of the decision sequence to the reception of the token input in response to the clock BCK when receiving a high token input. Is stored as the device ID of the device. The DID assignment downstream token generation unit 704 included in the device ID assignment circuit 70-2B includes a D-type flip-flop (F / F1) 7040 and a D-type flip-flop (F / F2) 7042. These F / Fs include an RST input that receives a Q output of F / F5 (7000) and a CK terminal that receives a clock BCK. Their D inputs are connected so that F / F1 receives the token from token discriminating circuit 703 and F / F2 receives the Q output of F / F1. With this configuration, F / F1 and F / F2 are reset at the start of the decision sequence (reset at the falling edge) and then receive the token via the token discrimination circuit 703. The clock BCK is delayed by two clocks (two stages of F / F), and operates so as to be generated as a downstream DID grant token at the Q output of the F / F2. The above is a general operation of the device including the head device. In the case of the head device, since the DID grant token input is always high, the head token needs to be generated specially. For this reason, as described above, the device ID assigning circuit 70-2B further includes circuits 703, 705, and 706.

  Specifically, the token discriminating circuit 703 includes a selector 7030, which has an input for receiving a DID grant token (which is always a high signal in the head device) and an input for receiving a head token (described later). And a control input for receiving a head device signal indicating that the device is the head device (when it is high). This selector operates to pass the head token to the output when the head device signal is high, and to pass the DID grant token from the upstream to the output when it is low. The head device determination circuit 705 includes a flip-flop (F / F6) 7050 and an AND gate 7052. F / F6 has a reset input that receives a system reset signal, a CK terminal that receives clock LRCK via inverter 7002, and a D terminal connected to the output of AND gate 7052, and the AND gate is the start An input for receiving a command and an input for receiving a DID grant token input are provided. For the first device, DCI is always high, so AND gate (AN1) 7052 outputs a high output when the start command goes high. The F / F 6 receiving this output generates a high Q output in response to the fall of the clock LRCK, and goes low at the next fall of the clock LRCK (see FIG. 10). On the other hand, in the downstream devices other than the head device, since the start command and the DCI input do not become high at the same time, the Q output of F / F 6 always remains low. Thus, a high Q output of F / F6 indicates that the device is the leading device.

  Next, the head token generation circuit 706 is provided to generate a token dedicated to the head device because DCI is always high in the head device. Specifically, the circuit 706 includes F / F3 (7060) and F / F4 (7062), an inverter 7064, and an AND gate (AN2) 7066. F / F3 and F / F4 have a reset terminal that receives the Q output of F / F5 and a CK terminal that receives the clock BCK, and F / F3 receives the head device signal (Q output of F / F6). The F / F4 has a D terminal connected to the Q output of F / F3. With this connection, the F / F 3 and the F / F 4 operate so as to delay the leading edge of the head device signal by one clock (see FIG. 10), and thus by two clocks. The AND gate AN2, which receives the signal obtained by inverting the delayed signal by the inverter 7064 and the head device signal, outputs a high signal for the length of two clocks of the clock BCK from the start of the communication frame (falling of the clock LRCK). Occurs in the output. This output constitutes the first token for the first device (see FIG. 10). This head token is supplied to the token discrimination circuit 703 as described above. In the downstream devices other than the head device, the head device signal is always low, and therefore the output of the AND gate AN2 is always low.

  Next, the operation of the device ID assigning circuit 70 will be described with reference to FIGS. First, the head device will be described with reference to the timing chart of FIG. First, after the system reset signal goes high, the clock LRCK goes high to start the VTDMCA frame, and the start command received thereafter indicates the start of the device ID determination sequence. The Q output of this becomes high to indicate the device ID determination sequence. As a result, the counter 7010 starts counting the clock BCK as shown, and also starts counting up the device identifier by the addition of the adder 7020. On the other hand, the F / F 6 outputs a head device signal indicating that the device is the head device, and in response to this, the F / F 6 is set high for two clocks via the F / Fs 3 and 4 as shown in the figure. The first token is generated. This leading token is supplied to the register 7022 and the F / F 1 through the output of the selector 7030 because the leading device signal is high. As a result, the register 7022 latches and stores the adder output “1” at that time in response to the head token. This “1” indicates that the device identifier of the device is “1”. On the other hand, the F / F1 that receives the leading token operates together with the F / F2 to delay the leading token by two clocks to generate a downstream token, which is generated at the Q output of the F / F2. Through the above operation, the device identifier = 1 is given to the head device.

  Next, referring to FIG. 11, a description will be given of a device downstream of the head device. In the case of the downstream device, as described above, the Q outputs of F / F 6 and F / Fs 3, 4, and 5 are all low. Therefore, the head device signal (Q output of F / F6) and the head token (AN output) are low. On the other hand, when the downstream token from the head device is received as a DID grant token via DCI, the selector 7030 passes the DID grant token to the output because the head device signal is low, and the register 7022, F / F1. To supply. Thus, the register 7022 latches the adder output at that time and stores device identifier = 2. At the same time, F / F1 and F / F2 generate a DID grant token for a further downstream device by delaying this token by two clocks.

  Through the above operation, each device in the IN device group can determine its own device ID, that is, be given a device ID. When the Q output of F / F5 falls to “low”, this determination sequence ends. This decision sequence only needs to be done once at system initialization, so the start command is only generated once at initialization. In the operation after the initialization, the device ID once determined remains stored in the register.

  Next, the overall operation of the time slot allocation circuit 72 shown in FIG. 3 will be described with reference to FIG. This circuit is used in variable time division multiplexing (VTDMCA) communication to assign a time slot in a communication frame to each slave device, such as an IN device or an OUT device. As in the case of the device ID assigning circuit 70, since the IN device group and the OUT device group perform this time slot assignment in the same manner independently of each other, the IN device group shown in FIG. Explained. As shown, one communication frame is a period from the rising edge of the clock LRCK to the next rising edge, and the first time slot starts from the rising edge of the clock LRCK, and this is followed by a number of time slots. In the example shown in FIG. 12, the command field of PDI input exists in the first time slot, and one of audio channel fields ch1 to ch8 exists in each of the second and subsequent time slots. Note that the period after ch8 is an unused period in the illustrated example. In the example of FIG. 12, when each IN device uses two channels, the most upstream device (DID = 1) uses ch1 and ch2, and the next device (DID = 2) uses ch3 and ch4. And the next device (DID = 3) uses ch5 and ch6, and the last device (DID = 4) uses ch7 and ch8.

  After the start of the communication frame, the first (most upstream) device with the device ID (DID = 1) number 1 has two audio channels enabled and the DCI1 port is always high, so the DSP1B changes to the PDI port. Capture two channels from the first audio channel field after the command field in the received PDI input. At that time, during the time slot period of the audio channel field of ch2, the DCO1 port is set high to generate a time slot allocation token (hereinafter referred to as a time slot allocation (SA) token), and one downstream. To the second IN device (DID = 2). Since this second IN device also captures two channels and fields, it captures ch3 and ch4. Similarly, at that time, during the time slot period of the audio channel field of ch4, the DCO2 port is set high to generate an SA token and send it to the third IN device (DID = 3) one downstream. Thereafter, in the same manner, the last IN device (DID = 4) receives the SA token, and from the audio channel field immediately after that, captures the audio channel field by the number of its own used channels (two), Then, an SA token is generated in the time slot period (ch8) of its last audio channel field, and this SA token is passed to the IN device one downstream. Thereby, time division multiplex communication is realized. In this example, the last IN device (DID = 4) does not need to recognize that it is the last, and outputs the SA token downstream. Also, variable time division multiplexing is realized by setting the number of time slots used by each device to be different from each other. The timing for the IN device group is the same for the OUT device group as shown in the figure.

  Next, the details of the circuit of the time slot allocation circuit 72 shown in FIG. 3 will be described with reference to FIGS. As shown in FIGS. 13A and 13B, the time slot allocation circuit 72 is roughly divided into a time slot position instruction unit 720, a use time slot instruction unit 721 (FIG. 13B), and an allocation. The time slot discriminating unit 722 (FIG. 13B), the data holding unit 724, the data storage unit 725, the SA (slot allocation) token generating unit 726, and the source token generating unit 727 are included. The time slot position instruction unit 720 includes a counter 7200 and an AND gate 7202. The counter 7200 has an RST terminal that receives the clock LRCK, a CK terminal that receives the clock BCK, and a 5-bit counter output (Q1 to Q5), and is reset at the falling edge of the clock LRCK, and one time When the counting of the number of clocks BCK generated during the slot (for 32 clocks BCK) is completed, all the 5-bit counter outputs (Q1 to Q5) become high (counting starts from the second clock BCK). Therefore, the count becomes “31” and all become high). The AND gate 7202 having an input connected to each bit of the counter output generates a high output only when the counter outputs are all “1”. This high AND gate output becomes a signal (bc31) indicating the end of each time slot.

  The use time slot instruction unit 721 instructs the number of time slots used by the IN device, and is composed of an N-bit register 7210. N is the total number of channels provided in the device. The register 7210 has channel enable bits from ch1 to chN. When the corresponding bit is “1”, the channel is enabled, that is, the channel is set to the IN device. (Or time slot) is set to be used. Therefore, a channel enable bit of “1” constitutes a time slot use enable signal. Since there are N bits, up to N channels can be assigned to this IN device, thereby realizing variable time division multiplexing. Here, the ch1 enable signal means not the ch1 slot shown in FIG. 12, but the first one of the slots set to be used by the device. This register 7210 is included in the command register 7212 which is an internal register in the IN device. Each bit of the register 7210 can be set in advance in the IN device, and in this case, it is preferably stored in advance in the memory of the DSP 1B as the master device at the time of system design. However, if the time slot assignments to slave devices are not known at the time of system design or are variable, the master device will assign time slot assignments to those slave devices set after system design in the master device. Can also be written by communication (using the command field) to the register 7210 in the slave device command register 7212 via the shift register 7240 and the address decode circuit (FIG. 13 (b)). Can be done. Alternatively, the setting contents of this register set in the slave device can be received by the master device by communication, which means that the reading of the register 7210 of the slave device is as shown in FIG. This is realized by receiving through a field output circuit (parallel / serial conversion circuit). The allocation time slot discriminating unit 722 includes N AND gates 7220-1 to 7220 -N corresponding to the channels 1 to N, respectively, and each AND gate 7220 receives channel enable signals ch 1 to chN as one input. Receives a corresponding one of the enable signals and receives the SA (Time Slot Allocation) token input (SA1-SAN (or DCO)) of the channel that also corresponds to another one input, and the remaining third input The slots are connected to receive the slot start position instruction signal bc31. Each of the SA tokens SA1 to SAN is assigned to make a time slot corresponding to each audio channel field 1 to N available to the device. Accordingly, the output of each AND gate 7220 is enabled to use this time slot (or channel) for a particular time slot, receives an SA token, and receives a time slot position indication signal. A high output is generated only when This high output includes an allocation slot usage instruction signal indicating that the time slot at the time of this high is a slot allocated to the device (that is, allocation slot) and that the device uses (that is, a usage slot). Become. When the channel enable signal is low, the assigned slot use instruction signal is low because the time slot is not used by the device.

  As shown in the figure, the data holding unit 724 includes a shift register 7240. This shift register has a PDI input from the PDI port, that is, a DATA terminal that receives packet data, and a CK terminal that receives the clock BCK. An output terminal for generating data held in the shift register is provided. The shift register 7240 operates to hold the incoming PDI input for the length of one packet (or one time slot).

  The data storage unit 725 includes N audio channel registers 7250-1 to 7250 -N that are the same as the number of N channels, and each of these registers is an enable that receives an allocation slot use instruction signal from the corresponding AND gate 7222. It has an EN terminal and a CK terminal that receives the clock BCK, and also has an input (shown schematically in the figure) connected to the output of the shift register 7240. In response to the allocation slot use instruction signal from the AND gate 7222, each register 7250 receives and latches the packet in the allocation slot (or allocation channel) from the shift register 7240, and stores the packet. Thereby, the IN device can receive data from the assigned time slot. The data in the register 7250 is read for subsequent processing (digital-analog conversion in the case of DAC).

  Next, the source token generation unit 727 is a circuit part that generates a source token, which generates a head token or outputs an SA token from the upstream. That is, the source token generation unit 727 includes a multiplexer (MUX) 7270 and a head token generation circuit 7272. The MUX 7270 has one input connected to the daisy chain input DCI, the other input connected to the output of the head token generation circuit 7272, and a circuit similar to the head device determination circuit 705 in FIG. 9 (can be shared). Control input for receiving the first device signal. Therefore, when the head device signal is true or high, that is, when the device is the head device, the head token from the circuit 7272 is passed to the output, and when it is low, that is, the device is a device other than the head. In some cases, the SA token received at the DCI port from the upstream is passed to the output. The leading token generation circuit 7272 has a BCK terminal that receives the clock BCK and an LRCK terminal that receives the clock LRCK, and has an output for generating a leading token.

  Specifically, as shown in FIG. 14, the head token generating circuit 7272 is composed of a 6-bit counter 72720, an AND gate 72722, and an OR gate 72724. Counter 72720 has a CLK terminal coupled to the output of AND gate 72722, an RST terminal connected to receive clock LRCK, and has 6-bit counter outputs Q1-Q6. The AND gate 72722 has one input receiving the clock BCK and the other input connected to the most significant Q6 terminal, thus providing the clock BCK to the counter CLK terminal while Q6 is low, and Q6 After that, the supply of the clock to the counter CLK terminal is stopped until it is reset. Thus, an OR gate that receives counter outputs Q1-Q5 is when at least one of the bit outputs of the 5-bit counter portion is high, i.e., the counter output is between 1 and 31 (ie, there is a command field in the time slot The first time slot) produces a high at the output (see token in FIG. 16). This high OR gate output constitutes the leading token.

  Finally, the SA token generation unit 726 shown in FIG. 13A includes N cascaded token propagation circuits 7260-1 to 7260-N provided corresponding to the N channels, respectively. Each token propagation circuit 7260 has a BCK terminal for receiving a clock BCK, a BC31 terminal for receiving a time slot start position indication signal bc31, an enable EN terminal for receiving a channel enable signal of a channel corresponding to the propagation circuit, and an input IN. Terminal and an output OUT terminal. The propagation circuit includes an input IN terminal that receives a token from the source token generation unit 727 in the first stage, and an input IN terminal connected to the previous OUT terminal in the subsequent stages. The output OUT terminal of each propagation circuit generates a token received at the IN terminal that is delayed by approximately one hour slot (approximately 32 clock BCKs) when the channel enable signal is high, and the channel. • When the enable signal is low, it passes without delay. The OUT terminal of the last stage 7260-N supplies the SA token (SAN) to the next downstream device to the DCO port. This allows downstream devices to use time slots in order. The token generated at the OUT terminal of each propagation circuit becomes a token for the next stage or next downstream device, and is used as the time slot allocation tokens SA1 to SAN in the device. When the channel enable signals of ch1 and ch2 are high, it means that two channels, that is, two slots are used, and the time slots shown in FIG. 12 with ch1 and ch2 are necessarily used. Does not mean to do. Therefore, if the upstream device of the device uses ch1 and ch2 in FIG. 12, the ch1 and ch2 used by the device correspond to the slots with ch3 and ch4 in FIG. .

  Specifically, as shown in FIG. 15, each propagation circuit 7260 includes a multiplexer (MUX) 72600 and a D-type F / F 72602 with enable control. The MUX 72600 has one input connected to the IN terminal of the propagation circuit, the other input connected to the Q output of the F / F 72602, and the control input connected to the EN terminal. When it is low, the token received at the IN terminal is passed as it is, and when the EN terminal is high, the Q output of the F / F is passed through the MUX output, that is, the token of the IN terminal delayed by one hour slot. . The D terminal of the F / F 72602 is connected to the IN terminal, and the EN terminal is connected to receive bc31. The F / F has a CLK terminal connected to receive the clock BCK, and latches an input signal only when EN is high. Therefore, this F / F generates a high signal during the next slot if the signal bc31 is high and the signal input from the IN terminal is high. Note that the channel settings used by the device are stored in the register 7210 as described above.

Next, the overall operation of the time slot allocation circuit 72 will be described with reference to the timing charts of FIGS.
First, the operation of one device, for example, the head device will be described with reference to FIGS. Here, in FIGS. 17 to 20, it is assumed that the device has a processing unit for four channels. FIG. 16 shows a case where the head device uses channel ch1 but does not use ch2 and uses another channel (not shown). Specifically, under the clocks LRCK and BCK shown, the 5-bit counter 7200 counts as shown to generate a bc31 signal that goes high at the end of each slot, thereby causing the end of the slot. Indicates. Next, the leading token generation circuit 7272 generates a leading token in the first slot as shown in the figure. Since the leading device uses ch1, the ch1 enable is high, and therefore the token propagation circuit 7260-1 Generates a token SA1 delayed by one slot at its output. In response to this token, the head device latches and stores the contents of the shift register 7240 (data of channel ch1) in the register 7250-1. Next, the next token propagation circuit 7260-2 that receives the token SA1 passes SA1 as it is without delaying SA2 because the ch2 enable is low. At this time, the output of the AND gate 7220-2 remains low because the ch2 enable signal is low, and therefore no latch to the register 7250-2 occurs. Furthermore, the head device finally generates a downstream token at the DCO port after using another channel or the like. In this way, the head device can receive only the channel data of the time slot used by this device.

  Next, FIG. 17 shows a case where the head device uses four channels ch1 to ch4 (the channel enable signal of ch1 to ch4 is high). In this case, since the enable signals of ch1 to ch4 are high, as shown in the figure, SA1, SA2, SA3, and SA4 (= DCO) are delayed by one slot from the head token. At this time, since the outputs of the AND gates 7220-1 to 7220-4 are high, latching of the registers 7250-1 to 7250-4 occurs. The SA4 token is output to the DCO port as a token for the downstream device. Thus, it can be seen that one device can use a large number of time slots, and can implement variable time division multiplexing.

  FIG. 18 is a timing chart when the leading device uses two channels by the high enable signals of ch1 and ch3. In this case, since the ch2 enable signal is low, the SA2 token is the same as the SA1 token. At this time, since the ch3 enable signal is high in the AND gate 7220-3, the register 7250-3 latches the data of the ch2 audio channel field in the ch3 register 7250-3 instead of the ch2 register 7250-2. It will be. Therefore, when using two or more receiving channels in one device, the channels to be enabled do not necessarily have to be continuous. Under certain conditions, if ch2 and ch4 in the device are not used, or if ch1 and ch2 and ch3 and ch4 in the device use the same data, the master device It is possible to increase the efficiency of data transmission. As a result, an arbitrary channel can be limited and used, and unnecessary data transmission is not required. In this example, the number of use time slots = 2.

  Next, FIG. 19 is a timing chart when only the ch2 enable signal is high in the head device. In this case, since the ch1 enable signal is low, SA1 is equal to the first token, and SA2 is delayed by one slot from SA1, and the subsequent SA3 and the like have no delay from SA2. In this case, since only the output of the AND gate 7220-2 becomes high, the ch2 register 7250-2 receives the data of the ch1 audio channel field. This is an example in which only ch2 in four channels provided in the device is used.

  FIG. 20 shows a timing chart when all ch enable signals are low in the head device, that is, when no time slot is used. In this case, the first token is transmitted as it is without delay as SA1, SA2, SA3, etc., and is transmitted as it is to the downstream device. This use mode can be used for devices that do not use the device at all under certain conditions, or that need to be daisy chained but do not make any input or output and need to utilize time slots. In this case, the case where the number of use time slots = 0 is configured. As described above, use / unuse can be set for each channel in the device, and it is not necessary to perform useless data transmission, so that transmission efficiency can be improved.

  FIG. 21 is a timing diagram showing delivery of SA tokens between a plurality of devices. The illustrated example shows a case where a plurality of devices are cascade-connected as shown in FIG. In addition, it is assumed that the device 1 uses one channel, the device 2 uses two channels, the device 3 uses no channels, and the device 4 uses three channels. In this case, as shown in the timing diagram of FIG. 21B, the device 1 uses the ch1 audio channel field to generate a token delayed by one slot from the head token at the output DCO1. Next, since the device 2 uses two channels, a token delayed by another two slots is generated in the DCO 2. Since the device 3 does not use the slot, the output token of the device 2 is output to the DCO 3 without being delayed. Since the next device 4 uses three channels, a token obtained by further delaying the token from the device 3 by three slots is generated in the DCO 4. In this way, time slot allocation tokens can be propagated in sequence using a daisy chain between devices. In addition, since the number of time slots to be used can be arbitrarily set in each device, in this example, the device 2 has a transmission band twice that of the device 1 and the device 4 is 3 of the device 1. Double the transmission band. Note that the transmission band of the device 3 is zero. Thus, according to the present invention, variable time division multiplexing can be realized by using a daisy chain.

  Although the data transmission from the DSP 1B to the IN device has been described above, the data transmission from the OUT device to the DSP 1B can be realized in the same manner as described above. The difference is that data to be sent to the register 7250 is arranged, and at the start of the allocation slot, the data is moved to the shift register 7240 and outputted from the PDO port. The other time slot assignment (SA) token delivery and channel enable signal usage is the same. As can be seen from the above description, since the IN device group and the OUT device group have separate daisy chains, it is possible to assign a device identifier and transmit a time slot allocation token independently of each other. Therefore, it is possible to operate simultaneously.

  Although a preferred embodiment of the present invention has been described above, various modifications can be made to this embodiment. First, the number of daisy chains can be any number of two or more corresponding to a device group. In this case, each daisy chain group device must store the daisy chain connection line identifier or number as a device group identifier. Second, the master device can be a programmable device such as a microprocessor other than a DSP, and its serial port can be used for data transmission with a slave device. Thirdly, the device identifier of the slave device can be transmitted from the slave device to the master device in addition to being stored in the memory of the master device in advance. This can be achieved by reading the internal register of the slave device.

  Fourth, as shown in FIG. 22, the same device can be connected to two or more daisy chains. For example, the slave device is an IN / OUT device such as a codec, as shown. In this case, only one device ID assigning circuit 70 needs to be provided, but two sets of time slot assignment circuits 72 need to be provided. This is because the device ID is used for transmission / reception of the command field, so it can be distinguished from the master side, but one audio channel field can be used for reception (IN side) and transmission (OUT side). Because it is independent, it requires two daisy chains. Fifth, as described above, by making the number of slots allocated to each slave device variable, a variable transmission band different for each slave device can be realized.

  Sixth, the bus in the above embodiment is a serial bus, but a parallel bus can be used as well. Seventh, as the predetermined order, the above embodiment shows an example in which the bus time slot allocation order is “predetermined order”, but the present invention can also be applied to other resource allocation orders. . Eighth, the above system is an example of an audio system, but the present invention can be applied to other systems (for example, LAN, ATM, remote monitoring system, automatic measuring device, etc.). Ninth, devices such as DACs and ADCs are shown as the above slave devices, but other integrated circuit chips, or other types, scales of circuits, units, devices, equipment (for example, terminals, computers, A camera, a microphone, a temperature sensor, a humidity sensor, a pressure sensor, an actuator, etc.).

  According to the present invention described above, an identifier can be automatically assigned to a device such as an integrated circuit chip. In addition, since more free identifiers can be assigned to devices, different device identifiers can be assigned to the same type of chip, which makes it possible to use or support multiple types of chips in the same system. It becomes possible to do. This makes it unnecessary to assign a device identifier or address to the chip by pre-baking it in the ROM at the time of chip manufacture, or to assign a specific device identifier to a specific device type, as in the past. Further, it is not necessary to give a device identifier to the device from the outside. As a result, the design of a system such as a circuit is not constrained by a chip-specific device identifier, so that the same type of chip from different manufacturers can be used interchangeably.

  Furthermore, the device identifier of the present invention given in a system such as a circuit can be a simple number as compared with a redundant identifier such as a conventional chip-specific device identifier. It can be used to form an optimum address, or it can be used as it is as the order of allocation of resources that can be shared in the system.

  Further, if the order of the resources that can be shared is used as the order, the resources can be used efficiently. In addition, if a time slot using a bus is used as a sharable resource, variable time division multiplex communication is realized, and a device that does not use a shared resource of the bus by changing the allocation amount of the time slot. Even if devices used, devices used frequently, etc. (IN device (DAC), OUT device (ADC), IN / OUT device (CODEC)) coexist, these devices optimize the amount of communication (less redundancy) Degrees).

FIG. 1 is a block diagram showing a communication system having a basic configuration according to an embodiment of the present invention. FIG. 2 is a block diagram showing an audio multichip system B which is one embodiment of the communication system of FIG. FIG. 3 is a block diagram showing a device ID assignment circuit and a time slot allocation circuit provided in each slave device of FIG. FIG. 4 shows a communication frame in variable time division multiplex communication (VTDMCA) used in the system of FIG. 2 and a format at the time of initialization and operation of transmission data (PDI input and PDO output) transmitted in this frame. FIG. FIG. 5 is a diagram showing the structure of the command field and extended command field in the transmission format shown in FIG. 4, where (a) is a command field, (b) is an extended command field, and (c) is a state. Indicates a field. 6 is a flowchart showing the overall operation of the audio multichip system B shown in FIG. FIG. 7 is a diagram showing timings of clocks LRCK and BCK for determining the VTDMCA mode. FIG. 8 is a timing chart showing various signals in the device ID assigning sequence. FIG. 9 is a circuit diagram showing details of the device ID assigning circuit 70 shown in FIG. FIG. 10 is a timing chart for explaining the operation of the device ID assigning circuit 70 of FIG. 9 in the head device (the most upstream device). FIG. 11 is a timing chart for explaining the operation of the device ID assigning circuit 70 of FIG. 9 in the second downstream device other than the head device. FIG. 12 is a timing chart for explaining the overall operation of the time slot allocation circuit group shown in FIG. FIG. 13 is a circuit diagram showing details of the time slot allocation circuit 72 shown in FIG. 3 by combining (a) and (b). FIG. 14 is a circuit diagram showing details of the first token generation circuit of FIG. FIG. 15 is a circuit diagram showing details of the token propagation circuit of FIG. FIG. 16 is a timing chart showing various signals in the time slot allocation circuit in a situation including a case where the head device uses channel ch1 but does not use ch2. FIG. 17 is a timing chart of various signals in the time slot allocation circuit when the head device uses four channels ch1 to ch4. FIG. 18 is a timing diagram of signals in the time slot allocation circuit when the leading device uses two channels by the high enable signals of ch1 and ch3. FIG. 19 is a timing diagram of signals in the time slot allocation circuit when the ch1 enable signal is low and only the ch2 enable signal is high in the head device. FIG. 20 is a timing diagram of signals in the time slot allocation circuit when all ch enable signals are low in the head device. FIG. 21 is a timing diagram showing delivery of SA tokens between a plurality of devices. FIG. 22 is a block diagram illustrating a system example in which the same device is connected to two daisy chains.

Explanation of symbols

1 Master device 3-1 to N Slave device group 5 Bus 30-1-1 to N Slave device 30-2-1 to N Slave device
7-1N Daisy chain connection line 1B DSP
30-1-1B to NB Slave device 30-2-1B to NB Slave device DC1B Daisy chain 50B Bus conductor 52B Bus conductor 60 Conductor 62 Conductor 70 Device ID assignment circuit 700 Device ID determination sequence start control unit 701 Time measurement unit 702 Device ID storage unit 703 Token discrimination circuit 704 Downstream token generation circuit 705 Start device determination circuit 706 Start token generation circuit 720 Time slot position instruction unit 721 Use time slot instruction unit 722 Allocation time slot determination unit 724 Data holding unit 725 Data storage Unit 726 time slot allocation (SA) token generation unit 727 source token generation unit 7260 token propagation circuit 7272 first token generation circuit

Claims (6)

A variable time division multiplex transmission system between a plurality of slave devices and a master device in a plurality of slave device groups each including a plurality of slave devices,
The master device includes a synchronous clock signal terminal connected to a first clock line to which a synchronous clock signal is supplied; a frame synchronous signal terminal connected to a second clock line to which a frame synchronous signal is supplied; A data output terminal connected to a first data line to which commands and data are supplied, and a data input terminal connected to a second data line to which commands and data are supplied,
Each slave device is connected to a synchronous clock signal input terminal connected to the first clock line, a frame synchronous signal input terminal connected to the second clock line, and the first data line. A data input terminal, a data output terminal connected to the second data line, a daisy chain input terminal, a daisy chain output terminal, and a device holding a device identifier indicating its own position in the slave device group Each having a device identifier providing circuit including an identifier holding circuit,
A predetermined logic signal is applied to the daisy chain input terminal of the first slave device of the plurality of slave devices in each slave device group, and the daisy chain output terminal of the first slave device is Connected to the daisy chain input terminal of the slave device of the stage, and the plurality of slave devices are cascaded by the daisy chain output terminal and the daisy chain input terminal,
When the master device supplies a device identifier setting command to the first data line in synchronization with the frame synchronization signal, the first-stage slave device receives the frame synchronization signal, the device identifier setting command, and the daisy chain input terminal. In response to the logic signal, a predetermined device identifier is set in the device identifier holding circuit, and a device identifier setting token is output from the daisy chain output terminal. The slave device in the next stage receives the frame synchronization signal and the device. In response to an identifier setting command and the device identifier setting token, a predetermined device identifier is set in the device identifier holding circuit, and a device identifier setting token is output from the daisy chain output terminal, and the device of each slave device Predetermined device identifier is set to the Besshi holding circuit,
The plurality of slave devices are identified by individual slave device group identifiers assigned to the plurality of slave device groups, respectively, and the device identifiers ;
A sequence start control circuit for outputting a sequence signal indicating a device identifier determination sequence in response to the device identifier setting command and the frame synchronization signal; and the synchronization clock signal in response to the sequence signal. And a token generator for generating a device identifier setting token for the next slave device in response to the predetermined logic signal or device identifier setting token input to the daisy chain input terminal and the synchronous clock signal And further comprising a circuit,
A predetermined device identifier is determined according to the count value of the counter and a predetermined logic signal or device identifier setting token input to the daisy chain input terminal.
Variable time division multiplex transmission system. A signal supplied to the first data line and the second data line has a plurality of time slots in one frame defined by the frame synchronization signal, and the master device and the slave device are Send and receive data using a predetermined time slot,
The variable time division multiplex transmission system according to claim 1 . The one frame is defined by a pulse of the frame synchronization signal corresponding to a time width of a plurality of cycles of the synchronization clock signal.
The variable time division multiplex transmission system according to claim 1 or 2 . The frame of the sync pulse has a duration of two periods of said synchronous clock signal, the variable time division multiplex transmission system according to claim 3. Each of the slave devices holds a time slot number holding circuit that can be used by itself among a plurality of time slots included in one frame, the synchronization clock signal input terminal, and the frame synchronization signal input A time slot position indicating circuit connected to a terminal for outputting a time slot signal indicating one time slot in response to the synchronous clock signal and the frame synchronous signal; the synchronous clock signal input terminal; and the frame synchronous signal input terminal And a time slot allocation circuit including a time slot allocation token supply circuit connected to the daisy chain input terminal and the daisy chain output terminal to generate a time slot allocation token,
When the master device supplies data for the slave device to the first data line in synchronization with the synchronization clock signal and the frame synchronization signal, the first-stage slave device transmits the time slot signal and the time The slot allocation token for the next stage slave device is generated according to the slot number and is output from the daisy chain output terminal, and the next stage slave device receives the time slot signal, the time slot number, and the above In response to the slot allocation token supplied to the daisy chain input terminal, a slot allocation token for the slave device of the next stage is generated and output from the daisy chain output terminal.
Variable time division multiplex transmission system according to any one of claims 1 to 4. It said master device and said slave device is a semiconductor integrated circuit, variable time division multiplex transmission system according to any one of claims 1 to 5.

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