JP4692501B2 - Data storage system and data storage method - Google Patents

Description

  The present invention relates to a data storage system and a data storage method, and more particularly to a data storage system and a data storage method capable of reducing a load on a CPU.

  An example of a conventional log data storage system is shown in FIG. As shown in FIG. 17, this conventional log data storage system includes a CPU 901, a memory 902, a DMA (Direct Memory Access) controller (DMAC) 920, and a disk system 910. Each device can transmit / receive data to / from each other via the bus 905.

  In the CPU 901, an application program operates. A log generation program for generating log data also operates. The log generation program outputs the operation state of the application program and the operation state of the OS as log data. The function for generating log data may be realized by a different program from that included in an application program or OS.

  The memory 902 temporarily stores data generated by the log generation program on the CPU 901 until it is written to the disk system 910.

  The disk system 910 includes a disk drive 911 and a disk cache 912.

  The disk drive 911 is a device that stores data. In general, since a disk drive uses a magnetic disk, data writing and reading are slower than the memory 902.

The disk cache 912 temporarily stores data from the memory 902 when writing data to the disk drive 911. The disk cache 912 generally uses a semiconductor memory that is faster in writing and reading data than a disk drive. By using a high-speed semiconductor memory for the disk cache 912, when a large amount of data is written from the memory to the disk, the memory is temporarily written to the high-speed disk cache and then written to the low-speed disk drive. The data writing process from the disk to the disk can be speeded up.
The DMA controller 920 includes a DMA start unit 921, an address count unit 922, a disk write control unit 923, and a completion interrupt notification unit 924.

  The DMA start unit 921 receives a DMA transfer request from the CPU 901, and sets a memory address to be transferred to the address count unit 922. Each time the data is transferred from the memory to the disk system, the address counting unit 922 updates the address of the memory from which the data is read, and notifies the disk writing control unit 923 of it. The disk write control unit 923 reads the data at the memory address designated from the memory count unit 922 and writes the data to the disk cache 912. When the completion interrupt transfer means 924 completes the transfer of all data requested by the DMA transfer request from the CPU 901, the completion interrupt notification means 924 notifies the CPU 901 of an interrupt indicating completion.

  The operation sequence of the conventional log data storage system having the above configuration is shown in FIGS. FIG. 18 shows an operation sequence of the CPU 901, and FIG. 19 shows an operation sequence of the DMA controller 920.

  The operation of the CPU 901 will be described with reference to FIG.

In step S <b> 901, the CPU 901 writes log data to the memory 902.
In general, the free space in the memory 902 is managed by an OS running on the CPU 901. Therefore, when the free space on the memory 902 becomes small, the OS on the CPU 901 issues a DMA transfer request for writing the data on the memory 902 to the disk system 910 to the DMA controller 920.

  In step 902, the CPU 902 sets the memory address and data size of the data to be transferred. In step S903, the CPU 901 sets a transfer destination disk address. Thereafter, in step S904, the CPU 901 notifies the DMA controller 920 of a DMA transfer request. In the DMA transfer request, the memory address and data size to be transferred are notified.

  When receiving the DMA transfer request, the DMA controller 920 reads the data at the address specified by the DMA transfer request from the memory 902 and writes it in the disk cache 912. This operation will be described later with reference to FIG. 19 as an operation flow of the DMA controller.

  When the transfer of all data requested by the DMA transfer request is completed, the CPU 901 receives a DMA transfer completion interrupt in step S905. When the DMA transfer completion interrupt is received, the OS managing the memory 902 updates the free state of the memory.

  Next, the operation flow of the DMA controller 920 will be described with reference to FIG.

  When the DMA controller 920 receives a DMA transfer request from the CPU 901, the DMA start unit 921 sets a memory address to be transferred in the address count unit 922 (step S921). In step S922, the address count unit 922 increments the memory address to be transferred for each data transfer, and sets the memory address in the disk write control unit 923.

  Next, the disk write control unit 923 reads data from the memory address set in the address count unit 922 (step S923), and writes the read data to the disk cache 912 (step S924). Data written to the disk cache 912 is written to the disk drive 911. The amount of data that can be transferred at one time by data transfer between the memory 902 and the disk system 910 is determined by the bus and OS. For this reason, if the data amount of the DMA transfer request is larger than the limited data amount, the above transfer operation is repeated until the transfer of the requested data amount is completed (step S925).

As described above, in the conventional log data storage system, by using DMA, the CPU does not perform processing related to data transfer from the memory to the disk system, and therefore the CPU for storing log data in the disk system. The load can be reduced.
In the conventional log data management system, when log data is transferred to a remote management computer, the log data is collected using the TCP / IP protocol.

For example, Patent Literature 1, Patent Literature 2, and Patent Literature 3 disclose techniques related to the present invention.
JP 2005-165439 A JP 2005-165619 A JP-A-2005-316700

  The first problem is that the CPU load increases as the amount of collected log data increases.

  The reason for this is that the CPU executes the disk device driver call and the DMA transfer completion interrupt process for each DMA transfer.

  The second problem is that the transfer processing CPU load increases when log data is transferred to a remote management computer different from the management target computer.

  The reason is that the processing load of the TCP / IP protocol for transfer processing between computers increases.

[Object of invention]
An object of the present invention is to provide a data storage system capable of reducing the CPU load.

  Another object of the present invention is to prevent duplication and omission of data stored in a disk drive.

A first data storage system of the present invention has a plurality of buffers, a memory including a data storage area that is a storage destination of data, and a buffer state storage area that stores the state of the buffer;
Memory address determining means for determining memory addresses of the data storage area, the plurality of buffers, and the buffer state storage area; and memory access order determining means for determining an address order for storing the data in the data storage area; The buffer access state of the buffer state storage area is acquired according to the order determined by the memory access order determination means, and if the buffer state is not a state where data can be written, the data write is suspended and the buffer state is a state where data can be written A processor that operates according to a program that functions as data writing means for writing data and updating the buffer state of the buffer state storage area,
A disk drive to which data in the data storage area is transferred;
Means for acquiring and storing addresses of the data storage area, the buffer and the buffer state storage area on the memory from the program;
The buffer status in the buffer status storage area is acquired in accordance with the address order in which the program writes the data in the data storage area. If the buffer status is not readable, the processing is suspended. If the data can be read, the disk write control means for reading the data in buffer units, writing the read data to the disk drive, and updating the buffer state;
It is characterized by having.
A second data storage system of the present invention has a plurality of buffers, a memory including a data storage area that is a data storage destination, and a buffer state storage area that stores the state of the buffer;
Memory address determining means for determining memory addresses of the data storage area, the plurality of buffers, and the buffer state storage area; and memory access order determining means for determining an address order for storing the data in the data storage area; The buffer status in the buffer status storage area is acquired according to the order determined by the memory access order determination means, and if the buffer status is not readable, the data reading is suspended and the buffer status is read from the data. A processor that operates according to a program that reads data if it can be output and functions as data reading means for updating the buffer state of the buffer state storage area;
A disk drive from which data in the data storage area is transferred;
Means for acquiring and storing addresses of the data storage area, the buffer and the buffer state storage area on the memory from the program;
The data in the data storage area is acquired according to the order of addresses in which the program writes data, and the buffer status in the buffer status storage area is acquired. Disk read control means for reading data from the disk drive, writing the read data to the data storage area on the memory, and updating the buffer status;
It is characterized by having.

  Having such a configuration, the processor and the data transfer control unit share the address of the area in which data is written to the memory in advance, and confirm that the buffer is writable or readable, thereby reducing processor load and storing The object of the present invention can be achieved to prevent duplication and omission of data.

  According to a third data storage system of the present invention, in the first invention, before the buffer status is confirmed from the buffer status storage area, the data transferred from the memory to the disk drive is stored, and the data read from the memory is If the stored data is different from the stored data, the disk write control means is instructed to transfer the data. By having such a configuration, the number of memory accesses can be reduced and the CPU load can be reduced.

  According to a fourth data storage system of the present invention, in the first or second invention, a time interval for confirming completion of data writing in units of buffers in the data storage area is stored, and when confirming completion of writing, When writing has already been completed, the waiting time until the next confirmation is shortened, and when writing has not been completed, the memory reading interval is controlled so as to increase the waiting time until the next confirmation. It has a transfer interval control means. By having such a configuration and controlling the time interval for accessing the memory, the number of memory accesses can be reduced and the CPU load can be reduced.

  According to a fifth data storage system of the present invention, in the first or second invention, the command on the bus is monitored, the content of the command is a data write request from the CPU to the data storage area, and a new buffer It is characterized by having a command monitoring means for performing memory reading when a write request is made. By having such a configuration and controlling the time interval for accessing the memory, the number of memory accesses can be reduced and the CPU load can be reduced.

  According to a sixth data storage system of the present invention, in the first to fifth aspects of the present invention, the data storage system includes a plurality of disk drives, and further includes a data transfer destination selection unit that selects a data transfer destination disk drive according to the contents of the data. It is characterized by that. By having such a configuration and distributing and storing data on a plurality of disks, it is possible to improve the writing speed to the disks and prevent data loss.

  According to a seventh data storage system of the present invention, in the sixth invention, a bus protocol transfer unit that encapsulates a command on the bus into a protocol of an external network of the computer, and a CPU that can control a disk drive connected to the bus. The partition control means for determining and the data transfer destination selecting means for designating the remote disk drive connected by the bus protocol transfer unit as the transfer destination are provided. With such a configuration, by encapsulating data in the bus protocol and transferring it to a remote disk, TCP / IP processing can be reduced and CPU load can be reduced.

  The first effect is that the CPU load when transferring data from the memory to the disk can be reduced.

  This is because the processor and the data transfer control unit share the address of the area in which data is written to the memory in advance, so that the process of notifying the memory address each time data is transferred can be omitted.

  Another reason is to control the timing at which the disk write control means accesses the memory for data reading.

  The second effect is to prevent duplication of data stored in the disk drive.

  The reason is that data read from the memory is temporarily stored, and only data different from the stored data is transferred.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

  In each embodiment described below, it is assumed that the CPU includes a data writing unit and a data reading unit, and the data transfer control unit includes a disk writing control unit and a disk reading control unit. However, a data storage system in which the CPU has no data writing means and the data transfer control unit has no disk writing control means, and a data storage system in which the CPU has no data reading means and the data transfer control unit has no disk reading control means are also included in the present invention. Shall be included.

[First Embodiment]
As shown in FIG. 1, the log data storage system of this embodiment includes a CPU 101, a memory 102, a data transfer control unit 130, and a disk system 110. The CPU (acting as a processor) 101, the memory 102, the data transfer control unit 130, and the disk system 110 can transmit and receive data to and from each other via the bus 105.

  The CPU 101 and the disk system 110 have the same functions as the conventional CPU 901 and the disk system 910 shown in FIG.

  The memory 102 includes a data storage area 120, a buffer status storage area 125, and a buffer allocation storage area 126. The data storage area 120 is divided into a plurality of buffers. Log data is written from the CPU 101 to the data storage area 120, and the data in this area is transferred to the disk system 110 by the data transfer control unit 130.

  By dividing the data storage area 120 into a plurality of buffers, when transferring data for each buffer, log data can be written to another buffer while the data in one buffer is being transferred. Therefore, even when data is being transferred from the memory 102 to the disk system 110, it is possible to continue writing log data to the memory 102. The size of each buffer may be the same or different.

  The writing speed to the memory 102 is generally higher than the writing speed to the disk system 110. For this reason, if the amount of data written to the memory 102 is excessively large, the data transfer from the memory 102 to the disk system 110 cannot catch up and the memory overflows and log data may be lost. One method for preventing this is a method in which a plurality of disk drives are used, and data transfer from a memory is processed in parallel by a plurality of disk drives.

  As shown in FIG. 1, the data storage area 120 creates a write area and a read area, respectively, when both a process for writing data to the disk system and a process for reading data from the disk system are mixed. To do. Further, when there are a plurality of programs for generating log data or reading log data from the disk system, such as the program 200a, program b, and program m in FIG. 1, a read area (becomes a data storage area for the program) is provided for each program. create. When writing and reading are mixed for each program, a writing area and a reading area (which becomes a data storage area for the program) are created for each program, and a ring buffer is configured in each area. The area allocated to each program is allowed to access only the processes related to the allocated program and the data transfer control unit.

  Information on the address or size used as a partition between these areas is stored in the buffer allocation storage area 126 on the memory. By storing this information in the memory address storage unit 132 of the data transfer control unit 130, the data transfer control unit 130 can specify an area for accessing the memory.

  The buffer state storage area 125 stores the data state of each buffer. The buffer status includes “write enabled”, “writing in progress”, “readable”, and “reading in progress”.

  In the area where the program writes data to the disk, “Writable” means that the program can write data to the memory, and “Writing” means that the program is writing data to the memory. "Indicates that the data transfer control unit can read data from the memory, and" during reading "indicates that the data transfer control unit is reading data from the memory. When “Writable” and “Writing”, the data transfer control unit cannot read data from the memory or write data to the memory. When “Readable” and “Reading”, the program cannot read data from the memory or write data to the memory.

  In the area where the program reads data from the disk, “Writable” indicates that the data transfer control unit can write data to the memory, and “Writing” indicates that the data transfer control unit is writing data to the memory. “Readable” means that the program can read data from the memory, and “Reading” means that the program is reading data from the memory. When “Writable” and “Writing”, the program cannot read data from the memory or write data to the memory. In the case of “Readable” and “Reading”, the data transfer control unit cannot read data from the memory or write data to the memory.

  As shown in FIG. 2, the data storage area 125 stores the state of each buffer. The example of FIG. 2 shows the state of the writing area of program 1 (program 200a). Here, the program 1 write area of the data storage area 120 is made up of N buffers, and in FIG. 2, the data storage area 125 shows the state of the N buffers.

  The buffer 1 can be written, the buffer 2 can be read, the buffers 3 and 4 can be read, the buffer 5 can be written, and the buffers 6 to N can be written. This state is updated by the program and data transfer control unit 130 on the CPU. In this way, control is performed using the state of each buffer so that the order of writing and reading does not reverse.

  Each of the programs 200a to 200m for generating log data operates on the CPU 101. Each of the programs 200a to 200m includes a memory address determining unit 201, a memory access order determining unit 202, a data writing unit 203, and a data reading unit 204.

  The memory address determination unit 201 determines addresses of the data storage area 120, the buffer, and the buffer status storage area 125 on the memory 102. The memory address determination unit 201 notifies the data transfer control unit 130 of the determined address information.

  The memory access order determination unit 202 determines the order of writing log data in the data storage area 120. As an example of the access order, there are a sequential order with respect to memory addresses and an order according to the importance of data. Further, the memory access order unit 202 notifies the data transfer control unit 130 of the determined access order.

  The data writing unit 203 performs processing for writing log data to the memory 102. This writing process requests writing to the disk system. However, when the writing of data to the memory 102 is completed without waiting for completion of writing to the disk system, a normal processing return value is returned as the completion processing of the writing processing function, and the processing ends normally. Since the data transfer control unit 130 executes writing from the memory 102 to the disk system 110, the function can be terminated when the data is stored in the memory 102 when viewed from the program. The area in which the program writes data to the memory 102 is the area determined by the memory address determining means 201, and the writing order is the order determined by the memory access order determining means 202.

  The data reading unit 204 performs processing for reading log data from the memory 102. In the reading process, when the reading of data from the memory 102 is completed, a reading process function is completed. The area from which data is read is the area determined by the memory address determining means 201, and the order of reading is the order determined by the memory access order determining means 202.

The data transfer control unit 130 controls data transfer from the memory 102 to the disk system 110. The data transfer control unit 130 includes a memory address acquisition unit 131, a memory address storage unit 132, a disk write control unit 133, and a disk read control unit 136.
The memory address acquisition unit 131 acquires the addresses of the data storage area 120 and the buffer and the memory access order from the CPU 101 and registers them in the memory address storage unit 132.

  The memory address storage unit 132 stores the addresses of the data storage area 120 and the buffer and the memory access order. The stored address information is used for determining the data transfer timing by the disk writing control means 133.

  The disk writing control unit 133 controls data transfer from the memory 102 to the disk system 110. More specifically, data is read from the data storage area 120 in units of buffers, and the read data is written to the disk cache 112 in the disk system 110.

The disk read control unit 136 controls data transfer from the memory 102 to the disk system 110.
Next, the overall operation of the present embodiment will be described with reference to the flowcharts of FIGS. In the present invention, there are two types of operations: writing log data to the disk system and reading log data from the disk system. First, the writing operation to the disk system will be described with reference to FIGS. Thereafter, a read operation from the disk will be described.

  FIG. 3 is a flowchart showing the operation of the CPU 101 in the present embodiment. FIG. 4 is a flowchart showing the operation of the data transfer control unit 130 in the present embodiment.

  In the present embodiment, a plurality of devices shown in FIG. 1 operate in cooperation with each other. Since a plurality of apparatuses perform processing simultaneously, each operation will be described with reference to individual flowcharts. Although the flowchart is shown individually, this embodiment achieves an effect by operating each other's devices in cooperation by notifying other devices of the start of operation and referring to the data write state from other devices. Is.

  First, the operation of the CPU 101 will be described with reference to FIG.

  First, initialization is performed in steps S501 and S502. In step S501, the CPU 101 notifies the data transfer control unit 130 of the data storage area 120 and the address of each buffer. The buffer may be information that can determine the boundary between the buffers, not the address, and may be, for example, the start address of the data storage area 120 and each buffer capacity. In this description, as shown in FIG. 1, the data storage area 120 is divided into N buffers, and IDs 1 to N are assigned to the respective buffers. Also, the order of accessing the memory is determined. Information regarding the determined memory is notified to the data transfer control unit 130.

  In step S502, the buffer state storage area 125 is initialized. The buffer that starts the access first (ID = 1 in the example of FIG. 3) is being written, and other buffer states are set to be writable.

  When the initial settings in steps S501 and S502 are completed, data is transferred in step S503 and subsequent steps. In step S503, the buffer status is confirmed according to the access order. If the state is writable in step S504, the state is updated to write in step S507. Thereafter, the process proceeds to step S508. If the data is being read or can be read in step S504, the data is temporarily stored in a cache in the program in step S505. Thereafter, after a certain time has elapsed, the buffer state is confirmed again (return to step S503). Such processing can prevent new data from being overwritten on data that has not been transferred from the memory to the disk. In step S505, a data storage area can be newly allocated on the memory 102, and data can be temporarily stored in the expansion area.

  If the buffer status is in writing in step S504, it is checked in step S508 whether there is sufficient space in the buffer size. If there is sufficient space, the log data is written to the memory in step S509. If there is no free space, the state of the currently accessed buffer is updated to be readable in step S511. In step S512, the state of the next buffer based on the access order is confirmed. If the state of the next buffer is writable, the state of the next buffer is updated during writing (step S514). Then, control goes to a step S509. If the state of the next buffer is not writable, the buffer state is confirmed again after a certain time has elapsed (return to step S503). Such storage of log data in the memory is continued until log collection is completed (step S510).

  Next, the operation of the data transfer control unit 130 will be described with reference to FIG.

  In step S531, the memory address acquisition unit 131 acquires the data storage area 120, the address of the buffer, and the access order to the memory from the CPU 101. This address information is registered in the memory address storage unit 132.

  In step S 532, the disk writing control unit 133 acquires the address of data to be transferred from the memory 102 to the disk system 110 from the memory address storage unit 132.

  In step S532, the state of the next buffer to be accessed is acquired from the buffer state storage area 125 in accordance with the memory access order determined by the memory access order determination unit 202 stored in the memory access storage unit 132.

  In step S533, it is determined whether the buffer state can be read. If it is not readable, the buffer status is confirmed again after a certain period of time (returns to step S532). If the buffer status can be read, the buffer status is updated during reading in step S534.

  In step S535, data is read from the corresponding buffer in the data storage area 120 of the memory 102. In step S536, the data is written into the disk cache 112 of the disk system 110. In the data transfer in steps S535 and S536, when the transfer data size at one time is limited by the bus bandwidth or the like, the data can be transferred in a plurality of times. When the data transfer is completed, the buffer state is updated to be writable in step S537. The data transfer from the memory to the disk is continued until the log collection is completed (step S538).

  In this way, by fixing the area in which the memory 120 writes data and the order in which data is written to the memory, the CPU 101 and the data transfer control unit 130 can share the memory address to which the CPU has written the data, and the address to which the CPU 101 has written the data. Can be omitted.

  In addition, since the free capacity management of the data storage area 120 is performed in the buffer status storage area 125, it is possible to omit the DMA transfer completion notification that was conventionally necessary for the management of the free state of the memory.

  In addition, the buffer state is stored in the buffer state storage area 125, and this state is shared by the CPU that is the data writing entity and the data transfer control unit that is the data reading entity, thereby writing data from the CPU to the memory. In addition, it is possible to avoid overwriting data that has not yet been transferred to the disk and duplication of data transferred from the memory to the disk.

  Next, an operation procedure for reading log data stored on the disk will be described with reference to FIGS.

  FIG. 5 is a flowchart showing the operation of the CPU 101 when reading the disk. FIG. 6 is a flowchart showing the operation of the data transfer control unit 130 when reading the disk. The basic operation is the reverse of the process of writing to the disc described above.

  With reference to FIG. 5, the operation of the CPU 101 when reading the disk will be described.

  First, initialization is performed in steps S631 and S632. This operation is the same processing as steps S501 and S502 in FIG. In this initialization process, log data to be read by the program is designated and notified to the data transfer control unit 130. The log data to be read can be specified by specifying a file name or an address in the disk. Subsequent steps S633 to S638 are basically the same as steps S532 to S538 in FIG. The difference is that the data read from the memory in step S535 and the data write to the disk cache of the disk system in step S536 are changed to the data read from the memory in step S636.

  With reference to FIG. 6, the operation of the data transfer control unit 130 at the time of disk reading will be described.

  First, in step S601, initialization is performed. This operation is the same processing as step S531 in FIG. Subsequent steps S603 to S615 are basically the same as steps S503 to S514 in FIG. The difference is that, in step S615, reading of log data from the disk is added between step S608 and step S609.

[Second Embodiment]
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 7, in the second embodiment of the present invention, in addition to the first embodiment shown in FIG. 1, a transfer data storage unit 135 and a data duplication filter unit 134 are added to the data transfer control unit 190. Have.

  The data duplication filter unit 134 determines whether the data read from the memory 102 has already been transferred in the past. If the data has already been transferred, the data write control unit 133 does not write to the disk system 110. Whether it has been transferred in the past can be determined by referring to a time stamp in the case of log data.

  The transfer data storage unit 135 stores the transferred data for a certain period. Based on the data stored in the transfer data storage unit 135, the data duplication filter unit 134 determines duplication of data read from the memory 102.

  Next, the operation of the second exemplary embodiment of the present invention will be described with reference to FIG. FIG. 8 is a flowchart showing the operation of the data transfer control unit 190 in the second embodiment. Since the operation of the CPU is the same as that already described with reference to FIG. 3, the description thereof is omitted here.

  In step S <b> 121, the memory address acquisition unit 131 acquires the data storage area 120, the buffer address, and the memory access order from the CPU 101. The address information is registered in the memory address storage unit 132.

  In step S122, the memory address of the buffer to be read is designated according to the memory access order registered in the memory address storage unit 132.

  In step S123, the disk write control unit 133 reads data in the memory 102 from the address specified by the memory address storage unit 132. The order in which the CPU 101 writes data to the memory and the order in which the disk writing control means 133 reads data from the memory only have to be shared by the CPU and the transfer control unit 133.

  In step S124, the data duplication filter unit 134 determines whether the data read from the memory is new data. If this determination does not match the data stored in the transfer data storage means 135, it is determined that the data is new. If it is determined that the data has not been transferred and has already been transferred, data is read again from the same memory address after a certain time.

  If it is determined in step S124 that the data read from the data storage area 120 is new, the data is written to the disk cache 112 (step S125). The transferred data is stored in the transfer data storage unit 135 in step S126. The timing for erasing the data stored in the transfer data storage means 135 includes the timing at which the number of data transfers and the data transfer size exceed a threshold after a certain time has elapsed after the transfer of the data size in the data storage area 120.

  Thereafter, in step S127, the buffer state is updated to be writable.

  The above process is continued until the log collection is completed (step S128).

  As described above, the data transfer control unit 190 confirms the duplication of data, so that the process of the data transfer control unit 190 accessing the buffer state storage area 125 before reading the data from the memory can be omitted. For this reason, the latency of data transfer can be suppressed.

[Third Embodiment]
Next, a third embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 9 is a block diagram showing the configuration of the third exemplary embodiment of the present invention. The third embodiment of the present invention shown in FIG. 9 is different from the data transfer control unit shown in FIG. 1 in that the data transfer control unit 140 includes a transfer interval control unit 141.

  Since the apparatus other than the transfer interval control unit 141 is the same as that of the first embodiment, description thereof is omitted here.

  The transfer interval control unit 141 notifies the disk write control unit 133 of a trigger for starting data transfer from the memory 102 to the disk system 110. In the first embodiment, the disk write control means 133 independently accesses the memory, but the third embodiment is different in that it is accessed by a trigger from the transfer interval control means 141. The time interval for notifying this trigger is the time until the next trigger occurs when the disk write control means 133 accesses the buffer in the data storage area 120 and the target buffer is writing data from the CPU 101. Increase the time interval. On the other hand, when the disk write control unit 133 accesses the buffer in the data storage area 120 to read data, if the target buffer has finished writing data from the CPU 101, the time interval until the next trigger is generated. shorten. In this way, by controlling the data read timing to the data storage area 120, the capacity of the data storage area 120 overflows due to an increase in the transfer interval from the data storage area 120 to the disk system 110, and the transfer request interval is shortened. As a result, it is possible to suppress an increase in the memory access load caused by repeatedly issuing read requests to the buffer that is still being written.

  Next, the operation of the third exemplary embodiment of the present invention will be described with reference to FIG. FIG. 10 is a flowchart illustrating the operation of the data transfer control unit 140 according to the third embodiment of this invention.

  Initialization processing is performed in steps S221 and S222.

  In step S <b> 221, the memory address acquisition unit 131 acquires the address information and the memory access order of the data storage area 120 and the buffer on the memory 102 from the CPU 101, and registers this address information in the memory address storage unit 132.

In step S222, it sets a t a waiting time until issuing a data transfer request to the initial value t _0. The waiting time t may be a numerical value that can be converted into time, for example, the number of clocks.

In step S223, the state of the buffer to be read is acquired according to the memory access order. If it is not possible to read in step S224, the process waits for time (Δt ₁ ) in step S225. Thereafter, in step S206, the elapsed time since the previous data transfer start trigger is issued is updated.

  For the buffer that is determined to be readable in step S224, the buffer status is updated during reading in step S227. Subsequently, data is read from the memory 102 in step S228. In step S229, the data read from the memory is written to the disk cache 112. When the transfer size of this data is limited by the bus standard or the like, this data transfer is repeated until all the data is transferred. Thereafter, in step S230, the buffer state is updated so as to be writable.

In step S231, it is compared whether the elapsed time between triggers is the same as the previous time. If the values differ depending on the determination in step S231, that is, if the process waits in step S225, the next time is waited for the elapsed time t in step S234. Same as the previous is determined in step S231, if that is the elapsed time increment was not, in step S232, a time to wait in step S234 Delta] t ₂ shortened. By reducing the waiting time, even when the writing speed from the log collection function to the log writing area 120 is increased, it is possible to prevent the memory from overflowing by shortening the data transfer request issuance interval. The shortening of the waiting time in step S232 is not limited to the subtraction process of shortening by a certain time, and for example, the time may be halved.

  When the log collection is finished, it is determined in step S233, and the data transfer issuance process is finished.

  As described above, in the third embodiment of the present invention, the transfer interval control unit 141 controls the data read timing to the data storage area 120 according to the data write status from the CPU 101 to the memory 102. be able to. As a result, when the writing frequency from the CPU 101 is high, the transfer interval from the data storage area 120 to the disk system 110 is shortened to prevent the log data from being lost due to the capacity of the data storage area 120 overflowing. Further, when the writing frequency from the CPU 101 to the memory 102 is low, it is possible to suppress an increase in the memory access load caused by issuing a read request to the buffer that is still being written by increasing the transfer request interval. It becomes possible.

[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 11 is a block diagram showing the configuration of the data storage system according to the fourth embodiment of this invention. A data transfer control unit 150 according to the fourth embodiment shown in FIG. 11 is different from the data transfer control unit according to the first embodiment shown in FIG.

  Since the apparatus other than the command monitoring unit 151 is the same as that of the first embodiment, the description thereof is omitted here.

  Command monitor means 151 monitors commands on bus 105. The command monitor unit 151 monitors a write command from the CPU 101 to the data storage area 120, and when the write address enters a new buffer area, requests the disk write control unit 133 to transfer data.

  The operation of the fourth embodiment of the present invention will be described with reference to FIG. In the fourth embodiment, since the operation of the CPU is the same as that in the first embodiment of the present invention, the description of the operation of the CPU 101 is omitted here, and the operation of the data transfer control unit 150 is performed. explain.

  The operation of the data transfer control unit 150 having the command monitoring unit 151 will be described with reference to the flowchart of FIG.

  In step S <b> 301, the memory address acquisition unit 131 acquires the address of the data storage area 120 and the buffer in the data storage area and the memory access order from the CPU 101 and registers them in the memory address storage unit 132.

  In step S <b> 302, the command monitor unit 151 monitors commands on the bus 105. In step S303 and S304, the monitored command determines whether to notify the disk write control means 133 of the start of data transfer.

  In step S303, it is determined whether the command content monitored in step S302 is a write command for the data storage area 120 from the CPU 101. Whether the command is a write is determined from the instruction type in the command. Whether the write destination address is in the data storage area 120 is determined by comparing the address of the data storage area 120 notified from the log collection function in step S301 with the processing target address in the monitored command.

  Since only log data is written in the data storage area 120, the command is a write command and the memory address of the write destination is in the data storage area 120 without looking at the contents of the data. The monitor unit 151 can detect that log data has been written on the memory 102 from the CPU 101.

  If the result of determination in step S303 is that the command is not a write request from the CPU 101 to the data storage area 120, processing returns to step S302. As a result of the determination in step S303, if it is determined that the command is a write request from the CPU 101 to the data storage area 120, it is determined in step S304 whether writing to the buffer has been completed.

Writing from the CPU 101 to the data storage area 120 is continuously performed on memory addresses. For this reason, if the address in the write command is an address in a new buffer area, it can be determined that the writing of log data to the previous buffer has been completed.
For example, if the address to be processed in the monitored command is in the buffer ID = 2, but the determination in step S304 at that time becomes the address in the buffer ID = 3, the buffer ID = 2 is set. It can be determined that the log data writing has been completed.

  In step S304, the disk write control unit 133 is notified of a data transfer request for the buffer for which it is determined that writing of log data to the buffer has been completed.

  For example, if it is determined in step S304 that the data writing of the buffer ID = 2 has been completed, the buffer state is updated during reading in step S305. In step S306, data with buffer ID = 2 is read from the memory. In step S307, the read data is written to the disk cache 112. In step S308, the buffer state is updated so as to be writable. The operations from step 302 to step S308 are performed until the log collection is completed (step S309). If it is determined in step S304 that writing to the buffer has not ended, the process returns to step S302.

  The effects of the fourth embodiment described above will be described.

  In the third embodiment, the transfer interval control unit 141 determines the trigger generation timing based on the past trigger generation interval. For this reason, when the data writing speed changes suddenly, etc., it differs from the past situation, even though the buffer is full and the memory read interval is long or the buffer is not full, It is possible that memory read requests occur frequently.

  On the other hand, in the fourth embodiment, since the command monitoring unit 151 monitors the instruction on the bus 105, the log data is written from the memory to the disk accurately when the writing of the log data to the buffer becomes full. A data transfer request to the system can be issued. For this reason, it is possible to prevent the interval from the time when the buffer is full until the memory is read from being long, or the occurrence of frequent memory read requests even though the buffer is not full.

[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described with reference to the drawings.

  FIG. 13 is a block diagram showing a configuration of the fifth exemplary embodiment of the present invention.

  In the fifth embodiment of the present invention, in addition to the first embodiment shown in FIG. 1, a data transfer control unit includes a data transfer destination selection means 161, and a plurality of disk systems 110a and 110b are provided. The point to be prepared is a feature. Since the configuration other than the data transfer destination selection unit 161 is the same as that of the first embodiment, only the data transfer destination selection unit 161 will be described here, and the other description will be omitted. In FIG. 13, the internal configuration of the disk system 110b is not shown, but the configuration is the same as that of the disk system 110a.

  The data transfer destination selection unit 161 selects the write destination disk system when the disk write control unit 133 writes data to the disk system 110. As a criterion for selecting a write destination disk system, there is a method of dividing by the importance level of data and the time when the data is generated. For example, data with high data importance can be stored in the disk system 110a, and data with low data priority can be stored in the disk system 110b.

  The operation of the fifth embodiment of the present invention will be described with reference to FIG. FIG. 14 is a flowchart showing the operation of the data transfer control unit 160. Since the operation of the CPU in the fifth embodiment is the same as the operation of the CPU in the first embodiment, a description thereof is omitted here.

  The operation of the data transfer control unit 160 shown in FIG. 15 includes step S401 between step S535 and step S536 in addition to the operation in the first embodiment. In step S401, the data transfer destination selection unit 161 selects a disk system to be written in accordance with the data content read from the memory 102. In addition, when the buffer state is not readable in step S533, the process returns to step S533 through step S402 for checking the buffer state after a predetermined time has elapsed.

  The effects of the fifth embodiment described above will be described.

  In the fifth embodiment, the data transfer destination selection unit 161 can select a transfer destination according to the importance of data. Therefore, it is possible to reduce the cost of the disk system by transferring data with high importance to a disk system with high reliability and data with low importance to a disk system with low reliability.

  The same effect can also be obtained by determining the transfer destination disk system for each buffer. In this case, when the CPU writes data into the memory, a means for selecting which buffer to write is necessary. Thus, if the data transfer control unit 160 monitors the buffer ID without monitoring the data contents in step S401, the transfer destination disk system can be determined.

[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described with reference to FIG. FIG. 15 is a block diagram showing the configuration of the sixth exemplary embodiment of the present invention. FIG. 15 shows a log in which a managed computer 11 that is a management target of log collection, a remote management computer 12 that analyzes log data, and a disk drive that stores log data is configured as a remote disk node 13 in another node. 1 shows a data storage system.

  The log data storage system of FIG. 15 is different from the fifth embodiment in that the managed computer 11 is a bus protocol transfer unit 180a, the remote management computer 12 is a bus protocol transfer unit 180b, and the remote disk node 13 is a bus protocol transfer. It differs in that it has a section 180c and is connected by a switch 190 with a partition control function. Since the configuration other than the bus protocol transfer units 180a to 180c and the switch with partition control function 190 is the same as that of the fifth embodiment, description thereof is omitted here. Since the configuration and operation of the bus protocol transfer units 180a to 180c are the same, the bus protocol transfer unit 180a will be described below as an example.

  The bus protocol transfer unit 180a performs processing for communicating the bus protocol used on the bus 105a with the network protocol used for connection between computers. For example, PCI Express is a bus protocol, and Ethernet (registered trademark) is a network protocol.

  The configuration of the bus protocol transfer unit 180a is shown in FIG. The bus protocol transfer units 180b and 180c have the same configuration. The bus protocol transfer unit 180 a includes a bus protocol processing unit 181, a network protocol processing unit 182, an encapsulation unit 183, and a decapsulation unit 184.

  The bus protocol processing means 181 performs header processing of the bus protocol. The network protocol processing means 182 performs network protocol header processing. The encapsulating means 183 encapsulates the bus protocol data with the network protocol when the data flow is from the internal bus side to the external network. Conversely, when the data flow is from the external network to the internal bus, the decapsulating means 184 removes the network protocol header from the network protocol and extracts the internal protocol data.

  The bus protocol transfer units 180a and 180c allow the bus 105a and the bus 105c to communicate data in the same way as the same bus.

  The switch with partition control function 190 controls a partition that associates the disk system 110c with the CPU that controls the disk system 110c. CPUs belonging to the same partition can control the disk system, and CPUs in different partitions cannot be controlled from the disk system. For example, when the network protocol processed by the bus protocol transfer unit is Ethernet (registered trademark), a partition can be configured for each VLAN ID by using a VLAN (Virtual LAN).

  When the log data from the CPU 101a is stored in the disk system 110c in the remote node 13, the switch with partition function 190 sets the disk system 110c and the CPU 101a to the same partition. Further, when the log data in the disk system 110c is analyzed by the CPU 101b, the disk system 110c and the CPU 101b are set to the same partition.

  In the operation of the sixth embodiment of the present invention, the procedure for transferring log data to the disk system is the same as that in the fifth embodiment. In step S401, the log data can be stored in the remote disk by setting the transfer destination disk to the remote disk. However, before transferring data to the disk system, the partition control function-equipped switch 190 sets the CPU 101a of the managed computer 11 and the disk system 110c as the transfer destination to the same partition. Further, when the log data stored in the disk system 110c is analyzed on the remote management computer, the CPU 101b and the disk system 110b are set to the same partition.

  The effects of the sixth embodiment described above will be described.

  In the sixth embodiment of the present invention, the TCP / IP processing necessary for data transfer to the remote disk is executed by a dedicated device that encapsulates the bus protocol into the network protocol, whereby the TCP / IP processing is performed by the CPU processing. Therefore, the CPU load can be reduced.

  As described above, in the description of each embodiment of the present invention, the log data written on the memory by the log collection function operating on the CPU has been described as an example. However, the effect of the present invention is not limited to the log data. In general, this is a technique that can be used when data written on a memory by a program on a CPU is transferred to a disk system.

  Further, in the description of the above operation, only the operation at the time of writing to the disk has been described except for the first embodiment. However, in all the above described embodiments, from the disk in the first embodiment. By performing the same operation as reading, the CPU load can be reduced even when reading data stored on the disk.

  In the description of each embodiment, there is a means for realizing a plurality of functions in the data transfer control unit, all of which may be configured by one device, or may be divided and realized by a plurality of devices. The effect of each embodiment can be realized. Even if some or all of these devices are configured in the disk system, the effects of the embodiments can be realized.

  The present invention is used in a data storage system and a data storage method capable of reducing the load on the CPU, and is used in a computer having a data storage system, a system in which such computers are connected via a network, and the like.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is a figure which shows the structure of a buffer state storage area. It is a flowchart which shows operation | movement of CPU at the time of the disk writing in the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the data transfer control part at the time of the disk writing of the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of CPU at the time of the disk reading of the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the data transfer control part at the time of the disk reading in the 1st Embodiment of this invention. It is a block diagram which shows the structure of the 2nd form of this invention. It is a flowchart which shows operation | movement of the data transfer control part in the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the 3rd Embodiment of this invention. It is a flowchart which shows operation | movement of the data transfer control part in the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the 4th Embodiment of this invention. It is a flowchart which shows operation | movement of the data transfer control part in the 4th Embodiment of this invention. It is a block diagram which shows the structure of the 5th Embodiment of this invention. It is a flowchart which shows operation | movement of the data transfer control part in the 5th Embodiment of this invention. It is a block diagram which shows the structure of the 6th Embodiment of this invention. It is a block diagram which shows the structure of a bus protocol transfer part. It is a block diagram which shows the structure of the conventional log data storage system. It is a flowchart which shows operation | movement of CPU in the conventional log data storage system. It is a flowchart which shows operation | movement of the DMA controller in the conventional log data storage system.

Explanation of symbols

101 CPU
102 Memory 105 Bus 110 Disk system 111 Disk drive 112 Disk cache 120 Data storage area 130, 140, 150, 160, 190 Data transfer control unit 131 Memory address acquisition unit 132 Memory address storage unit 133 Disk write control unit 134 Data duplication filter unit 135 Transfer Data Storage Unit 136 Disk Read Control Unit 141 Transfer Interval Control Unit 151 Command Monitor Unit 161 Data Transfer Destination Selection Unit 180 Bus Protocol Transfer Unit 181 Bus Protocol Processing Unit 182 Network Protocol Processing Unit 183 Encapsulation Unit 184 Decapsulation Unit 190 Partition Switch with control function 201 Memory address determining means 202 Memory writing order determining means 203 Data writing Only means 204 data reading means 901 CPU
902 Memory 910 Disk system 911 Disk drive 912 Disk cache 920 DMA controller 921 DMA start means 922 Address count means 923 Disk write control means 924 Completion interrupt notification means

Claims (18)

A memory having a plurality of buffers and having a data storage area for storing data, and a buffer state storage area for storing the state of the buffer;
Memory address determining means for determining memory addresses of the data storage area, the plurality of buffers, and the buffer state storage area; and memory access order determining means for determining an address order for storing the data in the data storage area; The buffer access state of the buffer state storage area is acquired according to the order determined by the memory access order determination means, and if the buffer state is not a state where data can be written, the data write is suspended and the buffer state is a state where data can be written A processor that operates according to a program that functions as data writing means for writing data and updating the buffer state of the buffer state storage area,
A disk drive to which data in the data storage area is transferred;
Means for acquiring and storing addresses of the data storage area, the buffer and the buffer state storage area on the memory from the program;
The buffer status in the buffer status storage area is acquired in accordance with the address order in which the program writes the data in the data storage area. If the buffer status is not readable, the processing is suspended. If the data can be read, the disk write control means for reading the data in buffer units, writing the read data to the disk drive, and updating the buffer state;
A data storage system comprising: The processor is operated by a plurality of the programs,
Each memory address determination means in the plurality of programs creates a data storage area for each program in the data storage area of the memory, and registers the allocated data storage area for the program in the buffer allocation storage area. ,
The data writing means accesses only the data storage area for the program allocated for the program to which it belongs,
2. The data storage system according to claim 1, wherein the disk write control means accesses only the data storage area for the program allocated for the designated program. A memory having a plurality of buffers and having a data storage area for storing data, and a buffer state storage area for storing the state of the buffer;
Memory address determining means for determining memory addresses of the data storage area, the plurality of buffers, and the buffer state storage area; and memory access order determining means for determining an address order for storing the data in the data storage area; The buffer status in the buffer status storage area is acquired according to the order determined by the memory access order determination means, and if the buffer status is not readable, the data reading is suspended and the buffer status is read from the data. A processor that operates according to a program that reads data if it can be output and functions as data reading means for updating the buffer state of the buffer state storage area;
A disk drive from which data in the data storage area is transferred;
Means for acquiring and storing addresses of the data storage area, the buffer and the buffer state storage area on the memory from the program;
The data in the data storage area is acquired in accordance with the address order in which the program writes data, and the buffer status in the buffer status storage area is acquired. If the buffer status is not in a state where data can be written, processing is suspended and the buffer status is data. Disk read control means for reading data from the disk drive, writing the read data to the data storage area on the memory, and updating the buffer status;
A data storage system comprising: The disk drive becomes a data transfer source in the data storage area,
The program obtains the buffer status of the buffer status storage area according to the order determined by the memory access order determination means, and if the buffer status is not readable, the data reading is suspended. If the data can be read, the data is read, and the processor functions as data reading means for updating the buffer status in the buffer status storage area.
The data in the data storage area is acquired in accordance with the address order in which the program writes data, and the buffer status in the buffer status storage area is acquired. If the buffer status is not in a state where data can be written, processing is suspended and the buffer status is data. 2. A disk read control means for reading data from the disk drive, writing the read data to the data storage area on the memory, and updating a buffer state if the data is in a state in which data can be written. Data storage system. The processor is operated by a plurality of the programs,
Each memory address determination means in the plurality of programs creates a data storage area for each program in the data storage area of the memory, and registers the allocated data storage area for the program in the buffer allocation storage area. ,
The data reading means accesses only the data storage area for the program allocated for the program to which it belongs,
5. The data storage system according to claim 3, wherein the disk read control means accesses only the data storage area for the program allocated for the designated program. Transfer data storage means for temporarily storing data transferred between the memory and the disk drive;
When the data read from the memory is different from the stored data, the data is transferred to the disk writing control means when writing data to the disk drive, and to the disk reading control means when reading data from the disk drive. A data duplication filter means for instructing;
The data storage system according to claim 4, comprising:   The time interval for confirming the completion of data transfer to the data storage area is stored, and when the transfer has already been completed at the time of confirming the transfer completion, the waiting time until the next confirmation is shortened and the transfer is still performed. 6. The data storage according to claim 1, further comprising transfer interval control means for controlling a memory access interval so as to lengthen a waiting time until the next confirmation when the data is not completed. system.   The memory and the processor are connected by a bus, monitors commands on the bus, and the content of the command is a data write request from the processor to the data storage area and a write request to a new address. 6. A data storage system according to claim 1, further comprising command monitor means for performing a memory read operation. A plurality of the disk drives;
9. The data storage system according to claim 1, further comprising data transfer destination selection means for selecting a data transfer destination disk drive from the plurality of disk drives in accordance with data contents. A first computer constituting the data storage system according to any one of claims 1 to 9;
A second computer for analyzing the data of the first computer;
A disk drive for storing data of the first computer,
A bus protocol transfer unit provided in each of the first and second computers and the disk drive and encapsulating a command on the bus into a protocol of an external network;
10. A partition control means for determining a processor to access a data transfer destination disk drive from the processor of the first computer or the processor of the second computer. The data storage system described in 1. A processor, a memory, a data transfer control unit, and a disk drive are connected by a bus, and the memory has a plurality of buffers and a data storage area in which data is stored, and a buffer state storage that stores the state of the buffer And a data storage method for a data storage system comprising:
A program running on the processor is
Determining memory addresses of the data storage area, the plurality of buffers and the buffer state storage area;
Determines the address order for writing the data in the data storage area, obtains the buffer state of the buffer state storage area according to the determined address order, and if the buffer state is not a state where data can be written, the data writing is suspended. , Write data if the buffer is ready to write data, write data to update the buffer status,
The data transfer control unit is
Obtaining and storing the addresses of the data storage area, the buffer, and the buffer state storage area on the memory from the program,
The buffer status in the buffer status storage area is acquired in accordance with the address order in which the program writes the data in the data storage area. If the buffer status is not readable, the processing is suspended. A data storage method comprising: reading data in units of buffers if the data can be read; writing the read data to the disk drive; and updating the buffer status. A processor, a memory, a data transfer control unit, and a disk drive are connected by a bus, and the memory has a plurality of buffers and a data storage area in which data is stored, and a buffer state storage that stores the state of the buffer And a data storage method for a data storage system comprising:
A program running on the processor is
Determining memory addresses of the data storage area, the plurality of buffers and the buffer state storage area;
Determining an address order for storing the data in the data storage area;
Acquires the buffer status of the buffer status storage area according to the determined address order. If the buffer status is not readable, the data reading is suspended. If the buffer status is readable, the data is stored. Read, read data to update buffer status,
The data transfer control unit is
The address on the disk of the data to be read, the data storage area on the memory, the address of the buffer and the buffer status storage area are acquired from the program, stored,
Obtaining the buffer status of the buffer status storage area according to the address order in which the program writes the data in the data storage area;
If the buffer state is not a state where data can be written, the processing is suspended, and if the buffer state is a state where data can be written, the data is read from the disk, and the read data is written to the data storage area in the memory. The data storage method characterized by updating. Storing data transferred between the memory and the disk drive in the data transfer control unit;
13. The data according to claim 11 or 12, wherein in the process of writing data to the disk drive, data transfer is performed when the data acquired from the memory is different from the data stored in the data transfer control unit. Memory method.   The data transfer control unit stores a time interval for confirming the completion of data transfer to the data storage area, and when the transfer has already been completed at the time of confirming the transfer completion, a waiting time until the next confirmation 13. The data storage method according to claim 11 or 12, wherein when the transfer is not completed yet, the access interval to the memory is controlled so as to increase the waiting time until the next confirmation. .   The memory and the processor are connected by a bus, the data transfer control unit monitors a command on the bus, the command content is a data write request from the processor to the data storage area, and a new 13. The data storage method according to claim 11, wherein memory read is performed when it is a write request to an address. A plurality of the disk drives;
16. The data storage method according to claim 11, wherein the data transfer control unit selects a data transfer destination disk drive from the plurality of disk drives according to data contents. A data storage method for a data storage system in which a managed computer that is a data storage system used in the data storage method according to any one of claims 11 to 16 and a remote disk are connected via a bus protocol transfer means. ,
Perform partition control so that the processor accessing the remote disk is a processor in the managed computer,
The data transfer control unit in the managed computer sets the data transfer destination disk as a remote disk,
Encapsulating the data transfer command to the remote disk into an external network protocol of the managed computer,
17. The data storage method according to claim 11, wherein the data transferred from the management target computer is written to the remote disk. After data is stored on the remote disk,
Perform partition control so that the processor accessing the remote disk is a processor in a remote management computer,
18. The data storage method according to claim 17, wherein data in the remote disk is read by a processor in the remote management computer.

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