JP4675352B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit equipment, in particular, a semiconductor substrate or SOI (Silicon On Insulator) insulating film multilayer wiring structure formed in the semiconductor element formed on a supporting substrate made of a substrate supported on a substrate is relates to a semiconductor integrated circuit equipment having a.

  In a semiconductor integrated circuit device (hereinafter also referred to as a chip) equipped with a MOS (Metal Oxide Semiconductor) transistor, heat generation of the device is achieved due to miniaturization of the manufacturing process, an increase in the number of devices mounted on the chip, and an improvement in operation speed. In some cases, the device and wiring may be damaged by the device, and the device performance may be deteriorated due to the temperature rise.

  Generally, as a countermeasure against heat generation of the chip, a heat dissipation mechanism provided in the package is used in an IC (Integrated Circuit) assembly process, and the surface opposite to the semiconductor element formation surface (back surface) with respect to the semiconductor element surface on which devices are formed ) Is radiated by bringing the silicon substrate (semiconductor substrate) into contact with the radiating mechanism.

  In addition, as countermeasures in chip design against chip heat generation, internal functions are divided and part of them are activated to reduce power consumption and suppress heat generation of the entire chip, or by using standard cell type cell placement and wiring In the layout method, each cell has a parameter for power consumption, and by using a software means of the cell placement and routing tool, cells such as a clock driver having a large power consumption are distributed and arranged locally in the chip. For example, there is a means for dispersing the heat generation area.

  For example, Japanese Patent No. 2971464 discloses a method of controlling the cell arrangement while adjusting the virtual temperature and the cost value by including the virtual temperature parameter in the standard cell library (Prior Art 1). Japanese Patent No. 2798048 discloses a method of adjusting the temperature distribution in the chip by arranging cells with a high activation rate around the chip (Prior Art 2).

  As a structure for solving the problem of the channel capacity (channel parasitic capacity) of the MOS transistor due to further miniaturization of the process, there is an SOI structure MOS transistor. There are roughly three types of SOI structures. FIG. 12 shows a cross-sectional view of a conventional MOS transistor and an SOI structure MOS transistor.

  As shown in FIG. 2A, the conventional MOS transistor includes two source or drain regions 9 and 9 formed on the surface side of the silicon substrate 1 with a gap, and a silicon substrate between the source or drain regions 9 and 9. 1 is provided with a gate electrode 13 via a gate oxide film 11.

  As shown in (B), a fully depleted SOI-MOS transistor (hereinafter referred to as a fully depleted SOI transistor) is formed on the SOI substrate 7. The SOI substrate 7 has a buried oxide film 3 formed on the silicon substrate 1 and a single crystal silicon layer 5 formed on the buried oxide film 3. Two source or drain regions 9 and 9 are formed with a gap in the single crystal silicon layer 5, and a gate electrode 13 is formed on the single crystal silicon layer 5 between the source or drain regions 9 and 9 via a gate oxide film 11. ing. In the fully depleted SOI transistor, the single crystal silicon layer 5 under the channel region is all depleted.

  As shown in (C), a partially depleted SOI-MOS transistor (hereinafter referred to as a partially depleted SOI transistor) is formed on the SOI substrate 7. Two source or drain regions 9, 9 are formed at a distance in the single crystal silicon layer 5, and a gate electrode 13 is formed on the single crystal silicon layer 5 between the source or drain regions 9, 9 via a gate oxide film 11. ing. The partially depleted SOI transistor has a single crystal silicon layer 5 that is thicker than a fully depleted SOI transistor, and has a region that is not depleted at the bottom of the single crystal silicon layer 5.

  An SON (Silicon On Nothing) -MOS transistor (hereinafter referred to as an SON transistor) shown in FIG. 4D is formed on a silicon substrate 1 in which a hole or a buried oxide film 14 is formed immediately below a region to be a channel region on the surface side. It is formed. In the silicon substrate 1, two source or drain regions 9, 9 are formed with a region serving as a channel region on the vacancy or the buried oxide film 14, and the single crystal silicon layer 5 between the source or drain regions 9, 9 is formed. A gate electrode 13 is formed thereon via a gate oxide film 11.

  In SOI-structure MOS transistors and SON transistors, the channel layer is thin, and heat conduction to the silicon substrate is difficult due to an insulator. Therefore, in the fully depleted SOI transistor, the self-heating phenomenon due to heat generation of the gate electrode is a problem. become.

  For example, in Japanese Patent No. 3128931, in consideration of heat generation in an SOI device, a temperature change due to self-heating of the SOI device itself and a mobility that changes due to the temperature change are calculated, and an SOI is calculated using the changed mobility. A semiconductor device simulation method for simulating device operation is disclosed (Prior Art 3).

However, none of the prior arts 1 to 3 described above reduce the temperature rise of the semiconductor integrated circuit device due to heat generation of the semiconductor element.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device and a method for manufacturing the same, which can reduce the temperature rise of the semiconductor integrated circuit device due to heat generation of a semiconductor element.

A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device including a semiconductor element formed on a semiconductor substrate and a multilayer wiring structure formed in an insulating film on the semiconductor substrate, and constitutes the multilayer wiring structure The connection hole and the metal wiring layer are made of the same conductive material, and are provided with a heat conducting portion extending to the upper layer side through a different path from the signal transmission connection hole and the metal wiring layer.
The heat conduction part can dissipate the heat generated in the semiconductor element to the upper layer side of the semiconductor integrated circuit device, thereby reducing the temperature rise of the semiconductor integrated circuit device.

  In the semiconductor integrated circuit device of the present invention, it is preferable that the heat conducting portion includes an uppermost wiring layer. As a result, heat generated in the semiconductor element can be conducted to the vicinity of the upper layer surface of the semiconductor integrated circuit device by the heat conducting portion, and the efficiency of heat radiation can be improved.

  Furthermore, it is preferable that an opening is formed in the insulating film on the uppermost wiring layer constituting the heat conducting portion. As a result, the efficiency of heat dissipation can be further improved.

  Further, a MOS transistor can be cited as a semiconductor element constituting the semiconductor integrated circuit device of the present invention. In that case, it is preferable that the heat conducting portion is connected to the gate electrode of the MOS transistor directly or via a signal transmission connecting hole and a metal wiring layer. As a result, heat generated at the gate electrode of the MOS transistor can be dissipated through the heat conducting portion.

  The heat conducting portion may be connected to the source or drain region of the MOS transistor directly or via a signal transmission connection hole and a metal wiring layer. As a result, the heat generated at the gate electrode of the MOS transistor can be radiated from the source or drain region via the heat conducting portion.

  Further, the heat conducting part may be directly connected to an element isolation film for electrically isolating the MOS transistor. As a result, heat generated at the gate electrode of the MOS transistor can be dissipated from the element isolation film via the heat conducting portion.

  Examples of the MOS transistor include a fully depleted SOI transistor, a partially depleted SOI transistor, and a SON transistor. In these MOS transistors, particularly in fully depleted SOI transistors, the problem of the self-heating phenomenon due to heat generation of the gate electrode can be solved.

  Further, in the semiconductor integrated circuit device of the present invention, the thermally conductive portion includes a dummy metal that is not used as an electrical wiring, and the dummy metal is arranged at the same coordinate in each layer, and the same coordinate in different layers. It is preferable that the dummy metal of a position is connected through the connection hole. As a result, the heat stored between the chip wiring layers can also be conducted to the upper layer side, and the temperature rise of the semiconductor integrated circuit device can be further reduced.

  Further, as a semiconductor integrated circuit device to which the present invention is applied, a semiconductor integrated circuit device of a system in which a circuit including a plurality of semiconductor elements is divided into functional blocks for each function and a plurality of functional blocks are arranged. Examples of such a semiconductor integrated circuit device include a standard cell type semiconductor integrated circuit device. In that case, it is preferable that a part or all of the functional blocks include one or a plurality of heat conducting portions constituting the semiconductor integrated circuit device of the present invention. As a result, in the semiconductor integrated circuit device in which a plurality of functional blocks are arranged, the heat conduction part can be arranged immediately above the semiconductor element serving as a heat generation source, and the heat dissipation effect can be obtained efficiently.

  Furthermore, it is preferable that the heat conducting portion is arranged according to the heat capacity of the gate electrode in the functional block. As a result, for example, by bypassing the signal wiring caused by the heat conduction part by selectively inserting the heat conduction part into a functional block that is expected to have a high activation rate such as a buffer cell used in a clock driver etc. Can be minimized.

  In addition, when the semiconductor integrated circuit device of the present invention is applied to a system in which a circuit including a plurality of semiconductor elements is divided into functional blocks for each function and a plurality of functional blocks are arranged, feed cells that fill gaps between the functional blocks are arranged. The feed cell may be provided with one or a plurality of heat conducting portions constituting the semiconductor integrated circuit device of the present invention. Here, a feed cell refers to a cell arranged between functional blocks, such as a gap formed when a functional block is arranged in a semiconductor integrated circuit device in which a plurality of functional blocks are arranged. The feed cell is also called a feed-through cell. By disposing the heat conduction part in the feed cell, the heat dissipation effect by the heat conduction part can be obtained without changing the conventional functional block.

  Furthermore, it is preferable that the feed cell provided with the heat conducting portion is arranged according to the heat capacity of the gate electrode in the functional block near the feed cell. As a result, the bypass of the signal wiring caused by the heat conduction part can be minimized by selectively inserting the heat conduction part into the feed cell in the vicinity of the functional block expected to have a high activation rate. it can.

One method of manufacturing a semiconductor integrated circuit device according to the present invention is to form a circuit including a plurality of semiconductor elements into functional blocks for each function, hold each functional block as a standard cell in a library, and arrange a plurality of standard cells. A standard cell type semiconductor integrated circuit device manufacturing method, wherein the standard cell is made of the same conductive material as the connection hole and metal wiring layer constituting the multilayer wiring structure, and the signal transmission connection hole and metal wiring layer Including a heat conducting portion extending to the upper layer side through a different path.

  Thus, in the manufacturing method of the standard cell type semiconductor integrated circuit device, the semiconductor integrated circuit device resulting from the heat generation of the semiconductor element is obtained by using the standard cell having the heat conducting portion constituting the semiconductor integrated circuit device of the present invention. Temperature rise can be reduced. Further, the step of changing to the standard cell having the heat conducting portion can be performed after the detailed wiring step in the manufacturing method of the standard cell type semiconductor integrated circuit device.

In the above manufacturing method, the standard cells also include feed cells that fill the gaps between the functional blocks. These feed cells are made of the same conductive material as the connection holes and metal wiring layers that constitute the multilayer wiring structure. It is preferable to include one provided with a heat conduction portion extending to the upper layer side through a path different from the connection hole for signal transmission and the metal wiring layer.

  Thus, in the manufacturing method of the standard cell type semiconductor integrated circuit device, the semiconductor integrated circuit device caused by the heat generation of the semiconductor element is used by using the feed cell having the heat conducting portion constituting the semiconductor integrated circuit device of the present invention. Temperature rise can be reduced. Further, the step of changing to the feed cell having the heat conducting portion can be performed after the detailed wiring step in the manufacturing method of the standard cell type semiconductor integrated circuit device.

In the semiconductor integrated circuit device of the present invention, in the semiconductor integrated circuit device of a system in which a plurality of functional blocks are arranged, the region includes feed cells that fill gaps between the functional blocks, and the feed cells are arranged on both sides thereof. A signal wiring that connects between the functional blocks, and a heat conduction portion that is connected to the signal wiring and that extends to the upper layer side through a path different from the connection hole for signal transmission of the functional block and the metal wiring layer Therefore, the heat dissipation effect by the heat conducting unit can be obtained without changing the conventional functional block.

  FIG. 1 is a sectional view showing an embodiment of a semiconductor integrated circuit device. In this embodiment, a fully depleted SOI transistor is used and a 6-layer metal wiring structure is used. In addition, the size of each metal wiring layer indicated by the horizontal width in the drawing is an example, and is not limited to the size shown in the drawing.

  A plurality of fully depleted SOI transistors are formed on an SOI substrate 1 on which a buried oxide film 3 is formed on a silicon substrate 1 and a single crystal silicon layer 5 is formed thereon. Each fully-depleted MOS transistor is electrically isolated by an isolation oxide film 15 formed by, for example, STI (Shallow Trench Isolation) technology in which a shallow trench is filled with an insulator to perform element isolation. The fully-depleted MOS transistor is formed by gate oxidation on two source or drain regions 9 and 9 formed on the single crystal silicon layer 5 of the SOI substrate 1 with an interval, and on the single crystal silicon layer 5 between the source or drain regions 9 and 9. A gate electrode 13 made of, for example, a polysilicon film formed through the film 11 is provided. The fully depleted SOI transistors in regions A and B have a common gate electrode 13.

  An insulating layer 17 formed by laminating a plurality of insulating layers on the fully depleted SOI transistor and on the SOI substrate 1 including the element isolation film 15 is formed. In the insulating layer 17, metal wiring layers M1, M2, M3, M4, M5, and M6 are formed in order from the lower layer side.

  In the regions A and D where the fully depleted SOI transistors are formed, the gate electrode 13 is electrically connected to the lowermost metal wiring layer M1 through the contact layer 19 and further through the via layer 21 to the metal. It is electrically connected to the wiring layer M2.

  In the region C, the metal wiring layer M2 is formed in the uppermost metal wiring layer M6 via the via layer 23, the metal wiring layer M3, the via layer 25, the metal wiring layer M4, the via layer 27, the metal wiring layer M5, and the via layer 29. Electrically connected. A pad opening 31 is formed in the insulating layer 17 on the metal wiring layer M6. The wiring path from the contact layer 19 to the metal wiring layer M6 in the region C constitutes a connection hole and a metal wiring layer for signal transmission.

  In a region A where a fully depleted SOI transistor is formed, a via layer 23, a metal wiring layer M3, a via layer 25, a metal wiring layer M4, a via layer 27, A metal wiring layer M5, a via layer 29, and an uppermost metal wiring layer M6 are formed. The heat conducting portion 33 is formed on the upper layer side of the metal wiring layer M2 through a path different from the connection hole for signal transmission and the metal wiring layer.

  In the region A, the heat generated by the gate operation of the fully depleted SOI transistor is conducted to the contact layer 19, the metal wiring layer M 1, the via layer 21, and the metal wiring layer M 2, and further through the heat conduction part 33. Conducted to the metal wiring layer M6 and radiated from the upper surface side of the insulating layer 17. Thereby, the temperature rise of the semiconductor integrated circuit device can be reduced.

  In this embodiment, the heat conducting section 33 is composed of metal wiring layers M3, M4, M5, M6 and via layers 23, 25, 27, 29, and a signal transmission contact layer 19, a metal wiring layer M1, and a via layer 21. And the metal wiring layer M2 is connected to the gate electrode 13. However, the heat conduction part constituting the semiconductor integrated circuit device of the present invention is not limited to this, and for example, from the contact layer 19 to the metal wiring layer M6. All of the conductive materials up to and including the metal wiring layer for signal transmission may be connected directly to the gate electrode.

  In the region E in the vicinity of the region D where the fully depleted SOI transistor is formed, the via layer 23, the metal wiring layer M3, the via layer 25, and the metal wiring layer M4 that constitute the heat conducting unit 35 are formed on the metal wiring layer M2. A via layer 27 and a metal wiring layer M5 are formed. The heat conducting portion 35 is formed on the upper layer side of the metal wiring layer M2 through a path different from the connection hole for signal transmission and the metal wiring layer.

  In the regions D and E, the heat generated by the gate operation of the fully depleted SOI transistor is conducted to the contact layer 19, the metal wiring layer M 1, the via layer 21, and the metal wiring layer M 2, and further to the metal through the heat conduction part 35. It is conducted to the wiring layer M5 and radiated from the upper surface side of the insulating layer 17. As described above, the heat conducting portion constituting the semiconductor integrated circuit device of the present invention may not include the uppermost metal wiring layer M6, and the heat conducting portion is on the gate electrode 13 of the fully depleted SOI transistor. It may be formed in a different region.

  Each of the metal wiring layers M3, M4, M5, and M6 constituting the heat conducting portions 33 and 35 may be a dummy metal that is not used as an electric wiring, or provided to form the heat conducting portion 33. Alternatively, a dedicated metal wiring layer may be used.

  In the region F, the metal wiring layer M3, the via layer 25, the metal wiring layer M4, the via layer 27, the metal wiring layer M5, the via layer 29, and the metal wiring layer M6 that form the heat conducting portion 37 are formed. The heat conduction part 37 is not connected to the metal wiring layer M2 constituting the metal wiring layer for signal transmission, and the metal wiring layers M3, M4, M5, M6 constituting the heat conduction part 37 are formed of a dummy metal. ing.

FIG. 2 is a plan view of a region where a dummy metal is formed. FIG. 2A shows a dummy metal that constitutes a heat conducting portion, and FIG. 2B shows a dummy metal that does not constitute a heat conducting portion.
For example, in each of the metal wiring layers M3 to M6, the dummy metal 39 is formed at the same coordinate position when viewed from the upper surface side (see FIG. 2B).
When the dummy metal 39 is used as the heat conducting portion, the metal wiring layers M3 to M6 are connected via the via layers 25, 27, and 29 (see region F in FIG. 1 and FIG. 2A). Thereby, the heat stored between the wiring layers can also be conducted to the upper layer side, and the temperature rise of the semiconductor integrated circuit device can be further reduced.

FIG. 3 is a sectional view showing another embodiment of the semiconductor integrated circuit device. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.
The difference from the embodiment shown in FIG. 1 is that heat radiation openings 41 are formed in the insulating layer 17 on the metal wiring layer M6 in the regions A and F, respectively. The heat radiation opening 41 is preferably formed at the same time as the pad opening 31 so as not to increase the number of manufacturing steps.

  By providing the heat radiation opening 41 on the metal wiring layer M6 constituting the heat conducting portions 33 and 35, the heat radiation efficiency can be improved. Furthermore, for example, it is applied to a semiconductor integrated circuit device in which an external connection terminal such as a solder ball is provided on a pad electrode (metal wiring layer M6 in the pad opening 31) such as BGA (Ball Grid Array) and CSP (Chip Size Package). In this case, by providing an external connection terminal also on the metal wiring layer M6 in the heat radiation opening 41, the area where the heat conduction part including the external connection terminal comes into contact with the space outside the semiconductor integrated circuit device is increased. Therefore, the heat dissipation efficiency can be further improved.

  FIG. 4 is a sectional view showing still another embodiment of the semiconductor integrated circuit device. The same parts as those in FIGS. 1 and 3 are denoted by the same reference numerals, and description thereof will be omitted.

  In the region G where the fully depleted SOI transistor is formed, the contact layer 19, the metal wiring layer M 1, the via layer 21, the metal wiring layer M 2, the via layer 23, the metal wiring layer M 3, and the via layer on the source or drain region 9. 25, a heat conductive portion 43 including a metal wiring layer M4, a via layer 27, a metal wiring layer M5, a via layer 29, and a metal wiring layer M6 is provided. Thereby, the heat generated in the gate electrode 13 can be dissipated from the source or drain region 9 through the heat conducting portion 43.

  In the region H in the vicinity of the region G where the fully depleted SOI transistor is formed, the contact layer 19, the metal wiring layer M1, the via layer 21, the metal wiring layer M2, the via layer 23, and the metal wiring layer are formed on the element isolation film 15. A heat conducting portion 45 including M3, via layer 25, metal wiring layer M4, via layer 27, metal wiring layer M5, via layer 29, and metal wiring layer M6 is provided. Thereby, the heat generated in the gate electrode 13 can be dissipated from the element isolation film 15 via the heat conducting portion 45.

  Each metal wiring layer constituting the heat conducting portions 43 and 45 may be a dummy metal, or may be a dedicated metal wiring layer provided for forming the heat conducting portion. Further, it may be connected to the source or drain region 9 or the element isolation curtain 15 through a signal transmission connection hole and a metal wiring layer.

  In the above embodiment, an example in which a fully depleted SOI transistor is provided as a semiconductor element is shown. However, the present invention is not limited to this, and as the semiconductor element, for example, a partially depleted SOI transistor or an SON transistor can be used. The semiconductor integrated circuit device may include other semiconductor elements such as a conventional MOS transistor, a capacitor element, and a resistor element.

  5A and 5B show a standard cell of a standard cell type semiconductor integrated circuit device and its circuit diagram. FIG. 5A is a plan view of the standard cell constituting one embodiment, and FIG. FIG. 3C is a cross-sectional view, FIG. 3C is a plan view of a conventional standard cell, and FIG. Here, two inverter cells are used as standard cells (functional blocks). First, a conventional standard cell will be described with reference to (C) and (D).

  In the inverter cells A ′ and B ′, a source or drain region 9 is formed in an active region surrounded by an element isolation film 15 formed on a semiconductor substrate, and a gate is formed on the semiconductor substrate between the source or drain regions 9 and 9. A gate electrode 13 made of a polysilicon film is formed through an oxide film (not shown). In each of the inverter cells A ′ and B ′, the gate electrode 13 is common to the plurality of MOS transistors.

  A power supply line VDD and a ground line GND are formed by the lowermost metal wiring layer M1 formed on the semiconductor substrate via an insulating layer. A part of the power supply line VDD and the ground line GND is formed extending on the source or drain region 9 and connected to the source or drain region 9 through a contact layer (not shown).

  Further, an input line and an output line are also formed by the metal wiring layer M1. The input line IN1 of the inverter cell A ′ is connected to the gate electrode 13 of the inverter cell A ′ via a contact layer (not shown), and the output line OUT1 is different from that connected to the power supply line VDD or the ground line GND. The source or drain region 9 is connected via a contact layer (not shown). The input line IN2 of the inverter cell B ′ is connected to the gate electrode 13 of the inverter cell B ′ via a contact layer (not shown), and the output line OUT2 is different from that connected to the power supply line VDD or the ground line GND. The source or drain region 9 is connected via a contact layer (not shown). The output line OUT1 of the inverter cell A 'and the input line IN2 of the inverter cell B' are connected.

  Next, a standard cell constituting one embodiment will be described with reference to (A) and (B). The configuration of the inverter cell A is the same as that of the inverter cell A 'shown in (C). In addition to the configuration of the inverter cell B ′ shown in (C), the inverter cell B has via layers 21, 23, 25, 27, 29 and metal wiring layers M2, M3, M4, M5 connected to the input line IN2. , M6.

  In this way, by connecting the heat conduction part 51 to the input line IN2 connected to the gate electrode 13 of the inverter cell B that becomes a heat generation source, the heat radiation effect by the heat conduction part is obtained also in the standard type semiconductor integrated circuit device. be able to.

  In this embodiment, one heat conducting portion 51 is provided, but the present invention is not limited to this, and a plurality of heat conducting portions may be provided in one standard cell. Further, the heat conducting portion is not limited to the signal wiring connected to the gate electrode, but may be directly connected to the gate electrode, or may be directly connected to the source or drain region or a signal transmission connection hole and metal. It may be connected via a wiring layer, or may be directly connected to the element isolation film.

6A and 6B are diagrams showing an example of a feed cell arranged in an embodiment of a standard cell type semiconductor integrated circuit device, where FIG. 6A is a plan view and FIG. 6B is a cross-sectional view showing a heat conduction portion.
For example, the power supply line VDD, the ground line GND, and the signal wiring 53 including the lowermost metal wiring layer M1 are formed on the element isolation film 15 of the feed cell 57 corresponding to the minimum wiring grid. Further, a heat conduction portion 55 composed of via layers 21, 23, 25, 27, 29 and metal wiring layers M2, M3, M4, M5, M6 connected to the signal wiring 53 is provided.

FIG. 7 is a plan view showing an exemplary arrangement of the feed cells shown in FIG. Here, inverter cells A ′ and B ′ shown in FIG. 5C are used as standard cells.
A feed cell 57 is arranged between the inverter cell A ′ and the inverter cell B ′. The output line OUT1 of the inverter cell A ′ and the input line IN2 of the inverter cell B ′ are connected via the signal wiring 53 of the feed cell 57.

  The heat generated in the gate electrode 13 of the inverter cell B is conducted to the heat conducting portion 55 through the input line IN2 and the signal wiring 53 and is radiated from the upper surface side of the semiconductor integrated circuit device. As described above, by providing the feed cell 57 with the heat conducting portion constituting the semiconductor integrated circuit device of the present invention, the temperature rise of the semiconductor integrated circuit device can be reduced. Furthermore, by disposing the heat conduction part in the feed cell, the heat radiation effect by the heat conduction part can be obtained without changing the conventional standard cell.

  In the embodiment shown in FIG. 7, one feed cell 57 is provided between the inverter cell A ′ and the inverter cell B ′. For example, as shown in FIG. Any number of feed cells may be arranged between the standard cells, for example, two feed cells 57 may be arranged.

  Further, in the heat conduction portion arranged in the feed cell 57, as shown in FIG. 9, the area of the upper metal wiring layer, for example, the metal wiring layers M4 and M5 may be increased to improve the heat radiation efficiency. Good.

Further, the size of the feed cell 57 in which the heat conducting unit is arranged is not limited to the one corresponding to the minimum wiring grid, and may be an arbitrary grid width as shown in FIG.
In the above embodiment, the area of each metal wiring layer M2 to M6 in the feed cell 57 is arbitrary.

  In the embodiments described with reference to FIGS. 5 to 10, the semiconductor integrated circuit device of the present invention is applied to a standard cell type semiconductor integrated circuit device. However, the semiconductor integrated circuit device of the present invention is not limited to this. For example, a gate array type semiconductor integrated circuit device or the like is applied to a semiconductor integrated circuit device of a type in which a circuit including a plurality of semiconductor elements is divided into functional blocks for each function and a plurality of functional blocks are arranged, and a method for manufacturing the same. can do. Also, the semiconductor integrated circuit device of the present invention can be applied to devices other than a semiconductor integrated circuit device having a plurality of functional blocks.

FIG. 11 is a flowchart showing an embodiment of a manufacturing method of a standard cell type semiconductor integrated circuit device.
Based on information such as the standard cell library, net list, timing constraint, etc., the standard cell is arranged by determining where on the chip each standard cell is arranged (step S1).

  Divide the wiring area into rectangular areas (channels) that do not overlap each other, determine which channel the wiring path of each net (a set of terminals that should be connected to the same potential) passes, and perform schematic wiring. Every time, detailed wiring is performed to determine a detailed wiring path in the channel (step S2).

  Place the feed cell in the gap after the standard cell and wiring layout. In the ECO (Engineering Change Order) process for improving timing problems due to delays caused by the layout by changing the layout, etc., the semiconductor of the present invention according to the heat capacity of the gate electrode in the adjacent standard cell for the feed cell The present invention is changed to a feed cell (see, for example, FIG. 6, FIG. 9 and FIG. 10) provided with a heat conducting portion constituting an integrated circuit device. Further, according to the present invention, the standard cell is changed according to the heat capacity of the gate electrode in the standard cell. The semiconductor integrated circuit device is changed to a standard cell (see, for example, inverter B in FIG. 5A) provided with a heat conducting portion (step S3).

  After correcting the wiring (step S4), the capacity and resistance of the wiring between the cells are extracted using software, and a logic simulation including the extracted capacity and resistance is performed to increase the accuracy and verify back-up. A tasting process is performed (step S5).

  If there is a defect in the result of the back annotation (step S5), the process returns to the standard cell arrangement (step S1), the schematic wiring and the detailed wiring (step S2), or the wiring correction (step S4). If the result of the back annotation (step S5) is appropriate, the layout is completed.

  In this embodiment, the semiconductor integrated circuit device of the present invention provided with the heat conducting portion is manufactured by the manufacturing method of the standard cell type semiconductor integrated circuit device. However, the semiconductor integrated circuit device of the present invention is manufactured by the standard method. However, the semiconductor integrated circuit device of the present invention can be applied to a semiconductor integrated circuit device manufactured by another manufacturing method.

  Although the embodiments of the semiconductor integrated circuit device and the manufacturing method thereof according to the present invention have been described above, the present invention is not limited to these, and various modifications can be made within the scope of the present invention described in the claims. Is possible.

It is sectional drawing which shows one Example of a semiconductor integrated circuit device. The top view of the area | region in which a dummy metal is formed is shown, (A) shows the dummy metal which comprises a heat conduction part, (B) shows the dummy metal which does not comprise a heat conduction part. It is sectional drawing which shows the other Example of a semiconductor integrated circuit device. It is sectional drawing which shows other Example of a semiconductor integrated circuit device. The standard cell of a standard cell system semiconductor integrated circuit device and its circuit diagram are shown, (A) is a top view of the standard cell which constitutes an example, (B) is a sectional view showing the heat conduction part of (A), (C) is a plan view of a conventional standard cell, and (D) is a circuit diagram. It is a figure which shows an example of the feed cell provided with the heat conductive part, (A) is a top view, (B) is sectional drawing which shows a heat conductive part. It is a top view which shows the example of arrangement | positioning of the feed cell provided with the heat conductive part. It is a top view which shows the other example of arrangement | positioning of the feed cell provided with the heat conductive part. It is a figure which shows the other example of the feed cell provided with the heat conductive part, (A) is a top view, (B) is sectional drawing which shows a heat conductive part. It is a figure which shows the further another example of the feed cell provided with the heat conductive part, (A) is a top view, (B) is sectional drawing which shows a heat conductive part. 3 is a flowchart showing an embodiment of a manufacturing method of a standard cell type semiconductor integrated circuit device. It is sectional drawing which shows the conventional MOS transistor and the MOS transistor of SOI structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 3 Embedded insulating layer 5 Single crystal silicon layer 7 SOI substrate 9 Source or drain region 11 Gate oxide film 13 Gate electrode 15 Element isolation film 17 Insulating layer 19 Contact layer 21, 23, 25, 27, 29 Via layer 31 Pad Opening 33, 35, 37 Thermal conduction part M1, M2, M3, M4, M5, M6 Metal wiring layer

Claims (1)

A plurality of semiconductor elements formed on a support substrate made of a semiconductor substrate or an SOI substrate, and a multilayer wiring structure formed in an insulating film on the support substrate, and a circuit including a plurality of semiconductor elements divided into blocks for each function In the semiconductor integrated circuit device in which the functional blocks are arranged,
Including areas where feed cells that fill gaps between functional blocks are located,
The feed cell is made of the same conductive material as the signal wiring that connects between the functional blocks arranged on both sides of the feed cell, and the connection holes and metal wiring layers that are connected to the signal wiring and form the multilayer wiring structure of the functional block. A heat conduction portion extending to the upper layer side through a path different from the connection hole for signal transmission of the functional block and the metal wiring layer ,
2. The semiconductor integrated circuit device according to claim 1, wherein the heat conducting portion has a multilayer structure, and an area of the upper wiring layer is larger than an area of the lower wiring layer in the multilayer wiring layer .

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