JP4672641B2 - Error correction processing apparatus and error correction processing method - Google Patents

Description

  The present invention relates to an improvement in an error correction processing apparatus and an error correction processing method for performing an encoding process for error correction on an information bit string.

  As is well known, for example, when an information bit string is recorded / reproduced on / from an information recording medium such as a hard disk or an optical disc, the information bit string is recorded by performing an error correction encoding process at the time of recording, and at the time of reproduction, the information recording medium is recorded. The information bit string read from is subjected to error correction processing based on the error correction code to restore the original information bit string.

  By the way, a low density parity check (LDPC) code is currently widely used for encoding processing for error correction performed on an information bit string to be recorded. This LDPC code is obtained by multiplying the information bit string u by the generator matrix G, and normally, c which is multiplied by the check matrix H and becomes 0 is defined as a code word.

  That is, when the multiplication result is 0, it can be considered that each row of the parity check matrix H constitutes an even parity equation. Since the code word c satisfying such even parity (hereinafter referred to as even parity LDPC code) is a linear code and is easy to handle, various methods for high-speed coding have been developed. ing.

  On the other hand, in the LDPC code, a code word c that is multiplied by the check matrix H and becomes 1 can be defined. In this case, each row of the parity check matrix H constitutes an odd parity equation. However, since the code word c satisfying such odd parity (hereinafter referred to as an odd parity LDPC code) is a non-linear code, it is inconvenient to handle compared to the even parity LDPC code. Is currently not actively conducted.

  Patent Document 1 discloses a check bit calculation unit that obtains a check bit string by a calculation using an LDPC code generation matrix, and a code assignment unit that assigns a conversion code including one inverted bit in three bits to each check bit It is disclosed that each conversion code is inserted into an information word string and output.

Further, Patent Document 2 forms an auxiliary set of three different bits representing the total parity of an N-bit set corresponding to a column of the input general-purpose parity check matrix, and modulo bit 2 of the auxiliary set S. When the sum is Xs, Xs = 0 describes that the sum of the bits of the set S is an even number, and Xs = 1 indicates that the parity of the set S is an odd number.
JP-A-2005-078687 JP 2004-274709 A

  Therefore, the present invention has been made in consideration of the above circumstances, and various kinds of high-speed encoding algorithms developed for encoding even parity LDPC codes are applied to encode information bit strings into odd parity LDPC codes. It is an object of the present invention to provide an error correction processing apparatus and an error correction processing method that can perform the conversion processing quickly and easily with a simple configuration.

  The error correction processing apparatus according to the present invention is intended for performing an error correction encoding process using an LDPC code on an information bit string. An encoding that performs an exclusive OR operation on one codeword that satisfies the odd parity that is multiplied by the check matrix and becomes “1” and the codeword that multiplies the check matrix and satisfies the even parity that becomes “0” Means are provided.

  The error correction processing method according to the present invention is directed to a method of performing an error correction encoding process using an LDPC code on an information bit string. Then, an exclusive OR operation is performed on one codeword that satisfies the odd parity that is “1” when multiplied by the parity check matrix and a codeword that satisfies the even parity that is “0” when multiplied by the parity check matrix. It is a thing.

  According to the above-described invention, one codeword that satisfies the odd parity that is multiplied by the check matrix and becomes “1” and the codeword that satisfies the even parity that is multiplied by the check matrix and becomes “0” are exclusive logic. Since the sum operation is performed, various high-speed encoding algorithms developed for encoding even parity LDPC codes can be applied to quickly encode information bit strings into odd parity LDPC codes with a simple configuration. And it becomes possible to carry out easily.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 schematically shows an HDD (hard disk drive) 11 which is an information recording / reproducing apparatus described in this embodiment. That is, the HDD 11 includes a host I / F (interface) 13 for exchanging information with the external host device 12.

  Here, the host device 12 is, for example, a PC (personal computer) or the like. For example, when executing predetermined application software, the host device 12 uses the HDD 11 to write and read information, and also uses the HDD 11 as a storage destination of finally obtained information. Can do.

  In this case, the host device 12 generates a command requesting the HDD 11 to write information or read information. These commands are supplied to the main control unit 14 via the host I / F 13 and analyzed. The main control unit 14 incorporates a CPU (central processing unit) and controls various operations executed by the HDD 11 in an integrated manner.

  For example, when a write request command is supplied from the host device 12, the write request command is supplied to the main control unit 14 through the host I / F 13 and analyzed. As a result, the main control unit 14 drives the modulation processing unit 15 and the encoding processing unit 16 and controls the hard disk 18 to the writing state via the disk I / F 17.

  The information bit string to be written is supplied to the modulation processing unit 15 via the host I / F 13. The modulation processing unit 15 performs compression modulation processing (for example, zero does not continue for a certain length or longer) in response to a request of the recording / reproducing system in the HDD 11, such as run length modulation processing, for the input information bit string. Modulation processing).

  The information bit string subjected to the modulation process by the modulation processing unit 15 is supplied to the encoding processing unit 16. As will be described in detail later, the encoding processing unit 16 performs an encoding process for error correction using an LDPC code on the input information bit string. In this case, the encoding processing unit 16 operates to encode the odd parity LDPC code.

  Then, the information bit string that has been subjected to the encoding process for error correction by the encoding processing unit 16 is written to the hard disk 18 via the disk I / F 17, and here, based on the write request from the host device 12, An information bit string writing process to the hard disk 18 is executed.

  Further, when a read request command is supplied from the host device 12, the read request command is supplied to the main control unit 14 via the host I / F 13 and analyzed. For this reason, the main control unit 14 drives the decoding processing unit 19 and the demodulation processing unit 20 and controls the hard disk 18 to a read state via the disk I / F 17.

  The information bit string that has been read from the hard disk 18 and has been subjected to the encoding process for error correction is supplied to the decoding processing unit 19 via the disk I / F 17. The decoding processing unit 19 performs error correction processing corresponding to the odd parity LDPC code on the input information bit string.

  The information bit string that has been subjected to the error correction processing by the decoding processing unit 19 is supplied to the demodulation processing unit 20. The demodulation processing unit 20 performs demodulation processing on compression modulation such as run length modulation processing applied to the input information bit sequence, and restores the original information bit sequence.

  The information bit string demodulated by the demodulation processing unit 20 is output to the host device 12 via the host I / F 13, and here, the information bit string from the hard disk 18 based on the read request from the host device 12 is output. An information bit string read process is executed.

Here, the LDPC encoding process in the encoding processing unit 16 will be described. That is, the encoding by the LDPC code is to generate the code word c by multiplying the information bit string u by the generator matrix G,

It is expressed as

In general, the codeword c is multiplied by the check matrix H to be 0, that is,

It is defined as That is, when the multiplication result is 0, it is considered that each row of the check matrix H constitutes an even parity equation. Since the code word c (even parity LDPC code) satisfying such even parity is a linear code, it is easy to handle, and various methods have been developed for realizing the high-speed encoding process.

On the other hand, in the LDPC code, the code word c multiplied by the check matrix H to be 1, that is,

Can also be defined. In this case, each row of the parity check matrix H constitutes an odd parity equation. By the way, since the code word c (odd parity LDPC code) satisfying such odd parity is a non-linear code, the encoding process is more difficult than the even parity LDPC code.

Therefore, in this embodiment, encoding of odd parity LDPC codes is realized as follows. First,

Find a codeword c ₁ that satisfies.

Also, the above equation (3) is

It can be deformed as follows.

In the above equation (5), the codeword c and c ₁ are both codewords satisfying odd parity, their difference c-c ₁ is the codeword c which satisfies the even parity shown in the above (2) Means that it matches.

For this reason, in the coding formula of the LDPC code shown in the above equation (1), if the code word c satisfies even parity, the code word c includes code words c and c ₁ satisfying odd parity. It can be expressed as the difference c−c ₁ .

In other words, a codeword c which satisfies the even parity c (even) when a codeword c and c ₁ satisfy the odd parity respectively and expressed as c (odd) and c _{1 (odd),} the generating the even parity LDPC code Equation (1) is

And transformed,

It is expressed as

Thus, the codeword c of even parity LDPC codes, adds one codeword c ₁ of the known odd parity LDPC code, i.e., by a very simple method of XORing readily odd parity It can be seen that the code word c of the LDPC code can be obtained.

  In the above method, since the code word c of the normal even parity LDPC code is generated, it becomes possible to directly apply various high-speed encoding algorithms developed for encoding the even parity LDPC code. The degree of freedom of handling for the user can be greatly increased.

  FIG. 2 shows a configuration of the encoding processing unit 16 for realizing the LDPC encoding process described above. That is, the information bit string output from the modulation processing unit 15 is supplied to the odd parity encoding processing unit 22 and the even parity encoding processing unit 23 via the input terminal 21.

Among these, the odd parity encoding processing unit 22 performs LDPC encoding processing using odd parity on the input information bit string, and finds and acquires a codeword c1 of _one odd parity LDPC code. It is.

  The even parity encoding processing unit 23 performs LDPC encoding processing using even parity on the input information bit string to generate a code word c (= u · G) of the even parity LDPC code. Yes.

The odd parity LDPC found by the odd parity encoding processing unit 22 by the adding unit 24 is added to the code word c (= u · G) of the even parity LDPC code generated by the even parity encoding processing unit 23. The code word c ₁ of the code is subjected to an exclusive OR operation to generate a code word c of an odd parity LDPC code, which is output to the disk I / F 17 via the output terminal 25.

FIG. 3 shows a flowchart summarizing the LDPC encoding processing operation in the encoding processing unit 16 described above. That is, when the processing is started (step S1), the encoding processing unit 16 causes the odd parity encoding processing unit 22 to find the code word c1 of _one odd parity LDPC code in step S2.

In step S3, the encoding processing unit 16 causes the even parity encoding processing unit 23 to generate the code word c of the even parity LDPC code from the input information bit string, and then in step S4, the adding unit 24 exclusively by ORing a codeword _{c 1} odd parity LDPC code codeword c of even parity LDPC code, the processing is terminated (step S5).

Here, a description will be given of how to find the code word c ₁ that satisfies the above expression (3). The code word c ₁ can be found by, for example, converting the parity check matrix H into a lower triangular matrix using the Gaussian elimination method and then specifying parity bits so as to satisfy odd parity in order from the bottom row. it can.

  If this finding method is adopted, it is possible to encode an arbitrary information bit string into an odd parity LDPC code, but it takes a lot of time to sequentially obtain the parity bits.

On the other hand, in the method of obtaining the code word c of the odd parity LDPC code by performing an exclusive OR operation on the code word c ₁ of the odd parity LDPC code to the code word c of the even parity LDPC code, the normal even parity LDPC is obtained. Since the code word c of the code is generated, various high-speed encoding algorithms developed for encoding the even parity LDPC code can be applied as they are, and the encoding process can be speeded up.

Further, if the code word c ₁ satisfying the above equation (3) is obtained by performing odd parity coding on an all-zero information bit string, a portion for performing an exclusive OR operation is generated only in the parity part. And the number of arithmetic elements for performing an exclusive OR operation can be reduced.

  The odd parity LDPC code obtained by the method described in the above embodiment basically has an error correction capability equivalent to that of a normal even parity LDPC code, and each bit constituting the parity equation has the same error correction capability. Of these, since it is guaranteed that “1” is set in at least one of them, the combination with a run length limit code or the like can be easily performed.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by variously modifying the constituent elements without departing from the scope of the invention in the implementation stage. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements according to different embodiments may be appropriately combined.

1 is a block diagram illustrating an outline of an HDD according to an embodiment of the present invention. The block block diagram shown in order to demonstrate an example of the encoding process part incorporated in HDD in the embodiment. The flowchart shown in order to demonstrate an example of the processing operation of the encoding process part in the embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... HDD, 12 ... Host apparatus, 13 ... Host I / F, 14 ... Main control part, 15 ... Modulation process part, 16 ... Encoding process part, 17 ... Disk I / F, 18 ... Hard disk, 19 ... Decoding Processing unit, 20 ... Demodulation processing unit, 21 ... Input terminal, 22 ... Odd parity coding processing unit, 23 ... Even parity coding processing unit, 24 ... Addition unit, 25 ... Output terminal.

Claims (7)

An error correction processing device that performs an error correction coding process using an LDPC code on an information bit string,
Coding means for performing an exclusive OR operation on one codeword that satisfies an odd parity that is "1" when multiplied by a parity check matrix and a codeword that satisfies an even parity that is "0" when multiplied by the parity check matrix An error correction processing apparatus comprising: The encoding means includes
Obtaining means for obtaining one codeword satisfying an odd parity which is multiplied by the check matrix and becomes “1”;
Generating means for generating a codeword satisfying an even parity of “0” by multiplying with the check matrix;
The error correction processing apparatus according to claim 1, further comprising: an adding unit that performs an exclusive OR operation on the codeword acquired by the acquiring unit and the codeword generated by the generating unit.   The acquisition unit obtains one codeword satisfying an odd parity of "1" by multiplying the parity check matrix by performing odd parity encoding on the information bit string of all zeros. The error correction processing apparatus described. An information recording apparatus that performs encoding processing for error correction using an LDPC code on an input information bit string and records the information on an information recording medium,
Coding means for performing an exclusive OR operation on one codeword that satisfies an odd parity that is "1" when multiplied by a parity check matrix and a codeword that satisfies an even parity that is "0" when multiplied by the parity check matrix When,
An information recording apparatus comprising: a recording unit that records the information bit string encoded by the encoding unit on the information recording medium. An error correction processing method for performing an error correction encoding process using an LDPC code on an information bit string,
An exclusive OR operation is performed on one codeword that satisfies an odd parity that is "1" when multiplied by a parity check matrix and a codeword that satisfies an even parity that is "0" when multiplied by the parity check matrix. An error correction processing method. A first step of obtaining one codeword satisfying an odd parity of “1” by multiplication with the parity check matrix;
A second step of generating a codeword satisfying an even parity of "0" by multiplying with the parity check matrix;
6. The error according to claim 5, further comprising a third step of performing an exclusive OR operation on the codeword acquired in the first step and the codeword generated in the second step. Correction processing method.   The first step is to obtain one codeword satisfying an odd parity of “1” by multiplying the parity check matrix by performing odd parity coding on the information bit string of all zeros. Item 7. The error correction processing method according to Item 6.

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