JP4666464B2 - Differential input circuit, receiver circuit, transmitter / receiver - Google Patents

Description

  The present invention relates to a differential input circuit that amplifies a differential input signal with a predetermined gain, a receiving circuit using the same, and a transmission / reception device.

  2. Description of the Related Art Conventionally, a transmission / reception apparatus (such as a mobile phone) that performs bidirectional signal transmission using a time division multiplexing method is known. Time division multiplexing is a method of dividing the data transmission path into frames at fixed time intervals, further dividing the frames into time slots at fixed time intervals, and assigning data to be transmitted / received to each time slot. Is a communication method for performing bidirectional transmission (see FIG. 2).

Note that the receiving circuit of the transmitting / receiving apparatus is generally configured to include an offset canceller in order to remove an offset component included in the received signal (see, for example, Patent Documents 1 and 2).
Japanese Patent Laid-Open No. 10-308684 JP 2004-201187 A

  Certainly, if it is a conventional receiving circuit equipped with an offset canceller as described in the above document, the offset component can be removed from the received signal, so that reception state fluctuations, secular changes, circuit component element characteristic variations, etc. The reception accuracy can be improved without depending on the above.

  In view of the same problems as in the above document, the present invention provides a differential input circuit for obtaining a similar effect with a simple configuration, a receiving circuit capable of removing its own internal offset, and uses these. It is an object to provide a transmission / reception apparatus.

  In order to achieve the above object, a differential input circuit according to the present invention amplifies a differential input signal input to each of a non-inverting input terminal and an inverting input terminal with a predetermined gain, and sends the differential input signal from an output terminal. An amplifier, a first resistor provided in the signal input path to the non-inverting input terminal, a second resistor provided in the signal input path to the inverting input terminal, and the non-inverting input terminal are pulled up to a predetermined potential. A third resistor provided in a pull-up path; a fourth resistor provided in a negative feedback loop from the output terminal to the inverting input terminal; and a first switch for opening and closing a signal input path to the non-inverting input terminal A circuit and a second switch circuit that opens and closes a signal input path to the inverting input terminal may be used. With such a configuration, it is possible to permit / shut off the input signal and check the offset of the differential input circuit.

  The differential input circuit having the above configuration includes at least one switch circuit having the same circuit configuration as the first switch circuit, and is a third switch circuit provided in the pull-up path in a normally closed state. And including at least one switch circuit having the same circuit configuration as the second switch circuit, and a fourth switch circuit provided in the negative feedback loop in a normally closed state. Good. By adopting such a configuration, it becomes possible to permit / cut off the input signal without causing a gain fluctuation at the time of permitting the input.

  In the differential input circuit configured as described above, the first switch circuit and the third switch circuit, and the second switch circuit and the fourth switch circuit may be formed in the same manufacturing process. . By adopting such a configuration, the gain of the differential amplifier can be adjusted with high accuracy without depending on the characteristic variation of the circuit elements (that is, the on-resistance variation of each switch circuit) due to the difference in the manufacturing process. It becomes possible.

  In the differential input circuit configured as described above, each of the third and fourth switch circuits is formed by connecting a plurality of switch circuits having the same circuit configuration as the first and second switch circuits in series or in parallel. It is good to have a configuration. With such a configuration, it is possible to arbitrarily adjust the gain of the differential amplifier while offsetting the above-described variation in on-resistance for each switch circuit.

  In addition, the differential input circuit having any one of the above configurations may be configured to include a fifth switch circuit that short-circuits the negative feedback loop when the first and second switch circuits are open. By adopting such a configuration, it becomes possible to permit / block the input signal without causing improper oscillation when the input is blocked.

  The receiving circuit according to the present invention includes a differential input circuit that amplifies a differentially input analog baseband signal with a predetermined gain, and an analog / digital converter that converts the amplified analog baseband signal into a digital baseband signal. A reception circuit having a conversion unit and an offset canceller that removes an offset component included in the digital baseband signal, wherein the differential input circuit has a differential input circuit having any one of the above configurations. Good. By adopting such a configuration, it is possible to permit / shut off the input signal and remove its own internal offset without causing gain fluctuations at the time of permitting input or improper oscillation at the time of shutting down the input.

  A receiving circuit according to the present invention includes a transmitting / receiving antenna and a transmitting circuit and a receiving circuit in which a signal transmitting path and a signal receiving path for the transmitting / receiving antenna are short-circuited to each other, using a time division multiplexing method. A transmission / reception apparatus that performs bidirectional transmission of a signal, wherein the reception circuit has a reception circuit having the above-described configuration, and the first and second switch circuits are closed in the reception slot. In the transmission slot, the first and second switch circuits are opened, and the offset canceller is configured to function in the transmission slot. With such a configuration, it is possible to remove the internal offset component of the receiving circuit in the transmission slot and improve the reception accuracy.

  As described above, according to the present invention, the offset of the differential input circuit can be confirmed with a simple configuration, and it is possible to prevent gain fluctuation at the time of input permission and unauthorized oscillation at the time of input cutoff. It is possible to provide a differential input circuit, a receiving circuit capable of removing its own internal offset, and a transmission / reception device using these.

  In the following, a detailed description will be given by taking as an example the case where the present invention is applied to a mobile phone that performs bidirectional signal transmission using the time division multiplexing method.

  FIG. 1 is a block diagram showing the periphery of a transmission / reception unit of a mobile phone according to the present invention. As shown in the figure, the mobile phone according to the present invention comprises a transmission / reception antenna 1, an analog signal processing unit 2, and a digital signal processing unit 3 around the transmission / reception unit. It is a transmission / reception apparatus that performs bidirectional transmission of signals. As described above, the time-division multiplexing method divides the data transmission path into frames at fixed time intervals, and further divides the frames into time slots at fixed time intervals to transmit / receive data to / from each time slot. By assigning, it is a communication system that performs bidirectional transmission between devices (see FIG. 2).

  The analog signal processing unit 2 includes a transmission circuit 21 and a reception circuit 22 in which a signal transmission path and a signal reception path for the transmission / reception antenna 1 are short-circuited with each other. Hereinafter, the internal configuration and operation of the receiving circuit 22 will be described in detail with reference to FIGS. 3 and 4.

  FIG. 3 is a circuit diagram showing an embodiment of the receiving circuit 22. As shown in the figure, the receiving circuit 22 of the present embodiment is a differential input circuit that amplifies an analog baseband signal that is differentially input from the transmitting / receiving antenna 1 via a high-frequency signal processing unit (not shown) with a predetermined gain. 221; an analog / digital converter 222 (hereinafter referred to as A / D converter 222) that converts the amplified analog baseband signal into a digital baseband signal and sends it to the digital signal processor 3; And an offset canceller 223 that removes an offset component included in the signal. The offset canceller 223 includes a differential amplifier 223a that functions as an offset correction unit, a correction value calculation unit 223b, and a digital / analog conversion unit 223c (hereinafter referred to as a D / A conversion unit 223c). Become.

  The A / D converter 222 samples and holds the analog baseband signal output from the differential amplifier 223a, and converts the analog baseband signal into a digital baseband signal having a predetermined number of bits (for example, 10 bits).

  In the offset canceller 223, the correction value calculation unit 223b averages a predetermined number of digital baseband signals, compares them with a predetermined reference value, and calculates an offset correction value so as to eliminate the error between the two. The D / A converter 223c converts the offset correction value into an analog signal to obtain an offset correction value signal, and sends the offset correction value signal to the non-inverting input terminal of the differential amplifier 223a. The differential amplifier 223a has an input signal to the non-inverting input terminal (offset correction value signal input from the D / A converter 223c) and an input signal to the inverting input terminal (uncorrected input from the differential input circuit 221). (Analog baseband signal) is obtained, and the difference signal is sent to the A / D converter 222 as a corrected analog baseband signal. By such an offset cancel operation, it is possible to improve the reception accuracy irrespective of reception state variation, secular change, characteristic variation of circuit components, and the like.

  The differential input circuit 221 which is a characteristic part of the present invention includes a differential amplifier AMP, first to fourth resistors R1 to R4, first to fifth switch circuits S1 to S5, as shown in FIG. And an inverter INV. The non-inverting input terminal (+) of the differential amplifier AMP is connected to one end of the first resistor R1 and one end of the third switch circuit S3, and the inverting input terminal (−) is one end of the second resistor R2. The four resistors R4 and one end of the fifth switch circuit S5 are connected to one end of the four resistors R4. The other ends of the first and second resistors R1 and R2 are connected to one ends of the first and second switch circuits S1 and S2, respectively. The other ends of the first and second switch circuits S1 and S2 correspond to the differential input terminals of the differential input circuit 221, respectively. The other end of the third switch circuit S3 is connected to the power supply line via the third resistor R3. The other end of the fourth resistor R4 is connected to one end of the fourth switch circuit S4. The other ends of the fourth and fifth switch circuits S4 and S5 are both connected to the output terminal of the differential amplifier AMP.

  As described above, the differential input circuit 221 of the present embodiment amplifies the differential input signals respectively input to the non-inverting input terminal (+) and the inverting input terminal (−) with a predetermined gain, and outputs from the output terminal. A differential amplifier AMP for sending, a first resistor R1 provided in the signal input path to the non-inverting input terminal (+), and a second resistor R2 provided in the signal input path to the inverting input terminal (−) , A third resistor R3 provided in a pull-up path for raising the non-inverting input terminal (+) to a predetermined potential, and a first feedback loop provided in the negative feedback loop from the output terminal of the differential amplifier AMP to the inverting input terminal (−). 4 resistors R4, a first switch circuit S1 that opens and closes a signal input path to the non-inverting input terminal (+), and a second switch circuit S2 that opens and closes a signal input path to the inverting input terminal (-). It is set as the structure which consists of. With such a configuration, the input signal can be permitted / cut off and the offset of the differential input circuit 221 can be confirmed.

  A switch switching signal is directly input to the control terminals of the first and second switch circuits S1 and S2, and both switch circuits S1 and S2 are controlled to open and close in accordance with the switch switching signal. On the other hand, the switch switching signal is logically inverted by the inverter INV and input to the control terminal of the fifth switch circuit S5, and the fifth switch circuit S5 performs open / close control according to the inverting switch switching signal. Is done. That is, in the differential input circuit 221 of the present embodiment, when the first and second switch circuits S1 and S2 are closed, the fifth switch circuit S5 is opened, and conversely, the first and second switch circuits When S1 and S2 are in the open state, the fifth switch circuit S5 is closed.

  As described above, the differential input circuit 221 of the present embodiment includes the fifth switch circuit S5 that short-circuits the negative feedback loop of the differential amplifier AMP when the first and second switch circuits S1 and S2 are open. It is set as the structure which has. With such a configuration, the differential amplifier AMP functions as a buffer amplifier when the first and second switch circuits S1 and S2 are opened. Therefore, in the differential input circuit 221 of the present embodiment, it is possible to permit / block the input signal without causing improper oscillation when the input is blocked.

  The mobile phone of the present embodiment performs normal reception operation after the first and second switches S1 and S2 are closed in the reception slot, while the first and second switches are in the transmission slot. The switch switch signal is generated so that the offset canceller 223 functions after the two switches S1 and S2 are opened. With such a configuration, it is possible to remove the internal offset component of the reception circuit 22 in the transmission slot and improve the reception accuracy.

  On the other hand, the third and fourth switch circuits S3 and S4 are connected to the first and second switch circuits when the first and second switch circuits S1 and S2 are closed to receive an analog baseband signal input from the previous stage. This is a dummy switch circuit installed so that the gain of the differential amplifier AMP is different from the desired value due to the ON resistance values of S1 and S2. More specifically, the third switch circuit S3 includes at least one switch circuit having the same circuit configuration as the first switch circuit S1, and is provided in the pull-up path in a normally closed state. Similarly, the fourth switch circuit S4 includes at least one switch circuit having the same circuit configuration as the second switch circuit S2, and is provided in the negative feedback loop in a normally closed state.

  As described above, the differential input circuit 221 according to the present embodiment includes a gain adjustment unit for the differential amplifier AMP when the first and second switch circuits S1 and S2 are closed (that is, when the input of the analog baseband signal is permitted). As shown in the figure, dummy third and fourth switch circuits S3 and S4 are provided. By adopting such a configuration, the differential amplifier AMP when the first and second switch circuits S1 and S2 are closed can be obtained by providing the third and fourth switch circuits S3 and S4 with appropriate on-resistance values. Can be adjusted to a desired value. Therefore, in the differential input circuit 221 of the present embodiment, it is possible to permit / cut off the input signal without causing a gain fluctuation at the time of permitting the input.

  In the differential input circuit 221 of this embodiment, the first switch circuit S1 and the third switch circuit S3, and the second switch circuit S2 and the fourth switch circuit S4 are formed by the same manufacturing process. . By adopting such a configuration, the gain of the differential amplifier AMP can be adjusted with high accuracy without depending on the characteristic variation of the circuit elements due to the difference in the manufacturing process (that is, on-resistance variation of each switch circuit). Is possible.

  For the above-described dummy third and fourth switch circuits S3 and S4, a plurality of switch circuits having the same circuit configuration as the first and second switch circuits S1 and S2 are connected in series or in parallel. It is good to have a configuration of With such a configuration, it is possible to arbitrarily adjust the gain of the differential amplifier AMP while offsetting the above-described variation in on-resistance for each switch circuit.

  For example, when the gain of the differential amplifier AMP is ½ (−6 [dB]) when the first and second switch circuits S1 and S2 are closed (when input is permitted), as shown in FIG. In addition, the resistance values of the third and fourth resistors R3 and R4 are set to 1/2 with respect to the first and second resistors R1 and R2, respectively, and the third switch circuit S3 is connected to the first switch circuit S1. The switch circuits S31 and S32 having the same circuit configuration are connected in parallel, and the fourth switch circuit S4 is connected in parallel with the switch circuits S41 and S42 having the same circuit configuration as the second switch circuit S2. It is good to have a configuration consisting of

  With this configuration, the gain G of the differential amplifier AMP can be adjusted to a desired value of 1/2 (−6 [dB]) based on the following equation (1). In the following equation (1), r1 to r4 are parameters representing the resistance values of the first to fourth resistors R1 to R4, and rs1 to rs4 are the parameters of the first to fourth switch circuits S1 to S4. It is a parameter representing each on-resistance value.

  Further, as shown in the above example, when the gain of the differential amplifier AMP is set to 0 [dB] or less, the first and second switch circuits S1 and S2 have first and second resistors R1 as shown in FIG. , R2 may be inserted near the input end of the differential amplifier AMP. With this configuration, even if each resistor generates noise, the noise can be attenuated.

  In the above embodiment, the case where the present invention is applied to a mobile phone that performs bidirectional signal transmission using the time division multiplexing method has been described as an example. However, the scope of application of the present invention is not limited thereto. The present invention is not limited, and can be widely applied to differential input circuits in general, including transmission / reception devices other than cellular phones and reception circuits mounted thereon. For example, the configuration as shown in FIGS. 5A to 5C may be used as long as gain variation and oscillation margin are not a concern. However, in order to confirm the offset in the configuration of FIG. 5A, each input must be pulled out.

  The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the spirit of the invention.

  The present invention is a technique useful for improving reception accuracy of, for example, a mobile phone.

These are the block diagrams which show the transmission-and-reception part periphery of the mobile telephone which concerns on this invention. These are the conceptual diagrams for demonstrating the time division multiplex communication operation | movement of a mobile telephone. FIG. 3 is a circuit diagram showing an embodiment of a receiving circuit 22. FIG. 3 is a circuit diagram showing a specific example of the receiving circuit 22. FIG. 6 is a circuit diagram showing another configuration example of the receiving circuit 22.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Transmission / reception antenna 2 Analog signal processing part 3 Digital signal processing part 21 Transmission circuit 22 Reception circuit 221 Differential input circuit 222 Analog / digital conversion part 223 Offset canceller 223a Offset correction part (differential amplifier)
223b Correction value calculation unit 223c Digital / analog conversion unit R1 to R4 First to fourth resistors S1 and S2 First and second switch circuits (for input cutoff)
S3 (S31, S32) Third switch circuit (dummy switch)
S4 (S41, S42) Fourth switch circuit (dummy switch)
S5 Fifth switch circuit (for negative feedback loop short)
AMP differential amplifier INV inverter

Claims (7)

A differential amplifier that amplifies the differential input signals respectively input to the non-inverting input terminal and the inverting input terminal with a predetermined gain and sends them out from the output terminal, and a signal input path to the non-inverting input terminal. 1 resistor, a second resistor provided in a signal input path to the inverting input terminal, a third resistor provided in a pull-up path for pulling up the non-inverting input terminal to a predetermined potential, and the inversion from the output terminal A fourth resistor provided in a negative feedback loop to the input terminal, a first switch circuit for opening and closing a signal input path to the non-inverting input terminal, and a second switch for opening and closing a signal input path to the inverting input terminal A differential input circuit comprising: a circuit; and a third switch circuit for short-circuiting the negative feedback loop when the first and second switch circuits are open . It includes at least one switching circuit of the same circuit configuration as the first switch circuit, a fourth switch circuit and provided on the pull-up path in a state of being constantly閉結; the same circuit configuration as the second switch circuit The differential input circuit according to claim 1, further comprising: a fifth switch circuit provided in the negative feedback loop in a normally closed state including at least one switch circuit. . 3. The differential input circuit according to claim 2, wherein the first switch circuit and the fourth switch circuit, and the second switch circuit and the fifth switch circuit are formed by the same manufacturing process. 4. The difference according to claim 3, wherein each of the fourth and fifth switch circuits is formed by connecting a plurality of switch circuits each having the same circuit configuration as the first and second switch circuits in series or in parallel. Dynamic input circuit.   A differential input circuit for amplifying a differentially input analog baseband signal with a predetermined gain, an analog / digital converter for converting the amplified analog baseband signal into a digital baseband signal, and the digital baseband signal A reception circuit having an offset canceller that removes an offset component contained therein, wherein the differential input circuit includes the differential input circuit according to any one of claims 1 to 4. circuit.   A transmission / reception apparatus that includes a transmission / reception antenna and a transmission circuit and a reception circuit in which a signal transmission path and a signal reception path for the transmission / reception antenna are short-circuited to each other, and performs bidirectional transmission of signals using a time division multiplexing method. The receiving circuit includes the receiving circuit according to claim 5, and the first and second switch circuits are closed in the receiving slot, and a normal receiving operation is performed. On the other hand, in the transmission slot, the first and second switch circuits are opened and the offset canceller is caused to function.   The offset canceller is
  A correction value computing unit that averages the digital baseband signal for a predetermined number of times and compares the averaged baseband signal with a predetermined reference value, and calculates an offset correction value so as to eliminate the error between the two,
  A D / A converter that analog-converts the offset correction value and outputs the offset correction value signal;
  A second differential amplifier that receives the offset correction value signal at a non-inverting input terminal, receives an output of the first differential amplifier at an inverting input terminal, and outputs the output to the analog / digital converter;
  The transmission / reception apparatus according to claim 6, further comprising:

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