JP4659892B2 - Design rule verification program, recording medium recording the program, and design rule verification device - Google Patents

Description

  The present disclosure relates to a design rule verification program that verifies whether layout data of a semiconductor circuit violates a design rule, a recording medium that records the program, and a design rule verification device.

  In LSI design, work efficiency has been conventionally demanded by shortening the design period. On the other hand, verification work for verifying whether an LSI operates correctly is indispensable. This verification work is important for maintaining high quality for LSIs that are required to be reduced in power consumption and power consumption.

  In a normal layout design, since a grid-based wiring method is performed, the coordinates of representative points of wirings and vias are located on a finite number of lattice points called wiring grids. There are only a few types of wiring and via shapes. Conventionally, layout design rules have been verified by examining the distance between graphic data of objects having representative points (see, for example, Patent Documents 1 and 2 below). At present, the design rules have become complicated, so that the layout design rules described above are not verified, and are performed by graphic operations using graphic data of rectangular or polygonal objects.

JP 63-56443 A JP-A-6-230067

  However, with the above-described conventional technology, with the increase in LSI design scale, the above-described graphic calculation has a problem that it takes time to verify the layout design rule, and the verification work takes a long time. In particular, the more complicated the design rules, the longer the verification work.

  The disclosed technology eliminates the problems caused by the above-described conventional technology, and thus a design rule verification apparatus, a design rule verification method, and a design rule verification that can efficiently shorten the verification period even when the design rules become complicated It is an object to provide a program and a recording medium.

  In order to solve the above-described problems and achieve the object, a design rule verification program according to the present disclosure, a recording medium on which the program is recorded, and a design rule verification apparatus use a polygon or a vertex in a predetermined coordinate system. Using the object format data representing an object in a semiconductor circuit and a representative point on a grid point of a grid coordinate system having a grid larger than the predetermined coordinate system or a line segment between the representative point and the representative point Among the represented representative format data, layout data including at least the representative format data is acquired, and among the representative format data in the acquired layout data, one representative format data includes the other representative format data. Whether or not the layout data violates the design rule by whether or not it is arranged in the grid group of the grid coordinate system, And requirements to output the testimony result.

  According to the design rule verification program, the recording medium on which the program is recorded, and the design rule verification device according to the present disclosure, the verification period can be efficiently shortened even if the design rule becomes complicated. Play.

It is a block diagram which shows the hardware constitutions of the design rule verification apparatus concerning embodiment. It is explanatory drawing which shows the content of the layout data regarding the semiconductor circuit concerning embodiment. It is a block diagram which shows the functional structure of the design rule verification apparatus concerning embodiment. It is a block diagram which shows a part of functional structure of the design rule verification apparatus of Example 1 concerning embodiment. It is a block diagram which shows a part of functional structure of the design rule verification apparatus of Example 2 concerning embodiment. It is a block diagram which shows a part of functional structure of the design rule verification apparatus of Example 3 concerning embodiment of this invention. It is a block diagram which shows a part of functional structure of the design rule verification apparatus of Example 4 concerning embodiment. It is explanatory drawing which shows a Linked List structure and a Segment Tree structure. It is explanatory drawing which shows a Bit Map structure. It is explanatory drawing which shows the prohibition area | region set by the area | region setting part. 10 is a flowchart of a design rule verification process procedure according to the fourth embodiment. It is a block diagram which shows a part of functional structure of the design rule verification apparatus of Example 5 concerning embodiment. 10 is a flowchart illustrating a design rule verification processing procedure according to the fifth embodiment. It is a block diagram which shows a part of functional structure of the design rule verification apparatus of Example 6 concerning embodiment. It is explanatory drawing which shows the verification content (first half) concerning Example 6. FIG. It is explanatory drawing which shows the verification content (second half) concerning Example 6. FIG. 12 is a flowchart illustrating a design rule verification processing procedure according to the sixth embodiment. It is explanatory drawing which shows generation | occurrence | production of a pseudo error. FIG. 10 is a block diagram illustrating an example of a functional configuration of a design rule verification apparatus according to a seventh embodiment. 14 is a flowchart illustrating a region determination processing procedure according to the seventh embodiment. 14 is a flowchart illustrating a region determination processing procedure according to the seventh embodiment.

  Exemplary embodiments of a design rule verification program, a recording medium storing the program, and a design rule verification device according to the present disclosure will be described below in detail with reference to the accompanying drawings.

(Hardware configuration of design rule verification device)
First, the hardware configuration of the design rule verification apparatus according to the embodiment will be described. FIG. 1 is a block diagram of a hardware configuration of the design rule verification apparatus according to the embodiment.

  In FIG. 1, the design rule verification apparatus is an example of a CPU 101, a ROM 102, a RAM 103, an HDD (hard disk drive) 104, an HD (hard disk) 105, an FDD (flexible disk drive) 106, and a removable recording medium. FD (flexible disk) 107, display 108, I / F (interface) 109, keyboard 110, mouse 111, scanner 112, and printer 113. Each component is connected by a bus 100.

  Here, the CPU 101 controls the entire design rule verification apparatus. The ROM 102 stores a program such as a boot program. The RAM 103 is used as a work area for the CPU 101. The HDD 104 controls reading / writing of data with respect to the HD 105 according to the control of the CPU 101. The HD 105 stores data written under the control of the HDD 104.

  The FDD 106 controls reading / writing of data with respect to the FD 107 according to the control of the CPU 101. The FD 107 stores data written under the control of the FDD 106 or causes the design rule verification apparatus to read data stored in the FD 107.

  In addition to the FD 107, the removable recording medium may be a CD-ROM (CD-R, CD-RW), MO, DVD (Digital Versatile Disk), memory card, or the like. The display 108 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As this display 108, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The I / F 109 is connected to a network 114 such as the Internet through a communication line, and is connected to other devices via the network 114. The I / F 109 controls an internal interface with the network 114 and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 109.

  The keyboard 110 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 111 performs cursor movement, range selection, window movement, size change, and the like. A trackball or a joystick may be used as long as they have the same function as a pointing device.

  The scanner 112 optically reads an image and takes in the image data into the design rule verification device. The scanner 112 may have an OCR function. The printer 113 prints image data and document data. For example, a laser printer or an ink jet printer can be employed as the printer 113.

(Contents of layout data)
Next, the contents of the layout data relating to the semiconductor circuit according to the embodiment will be described. FIG. 2 is an explanatory diagram of contents of layout data relating to the semiconductor circuit according to the embodiment. In FIG. 2, layout data 200 is graphic information representing objects such as wirings, vias, and power supply circuits constituting a semiconductor circuit. The layout data 200 is configured in, for example, a DEF / LEF format. Specifically, the layout data 200 includes object format data 201 indicating an object and representative format data 202.

  The object format data 201 is composed of the coordinates of the vertex of the object. For example, the object format data 211 represents wiring, and the number of vertices is four. The object format data 212 represents a figure in which two wires are connected, and the number of vertices is six. The object format data 213 represents a figure in which two wirings and vias are connected, and the number of vertices is 12.

  The representative format data 202 is data representing an object in the semiconductor circuit using a representative point. The representative format data 221 representing a via is composed of coordinates of a point (representative point) 221a on a grid point of the grid and a distance from the representative point 221a to the outer edge of the via.

  In addition, the representative data of the wiring is composed of points at both ends (representative points), a line segment between the representative points, and a line width of the wiring with the line segment as the center. For example, the representative format data 222 includes representative points 222a and 222b, a line segment 222c, and a line width 222d. The representative format data 223 is composed of representative points 223a and 223b, a line segment 223c, and a line width 223d, and the representative format data 224 is composed of representative points 223a and 224b, a line segment 224c, and a line width 224d.

  In actual layout data, most of the data is representative format data, and the remaining data is object format data. Further, all layout data may be object format data. In other words, the layout data only needs to include at least object format data.

(Functional configuration of design rule verification device)
Next, a functional configuration of the design rule verification apparatus according to the embodiment will be described. FIG. 3 is a block diagram of a functional configuration of the design rule verification apparatus according to the embodiment. In FIG. 3, the design rule verification apparatus 300 includes an acquisition unit 301, a verification unit 302, and an output unit 303.

  The acquisition unit 301 acquires representative format data 202 representing an object in a semiconductor circuit using representative points from the layout data 200 related to the semiconductor circuit. The verification unit 302 verifies whether the layout data 200 violates the design rule 310 based on the representative format data 202 acquired by the acquisition unit 301. The output unit 303 outputs the verification result verified by the verification unit 302. Specific contents of the acquisition unit 301 and the verification unit 302 will be described later. Note that the acquisition unit 301, the verification unit 302, and the output unit 303 described above specifically cause the CPU 101 to execute a program recorded on a recording medium such as the ROM 102, the RAM 103, and the HD 105 illustrated in FIG. Or the I / F 109 realizes the function.

  Next, a design rule verification device of Example 1 according to the embodiment will be described. FIG. 4 is a block diagram illustrating a part of the functional configuration of the design rule verification apparatus according to the first embodiment according to the embodiment. FIG. 4 shows an example of a functional configuration inside the acquisition unit 301 shown in FIG. In FIG. 4, the acquisition unit 301 includes an extraction unit 401 and a data format conversion unit 402 that is an existing data format conversion tool. The first embodiment is an example in which the layout data 200 is mostly representative format data 202 and part of the object format data 201 is mixed.

  The extraction unit 401 extracts representative format data 411 that matches the verification target condition from the layout data 200. Here, the verification target condition is a condition for specifying the representative format data to be verified, and is determined by the attribute of the representative format data. For example, when the determination is made based on the attributes of the net, for example, representative format data 411 representing general digital signal wiring can be extracted. Further, when judging based on the size of the object, for example, the representative format data 411 of the line width x [nm] and the line interval y [nm] can be extracted for the wiring, and the vertical and horizontal z [ nm] size representative format data 411 can be extracted.

  The data format conversion unit 402 can apply a general conversion tool, and converts all representative format data 202 in the layout data 200 into object format data 412 such as a GDS format. The object format data 412 also includes object format data 201 in the layout data 200. The representative format data 411 and the object format data 412 acquired by the acquisition unit 301 are output to the verification unit 302. As described above, according to the first embodiment, since the data can be configured using the existing data format conversion tool (data format conversion unit 402), the representative format data 411 can be acquired with a simple improvement. .

  Next, a design rule verification device of Example 2 according to the embodiment will be described. FIG. 5 is a block diagram illustrating a part of a functional configuration of the design rule verification apparatus according to the second embodiment according to the embodiment. FIG. 5 illustrates an example of a functional configuration inside the acquisition unit 301 illustrated in FIG. The second embodiment is an example in which the layout data 200 is mostly representative format data 202 and part of the object format data 201 is mixed, and the acquisition process can be speeded up compared to the first embodiment. Can do.

  In FIG. 5, the acquisition unit 301 includes a distribution unit 501 and a data format conversion unit 502. The distribution unit 501 extracts representative format data 202 from the layout data 200, and distributes the representative format data 202 to representative format data 511 that matches the verification target condition and representative format data 512 that does not match. Here, since the verification target condition is the same as the content described in the first embodiment, the description is omitted here.

  Further, the data format conversion unit 502 converts the representative format data 512 that does not match the verification target condition in the distribution unit 501 into object format data 521 such as a GDS format, for example. The representative format data 511 and the object format data 521 acquired by the acquisition unit 301 are output to the verification unit 302.

  Thus, according to the second embodiment, the data converted by the data format conversion unit 502 is not limited to all the representative format data 202 as in the first embodiment, but is limited to representative format data that does not meet the predetermined condition. Therefore, it is possible to prevent useless data conversion and improve the verification processing speed.

  Next, a design rule verification device of Example 3 according to the embodiment will be described. FIG. 6 is a block diagram illustrating a part of a functional configuration of the design rule verification apparatus according to the third embodiment according to the embodiment. FIG. 6 illustrates an example of a functional configuration inside the acquisition unit 301 illustrated in FIG. In the third embodiment, all the data in the layout data 200 is object format data 201 such as GDS format.

  6, the acquisition unit 301 includes a distribution unit 601 and a data format conversion unit 602. The distribution unit 601 extracts the object format data 201 from the layout data 200 and distributes the object format data 201 to the object format data 611 that matches the verification target condition and the object format data 612 that does not match. Here, since the verification target condition is the same as the content described in the first embodiment, the description is omitted here.

  Further, the data format conversion unit 602 converts the object format data 612 that does not match the verification target condition in the distribution unit 601 into the representative format data 621. The object format data 611 and the representative format data 621 acquired by the acquisition unit 301 are output to the verification unit 302.

  Thus, according to the third embodiment, the representative format data 621 can be obtained even when the representative format data 202 does not exist in the layout data 200. The representative format data 621 has a smaller data amount than the object format data 611. Therefore, by using the representative format data 621, the verification processing speed can be improved. In addition, the data converted by the data format conversion unit 602 is not limited to all the object format data 201 but is limited to the object format data 612 that does not meet the predetermined condition. Can be improved.

  Next, a design rule verification device of Example 4 according to the embodiment will be described. The fourth embodiment is a design rule verification between representative format data. FIG. 7 is a block diagram illustrating a part of a functional configuration of the design rule verification apparatus according to the fourth embodiment according to the embodiment. FIG. 7 shows an example of a functional configuration inside the verification unit 302 shown in FIG. Note that any of the acquisition units 301 of the first to third embodiments described above may be applied to the acquisition unit 301 illustrated in FIG. 3. Therefore, in FIG. 7 (the same applies to FIGS. 12 and 14), the representative format data 411, 511, and 621 are collectively referred to as representative format data 700.

  In FIG. 7, the verification unit 302 includes a data structure conversion unit 701, a designation unit 702, an area setting unit 703, and an area determination unit 704. The data structure conversion unit 701 converts the representative format data 700 into representative format data 710 having a data structure with high-speed access. As an example of data structure conversion, a Linked List structure, a Segment Tree structure, or a Bit Map structure can be used.

  Here, the Linked List structure and the Segment Tree structure will be described. FIG. 8 is an explanatory diagram showing a Linked List structure and a Segment Tree structure. In FIG. 8, representative format data 700 is composed of representative format data A to E, G representing wiring and representative format data F representing vias.

  The Linked List structure 711 is a structure in which, for example, a row number and an object are associated, and when a row is specified, an object arranged in the row can be extracted. For example, representative format data A can be extracted by designating a row, representative format data B and C can be extracted by designating b row, and representative format data D to G can be extracted by designating c row.

  The Segment Tree structure 712 is a tree structure using column numbers, and can extract an object that intersects a specified column number. For example, the Segment Tree structure 712 indicates that the representative format data A and E intersect with the grid line of the eighth column, and the representative format data B intersects with the grid line of the fourth column. The representative format data D indicates that it intersects with the grid line of the second column, and the representative format data G indicates that it intersects with the grid line of the twelfth column. Data C and F indicate that they intersect the grid line in the 10th column. By converting into a calculation geometric data structure in this way, it is possible to access at high speed.

  FIG. 9 is an explanatory diagram showing a Bit Map structure. In FIG. 9, the representative format data 700 is composed of representative points 901 and 902 and a line segment 903 between the representative points 901 and 902. The Bit Map structure is composed of lattice points (displayed as black dots in the figure) in actual object data 910 (displayed by diagonal lines in the figure) represented by the representative format data 700. In this way, it is possible to access at high speed by converting to a computational geometric Bit Map structure.

  In FIG. 7, the designation unit 702 designates representative format data constituting an arbitrary net from the representative format data 700 acquired by the acquisition unit 301. Specifically, it is designated from the representative format data 710 obtained from the data structure conversion unit 701. Here, an arbitrary net is a set of representative format data 700 having the same potential.

  The region setting unit 703 sets a region including the representative format data 700 acquired by the acquisition unit 301 based on the semiconductor circuit design rules. Specifically, an area including the representative format data 710 in the net designated by the designation unit 702 is set. Here, the area is a prohibited area where the arrangement of representative format data and object format data of other nets is prohibited by the design rule 310. Here, the prohibited area will be described with reference to the drawings.

  FIG. 10 is an explanatory diagram showing prohibited areas set by the area setting unit. In FIG. 10, representative format data 1001 and 1002 are representative format data designated by the designation unit 702. Therefore, the representative format data 1001 and 1002 are representative format data constituting the same net, that is, representative format data of the same potential. Reference numeral 1011 represents object data represented by the representative format data 1001, and reference numeral R represents a prohibited area including the representative format data 1001.

  The area determination unit 704 determines whether or not representative format data (at least a part of) of other nets is arranged in the prohibited area R. In FIG. 10, the representative format data 1003 is not arranged in the prohibited area, but the representative points of the representative format data 1004 of other nets are arranged in the prohibited area R. Therefore, the representative format data 1003 complies with the design rule 310, but the representative format data 1004 violates the design rule 310.

(Design rule verification processing procedure)
Next, a design rule verification processing procedure according to the fourth embodiment will be described. FIG. 11 is a flowchart of a design rule verification process procedure according to the fourth embodiment. First, when the representative format data 700 is acquired (step S1101: Yes), the data structure conversion of the representative format data 700 is performed (step S1102). Then, i = 1, the number of nets in the same potential group is set to n (step S1103), and the net Ni is extracted (step S1104).

  If j = 1 and the number of representative format data 710 in the net Ni (hereinafter referred to as “representative format data Dj” in the fourth embodiment) is d (step S1105), the prohibited area Rj of the representative format data Dj. Is set (step S1106). Then, an area determination process is executed (step S1107). In the area determination process (step S1107), first, it is determined whether or not representative format data of another net is arranged in the prohibited area Rj (step S1120).

  When representative format data of another net is arranged (step S1120: Yes), a verification result (design rule violation) is output (step S1121), and when representative format data of another net is not arranged (step) S1120: No), the verification result (design rule compliance) is output (step S1122).

  Then, j is incremented (step S1108). If j> d is not satisfied (step S1109: No), the process proceeds to step S1107. As a result, the prohibited area Rj of the next representative format data Dj in the net Ni can be set. On the other hand, if j> d (step S1109: Yes), i is incremented (step S1110). If i> n is not satisfied (step S1111: No), the process proceeds to step S1104. Thereby, the next net Ni can be extracted. On the other hand, if i> n (step S1111: Yes), the series of processing ends.

  According to the fourth embodiment, design rule verification can be performed between representative format data, and design rule verification can be speeded up. In particular, there are only limited types of objects such as wiring and vias that can be represented by representative format data, and representative points are often arranged on grid points. Therefore, design rule verification can be realized at higher speed by converting the data structure. In order to increase the speed, there is a method of setting all prohibited areas of the same net in S1106.

  Next, a design rule verification device of Example 5 according to the embodiment will be described. The fifth embodiment is design rule verification between representative format data and object format data. FIG. 12 is a block diagram illustrating a part of a functional configuration of the design rule verification apparatus according to the fifth embodiment according to the embodiment. FIG. 12 illustrates an example of a functional configuration inside the verification unit 302 illustrated in FIG. Note that any of the acquisition units 301 of the first to third embodiments described above may be applied to the acquisition unit 301 illustrated in FIG. 3. Therefore, in FIG. 12 (also in FIG. 14), the object format data 412, 521, and 611 are collectively referred to as object format data 1200. Moreover, the same code | symbol is attached | subjected to the same structure as Example 4 mentioned above, and the description is abbreviate | omitted.

  In FIG. 12, the verification unit 302 includes a designation unit 1201, a region setting unit 1202, and a region determination unit 1203. The designation unit 1201 designates object format data constituting an arbitrary net from the object format data 1200 acquired by the acquisition unit 301. The region setting unit 1202 sets a region (prohibited region) R including the object format data 1200 specified by the specifying unit 1201 based on the semiconductor circuit design rule 310. A specific example of setting the prohibited area R is the same as that in FIG.

  In addition, the area determination unit 1203 determines whether or not the representative format data 700 constituting another net other than the net for which the object format data 1200 is specified is arranged in the prohibited area R set by the area setting unit 1202. Determine. Specifically, it is determined whether or not representative format data 710 constituting a net other than the net in which the object format data 1200 is designated is arranged in the prohibited area R.

(Design rule verification processing procedure)
Next, a design rule verification processing procedure according to the fifth embodiment will be described. FIG. 13 is a flowchart of a design rule verification process procedure according to the fifth embodiment. First, when the representative format data 700 is acquired (step S1301: Yes), the data structure of the representative format data 700 is converted (step S1302). Then, i = 1, the number of nets in the same potential group is n (step S1303), and net Ni is extracted (step S1304).

  Then, if k = 1 and the number of object format data 1200 (hereinafter referred to as “object format data Fk” in the fifth embodiment) in the network Ni is f (step S1305), the prohibited area Rk of the object format data Fk. Is set (step S1306). Then, an area determination process is executed (step S1307). In the area determination process (step S1307), first, it is determined whether or not representative format data of another net is arranged in the prohibited area Rk (step S1320).

  When representative format data of another net is arranged (step S1320: Yes), a verification result (design rule violation) is output (step S1321), and when representative format data of another net is not arranged (step) S1320: No), the verification result (design rule compliance) is output (step S1322).

  Then, k is incremented (step S1308). If k> f is not satisfied (step S1309: No), the process proceeds to step S1307. As a result, the prohibited area Rk of the next object format data Fk in the net Ni can be set. On the other hand, if k> f (step S1309: Yes), i is incremented (step S1310). If i> n is not satisfied (step S1311: No), the process proceeds to step S1304. Thereby, the next net Ni can be extracted. On the other hand, if i> n (step S1311: Yes), the series of processing ends.

  According to the fifth embodiment, design rule verification can be performed between the representative format data and the object format data, and the design rule verification can be speeded up. In particular, there are only limited types of objects such as wiring and vias that can be represented by representative format data, and representative points are often arranged on grid points. Therefore, design rule verification can be realized at higher speed by converting the data structure.

  Next, a design rule verification device of Example 6 according to the embodiment will be described. Example 6 is design rule verification between representative format data and object format data. FIG. 14 is a block diagram illustrating a part of the functional configuration of the design rule verification apparatus according to the sixth embodiment. FIG. 14 illustrates an example of a functional configuration inside the verification unit 302 illustrated in FIG. Note that any of the acquisition units 301 of the first to third embodiments described above may be applied to the acquisition unit 301 illustrated in FIG. 3. Moreover, the same code | symbol is attached | subjected to the same structure as Example 4 and 5 mentioned above, and the description is abbreviate | omitted.

  The verification unit 302 includes a data structure conversion unit 1401, a designation unit 402, and an area determination unit 1403. The data structure conversion unit 1401 converts the data structure of the object format data 1200 in which the region R is set by the region setting unit 1202. As an example of data structure conversion, the above-described Linked List structure, Segment Tree structure, or Bit Map structure can be used. Here, it is assumed that the converted object format data 1400 has been converted to a Bit Map structure.

  The designation unit 1402 designates representative format data included in an arbitrary net from the representative format data 700. The area determination unit 1403 determines whether the representative format data 700 specified by the specification unit 1402 is arranged in the object format data 1400 included in another net. Here, the verification content of Example 6 is demonstrated concretely.

  FIGS. 15A and 15B are schematic diagrams illustrating the verification contents according to the sixth embodiment. In the stage (A), the object format data 1200 shown in FIG. 14 has object format data 1501 to 1504. The representative format data 700 shown in FIG. 14 includes representative format data 1511 to 1514.

  In the stage (B), the prohibited areas R1 to R4 of all the object format data 1501 to 1504 are set and converted into a Bit Map structure. In step (C), a net N1 that is the same potential group is designated. The net N1 includes object format data 1501 and representative format data 1511 and 1512.

  In step (D), the prohibited area R1 in the net N1 is temporarily erased. In step (E), the representative format data 1511 in the net N1 is designated. In step (F), it is determined whether or not the representative format data 1511 specified in step (E) is arranged in the other prohibited areas R2 to R4. In step (F), it can be seen that the representative format data 1511 is arranged in the prohibited area R2.

  Next, in step (G), the representative format data 1512 in the net N1 that has not been specified is specified. At stage (G), the representative format data 1512 is not included in the prohibited areas R2 to R4 in other nets. In step (H), the prohibited area R1 erased in step (D) is restored. Thereafter, in the stage (I), the next net N2 is extracted.

(Design rule verification processing procedure)
Next, a design rule verification processing procedure according to the sixth embodiment will be described. FIG. 16 is a flowchart of a design rule verification process procedure according to the sixth embodiment. First, when all object format data 1200 has been acquired (step S1601: Yes), the prohibited area R of all object format data 1200 is set (step S1602). Then, all of the prohibited areas R are converted into a Bit Map structure (step S1603).

  Next, i = 1, the number of nets in the same potential group is set to n (step S1604), and the net Ni is extracted (step S1605). Then, j = 1 is set, and the number of representative format data in the net Ni is set to m (step S1606), and the region determination process is executed (step S1607). In the area determination process (step S1607), first, representative format data 700 (hereinafter referred to as “representative format data Dj” in the sixth embodiment) is provided in the prohibited area R of the Bit Map structure of the net other than the net Ni. It is determined whether or not they are arranged (step S1620).

  When it is determined that the representative format data Dj is arranged (step S1620: Yes), a verification result (design rule violation) is output (step S1621). On the other hand, when it is determined that the representative format data Dj is not arranged (step S1620: No), a verification result (design rule compliance) is output (step S1622).

  Thereafter, j is incremented (step S1608), and if j> m is not satisfied (step S1609: No), the process proceeds to step S1607, and the area determination process for the next representative format data Dj is executed. On the other hand, if j> m (step S1609: Yes), i is incremented (step S1610). If i> n is not satisfied (step S1611: No), the process proceeds to step S1605 to extract the next net Ni. If i> n (step S1611: Yes), the series of processes is terminated.

  According to the sixth embodiment, design rule verification can be performed between the representative format data and the object format data, and the design rule verification can be speeded up. In particular, there are only limited types of objects such as wiring and vias that can be represented by representative format data, and representative points are often arranged on grid points. Therefore, design rule verification can be realized at higher speed by converting the data structure. In particular, the verification speed can be improved by converting the data structure of the object format data into the Bit Map structure.

  Next, a design rule verification device of Example 7 according to the embodiment will be described. The seventh embodiment is design rule verification when there is a possibility of so-called pseudo error. When there are a plurality of types of adjacent objects for arbitrary representative format data (or object format data) according to the design rule 310, it is necessary to set the number of prohibited areas of that type. In particular, when the prohibited area has a Bit Map structure, the amount of memory used increases. Therefore, a pseudo error occurs when only the largest prohibited area is set to save memory.

  FIG. 17 is an explanatory diagram showing the occurrence of a pseudo error. In FIG. 17, it is assumed that objects X and Y are constituted by representative format data or object format data. In FIG. 17, for example, if the design rule 310 allows setting of the prohibited area Ra of the object A and the prohibited area Rb of the object B that are different from each other for the object X, the prohibited area Rb is saved to save memory. It is assumed that only is set. When the adjacent object Y is the object B, a true error determination, that is, a determination result of design rule violation can be obtained.

  On the other hand, when the object Y is also the object A, it is not arranged in the prohibited area Ra, but since the object Y is arranged in the prohibited area Rb, it is determined as a pseudo error, that is, a design rule violation. Become. Therefore, whether or not it is a pseudo error is detected based on whether or not the object Y arranged in the prohibited area Rb is the object B to be determined. When a pseudo error is detected, verification by graphic calculation is performed between the object Y (that is, the object A) and the object X as in the conventional case.

  Next, a functional configuration of the design rule verification apparatus according to the seventh embodiment will be described. FIG. 18 is a block diagram of an example of a functional configuration of the design rule verification apparatus according to the seventh embodiment. FIG. 18 shows a part of the verification unit 302. The configuration illustrated in FIG. 18 is a configuration that is added to the verification unit 302 (see FIGS. 7, 12, and 14) according to the fifth to seventh embodiments. Therefore, the area determination unit 1801 illustrated in FIG. 18 is a generic name of the area determination units 704, 1203, and 1403 illustrated in FIG. In FIG. 18, the verification unit 302 includes a pseudo error determination unit 1802 and a graphic operation verification unit 1803 in addition to the region determination unit 1801.

  The pseudo error determination unit 1802 determines whether or not the error is a pseudo error when the region determination unit 1801 determines that the design rule is violated, that is, an error determination is made. Specifically, referring to FIG. 17, when the object Y is arranged in the prohibited area Rb, the area determination unit 1801 determines an error. When there is an error determination, the pseudo error determination unit 1802 determines whether the object Y is the object A or the object B. In the case of the object A, the error is determined as a pseudo error, and in the case of the object B, the error is determined as a true error.

  If it is determined that the error is a pseudo error, the graphic operation verification unit 1803 performs a graphic operation on the object X and the object Y based on the description information of the prohibited area Ra in the design rule 310 and violates the design rule 310. Verify whether or not. Since this graphic operation verification unit 1803 is a verification processing function of a conventional verification tool, its description is omitted here.

(Region determination procedure)
Next, an area determination processing procedure according to the seventh embodiment will be described. FIGS. 19 and 20 are flowcharts illustrating the region determination processing procedure according to the seventh embodiment. The flowchart shown in FIG. 19 is a procedure replacing step S1107 shown in FIG. 11 and step S1307 shown in FIG. 13, and the flowchart shown in FIG. 20 is a procedure replacing step S1607 shown in FIG.

  First, in FIG. 19, it is determined whether or not representative format data of another net is arranged in the prohibited area (step S1901). If it is determined that the representative format data of another net is not arranged (step S1901: No), a verification result (design rule compliance) is output (step S1906). On the other hand, when representative format data of other nets are arranged, that is, when it is determined as an error (step S1901: Yes), it is determined whether or not the error is a pseudo error (step S1902).

  If it is determined that the error is a pseudo error (step S1902: YES), graphic operation verification is executed (step S1903). If it is determined by this graphic operation verification that the design rule is violated (step S1904: Yes), a verification result (design rule violation) is output (step S1905). On the other hand, if the graphic operation verification does not violate the design rule (step S1904: No), the verification result (observation of the design rule) is output (step S1906). If it is determined in step S1902 that the error is not a pseudo error (step S1902: No), a verification result (design rule violation) is output (step S1905).

  In FIG. 20, it is determined whether or not the representative format data Dj is arranged in the prohibited area of the Bit Map structure of another net (step S2001). If it is determined that the representative format data Dj of another net is not arranged (step S2001: No), the verification result (design rule compliance) is output (step S2006). On the other hand, when the representative format data Dj is arranged, that is, when it is determined to be an error (step S2001: Yes), it is determined whether or not the error is a pseudo error (step S2002).

  When it is determined that the error is a pseudo error (step S2002: Yes), graphic operation verification is executed (step S2003). If it is determined by this graphic operation verification that the design rule is violated (step S2004: Yes), a verification result (design rule violation) is output (step S2005). On the other hand, if the graphic operation verification does not violate the design rule (step S2004: No), the verification result (observation of the design rule) is output (step S2006). If it is determined in step S2002 that the error is not a pseudo error (step S2002: No), a verification result (design rule violation) is output (step S2005).

  According to the seventh embodiment, even when there are a plurality of types of prohibited areas (Ra, Rb) according to the design rule 310, design rule verification can be performed only by setting only the largest prohibited area Rb. . Further, since the setting of the prohibited area can be suppressed to the minimum necessary, the amount of memory used can be reduced, and the design rule verification can be speeded up.

  As described above, according to the design rule verification program according to the embodiment, the recording medium recording the program, the design rule verification method, and the design rule verification apparatus, by simplifying the layout data of the semiconductor circuit, The design rule verification can be speeded up. Even if the design rule is complicated, it can be used as a screening means for pessimistically determining whether the design rule is followed (not violated), and the number of verification processing executions can be greatly reduced. it can.

  The design rule verification method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The program may be a transmission medium that can be distributed via a network such as the Internet.

  As described above, the design rule verification program, the recording medium on which the program is recorded, and the design rule verification apparatus according to the present invention are useful for design rule verification of layout data related to a semiconductor circuit.

DESCRIPTION OF SYMBOLS 300 Design rule verification apparatus 301 Acquisition part 302 Verification part 303 Output part 310 Design rule 401 Extraction part 402 Data format conversion part 501,601 Distribution part 502,602 Data format conversion part 701 Data structure conversion part 702 Specification part 703 Area | region setting part 704 Area determination unit

Claims (9)

Object format data representing an object in a semiconductor circuit using polygons or vertices in a predetermined coordinate system, a representative point on a grid point of a grid coordinate system having a grid larger than the predetermined coordinate system, or the representative point An acquisition step of acquiring layout data including at least the representative format data among representative format data representing the object using a line segment between representative points;
Depending on whether one representative format data is arranged in a grid group of the grid coordinate system including other representative format data, among the representative format data in the layout data acquired by the acquisition step, A verification process for verifying whether layout data violates design rules;
An output step of outputting a verification result verified by the verification step;
A design rule verification program characterized by causing a computer to execute. Causing the computer to execute a distribution step of distributing the representative format data group to representative format data that does not match the representative format data that matches a predetermined verification target condition;
The verification step includes
Depending on whether or not one representative format data is arranged in a lattice group of the grid coordinate system including other representative format data among the representative format data matching the verification target by the distribution step, the layout data The design rule verification program according to claim 1, wherein the design rule is verified to violate the design rule. When the object format data is included in the layout data, the computer is caused to execute a conversion step of converting the object format data into the representative format data,
The verification step includes
Depending on whether or not one representative format data is arranged in a grid group of the grid coordinate system including other representative format data between the representative format data including the one converted by the conversion step, the layout The design rule verification program according to claim 1, wherein data is verified to violate a design rule. When the layout data includes the object format data, a sorting step for sorting the object format data that does not match the object format data that matches a predetermined verification target condition;
Causing the computer to execute a conversion step of converting the object format data that matches the predetermined verification target condition into the representative format data by the distribution step,
The verification step includes
Depending on whether or not one representative format data is arranged in a grid group of the grid coordinate system including other representative format data between the representative format data including the one converted by the conversion step, the layout The design rule verification program according to claim 1, wherein data is verified to violate a design rule. A structure conversion step for converting the representative format data into a data structure for faster access;
Of the representative format data group whose data structure has been converted by the structure conversion step, the same potential extraction step of extracting representative format data belonging to one net to be the same potential group, and
A region setting step for setting a prohibited region of representative format data belonging to the one net extracted by the same potential extraction step;
An area determination step for determining whether or not representative format data belonging to other nets other than the one net is arranged in the prohibited area set by the area setting step;
The design rule verification program according to any one of claims 1 to 4, further comprising: When there are a plurality of types of design rules, the computer is caused to execute a pseudo error determination step that determines whether the determination result determined by the region determination step is a pseudo error,
The verification step includes
6. The design rule verification program according to claim 5, wherein the design rule verification program verifies whether or not the layout data violates a design rule based on a determination result determined by the pseudo error determination step. The verification step includes
When the pseudo error is determined by the pseudo error determination step, the layout data is determined as a design rule by a graphic operation based on a distance between the representative format data belonging to the one net and the representative format data belonging to the other net. The design rule verification program according to claim 6, wherein the program verifies whether or not the information is violated.   A computer-readable recording medium on which the design rule verification program according to claim 1 is recorded. Object format data representing an object in a semiconductor circuit using polygons or vertices in a predetermined coordinate system, a representative point on a grid point of a grid coordinate system having a grid larger than the predetermined coordinate system, or the representative point An acquisition means for acquiring layout data including at least the representative format data among representative format data representing the object using a line segment between representative points;
Depending on whether one representative format data is arranged in a lattice group of the grid coordinate system including other representative format data between the representative format data in the layout data acquired by the acquisition means, A verification means for verifying whether the layout data violates the design rule;
Output means for outputting a verification result verified by the verification means;
A design rule verification device comprising:

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