JP4659238B2 - Method for forming semiconductor layer - Google Patents
Method for forming semiconductor layer Download PDFInfo
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- JP4659238B2 JP4659238B2 JP2001061718A JP2001061718A JP4659238B2 JP 4659238 B2 JP4659238 B2 JP 4659238B2 JP 2001061718 A JP2001061718 A JP 2001061718A JP 2001061718 A JP2001061718 A JP 2001061718A JP 4659238 B2 JP4659238 B2 JP 4659238B2
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Description
【0001】
【発明の属する技術分野】
本発明は半導体層の製膜方法に関する。
【0002】
【従来の技術】
例えば薄膜太陽電池モジュールは、透明基板上に積層された透明電極層、光電変換半導体層、ならびに裏面電極層からなるストリング状の複数段の太陽電池セルを直列に接続した構造を有する。上記の光電変換半導体層はアモルファスシリコンで形成するのが最も安価であるが、光電変換効率が低いという問題がある。光電変換効率を向上させるためには、例えばpin型アモルファスシリコンとpin型ポリシリコン(多結晶シリコン)とを積層したハイブリッド型またはpin型ポリシリコンのみを用いたポリシリコン型のものが有利である。また、薄膜太陽電池モジュールの生産効率を上げるために大面積の基板が用いられるようになってきている。
【0003】
ところで、アモルファスシリコンは吸収係数が比較的高いため膜厚が薄くてもよいが、吸収係数が低いポリシリコンは膜厚を厚くする必要がある。プラズマCVD法により厚いポリシリコン層の製膜時間を短縮して生産効率を向上するには、基板へ投入する電力密度を上げて製膜速度を速くしなければならない。基板への投入電力密度を上げるには、高周波電源の出力を上げることおよび周波数を上げることが有効である。このうち周波数に関しては、従来の13.56MHzから2倍の27.12MHzへ上げることが試みられている。将来的には従来の3倍の40MHzに上げることも想定されている。
【0004】
図1に、大面積の基板上に半導体層を製膜するために用いられる縦型インライン式プラズマCVD装置を示す。図1に示すように、チャンバー(製膜室)1内の両端部に1対のカソード2a、2bが設けられている。各カソード2a、2bに対向するように、それぞれ基板10a、10bを保持したアノード3a、3bが配置される。各カソード2a、2bにはそれぞれ高周波電源4a、4bが接続されている。これらの高周波電源4a、4bは、発振器を内蔵したフェイズシフター5に接続されている。
【0005】
図1に示されるようなプラズマCVD装置において、高周波電源4a、4bから27.12MHzという高周波を供給した場合、2つの放電領域間での干渉が強く、放電が安定しなくなる。このため、図1のようにフェイズシフター5を設けて、干渉の影響を少なくするために高周波電源4a、4bから供給される高周波の位相を完全に同期させるか(位相差0度)または位相を180度ずらすように位相を調整し、放電状態を安定させて安定製膜を実現していた。
【0006】
上記と同様に、特開昭60−202929号公報には、複数の電極対を設置したプラズマCVD装置において、複数の高周波電源に位相調整器を接続して位相調整を行うことが記載されている。そして、高周波電源を独立することにより各電極へ印加する電力を個々に調整できるため各電極の形状が異なる場合でも各電極の均等な放電が可能となることが記載されている。また、電極の幾何学的形状が等価な場合に並列接続し、一括して放電させてもほぼ均等な放電が得られることが記載されている。しかし、この公報で用いられている高周波電力は13.56MHzであり、27.12MHzというさらに周波数の高い電力を用いることは記載されていない。
【0007】
図1に示した現状のプラズマCVD装置および特開昭60−202929号公報のプラズマCVD装置のようにほぼ同一形状の電極をほぼ対称位置に配置したものでは、13.56MHzの高周波電源を用いる場合には干渉が生じないように改良されている。しかし、27.12MHzの高周波電源を用いた場合には、フェイズシフター5により位相差を0度または180度に設定して安定製膜を達成したとしても、真空チャンバー内でのわずかな寸法の差異例えば基板−電極間距離の微妙な差やLC成分のわずかな差などに基づいて、2つの基板10a、10b上でのポリシリコン層の製膜速度が異なるという問題があることがわかってきた。特に、2つの基板でポリシリコン層の膜厚が10%以上も異なると、製品の品質を保つことが困難になる。この問題に対する対策として、例えばガス流量によって製膜速度を調整することも考えられるが、この方法では効果的な調整は期待できない。
【0008】
【発明が解決しようとする課題】
本発明の目的は、複数の電極対を備えたプラズマCVD装置を用い13.56MHzより高い周波数の高周波電力を供給する場合に、複数の基板上における半導体層の製膜速度を均一にできる方法を提供することにある。
【0009】
【課題を解決するための手段】
本発明の半導体層の製膜方法は、1つの製膜室内に設けられた略同一形状を有し略対称位置に配置された複数のカソードと各カソードに接続された13.56MHzより高い周波数の高周波電力を供給する複数の高周波電源とを有するプラズマCVD装置を用い、各カソードに対して基板を保持したアノードをそれぞれ対向させ、前記製膜室内で原料ガスを分解して複数の基板上に半導体層を製膜するにあたり、複数の基板上において所望の製膜速度で半導体層が製膜されるように、各高周波電源から各カソードに供給される高周波電力に、0度または180度の位相差からはずした位相差を与えることを特徴とする。
【0010】
本発明の半導体層の製膜方法においては、例えば前記複数の基板上における半導体層の製膜速度の差が10%以内になるように、各高周波電源から各カソードに供給される高周波電力の位相をずらす。
【0012】
【発明の実施の形態】
以下、本発明をより詳細に説明する。
【0013】
実施例1
図1に示す縦型インライン式プラズマCVD装置を用いて基板上にポリシリコン層の製膜を行った例を説明する。図1に示すように、チャンバー1内の両端部に1対のカソード2a、2bが設けられている。各カソード2a、2bに対向するように、それぞれ基板10a、10bを保持したアノード3a、3bが配置される。チャンバー1は接地されており、アノード3a、3bは接地電位となるようにチャンバー1に接続されている。各カソード2a、2bにはそれぞれ周波数27.12MHz、最大出力5kWの高周波電源4a、4bが接続されている。これらの高周波電源4a、4bは、発振器を内蔵したフェイズシフター5に接続されている。このように、2つの放電領域が表裏の関係で対称的に形成されていると、高周波電源4a、4bからの電力投入により2つの放電領域間で干渉が生じやすくなる。
【0014】
従来技術に従い、フェイズシフター5により高周波電源4a、4bから供給される高周波電力の位相を互いに180度ずらせて2つの基板上にポリシリコン層を製膜した。このように位相を180度ずらすと、干渉なしに安定な製膜が可能である。
【0015】
また、フェイズシフター5により高周波電源4a、4bから供給される高周波電力の位相を180度からさらに15度、すなわち互いに約195度ずらせて2つの基板上にポリシリコン層を製膜した。
【0016】
表1に、上記の2つの条件における基板10a上(表1のA面)および基板10b上(表1のB面)でのポリシリコン層の製膜速度を示す。
【0017】
【表1】
【0018】
表1から以下のことがわかる。すなわち、2つの高周波電源から供給される高周波電力の位相を互いに180度ずらした場合、真空チャンバー内のわずかな寸法の差異などの装置的な影響により、2つの基板上でのポリシリコン層の製膜速度に10%以上の大きな差が生じた。一方、2つの高周波電源から供給される高周波電力の位相を互いに195度ずらした場合、2つの基板上でのポリシリコン層の製膜速度をほぼ等しくすることができた。
【0019】
なお、上記の実施例では高周波電力の位相を互いに195度ずらしたが、高周波電力の位相を0度または180度からずらす程度は使用するプラズマCVD装置に応じて変化する。
【0020】
実施例2
図1のプラズマCVD装置を用い、一方の高周波電源4aのみから周波数27.12MHz、出力5kWの高周波電力を供給し、一方の基板10a(A面)上にポリシリコン層を製膜し、そのときの製膜速度を調べた。
【0021】
図1のプラズマCVD装置を用い、フェイズシフター5により2つの高周波電源4a、4bから供給される周波数27.12MHz、出力5kWの高周波電力の位相を互いに約135度ずらせて2つの基板10a、10b上にポリシリコン層を製膜し、そのときのA面における製膜速度を調べた。表2に上記の2つの条件におけるポリシリコン層の製膜速度を示す。
【0022】
【表2】
【0023】
高周波電力の位相を互いに約135度ずらすと、2つの放電領域間での干渉状態を積極的に利用してA面側に出力を集中させ7kW相当の出力を与えることができる。このように高周波電力の位相を適切にずらすと一方の放電領域に定格電力以上の電力を出力して高速製膜が可能となり、表2のように片面放電の場合と比較して製膜速度が2割以上速くなる。
【0024】
なお、上記の条件ではB面での製膜速度は低くなる。したがって、この方法は意図的に厚い膜と薄い膜を製膜する場合に好適に採用することができる。この方法でも、高周波電力の位相をずらす角度は135度に限らず、使用するプラズマCVD装置に応じて変化する。
【0025】
本発明の方法は、特にポリシリコン層を含む光電変換装置、例えば太陽電池モジュールの製造に好適に採用できる。
【0026】
図2にポリシリコン層を含むハイブリッド型の太陽電池モジュールの断面図を示す。図2において、ガラス基板11上には透明電極層12が形成され、レーザースクライブにより分離溝が加工されている。透明電極層12上にはpin型アモルファスシリコン層13およびpin型ポリシリコン層14が順次形成されており、レーザースクライブにより透明電極−裏面電極間の接続溝が加工されている。これらの光電変換半導体層上に裏面電極層15が形成され、レーザースクライブにより分離溝が加工されている。
【0027】
図2におけるポリシリコン層14の製膜時に、図1に示したプラズマCVD装置を用い、例えば実施例1に示した条件を採用することにより、均一な膜厚のポリシリコン層を速い製膜速度で製膜することができる。
【0028】
【発明の効果】
以上詳述したように本発明の方法を用いれば、複数の電極対を備えたプラズマCVD装置を用い13.56MHzより高い周波数の高周波電力を供給する場合に、複数の基板上における半導体層の製膜速度を均一にできる。
【図面の簡単な説明】
【図1】本発明の実施例において用いられたプラズマCVD装置を概略的に示す図。
【図2】本発明の一実施形態において製造されるハイブリッド型薄膜太陽電池セルを示す断面図。
【符号の説明】
1…チャンバー
2a、2b…カソード
3a、3b…アノード
4a、4b…高周波電源
5…フェイズシフター
10a、10b…基板
11…ガラス基板
12…透明電極層
13…アモルファスシリコン層
14…ポリシリコン層
15…裏面電極層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a film how the semiconductor layer.
[0002]
[Prior art]
For example, a thin-film solar cell module has a structure in which a plurality of string-like solar cells that are formed of a transparent electrode layer, a photoelectric conversion semiconductor layer, and a back electrode layer stacked on a transparent substrate are connected in series. The photoelectric conversion semiconductor layer is most inexpensive to be formed of amorphous silicon, but has a problem that the photoelectric conversion efficiency is low. In order to improve the photoelectric conversion efficiency, for example, a hybrid type in which pin type amorphous silicon and pin type polysilicon (polycrystalline silicon) are stacked or a polysilicon type using only pin type polysilicon is advantageous. In addition, a large-area substrate has been used in order to increase the production efficiency of the thin film solar cell module.
[0003]
By the way, although amorphous silicon has a relatively high absorption coefficient, the film thickness may be thin. However, polysilicon having a low absorption coefficient needs to be thick. In order to shorten the time for forming a thick polysilicon layer by plasma CVD and improve the production efficiency, it is necessary to increase the power density to be applied to the substrate and increase the film forming speed. In order to increase the power density input to the substrate, it is effective to increase the output of the high-frequency power source and increase the frequency. Of these, an attempt has been made to increase the frequency from the conventional 13.56 MHz to 27.12 MHz, which is twice as high. In the future, it is assumed that the frequency will be increased to 40 MHz, which is three times the conventional level.
[0004]
FIG. 1 shows a vertical in-line plasma CVD apparatus used for forming a semiconductor layer on a large-area substrate. As shown in FIG. 1, a pair of cathodes 2 a and 2 b are provided at both ends in a chamber (film forming chamber) 1. Anodes 3a and 3b holding substrates 10a and 10b are arranged so as to face the cathodes 2a and 2b, respectively. High frequency power supplies 4a and 4b are connected to the cathodes 2a and 2b, respectively. These high frequency power supplies 4a and 4b are connected to a phase shifter 5 incorporating an oscillator.
[0005]
In the plasma CVD apparatus as shown in FIG. 1, when a high frequency of 27.12 MHz is supplied from the high frequency power sources 4a and 4b, the interference between the two discharge regions is strong and the discharge becomes unstable. For this reason, a phase shifter 5 is provided as shown in FIG. 1 to completely synchronize the phase of the high frequency supplied from the high frequency power sources 4a and 4b in order to reduce the influence of interference (phase difference 0 degree) or the phase. The phase was adjusted so as to be shifted by 180 degrees to stabilize the discharge state, thereby realizing stable film formation.
[0006]
Similarly to the above, Japanese Patent Application Laid-Open No. 60-202929 describes that in a plasma CVD apparatus provided with a plurality of electrode pairs, phase adjustment is performed by connecting a phase adjuster to a plurality of high frequency power supplies. . Further, it is described that since the power applied to each electrode can be individually adjusted by making the high-frequency power supply independent, even when the shape of each electrode is different, each electrode can be discharged evenly. In addition, it is described that even when the electrodes have the same geometric shape, a substantially uniform discharge can be obtained even if they are connected in parallel and discharged together. However, the high-frequency power used in this publication is 13.56 MHz, and it is not described that power with a higher frequency of 27.12 MHz is used.
[0007]
In the case of using a high-frequency power source of 13.56 MHz in the case where the electrodes having substantially the same shape are arranged at almost symmetrical positions, such as the current plasma CVD apparatus shown in FIG. Has been improved to prevent interference. However, when a high frequency power source of 27.12 MHz is used, even if the phase shifter 5 sets the phase difference to 0 degrees or 180 degrees to achieve stable film formation, a slight difference in dimensions within the vacuum chamber. For example, it has been found that there is a problem that the deposition rates of the polysilicon layers on the two substrates 10a and 10b are different based on a subtle difference in the distance between the substrate and the electrode or a slight difference in the LC component. In particular, if the thickness of the polysilicon layer differs by 10% or more between the two substrates, it becomes difficult to maintain product quality. As a countermeasure against this problem, for example, it is conceivable to adjust the film forming speed by the gas flow rate. However, effective adjustment cannot be expected by this method.
[0008]
[Problems to be solved by the invention]
An object of the present invention is to provide a method capable of uniformizing the deposition rate of semiconductor layers on a plurality of substrates when a high-frequency power having a frequency higher than 13.56 MHz is supplied using a plasma CVD apparatus having a plurality of electrode pairs. It is to provide.
[0009]
[Means for Solving the Problems]
The semiconductor layer deposition method of the present invention has a plurality of cathodes having substantially the same shape provided in one deposition chamber and arranged at substantially symmetrical positions, and a frequency higher than 13.56 MHz connected to each cathode. Using a plasma CVD apparatus having a plurality of high-frequency power supplies for supplying high-frequency power, the anode holding the substrate is opposed to each cathode, the source gas is decomposed in the film forming chamber, and a semiconductor is formed on the plurality of substrates. When forming a layer, the phase difference of 0 degree or 180 degrees is applied to the high-frequency power supplied from each high-frequency power source to each cathode so that the semiconductor layer is formed on a plurality of substrates at a desired film-forming speed. It is characterized in that a phase difference removed from the above is given.
[0010]
In the method for forming a semiconductor layer of the present invention, for example, the phase of the high-frequency power supplied from each high-frequency power source to each cathode so that the difference in the film-forming speed of the semiconductor layer on the plurality of substrates is within 10%. Move.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in more detail.
[0013]
Example 1
An example in which a polysilicon layer is formed on a substrate using the vertical in-line type plasma CVD apparatus shown in FIG. 1 will be described. As shown in FIG. 1, a pair of cathodes 2 a and 2 b are provided at both ends in the chamber 1. Anodes 3a and 3b holding substrates 10a and 10b are arranged so as to face the cathodes 2a and 2b, respectively. The chamber 1 is grounded, and the anodes 3a and 3b are connected to the chamber 1 so as to have a ground potential. High frequency power supplies 4a and 4b having a frequency of 27.12 MHz and a maximum output of 5 kW are connected to the cathodes 2a and 2b, respectively. These high frequency power supplies 4a and 4b are connected to a phase shifter 5 incorporating an oscillator. Thus, if the two discharge areas are formed symmetrically with respect to the front and back, interference is likely to occur between the two discharge areas due to the power input from the high-frequency power sources 4a and 4b.
[0014]
In accordance with the prior art, the phase shifter 5 shifted the phase of the high frequency power supplied from the high frequency power sources 4a and 4b by 180 degrees to form a polysilicon layer on the two substrates. By shifting the phase by 180 degrees in this way, stable film formation is possible without interference.
[0015]
Further, the phase shifter 5 shifted the phase of the high-frequency power supplied from the high-frequency power sources 4a and 4b from 180 degrees to another 15 degrees, that is, about 195 degrees from each other to form polysilicon layers on the two substrates.
[0016]
Table 1 shows the deposition rate of the polysilicon layer on the substrate 10a (A surface in Table 1) and on the substrate 10b (B surface in Table 1) under the above two conditions.
[0017]
[Table 1]
[0018]
Table 1 shows the following. That is, when the phases of the high-frequency power supplied from the two high-frequency power sources are shifted from each other by 180 degrees, the production of the polysilicon layer on the two substrates is effected due to a device effect such as a slight dimensional difference in the vacuum chamber. A large difference of 10% or more occurred in the film speed. On the other hand, when the phases of the high-frequency power supplied from the two high-frequency power sources were shifted from each other by 195 degrees, the deposition rates of the polysilicon layers on the two substrates could be made substantially equal.
[0019]
In the above embodiment, the phases of the high-frequency power are shifted from each other by 195 degrees, but the extent to which the phase of the high-frequency power is shifted from 0 degrees or 180 degrees varies depending on the plasma CVD apparatus used.
[0020]
Example 2
Using the plasma CVD apparatus of FIG. 1, a high frequency power with a frequency of 27.12 MHz and an output of 5 kW is supplied from only one high frequency power source 4a, and a polysilicon layer is formed on one substrate 10a (A surface). The film forming speed of was examined.
[0021]
Using the plasma CVD apparatus of FIG. 1, the phases of the high frequency power of 27.12 MHz and the output of 5 kW supplied from the two high frequency power sources 4a and 4b by the phase shifter 5 are shifted from each other by about 135 degrees on the two substrates 10a and 10b. Then, a polysilicon layer was formed, and the film forming speed on the A surface at that time was examined. Table 2 shows the deposition rate of the polysilicon layer under the above two conditions.
[0022]
[Table 2]
[0023]
When the phases of the high-frequency power are shifted from each other by about 135 degrees, the interference state between the two discharge regions can be positively utilized to concentrate the output on the A-plane side and provide an output equivalent to 7 kW. As described above, when the phase of the high frequency power is appropriately shifted, power higher than the rated power can be output to one discharge region to enable high speed film formation. As shown in Table 2, the film formation speed is higher than that in the case of single-sided discharge. More than 20% faster.
[0024]
Note that the film forming speed on the B surface is low under the above conditions. Therefore, this method can be suitably used when intentionally forming a thick film and a thin film. Even in this method, the angle by which the phase of the high-frequency power is shifted is not limited to 135 degrees, but varies depending on the plasma CVD apparatus used.
[0025]
The method of the present invention can be suitably used particularly for the production of a photoelectric conversion device including a polysilicon layer, for example, a solar cell module.
[0026]
FIG. 2 shows a cross-sectional view of a hybrid solar cell module including a polysilicon layer. In FIG. 2, a
[0027]
When the
[0028]
【The invention's effect】
As described in detail above, when the method of the present invention is used, when a high-frequency power having a frequency higher than 13.56 MHz is supplied using a plasma CVD apparatus having a plurality of electrode pairs, the production of semiconductor layers on a plurality of substrates is performed. The film speed can be made uniform.
[Brief description of the drawings]
FIG. 1 is a diagram schematically showing a plasma CVD apparatus used in an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a hybrid thin-film solar battery manufactured in an embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Chamber 2a, 2b ... Cathode 3a, 3b ... Anode 4a, 4b ... High frequency power supply 5 ... Phase shifter 10a, 10b ...
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Priority Applications (1)
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